spice2wireviz/tests/fixtures/1002A.net

* Z:\tmp\1002A.asc
* Generated by LTspice 26.0.1 for Windows.
V1 +V 0 15
V2 -V 0 -15
R1 N003 N001 10K
R2 N001 0 100K
V3 IN- IN+ SINE(0 1m 100)
R3 N002 N001 2.2K
R4 N002 N003 10K
R5 OUT N002 100K
V4 IN+ 0 SINE(0 1 10)
X§U1 IN- N001 +V -V N003 LT1001 ;§pnba In+)In-)V+)V-)OUT
X§U2 IN+ N002 +V -V OUT LT1001 ;§pnba In+)In-)V+)V-)OUT
.tran 300m
* Two Op Amp Instrumentation Amplifier
* Library below included based on ModelFile attribute of instance X§U1, X§U2 (C:\users\rpm\AppData\Local\LTspice\lib\sym\OpAmps\LT1002A.asy)
.lib LTC.lib
.backanno
.end
Add BOM output, fix LTspice Tier 2 import, real .asc integration tests - Fix _try_ltspice_generation() to use spicelib.simulators.ltspice_simulator.LTspice instead of the abstract Simulator base class (which always returned unavailable) - Use LTspice.create_netlist() instead of Simulator.run() for correct netlist generation - Add --ltspice-exe CLI option to specify LTspice binary path - Add --bom flag for component BOM CSV output (works on any parse completeness) - Add --bom-wiring flag for wiring BOM CSV from mapped output - Add real 1002A.asc demo circuit and pre-generated .net as test fixtures - Add @pytest.mark.ltspice marker for tests requiring LTspice binary - Bump version to 2026.2.14 2026-02-13 07:00:39 -07:00			`* Z:\tmp\1002A.asc`
			`* Generated by LTspice 26.0.1 for Windows.`
			`V1 +V 0 15`
			`V2 -V 0 -15`
			`R1 N003 N001 10K`
			`R2 N001 0 100K`
			`V3 IN- IN+ SINE(0 1m 100)`
			`R3 N002 N001 2.2K`
			`R4 N002 N003 10K`
			`R5 OUT N002 100K`
			`V4 IN+ 0 SINE(0 1 10)`
			`X§U1 IN- N001 +V -V N003 LT1001 ;§pnba In+)In-)V+)V-)OUT`
			`X§U2 IN+ N002 +V -V OUT LT1001 ;§pnba In+)In-)V+)V-)OUT`
			`.tran 300m`
			`* Two Op Amp Instrumentation Amplifier`
			`* Library below included based on ModelFile attribute of instance X§U1, X§U2 (C:\users\rpm\AppData\Local\LTspice\lib\sym\OpAmps\LT1002A.asy)`
			`.lib LTC.lib`
			`.backanno`
			`.end`