warehack.ing/spice2wireviz
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
spice2wireviz/tests
History
Exact
Ryan Malloy 95ed08866c Add verbose flag, WireViz dev dep, and rendered diagram examples 
- Gate model/value heuristic output behind --verbose/-v flag (quiet by default)
- Add wireviz>=0.4 as dev dependency for roundtrip render tests
- Generate SVG/PNG diagram renders for inter_module, single_module, hierarchical
- Embed rendered diagrams in README with layout optimization callout
2026-02-13 09:19:18 -07:00
..
fixtures Add BOM output, fix LTspice Tier 2 import, real .asc integration tests 2026-02-13 07:00:39 -07:00
__init__.py Initial project structure for spice2wireviz 2026-02-13 01:24:41 -07:00
test_asc.py Add BOM output, fix LTspice Tier 2 import, real .asc integration tests 2026-02-13 07:00:39 -07:00
test_bom_emitter.py Add BOM output, fix LTspice Tier 2 import, real .asc integration tests 2026-02-13 07:00:39 -07:00
test_cli.py Add BOM output, fix LTspice Tier 2 import, real .asc integration tests 2026-02-13 07:00:39 -07:00
test_filter.py Fix linting issues and ground/power filtering in inter-module mapper 2026-02-13 01:27:45 -07:00
test_inter_module.py Add Sugiyama-lite layout optimization for inter-module diagrams 2026-02-13 02:01:06 -07:00
test_netlist_parser.py Add verbose flag, WireViz dev dep, and rendered diagram examples 2026-02-13 09:19:18 -07:00
test_roundtrip.py Address all critical and important findings from safety review 2026-02-13 01:34:30 -07:00
test_single_module.py Add tiered .asc parser with companion netlist resolution 2026-02-13 04:59:03 -07:00
test_yaml_emitter.py Initial project structure for spice2wireviz 2026-02-13 01:24:41 -07:00