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Ryan Malloy b9154e851b Address all critical and important findings from safety review 
C1: Port count mismatch now emits ERROR to stderr and marks
    unconnected ports as __UNCONNECTED_<name>__ (never silent)
C2: Single-module pin mapping built in lockstep — cable_wires
    always matches header_pins length, warns on unmappable nets
C3: VSS removed from is_power_net (it's ground per CMOS convention),
    dead _POWER_PATTERN regex replaced with _KNOWN_NET_PATTERN
C4: apply_filters dead computation removed, docstring clarifies
    that net-level filtering is a mapper concern

I3: WireViz render catches (ValueError, TypeError, OSError) with
    diagnostic context instead of bare Exception
I5: Invalid --format flags now warn and error instead of silently
    falling through to defaults
I6: Model/value heuristic warns on stderr when it triggers, since
    signal names like ALERT or DATA could be misidentified

New tests: VSS classification, port count mismatch (C1), model/value
heuristic warning (I6), duplicate refs (S3), empty subcircuit (S2),
full pipeline determinism across 3 runs (S1)

115 tests pass, ruff clean
2026-02-13 01:34:30 -07:00
src/spice2wireviz Address all critical and important findings from safety review 2026-02-13 01:34:30 -07:00
tests Address all critical and important findings from safety review 2026-02-13 01:34:30 -07:00
.gitignore Fix linting issues and ground/power filtering in inter-module mapper 2026-02-13 01:27:45 -07:00
pyproject.toml Fix linting issues and ground/power filtering in inter-module mapper 2026-02-13 01:27:45 -07:00
README.md Fix linting issues and ground/power filtering in inter-module mapper 2026-02-13 01:27:45 -07:00
uv.lock Fix linting issues and ground/power filtering in inter-module mapper 2026-02-13 01:27:45 -07:00

README.md

spice2wireviz

Convert LTspice SPICE netlists to WireViz wiring diagrams.

What it does

spice2wireviz reads SPICE netlist files (.net, .cir, .sp) and generates WireViz YAML that documents the physical wiring: connectors, test points, and inter-module cables.

Two operating modes:

  • Single module — External interface of one subcircuit (its connectors, test points, port interface)
  • Inter-module — How multiple subcircuits/boards connect to each other

Install

uv tool install spice2wireviz
# or
pip install spice2wireviz

Usage

# Inter-module wiring (auto-detected from top-level X instances)
spice2wireviz top_level.net -o wiring.yml --render

# Single module external interface
spice2wireviz design.net -s amplifier_board -o amp.yml

# Only connectors and test points, no ground
spice2wireviz design.net --include-prefixes J,TP --no-ground

# Inspect before converting
spice2wireviz design.net --list-subcircuits
spice2wireviz design.net --list-components
spice2wireviz design.net --dry-run

Filtering

Cherry-pick what appears in the diagram:

--include-prefixes J,TP     # Only these component types
--exclude-refs X3,J_DEBUG   # Hide specific references
--include-nets "SIG_*"      # Glob patterns for net names
--no-ground                 # Hide GND connections
--no-power                  # Hide VCC/VDD connections

Development

uv sync --extra dev
uv run pytest
uv run ruff check src/ tests/