Ryan Malloy b8ff2d19da Add Sugiyama-lite layout optimization for inter-module diagrams ... Layered graph drawing approach to minimize cable crossings: - Layer assignment via BFS from external connectors (J*, TP*, P*) - Barycenter ordering (forward + backward sweep) within each layer - Connection orientation: earlier connector always on the left - Pin reordering: weighted average neighbor position groups pins by destination, reducing within-connector crossings - Connection sorting: shorter (adjacent-pair) connections first Fixes from Apollo safety review: - Explicit ValueError on pin remapping failures (was silent KeyError) - Weighted pin averaging for star topology (GND shared across modules) - Fully deterministic sort keys for reproducible output - Documented closure capture pattern in loop sort keys		2026-02-13 02:01:06 -07:00
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fixtures	Initial project structure for spice2wireviz	2026-02-13 01:24:41 -07:00
__init__.py	Initial project structure for spice2wireviz	2026-02-13 01:24:41 -07:00
test_cli.py	Fix linting issues and ground/power filtering in inter-module mapper	2026-02-13 01:27:45 -07:00
test_filter.py	Fix linting issues and ground/power filtering in inter-module mapper	2026-02-13 01:27:45 -07:00
test_inter_module.py	Add Sugiyama-lite layout optimization for inter-module diagrams	2026-02-13 02:01:06 -07:00
test_netlist_parser.py	Address all critical and important findings from safety review	2026-02-13 01:34:30 -07:00
test_roundtrip.py	Address all critical and important findings from safety review	2026-02-13 01:34:30 -07:00
test_single_module.py	Initial project structure for spice2wireviz	2026-02-13 01:24:41 -07:00
test_yaml_emitter.py	Initial project structure for spice2wireviz	2026-02-13 01:24:41 -07:00