spice2wireviz/tests
Ryan Malloy 5a5337566c Add BOM output, fix LTspice Tier 2 import, real .asc integration tests
- Fix _try_ltspice_generation() to use spicelib.simulators.ltspice_simulator.LTspice
  instead of the abstract Simulator base class (which always returned unavailable)
- Use LTspice.create_netlist() instead of Simulator.run() for correct netlist generation
- Add --ltspice-exe CLI option to specify LTspice binary path
- Add --bom flag for component BOM CSV output (works on any parse completeness)
- Add --bom-wiring flag for wiring BOM CSV from mapped output
- Add real 1002A.asc demo circuit and pre-generated .net as test fixtures
- Add @pytest.mark.ltspice marker for tests requiring LTspice binary
- Bump version to 2026.2.14
2026-02-13 07:00:39 -07:00
..
fixtures Add BOM output, fix LTspice Tier 2 import, real .asc integration tests 2026-02-13 07:00:39 -07:00
__init__.py Initial project structure for spice2wireviz 2026-02-13 01:24:41 -07:00
test_asc.py Add BOM output, fix LTspice Tier 2 import, real .asc integration tests 2026-02-13 07:00:39 -07:00
test_bom_emitter.py Add BOM output, fix LTspice Tier 2 import, real .asc integration tests 2026-02-13 07:00:39 -07:00
test_cli.py Add BOM output, fix LTspice Tier 2 import, real .asc integration tests 2026-02-13 07:00:39 -07:00
test_filter.py Fix linting issues and ground/power filtering in inter-module mapper 2026-02-13 01:27:45 -07:00
test_inter_module.py Add Sugiyama-lite layout optimization for inter-module diagrams 2026-02-13 02:01:06 -07:00
test_netlist_parser.py Address all critical and important findings from safety review 2026-02-13 01:34:30 -07:00
test_roundtrip.py Address all critical and important findings from safety review 2026-02-13 01:34:30 -07:00
test_single_module.py Add tiered .asc parser with companion netlist resolution 2026-02-13 04:59:03 -07:00
test_yaml_emitter.py Initial project structure for spice2wireviz 2026-02-13 01:24:41 -07:00