Ryan Malloy c2197f6fe6 Add star-topology layout optimization for single-module diagrams ... Three-pass optimization eliminates cable crossings: 1. Order boundary components by average header pin position 2. Regroup header pins by boundary component (reduces inter-cable crossings) 3. Reorder boundary component pins to parallel header (eliminates within-cable crossings) Safety hardening from Apollo review: - Duplicate header pin deduplication (prevents silent mapping corruption) - Connection structure validation at entry - Fan-out averaging for component pins connected to multiple header pins - Explicit ValueError on pin remapping failures with diagnostic context 145 tests passing (was 130).		2026-02-13 03:07:50 -07:00
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hierarchical.yml	Add Sugiyama-lite layout optimization for inter-module diagrams	2026-02-13 02:01:06 -07:00
inter_module.yml	Add Sugiyama-lite layout optimization for inter-module diagrams	2026-02-13 02:01:06 -07:00
single_module.yml	Add star-topology layout optimization for single-module diagrams	2026-02-13 03:07:50 -07:00