Fix linting issues and ground/power filtering in inter-module mapper

- Use CalVer dot notation (2026.2.13) for PEP 440 compliance
- Filter pinlabels for top-level components when ground/power hidden
- Fix unused variables, long lines, import ordering (ruff clean)
- Use StrEnum for PinDirection (Python 3.11+)
- Add .gitignore and README.md
- All 105 tests pass including WireViz roundtrip validation

tests/test_cli.py

@@ -14,7 +14,7 @@ class TestCLIBasic:
         runner = CliRunner()
         result = runner.invoke(main, ["--version"])
         assert result.exit_code == 0
-        assert "2026-02-13" in result.output
+        assert "2026.2.13" in result.output
 
     def test_list_subcircuits(self):
         runner = CliRunner()

tests/test_filter.py

@@ -1,6 +1,12 @@
 """Tests for the filter engine."""
 
-from spice2wireviz.filter import FilterConfig, apply_filters, filter_component, filter_instance, filter_net
+from spice2wireviz.filter import (
+    FilterConfig,
+    apply_filters,
+    filter_component,
+    filter_instance,
+    filter_net,
+)
 from spice2wireviz.parser.models import (
     ParsedNetlist,
     SpiceComponent,