Initial project structure for spice2wireviz

SPICE netlist to WireViz YAML converter with:
- Custom lightweight netlist parser (.net/.cir/.sp)
- Single-module mapper (subcircuit external interface)
- Inter-module mapper (multi-board wiring)
- Filter engine with glob patterns
- Click CLI with auto-detection, inspection commands
- Optional .asc parser via spicelib
- Comprehensive test suite with fixtures

tests/fixtures/simple_board.net

@@ -0,0 +1,14 @@
+* Simple board netlist with one subcircuit
+* Has connectors J1 (power), J2 (signal I/O), and test point TP1
+
+.subckt amplifier_board VIN GND VOUT SIGNAL_IN
+* Internal components (passives, ICs — not relevant to wiring)
+R1 VIN N001 10k
+R2 N001 GND 10k
+U1 N001 VOUT GND VCC opamp
+
+* Boundary components (connectors/test points visible at board edge)
+J1 VIN GND PWR_CONN
+J2 SIGNAL_IN VOUT SIG_CONN
+TP1 N001
+.ends amplifier_board