Initial project structure for spice2wireviz

SPICE netlist to WireViz YAML converter with:
- Custom lightweight netlist parser (.net/.cir/.sp)
- Single-module mapper (subcircuit external interface)
- Inter-module mapper (multi-board wiring)
- Filter engine with glob patterns
- Click CLI with auto-detection, inspection commands
- Optional .asc parser via spicelib
- Comprehensive test suite with fixtures
This commit is contained in:
Ryan Malloy 2026-02-13 01:24:41 -07:00
commit e20a956f51
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tests/fixtures/multi_board.net vendored Normal file
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* Multi-board system: power supply, amplifier, and I/O board
* Demonstrates inter-module wiring
.subckt power_supply VCC GND
J1 AC_IN AC_GND AC_INLET
.ends power_supply
.subckt amplifier VIN GND VOUT
R1 VIN N001 10k
C1 N001 GND 100n
J1 VIN GND INPUT_CONN
TP1 VOUT
.ends amplifier
.subckt io_board SIG_IN SIG_OUT GND CTRL
J1 SIG_IN SIG_OUT DB9_CONN
J2 CTRL GND CTRL_CONN
.ends io_board
* Top-level instantiation
X1 VCC GND power_supply
X2 VCC GND AUDIO_OUT amplifier
X3 AUDIO_OUT CTRL_SIG GND ENABLE io_board
* Top-level connectors
J_CHASSIS GND EARTH chassis_gnd
TP_VCC VCC