Add star-topology layout optimization for single-module diagrams

Three-pass optimization eliminates cable crossings:
1. Order boundary components by average header pin position
2. Regroup header pins by boundary component (reduces inter-cable crossings)
3. Reorder boundary component pins to parallel header (eliminates within-cable
   crossings)

Safety hardening from Apollo review:
- Duplicate header pin deduplication (prevents silent mapping corruption)
- Connection structure validation at entry
- Fan-out averaging for component pins connected to multiple header pins
- Explicit ValueError on pin remapping failures with diagnostic context

145 tests passing (was 130).

examples/single_module.yml

@@ -20,8 +20,8 @@ connectors:
   J2:
     type: SIG_CONN
     pinlabels:
-    - SIGNAL_IN
     - VOUT
+    - SIGNAL_IN
     notes: 'SPICE ref: J2, nets: SIGNAL_IN, VOUT'
   TP1:
     type: TP
@@ -63,5 +63,5 @@ connections:
     - 1
     - 2
   - J2:
-    - 2
     - 1
+    - 2