Add Sugiyama-lite layout optimization for inter-module diagrams

Layered graph drawing approach to minimize cable crossings:
- Layer assignment via BFS from external connectors (J*, TP*, P*)
- Barycenter ordering (forward + backward sweep) within each layer
- Connection orientation: earlier connector always on the left
- Pin reordering: weighted average neighbor position groups pins
  by destination, reducing within-connector crossings
- Connection sorting: shorter (adjacent-pair) connections first

Fixes from Apollo safety review:
- Explicit ValueError on pin remapping failures (was silent KeyError)
- Weighted pin averaging for star topology (GND shared across modules)
- Fully deterministic sort keys for reproducible output
- Documented closure capture pattern in loop sort keys

examples/single_module.yml

@@ -0,0 +1,67 @@
+metadata:
+  title: 'Wiring diagram: simple_board'
+  source: tests/fixtures/simple_board.net
+  generator: spice2wireviz 2026.2.13
+connectors:
+  amplifier_board:
+    type: Module Interface
+    pinlabels:
+    - VIN
+    - GND
+    - VOUT
+    - SIGNAL_IN
+    notes: 'SPICE subcircuit: .subckt amplifier_board'
+  J1:
+    type: PWR_CONN
+    pinlabels:
+    - VIN
+    - GND
+    notes: 'SPICE ref: J1, nets: VIN, GND'
+  J2:
+    type: SIG_CONN
+    pinlabels:
+    - SIGNAL_IN
+    - VOUT
+    notes: 'SPICE ref: J2, nets: SIGNAL_IN, VOUT'
+  TP1:
+    type: TP
+    style: simple
+    pinlabels:
+    - N001
+    notes: 'SPICE ref: TP1, nets: N001'
+cables:
+  W_J1:
+    category: bundle
+    colors:
+    - ''
+    - BK
+    wirelabels:
+    - VIN
+    - GND
+    notes: 'Nets: VIN, GND'
+  W_J2:
+    category: bundle
+    wirecount: 2
+    wirelabels:
+    - VOUT
+    - SIGNAL_IN
+    notes: 'Nets: VOUT, SIGNAL_IN'
+connections:
+- - amplifier_board:
+    - 1
+    - 2
+  - W_J1:
+    - 1
+    - 2
+  - J1:
+    - 1
+    - 2
+- - amplifier_board:
+    - 3
+    - 4
+  - W_J2:
+    - 1
+    - 2
+  - J2:
+    - 2
+    - 1