Add verbose flag, WireViz dev dep, and rendered diagram examples

- Gate model/value heuristic output behind --verbose/-v flag (quiet by default)
- Add wireviz>=0.4 as dev dependency for roundtrip render tests
- Generate SVG/PNG diagram renders for inter_module, single_module, hierarchical
- Embed rendered diagrams in README with layout optimization callout

README.md

@@ -46,6 +46,28 @@ spice2wireviz design.net --bom
 spice2wireviz top_level.net --bom-wiring
 ```
 
+## Rendered diagrams
+
+### Inter-module wiring
+
+How multiple boards/modules connect to each other — power supply, amplifier, and I/O board with shared power and signal routing:
+
+![Inter-module wiring diagram](docs/examples/inter_module.png)
+
+### Single-module interface
+
+External interface of one subcircuit — the amplifier board's connectors and test points radiating from a central port header:
+
+![Single-module wiring diagram](docs/examples/single_module.png)
+
+### Hierarchical system
+
+A complex multi-level system with voltage regulator, main board, sensor module, and external connectors:
+
+![Hierarchical wiring diagram](docs/examples/hierarchical.png)
+
+These diagrams are generated automatically by piping `spice2wireviz` output through WireViz (`--render` flag). The layout optimizer minimizes cable crossings — notice how parallel wires between the same module pair are bundled into multi-wire cables.
+
 ## Output examples
 
 ### Input: SPICE netlist
@@ -324,7 +346,7 @@ The parser extracts subcircuit definitions (`.subckt`), instances (`X*`), and bo
 
 ```bash
 uv sync --extra dev --extra asc
-uv run pytest                      # 188 tests
+uv run pytest                      # 194 tests
 uv run ruff check src/ tests/
 ```