warehack.ing/spice2wireviz
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Add tiered .asc parser with companion netlist resolution

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Implement three-tier resolution for LTspice .asc schematic files:

1. Companion netlist - finds .net/.cir/.sp beside the .asc (automatic)
2. LTspice generation - invokes LTspice binary (opt-in via --generate-netlist)
3. Metadata-only fallback - extracts component refs/values without connectivity

Safety: DataCompleteness enum forces callers to check completeness.
CLI blocks diagram generation on METADATA_ONLY with clear remediation.
Metadata enrichment is additive-only with protected field guards.

Also: update project URLs to Gitea, add .asc usage docs to README,
fix pre-existing ruff warning in test_single_module.py.
This commit is contained in:
Ryan Malloy 2026-02-13 04:59:03 -07:00
parent ad03798b4d
commit 08c92bfefb
9 changed files with 833 additions and 61 deletions
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6
pyproject.toml
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@ -29,9 +29,9 @@ dependencies = [
]
[project.urls]
Homepage = "https://github.com/ryanmalloy/spice2wireviz"
Repository = "https://github.com/ryanmalloy/spice2wireviz"
Issues = "https://github.com/ryanmalloy/spice2wireviz/issues"
Homepage = "https://git.supported.systems/warehack.ing/spice2wireviz"
Repository = "https://git.supported.systems/warehack.ing/spice2wireviz"
Issues = "https://git.supported.systems/warehack.ing/spice2wireviz/issues"
[project.optional-dependencies]
asc = ["spicelib>=1.4.9"]