From a70b9b0a29b1751ca6d2bca59e9e731df064eed6 Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Fri, 13 Feb 2026 05:20:34 -0700 Subject: [PATCH 01/30] =?UTF-8?q?Ignore=20site/=20directory=20=E2=80=94=20?= =?UTF-8?q?now=20its=20own=20repo=20(warehack.ing/birdcage-docs)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .gitignore | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitignore b/.gitignore index f9e9018..39605de 100644 --- a/.gitignore +++ b/.gitignore @@ -11,6 +11,9 @@ build/ *.so .ruff_cache/ +# Documentation site (separate repo: warehack.ing/birdcage-docs) +site/ + # PlatformIO .pio/ .pioenvs/ From 7271b53c633258d99f8f9fac19a01e49c5261129 Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Fri, 13 Feb 2026 08:53:03 -0700 Subject: [PATCH 02/30] Add Birdcage TUI: 5-screen Textual interface for Carryout G2 F1 Position (compass rose, motor control, sparklines), F2 Signal (RSSI gauge with sub-char precision, DVB/ADC sparklines, LNA toggle), F3 Scan (AZ/EL grid sweep with heatmap and CSV export), F4 System (NVS table, A3981 diagnostics, motor dynamics), F5 Console (raw serial terminal with prompt detection and safety gates). Includes SerialBridge (thread-safe protocol wrapper), DemoDevice (synthetic simulation for --demo mode), dark RF theme with rounded borders and teal accents, and send_raw() on CarryoutG2Protocol. --- src/birdcage/protocol.py | 4 + tui/pyproject.toml | 31 + tui/src/birdcage_tui/__init__.py | 1 + tui/src/birdcage_tui/app.py | 165 +++++ tui/src/birdcage_tui/bridge.py | 439 ++++++++++++ tui/src/birdcage_tui/demo.py | 631 ++++++++++++++++++ tui/src/birdcage_tui/screens/__init__.py | 1 + tui/src/birdcage_tui/screens/console.py | 232 +++++++ tui/src/birdcage_tui/screens/position.py | 282 ++++++++ tui/src/birdcage_tui/screens/scan.py | 272 ++++++++ tui/src/birdcage_tui/screens/signal.py | 233 +++++++ tui/src/birdcage_tui/screens/system.py | 358 ++++++++++ tui/src/birdcage_tui/theme.tcss | 496 ++++++++++++++ tui/src/birdcage_tui/widgets/__init__.py | 21 + tui/src/birdcage_tui/widgets/compass_rose.py | 183 +++++ .../birdcage_tui/widgets/device_status_bar.py | 92 +++ tui/src/birdcage_tui/widgets/motor_status.py | 76 +++ tui/src/birdcage_tui/widgets/nvs_table.py | 93 +++ tui/src/birdcage_tui/widgets/serial_log.py | 84 +++ tui/src/birdcage_tui/widgets/signal_gauge.py | 90 +++ tui/src/birdcage_tui/widgets/sky_heatmap.py | 123 ++++ .../birdcage_tui/widgets/sparkline_widget.py | 74 ++ tui/uv.lock | 179 +++++ 23 files changed, 4160 insertions(+) create mode 100644 tui/pyproject.toml create mode 100644 tui/src/birdcage_tui/__init__.py create mode 100644 tui/src/birdcage_tui/app.py create mode 100644 tui/src/birdcage_tui/bridge.py create mode 100644 tui/src/birdcage_tui/demo.py create mode 100644 tui/src/birdcage_tui/screens/__init__.py create mode 100644 tui/src/birdcage_tui/screens/console.py create mode 100644 tui/src/birdcage_tui/screens/position.py create mode 100644 tui/src/birdcage_tui/screens/scan.py create mode 100644 tui/src/birdcage_tui/screens/signal.py create mode 100644 tui/src/birdcage_tui/screens/system.py create mode 100644 tui/src/birdcage_tui/theme.tcss create mode 100644 tui/src/birdcage_tui/widgets/__init__.py create mode 100644 tui/src/birdcage_tui/widgets/compass_rose.py create mode 100644 tui/src/birdcage_tui/widgets/device_status_bar.py create mode 100644 tui/src/birdcage_tui/widgets/motor_status.py create mode 100644 tui/src/birdcage_tui/widgets/nvs_table.py create mode 100644 tui/src/birdcage_tui/widgets/serial_log.py create mode 100644 tui/src/birdcage_tui/widgets/signal_gauge.py create mode 100644 tui/src/birdcage_tui/widgets/sky_heatmap.py create mode 100644 tui/src/birdcage_tui/widgets/sparkline_widget.py create mode 100644 tui/uv.lock diff --git a/src/birdcage/protocol.py b/src/birdcage/protocol.py index dc7bbc7..c03885e 100644 --- a/src/birdcage/protocol.py +++ b/src/birdcage/protocol.py @@ -392,6 +392,10 @@ class CarryoutG2Protocol(FirmwareProtocol): raise ValueError(f"Could not parse RSSI from: {response!r}") + def send_raw(self, cmd: str) -> str: + """Send arbitrary command, return raw prompt-terminated response.""" + return self._send(cmd) + def quit_submenu(self) -> None: """Exit current submenu and return to parent.""" self._send("q") diff --git a/tui/pyproject.toml b/tui/pyproject.toml new file mode 100644 index 0000000..85f6d7e --- /dev/null +++ b/tui/pyproject.toml @@ -0,0 +1,31 @@ +[build-system] +requires = ["hatchling"] +build-backend = "hatchling.build" + +[project] +name = "birdcage-tui" +version = "2026.02.13" +description = "Textual TUI for Winegard Carryout G2 satellite dish control" +license = "MIT" +requires-python = ">=3.11" +authors = [{name = "Ryan Malloy", email = "ryan@supported.systems"}] +dependencies = [ + "birdcage", + "textual>=1.0.0", +] + +[project.scripts] +birdcage-tui = "birdcage_tui.app:main" + +[tool.uv.sources] +birdcage = { path = ".." } + +[tool.ruff] +target-version = "py311" +src = ["src"] + +[tool.ruff.lint] +select = ["E", "F", "I", "UP", "B", "SIM"] + +[tool.hatch.build.targets.wheel] +packages = ["src/birdcage_tui"] diff --git a/tui/src/birdcage_tui/__init__.py b/tui/src/birdcage_tui/__init__.py new file mode 100644 index 0000000..d5dfabc --- /dev/null +++ b/tui/src/birdcage_tui/__init__.py @@ -0,0 +1 @@ +"""Birdcage TUI — Textual interface for Winegard satellite dish control.""" diff --git a/tui/src/birdcage_tui/app.py b/tui/src/birdcage_tui/app.py new file mode 100644 index 0000000..1349e63 --- /dev/null +++ b/tui/src/birdcage_tui/app.py @@ -0,0 +1,165 @@ +"""Birdcage TUI — main application shell. + +ContentSwitcher-based layout with sidebar navigation (F1-F5), +device status bar, and five swappable screen panels. +""" + +import argparse +import logging + +from textual.app import App, ComposeResult +from textual.binding import Binding +from textual.containers import Horizontal, Vertical +from textual.widgets import Button, ContentSwitcher, Footer, Header, Static + +from birdcage_tui.screens.console import ConsoleScreen +from birdcage_tui.screens.position import PositionScreen +from birdcage_tui.screens.scan import ScanScreen +from birdcage_tui.screens.signal import SignalScreen +from birdcage_tui.screens.system import SystemScreen +from birdcage_tui.widgets.device_status_bar import DeviceStatusBar + +log = logging.getLogger(__name__) + +MODES: dict[str, tuple[str, type]] = { + "position": ("F1 Position", PositionScreen), + "signal": ("F2 Signal", SignalScreen), + "scan": ("F3 Scan", ScanScreen), + "system": ("F4 System", SystemScreen), + "console": ("F5 Console", ConsoleScreen), +} + + +class BirdcageApp(App): + """Textual application for Winegard satellite dish control.""" + + TITLE = "Birdcage" + CSS_PATH = "theme.tcss" + + BINDINGS = [ + Binding("f1", "switch_mode('position')", "Position"), + Binding("f2", "switch_mode('signal')", "Signal"), + Binding("f3", "switch_mode('scan')", "Scan"), + Binding("f4", "switch_mode('system')", "System"), + Binding("f5", "switch_mode('console')", "Console"), + Binding("q", "quit", "Quit"), + Binding("d", "toggle_dark", "Dark"), + ] + + # Set from CLI args before run() + demo_mode: bool = False + serial_port: str = "/dev/ttyUSB0" + firmware_name: str = "g2" + skip_init: bool = False + device: object = None + + @property + def SUB_TITLE(self) -> str: # noqa: N802 + if self.demo_mode: + return "DEMO" + return self.serial_port + + def compose(self) -> ComposeResult: + yield Header() + with Horizontal(id="main-area"): + with Vertical(id="sidebar"): + yield Static("\U0001f6f0\ufe0f Birdcage", classes="sidebar-title") + yield Static("Carryout G2", classes="sidebar-subtitle") + for mode_key, (label, _) in MODES.items(): + yield Button(label, id=f"btn-{mode_key}", classes="sidebar-btn") + yield DeviceStatusBar(id="device-status") + with ContentSwitcher(id="content-area", initial="position"): + for mode_key, (_, screen_cls) in MODES.items(): + yield screen_cls(id=mode_key) + yield Footer() + + def on_mount(self) -> None: + self.query_one("#btn-position").add_class("active") + self._setup_device() + + def _setup_device(self) -> None: + """Create device (demo or real) and hand it to each screen.""" + if self.demo_mode: + from birdcage_tui.demo import DemoDevice + + self.device = DemoDevice() + self.device.connect() + else: + from birdcage.protocol import get_protocol + + from birdcage_tui.bridge import SerialBridge + + protocol = get_protocol(self.firmware_name) + self.device = SerialBridge(protocol) + self.device.connect(self.serial_port) + if not self.skip_init: + self.run_worker(self._initialize_device, thread=True) + + self._distribute_device() + + async def _initialize_device(self) -> None: + """Run device init in a worker thread (blocks on serial I/O).""" + try: + self.device.initialize() + except Exception: + log.exception("Device initialization failed") + self.notify("Init failed -- check serial connection", severity="error") + + def _distribute_device(self) -> None: + """Pass the device reference to every screen that wants it.""" + for mode_key in MODES: + screen = self.query_one(f"#{mode_key}") + if hasattr(screen, "set_device"): + screen.set_device(self.device) + + status_bar = self.query_one("#device-status", DeviceStatusBar) + if hasattr(status_bar, "set_device"): + status_bar.set_device(self.device) + + def action_switch_mode(self, mode: str) -> None: + """Switch the content area to *mode* and update sidebar highlight.""" + switcher = self.query_one("#content-area", ContentSwitcher) + switcher.current = mode + + for btn in self.query(".sidebar-btn"): + btn.remove_class("active") + self.query_one(f"#btn-{mode}").add_class("active") + + screen = self.query_one(f"#{mode}") + if hasattr(screen, "on_show"): + screen.on_show() + + def action_toggle_dark(self) -> None: + self.dark = not self.dark + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + if button_id.startswith("btn-"): + mode = button_id.removeprefix("btn-") + if mode in MODES: + self.action_switch_mode(mode) + + +def main() -> None: + parser = argparse.ArgumentParser( + description="Birdcage TUI -- Satellite Dish Control" + ) + parser.add_argument("--demo", action="store_true", help="Run with simulated device") + parser.add_argument("--port", default="/dev/ttyUSB0", help="Serial port") + parser.add_argument( + "--firmware", + default="g2", + choices=["g2", "hal205", "hal000"], + help="Firmware version", + ) + parser.add_argument( + "--skip-init", action="store_true", help="Skip firmware initialization" + ) + args = parser.parse_args() + + app = BirdcageApp() + app.demo_mode = args.demo + app.serial_port = args.port + app.firmware_name = args.firmware + app.skip_init = args.skip_init + app.run() diff --git a/tui/src/birdcage_tui/bridge.py b/tui/src/birdcage_tui/bridge.py new file mode 100644 index 0000000..a90e218 --- /dev/null +++ b/tui/src/birdcage_tui/bridge.py @@ -0,0 +1,439 @@ +"""Thread-safe bridge between Birdcage TUI and CarryoutG2Protocol. + +Wraps all serial I/O in a threading.Lock so the TUI's worker threads +don't stomp on each other. Tracks the current firmware submenu to +minimize unnecessary q-then-reenter transitions. +""" + +import contextlib +import logging +import re +import threading +from enum import Enum, auto + +from birdcage.protocol import CarryoutG2Protocol + +logger = logging.getLogger(__name__) + + +class Menu(Enum): + """Firmware submenu states.""" + + ROOT = auto() + MOT = auto() + DVB = auto() + NVS = auto() + A3981 = auto() + ADC = auto() + OS = auto() + STEP = auto() + PEAK = auto() + EEPROM = auto() + GPIO = auto() + LATLON = auto() + DIPSWITCH = auto() + UNKNOWN = auto() + + +# Map Menu enum to the command that enters it from root. +_MENU_COMMANDS: dict[Menu, str] = { + Menu.MOT: "mot", + Menu.DVB: "dvb", + Menu.NVS: "nvs", + Menu.A3981: "a3981", + Menu.ADC: "adc", + Menu.OS: "os", + Menu.STEP: "step", + Menu.PEAK: "peak", + Menu.EEPROM: "eeprom", + Menu.GPIO: "gpio", + Menu.LATLON: "latlon", + Menu.DIPSWITCH: "dipswitch", +} + + +class SerialBridge: + """Thread-safe wrapper around CarryoutG2Protocol for TUI consumption. + + All public methods acquire a lock before touching the serial port. + The bridge tracks the current firmware submenu so it can skip + redundant quit-and-reenter cycles. + """ + + def __init__(self, protocol: CarryoutG2Protocol) -> None: + self._proto = protocol + self._lock = threading.Lock() + self._menu = Menu.UNKNOWN + self._connected = False + + # ------------------------------------------------------------------ + # Internal helpers + # ------------------------------------------------------------------ + + def _send(self, cmd: str) -> str: + """Send a command via the protocol's prompt-terminated send. + + Caller must hold ``_lock``. + """ + return self._proto.send_raw(cmd) + + def _go_to_root(self) -> None: + """Return to TRK> root menu. Caller must hold ``_lock``.""" + self._proto.reset_to_root() + self._menu = Menu.ROOT + + def _ensure_menu(self, target: Menu) -> None: + """Navigate to *target* submenu if not already there. + + Caller must hold ``_lock``. + """ + if self._menu == target: + return + + # Always go back to root first — we don't know how to go + # directly between arbitrary submenus. + if self._menu != Menu.ROOT: + self._go_to_root() + + if target == Menu.ROOT: + return + + cmd = _MENU_COMMANDS.get(target) + if cmd is None: + raise ValueError(f"No entry command for menu {target!r}") + + self._send(cmd) + self._menu = target + + # ------------------------------------------------------------------ + # Connection + # ------------------------------------------------------------------ + + def connect(self, port: str, baudrate: int = 115200) -> None: + """Open the RS-422 serial connection.""" + with self._lock: + self._proto.connect(port, baudrate) + self._connected = True + self._menu = Menu.UNKNOWN + + def disconnect(self) -> None: + """Close the serial connection.""" + with self._lock: + with contextlib.suppress(Exception): + self._go_to_root() + self._proto.disconnect() + self._connected = False + self._menu = Menu.UNKNOWN + + @property + def is_connected(self) -> bool: + return self._connected and self._proto.is_connected + + def initialize(self, skip_init: bool = False) -> None: + """Prepare the dish for motor commands. + + Args: + skip_init: If True, skip the protocol initialize step + (useful when re-connecting to an already-running dish). + """ + with self._lock: + if not skip_init: + self._proto.initialize() + self._menu = Menu.MOT # initialize() ends in MOT> + + # ------------------------------------------------------------------ + # Motor (MOT>) + # ------------------------------------------------------------------ + + def get_position(self) -> dict[str, float]: + """Query current AZ/EL position. + + Returns: + ``{"azimuth": float, "elevation": float}`` + """ + with self._lock: + self._ensure_menu(Menu.MOT) + response = self._send("a") + + az_m = re.search(r"Angle\[0\]\s*=\s*(-?\d+\.?\d*)", response) + el_m = re.search(r"Angle\[1\]\s*=\s*(-?\d+\.?\d*)", response) + + if not az_m or not el_m: + raise ValueError(f"Could not parse position: {response!r}") + + return { + "azimuth": float(az_m.group(1)), + "elevation": float(el_m.group(1)), + } + + def move_to(self, az: float, el: float) -> None: + """Move the dish to an absolute AZ/EL position.""" + with self._lock: + self._ensure_menu(Menu.MOT) + self._send(f"a 0 {az}") + self._send(f"a 1 {el}") + + def move_motor(self, motor_id: int, degrees: float) -> None: + """Move a single motor to an absolute position.""" + with self._lock: + self._ensure_menu(Menu.MOT) + self._send(f"a {motor_id} {degrees}") + + def home_motor(self, motor_id: int) -> None: + """Home a motor to its reference position.""" + with self._lock: + self._ensure_menu(Menu.MOT) + self._send(f"h {motor_id}") + + def engage(self) -> None: + """Engage (energize) the stepper motors.""" + with self._lock: + self._ensure_menu(Menu.MOT) + self._send("e") + + def release(self) -> None: + """Release (de-energize) the stepper motors.""" + with self._lock: + self._ensure_menu(Menu.MOT) + self._send("r") + + def get_motor_list(self) -> str: + """List motors and their state.""" + with self._lock: + self._ensure_menu(Menu.MOT) + return self._send("l") + + def get_motor_dynamics(self) -> dict[str, float]: + """Read max velocity and acceleration for both axes. + + Returns: + ``{"az_max_vel": float, "el_max_vel": float, + "az_accel": float, "el_accel": float}`` + """ + with self._lock: + self._ensure_menu(Menu.MOT) + mv_resp = self._send("mv") + ma_resp = self._send("ma") + + result: dict[str, float] = { + "az_max_vel": 0.0, + "el_max_vel": 0.0, + "az_accel": 0.0, + "el_accel": 0.0, + } + + # mv → "Max Vel [0] = 65.0 Max Vel [1] = 45.0" or similar + vel_matches = re.findall(r"Max Vel\s*\[(\d)\]\s*=\s*(-?\d+\.?\d*)", mv_resp) + for motor_id, val in vel_matches: + if motor_id == "0": + result["az_max_vel"] = float(val) + elif motor_id == "1": + result["el_max_vel"] = float(val) + + # ma → "Accel[0] = 400.0 Accel[1] = 400.0" + acc_matches = re.findall(r"Accel\[(\d)\]\s*=\s*(-?\d+\.?\d*)", ma_resp) + for motor_id, val in acc_matches: + if motor_id == "0": + result["az_accel"] = float(val) + elif motor_id == "1": + result["el_accel"] = float(val) + + return result + + def get_motor_life(self) -> str: + """Read motor lifetime / usage statistics.""" + with self._lock: + self._ensure_menu(Menu.MOT) + return self._send("life") + + def get_el_limits(self) -> dict[str, float]: + """Read elevation min, max, and home angles. + + Firmware returns centidegrees: ``Min: 1800 Max: 6500 Home: 6500`` + + Returns: + ``{"min": 18.0, "max": 65.0, "home": 65.0}`` + """ + with self._lock: + self._ensure_menu(Menu.MOT) + response = self._send("elminmaxhome") + + result: dict[str, float] = {"min": 0.0, "max": 0.0, "home": 0.0} + + min_m = re.search(r"Min:\s*(\d+)", response) + max_m = re.search(r"Max:\s*(\d+)", response) + home_m = re.search(r"Home:\s*(\d+)", response) + + if min_m: + result["min"] = int(min_m.group(1)) / 100.0 + if max_m: + result["max"] = int(max_m.group(1)) / 100.0 + if home_m: + result["home"] = int(home_m.group(1)) / 100.0 + + return result + + def get_step_positions(self) -> dict[str, int]: + """Read raw step positions for both axes. + + Firmware returns: ``Position[0] = 19998 Position[1] = 3116`` + + Returns: + ``{"az_steps": int, "el_steps": int}`` + """ + with self._lock: + self._ensure_menu(Menu.MOT) + response = self._send("p") + + result: dict[str, int] = {"az_steps": 0, "el_steps": 0} + + matches = re.findall(r"Position\[(\d)\]\s*=\s*(-?\d+)", response) + for motor_id, val in matches: + if motor_id == "0": + result["az_steps"] = int(val) + elif motor_id == "1": + result["el_steps"] = int(val) + + return result + + # ------------------------------------------------------------------ + # Signal (DVB>) + # ------------------------------------------------------------------ + + def get_rssi(self, iterations: int = 10) -> dict[str, int]: + """Read averaged RSSI signal strength. + + Returns: + ``{"reads": int, "average": int, "current": int}`` + """ + with self._lock: + self._ensure_menu(Menu.DVB) + response = self._send(f"rssi {iterations}") + + match = re.search( + r"Reads:(\d+)\s+RSSI\[avg:\s*(\d+)\s+cur:\s*(\d+)\]", + response, + ) + if match: + return { + "reads": int(match.group(1)), + "average": int(match.group(2)), + "current": int(match.group(3)), + } + + raise ValueError(f"Could not parse RSSI: {response!r}") + + def enable_lna(self) -> None: + """Enable LNA in ODU mode (sets LNB to 13V).""" + with self._lock: + self._ensure_menu(Menu.DVB) + self._send("lnbdc odu") + + def get_lock_status(self) -> str: + """Read quick lock status (single-shot).""" + with self._lock: + self._ensure_menu(Menu.DVB) + return self._send("qls") + + def get_dvb_config(self) -> str: + """Read BCM hardware/firmware version.""" + with self._lock: + self._ensure_menu(Menu.DVB) + return self._send("config") + + def get_channel_params(self) -> str: + """Read current channel parameters.""" + with self._lock: + self._ensure_menu(Menu.DVB) + return self._send("dis") + + # ------------------------------------------------------------------ + # A3981 + # ------------------------------------------------------------------ + + def get_a3981_diag(self) -> str: + """Read A3981 diagnostic/fault status.""" + with self._lock: + self._ensure_menu(Menu.A3981) + return self._send("diag") + + def get_a3981_modes(self) -> dict[str, str]: + """Read A3981 step mode, current mode, and step size. + + Returns: + ``{"step_mode": str, "current_mode": str, "step_size": str}`` + """ + with self._lock: + self._ensure_menu(Menu.A3981) + sm_resp = self._send("sm") + cm_resp = self._send("cm") + ss_resp = self._send("ss") + + return { + "step_mode": sm_resp, + "current_mode": cm_resp, + "step_size": ss_resp, + } + + def get_a3981_torque(self) -> str: + """Read A3981 torque levels.""" + with self._lock: + self._ensure_menu(Menu.A3981) + return self._send("st") + + # ------------------------------------------------------------------ + # NVS + # ------------------------------------------------------------------ + + def nvs_dump(self) -> str: + """Dump all NVS values.""" + with self._lock: + self._ensure_menu(Menu.NVS) + return self._send("d") + + def nvs_read(self, index: int) -> str: + """Read a single NVS value by index.""" + with self._lock: + self._ensure_menu(Menu.NVS) + return self._send(f"e {index}") + + # ------------------------------------------------------------------ + # ADC + # ------------------------------------------------------------------ + + def get_adc_rssi(self) -> str: + """Read single-shot ADC RSSI value.""" + with self._lock: + self._ensure_menu(Menu.ADC) + return self._send("rssi") + + def get_board_id(self) -> str: + """Read board identification string.""" + with self._lock: + self._ensure_menu(Menu.ADC) + return self._send("bdid") + + # ------------------------------------------------------------------ + # OS + # ------------------------------------------------------------------ + + def get_firmware_id(self) -> str: + """Read full MCU and firmware identification.""" + with self._lock: + self._ensure_menu(Menu.OS) + return self._send("id") + + # ------------------------------------------------------------------ + # Raw / Console + # ------------------------------------------------------------------ + + def send_raw(self, cmd: str) -> str: + """Send an arbitrary command and return the raw response. + + After a raw command, the menu state is marked UNKNOWN because + the user may have navigated to a different submenu. + """ + with self._lock: + response = self._send(cmd) + self._menu = Menu.UNKNOWN + return response diff --git a/tui/src/birdcage_tui/demo.py b/tui/src/birdcage_tui/demo.py new file mode 100644 index 0000000..e86ab88 --- /dev/null +++ b/tui/src/birdcage_tui/demo.py @@ -0,0 +1,631 @@ +"""Synthetic demo device for the Birdcage TUI. + +Drop-in replacement for SerialBridge that simulates a Winegard Carryout G2 +dish with motor movement, RSSI signal modeling, and canned firmware responses. +No serial hardware required. +""" + +import contextlib +import math +import random +import time +from enum import Enum, auto + + +class _DemoMenu(Enum): + """Simulated firmware submenu states.""" + + ROOT = auto() + MOT = auto() + DVB = auto() + NVS = auto() + A3981 = auto() + ADC = auto() + OS = auto() + STEP = auto() + PEAK = auto() + EEPROM = auto() + GPIO = auto() + LATLON = auto() + DIPSWITCH = auto() + + +# Complete NVS dump text from firmware 02.02.48 (captured 2026-02-12). +_NVS_DUMP_TEXT = """\ +Num Name Current Saved Default +---- -------------------------- ---------- ---------- ---------- + 0) Log ID's 0x00000007 0x00000007 0x00000007 + 1) Log Device 0x00000001 0x00000001 0x00000001 + 2) Debug 2nd Console Port 0 0 0 + 3) Debug 2nd Packet Port 0 0 0 + 4) Debug Port Connection 0 0 0 + 16) Pitch Deadband 0.00 0.00 0.00 + 17) Roll Deadband 0.00 0.00 0.00 + 18) Yaw Deadband 0.00 0.00 0.00 + 20) Disable Tracker Proc? TRUE TRUE FALSE + 21) Tracker Proc Run Mode 0 0 0 + 22) Conical Alpha Az 200 200 200 + 23) Conical Alpha El 200 200 200 + 24) Conical Radius 1.00 1.00 1.00 + 25) Conical Count Max 20 20 20 + 26) Conical Test Drift +0 +0 +0 + 27) Circle RPM 120 120 120 + 28) Circle Pts/Rev 6 6 6 + 32) Conical Az Clamp 8.00 8.00 8.00 + 33) Conical El Clamp 8.00 8.00 8.00 + 35) Motor Pts/Rev 72 72 72 + 36) Circle Az Radius 1.00 1.00 1.00 + 37) Circle El Radius 1.00 1.00 1.00 + 38) Sleep Mode Timer Secs 420 420 420 + 40) Motor Type 0 0 0 + 41) Satellite Scan Velocity 55.00 55.00 55.00 + 48) Motor Spiral Velocity 55.00 55.00 55.00 + 49) Motor Gear Ratio 0x00000000 0x00000000 0x00000000 + 63) GPS Heading Threshold 1.00 1.00 1.00 + 64) GPS Moving Threshold 5.00 MPH 5.00 MPH 5.00 MPH + 66) Spiral Signal In A Row Min +3 +3 +3 + 67) Spiral Signal In A Row Max +20 +20 +20 + 68) Signal Odd to Even Offset +0 +0 +0 + 69) Signal Offset 80 80 80 + 70) Signal Baseline Angle 65.00 65.00 65.00 + 71) Signal Re-Peak Degrade Percent 25 25 25 + 72) Gyro Sensitivity +1110 +1110 +1110 + 73) Gyro Filter Size +1 +1 +1 + 74) Gyro Calib Readings 100 100 100 + 75) Gyro Mount Type 1 1 1 + 76) Gyro Velocity Offset 4 4 4 + 77) Gyro Max Accel 600 600 600 + 80) AZ Max Vel 65.00 65.00 65.00 + 81) AZ Max Accel 400.00 400.00 400.00 + 82) AZ Home Velocity 55.00 55.00 55.00 + 83) AZ Steps/Rev 40000 40000 40000 + 84) AZ Direction +1 +1 +1 + 85) EL Max Vel 45.00 45.00 45.00 + 86) EL Max Accel 400.00 400.00 400.00 + 87) EL Home Velocity 45.00 45.00 45.00 + 88) EL Steps/Rev 24960 24960 24960 + 89) EL Direction +1 +1 +1 + 95) AZ Low current limit 0x0000ff0c 0x0000ff0c 0x0000ff0c + 96) AZ High current limit 0x0000ff30 0x0000ff30 0x0000ff30 + 97) EL Low current limit 0x0000ff0c 0x0000ff0c 0x0000ff0c + 98) EL High current limit 0x0000ff40 0x0000ff40 0x0000ff40 +101) Minimum Elevation Angle 18.00 18.00 18.00 +102) Maximum Elevation Angle 65.00 65.00 65.00 +103) Elevation Home Angle 65.00 65.00 65.00 +106) Az Stall Detect 78 78 78 +107) El Stall Detect 75 75 75 +108) Az Stall Samples 100 100 100 +109) El Stall Samples 100 100 100 +110) EL Home Current Limit 0x0000ff28 0x0000ff28 0x0000ff28 +111) AZ Home Current Limit 0x0000ff40 0x0000ff40 0x0000ff40 +112) Disable Dipswitch? FALSE FALSE FALSE +113) Dipswitch Value 101 101 101 +114) Dipswitch Front/Rear Mount 0 0 0 +115) Mount Offset Angle +0 +0 +0 +118) Signal Use LNB Clamp FALSE FALSE FALSE +128) AZ PID Kp +600 +600 +600 +129) AZ PID Kv +60 +60 +60 +130) AZ PID Ki +1 +1 +1 +131) EL PID Kp +250 +250 +250 +132) EL PID Kv +50 +50 +50 +133) EL PID Ki +1 +1 +1 +136) AZ PWM Stall Cnt 6 6 6 +137) EL PWM Stall Cnt 5 5 5 +143) Tracking Number 0 0 0""" + +# Parse NVS lines into a dict keyed by index for nvs_read(). +_NVS_LINES: dict[int, str] = {} +for _line in _NVS_DUMP_TEXT.splitlines(): + _line_stripped = _line.strip() + if _line_stripped and _line_stripped[0].isdigit(): + _idx_str = _line_stripped.split(")")[0].strip() + with contextlib.suppress(ValueError): + _NVS_LINES[int(_idx_str)] = _line_stripped + +# Firmware identification text matching ``os > id`` output. +_FIRMWARE_ID = """\ +NVS Version: 1.02.13 +System ID: TWELINCH + K60-144pin + Silicon Rev 2.4 + Mask Set 4N22D + 512 kBytes of P-flash + P-flash only + 128 kBytes of RAM + Board Rev ID: A + Board ID: STATIONARY + Ant ID: 12-IN G2 + Software version: 02.02.48 + CCLK: 96000000 + BCLK: 48000000 + Flash Base Address: 65536 + Flash Size: 458752""" + +_DVB_CONFIG = """\ +BCM Hardware= ID: 0x4515 VER: 0xB0 +BCM Firmware= MAJOR VER: 0x71 (113) MINOR VER: 0x25 (37) +BCM Strap Config: 0x25018""" + +_CHANNEL_PARAMS = """\ +Power Mode: ON +Search Transponders: ON +Auto Search Mode: 1 +Shuffle Mode: ON +Frequency List: Non-Stacked + +Num Parameter Current Default +1 Frequency 1090640 (kHz) 974000 (kHz) +2 Symbol Rate 0 (PeakScanEnabled) 20000 (ksps) +3 Trans_Mod_CRate blind_scan blind_scan +4 Blind Scan Mode ___trb_dvb_dss_____ ___trb_dvb_dss_____ +5 LNB Polarity ODU:13V --- +6 LNB Tone (ODU) off off +7 Roll-off 0.35 0.35 +8 LPF Cutoff 0 (auto) 0 (MHz) +9 Carrier Offset 0 (kHz) 0 (kHz) +10 FreqSearchRange 5000 (kHz) 5000 (kHz) +11 DCII Mode dcii_qpsk_comb dcii_qpsk_comb +12 Spectral Inv scan scan +13 PScnSymRtRngMin 18000 (ksps) 18000 (ksps) +14 PScnSymRtRngMax 24000 (ksps) 24000 (ksps) +15 SignalDetectMode off off""" + +_MOTOR_LIFE = """\ +AZ total moves: 847 +AZ total degrees: 52340.50 +EL total moves: 423 +EL total degrees: 18920.75 +Uptime hours: 312.4""" + +# Simulated satellite at AZ=200, EL=38 for RSSI modeling. +_SAT_AZ = 200.0 +_SAT_EL = 38.0 +_RSSI_NOISE_FLOOR = 500 +_RSSI_PEAK = 2000 +_RSSI_BEAM_WIDTH = 50.0 # Gaussian denominator (degrees squared) + +# Motor simulation speed (degrees per second). +_MOTOR_SPEED = 10.0 + + +class DemoDevice: + """Synthetic demo device implementing the same interface as SerialBridge. + + Simulates a Carryout G2 dish with motor movement, RSSI signal modeling, + and canned firmware responses. No serial hardware required. + """ + + def __init__(self) -> None: + self._connected = False + self._engaged = True + + # Current position and movement targets. + self._az = 180.0 + self._el = 45.0 + self._target_az = 180.0 + self._target_el = 45.0 + self._last_move_time = time.monotonic() + + # Submenu tracking for console simulation. + self._menu = _DemoMenu.ROOT + + # ------------------------------------------------------------------ + # Internal helpers + # ------------------------------------------------------------------ + + def _update_position(self) -> None: + """Interpolate position toward target at ~10 deg/s.""" + now = time.monotonic() + dt = now - self._last_move_time + self._last_move_time = now + + max_step = _MOTOR_SPEED * dt + + for axis in ("az", "el"): + current = getattr(self, f"_{axis}") + target = getattr(self, f"_target_{axis}") + delta = target - current + + if abs(delta) < 0.001: + continue + + if abs(delta) <= max_step: + # Arrived — add a tiny settling noise. + noise = random.gauss(0.0, 0.02) + setattr(self, f"_{axis}", target + noise) + else: + direction = 1.0 if delta > 0 else -1.0 + noise = random.gauss(0.0, 0.02) + setattr(self, f"_{axis}", current + direction * max_step + noise) + + def _compute_rssi(self) -> float: + """Gaussian signal model centered on the simulated satellite.""" + self._update_position() + dist_sq = (self._az - _SAT_AZ) ** 2 + (self._el - _SAT_EL) ** 2 + signal = _RSSI_PEAK * math.exp(-dist_sq / _RSSI_BEAM_WIDTH) + drift = math.sin(time.monotonic() / 60.0) * 50.0 + return _RSSI_NOISE_FLOOR + signal + drift + + @property + def _is_moving(self) -> bool: + return ( + abs(self._az - self._target_az) > 0.05 + or abs(self._el - self._target_el) > 0.05 + ) + + # ------------------------------------------------------------------ + # Connection + # ------------------------------------------------------------------ + + def connect(self, port: str = "/dev/demo", baudrate: int = 115200) -> None: + self._connected = True + self._menu = _DemoMenu.ROOT + + def disconnect(self) -> None: + self._connected = False + self._menu = _DemoMenu.ROOT + + @property + def is_connected(self) -> bool: + return self._connected + + def initialize(self, skip_init: bool = False) -> None: + self._connected = True + self._menu = _DemoMenu.MOT + + # ------------------------------------------------------------------ + # Motor (MOT>) + # ------------------------------------------------------------------ + + def get_position(self) -> dict[str, float]: + self._update_position() + return { + "azimuth": round(self._az, 2), + "elevation": round(self._el, 2), + } + + def move_to(self, az: float, el: float) -> None: + self._target_az = az + self._target_el = el + self._last_move_time = time.monotonic() + + def move_motor(self, motor_id: int, degrees: float) -> None: + if motor_id == 0: + self._target_az = degrees + elif motor_id == 1: + self._target_el = degrees + self._last_move_time = time.monotonic() + + def home_motor(self, motor_id: int) -> None: + if motor_id == 0: + self._target_az = 0.0 + elif motor_id == 1: + self._target_el = 65.0 + self._last_move_time = time.monotonic() + + def engage(self) -> None: + self._engaged = True + + def release(self) -> None: + self._engaged = False + + def get_motor_list(self) -> str: + return "Motors:\n 0 - AZIMUTH: local\n 1 - ELEVATION: local" + + def get_motor_dynamics(self) -> dict[str, float]: + return { + "az_max_vel": 65.0, + "el_max_vel": 45.0, + "az_accel": 400.0, + "el_accel": 400.0, + } + + def get_motor_life(self) -> str: + return _MOTOR_LIFE + + def get_el_limits(self) -> dict[str, float]: + return {"min": 18.0, "max": 65.0, "home": 65.0} + + def get_step_positions(self) -> dict[str, int]: + self._update_position() + return { + "az_steps": int(self._az * 40000 / 360), + "el_steps": int(self._el * 24960 / 360), + } + + # ------------------------------------------------------------------ + # Signal (DVB>) + # ------------------------------------------------------------------ + + def get_rssi(self, iterations: int = 10) -> dict[str, int]: + rssi = self._compute_rssi() + noise = random.gauss(0.0, 30.0) + return { + "reads": iterations, + "average": int(rssi), + "current": int(rssi + noise), + } + + def enable_lna(self) -> None: + pass # No-op in demo mode. + + def get_lock_status(self) -> str: + rssi = int(self._compute_rssi()) + locked = 1 if rssi > 1500 else 0 + return f"Lock:{locked} rssi:{rssi} cnt:0" + + def get_dvb_config(self) -> str: + return _DVB_CONFIG + + def get_channel_params(self) -> str: + return _CHANNEL_PARAMS + + # ------------------------------------------------------------------ + # A3981 + # ------------------------------------------------------------------ + + def get_a3981_diag(self) -> str: + return "AZ DIAG: OK\nEL DIAG: OK" + + def get_a3981_modes(self) -> dict[str, str]: + return { + "step_mode": "AZ Step Size Mode = AUTO\nEL Step Size Mode = AUTO", + "current_mode": "AZ: Mode = AUTO\nEL: Mode = AUTO", + "step_size": ( + "KEY: FULL-16, HALF-8, QTR-4, EIGHTH-2, SIXTEENTH-1\n" + "AZ Step Size:1\n" + "EL Step Size:1" + ), + } + + def get_a3981_torque(self) -> str: + if self._is_moving: + return "AZ Torq:HIGH\nEL Torq:HIGH" + return "AZ Torq:LOW\nEL Torq:LOW" + + # ------------------------------------------------------------------ + # NVS + # ------------------------------------------------------------------ + + def nvs_dump(self) -> str: + return _NVS_DUMP_TEXT + + def nvs_read(self, index: int) -> str: + line = _NVS_LINES.get(index) + if line: + return line + return f"NVS index {index} not found" + + # ------------------------------------------------------------------ + # ADC + # ------------------------------------------------------------------ + + def get_adc_rssi(self) -> str: + rssi = self._compute_rssi() + return str(int(rssi)) + + def get_board_id(self) -> str: + return "STATIONARY" + + # ------------------------------------------------------------------ + # OS + # ------------------------------------------------------------------ + + def get_firmware_id(self) -> str: + return _FIRMWARE_ID + + # ------------------------------------------------------------------ + # Raw / Console + # ------------------------------------------------------------------ + + def send_raw(self, cmd: str) -> str: + """Simulate firmware console with basic submenu tracking.""" + cmd_stripped = cmd.strip().lower() + + # Submenu navigation. + if cmd_stripped == "q": + self._menu = _DemoMenu.ROOT + return "TRK>" + + _enter_map: dict[str, _DemoMenu] = { + "mot": _DemoMenu.MOT, + "dvb": _DemoMenu.DVB, + "nvs": _DemoMenu.NVS, + "a3981": _DemoMenu.A3981, + "adc": _DemoMenu.ADC, + "os": _DemoMenu.OS, + "step": _DemoMenu.STEP, + "peak": _DemoMenu.PEAK, + "eeprom": _DemoMenu.EEPROM, + "gpio": _DemoMenu.GPIO, + "latlon": _DemoMenu.LATLON, + "dipswitch": _DemoMenu.DIPSWITCH, + } + + if cmd_stripped in _enter_map and self._menu == _DemoMenu.ROOT: + self._menu = _enter_map[cmd_stripped] + prompt = cmd_stripped.upper() + ">" + return prompt + + # Context-dependent responses. + if self._menu == _DemoMenu.MOT: + return self._handle_mot(cmd_stripped) + if self._menu == _DemoMenu.DVB: + return self._handle_dvb(cmd_stripped) + if self._menu == _DemoMenu.NVS: + return self._handle_nvs(cmd_stripped) + if self._menu == _DemoMenu.A3981: + return self._handle_a3981(cmd_stripped) + if self._menu == _DemoMenu.ADC: + return self._handle_adc(cmd_stripped) + if self._menu == _DemoMenu.OS: + return self._handle_os(cmd_stripped) + if self._menu == _DemoMenu.ROOT: + return self._handle_root(cmd_stripped) + + return f"Unknown command: {cmd}\nTRK>" + + def _handle_root(self, cmd: str) -> str: + if cmd in ("?", "help"): + return ( + "Available commands:\n" + " a3981 adc dipswitch dvb eeprom gpio\n" + " latlon mot nvs os peak step\n" + " q reboot stow\n" + "TRK>" + ) + if cmd == "reboot": + return "Rebooting...\nApplication Starting Kinetis PCB...\nTRK>" + return f"Unknown command: {cmd}\nTRK>" + + def _handle_mot(self, cmd: str) -> str: + if cmd in ("?", "help"): + return ( + "Available commands:\n" + " a azscan azscanwxp e ela2s elminmaxhome\n" + " els2a g h l life ma motorboth motorlife\n" + " mv p pid r sd sp sw v vms w\n" + "MOT>" + ) + if cmd == "a": + self._update_position() + return f" Angle[0] = {self._az:.2f}\n Angle[1] = {self._el:.2f}\nMOT>" + if cmd == "l": + return "Motors:\n 0 - AZIMUTH: local\n 1 - ELEVATION: local\nMOT>" + if cmd == "e": + self._engaged = True + return "Motors engaged\nMOT>" + if cmd == "r": + self._engaged = False + return "Motors released\nMOT>" + if cmd == "elminmaxhome": + return "Min: 1800 Max: 6500 Home: 6500\nMOT>" + if cmd == "life": + return _MOTOR_LIFE + "\nMOT>" + if cmd.startswith("a "): + parts = cmd.split() + if len(parts) >= 3: + motor_id = int(parts[1]) + degrees = float(parts[2]) + if motor_id == 0: + self._target_az = degrees + elif motor_id == 1: + self._target_el = degrees + self._last_move_time = time.monotonic() + return f" Angle = {degrees:.2f}\nMOT>" + return "Invalid parameters\nMOT>" + if cmd.startswith("h "): + parts = cmd.split() + if len(parts) >= 2: + motor_id = int(parts[1]) + self.home_motor(motor_id) + return f"Homing motor {motor_id}\nMOT>" + return "Invalid parameters\nMOT>" + if cmd == "mv": + return "Max Vel [0] = 65.0 Max Vel [1] = 45.0\nMOT>" + if cmd == "ma": + return "Accel[0] = 400.0 Accel[1] = 400.0\nMOT>" + if cmd == "p": + self._update_position() + az_steps = int(self._az * 40000 / 360) + el_steps = int(self._el * 24960 / 360) + return f"Position[0] = {az_steps} Position[1] = {el_steps}\nMOT>" + return f"Unknown command: {cmd}\nMOT>" + + def _handle_dvb(self, cmd: str) -> str: + if cmd in ("?", "help"): + return ( + "Available commands:\n" + " agc config def diag dis e freqs\n" + " lnbdc lnbv ls man msw nid pwr\n" + " qls range rssi shuf snr srch srch_mode\n" + " stats t table tablex tabto to\n" + "DVB>" + ) + if cmd.startswith("rssi"): + rssi_val = int(self._compute_rssi()) + parts = cmd.split() + iters = int(parts[1]) if len(parts) > 1 else 10 + noise = random.gauss(0.0, 30.0) + cur = int(rssi_val + noise) + return ( + f"iterations:{iters} interval(msec):20\n" + f" Reads:{iters} RSSI[avg: {rssi_val} cur: {cur}]\n" + "DVB>" + ) + if cmd == "config": + return _DVB_CONFIG + "\nDVB>" + if cmd == "dis": + return _CHANNEL_PARAMS + "\nDVB>" + if cmd == "lnbdc odu": + return "Enabled LNB ODU 13V\nDVB>" + if cmd == "qls": + rssi_val = int(self._compute_rssi()) + locked = 1 if rssi_val > 1500 else 0 + return f"Lock:{locked} rssi:{rssi_val} cnt:0\nDVB>" + return f"Unknown command: {cmd}\nDVB>" + + def _handle_nvs(self, cmd: str) -> str: + if cmd in ("?", "help"): + return "Available commands:\n d e s\nNVS>" + if cmd == "d": + return _NVS_DUMP_TEXT + "\nNVS>" + if cmd == "s": + return "NVS saved\nNVS>" + if cmd.startswith("e "): + parts = cmd.split() + if len(parts) >= 2: + try: + idx = int(parts[1]) + line = _NVS_LINES.get(idx) + if line: + return line + "\nNVS>" + return f"NVS index {idx} not found\nNVS>" + except ValueError: + pass + return "Invalid parameters\nNVS>" + return f"Unknown command: {cmd}\nNVS>" + + def _handle_a3981(self, cmd: str) -> str: + if cmd in ("?", "help"): + return "Available commands:\n cm diag reset sm ss st\nA3981>" + if cmd == "diag": + return "AZ DIAG: OK\nEL DIAG: OK\nA3981>" + if cmd == "sm": + return "AZ Step Size Mode = AUTO\nEL Step Size Mode = AUTO\nA3981>" + if cmd == "cm": + return "AZ: Mode = AUTO\nEL: Mode = AUTO\nA3981>" + if cmd == "ss": + return ( + "KEY: FULL-16, HALF-8, QTR-4, EIGHTH-2, SIXTEENTH-1\n" + "AZ Step Size:1\n" + "EL Step Size:1\n" + "A3981>" + ) + if cmd == "st": + if self._is_moving: + return "AZ Torq:HIGH\nEL Torq:HIGH\nA3981>" + return "AZ Torq:LOW\nEL Torq:LOW\nA3981>" + if cmd == "reset": + return "Az/El A3981 Faults Reset.\nA3981>" + return f"Unknown command: {cmd}\nA3981>" + + def _handle_adc(self, cmd: str) -> str: + if cmd in ("?", "help"): + return "Available commands:\n bdid bdrevid m rssi scan\nADC>" + if cmd == "rssi": + return str(int(self._compute_rssi())) + "\nADC>" + if cmd == "bdid": + return "STATIONARY\nADC>" + if cmd == "bdrevid": + return "A\nADC>" + return f"Unknown command: {cmd}\nADC>" + + def _handle_os(self, cmd: str) -> str: + if cmd in ("?", "help"): + return "Available commands:\n id reboot\nOS>" + if cmd == "id": + return _FIRMWARE_ID + "\nOS>" + if cmd == "reboot": + return "Rebooting...\nApplication Starting Kinetis PCB...\nTRK>" + return f"Unknown command: {cmd}\nOS>" diff --git a/tui/src/birdcage_tui/screens/__init__.py b/tui/src/birdcage_tui/screens/__init__.py new file mode 100644 index 0000000..5dd3480 --- /dev/null +++ b/tui/src/birdcage_tui/screens/__init__.py @@ -0,0 +1 @@ +"""TUI screen modules — one per F-key mode.""" diff --git a/tui/src/birdcage_tui/screens/console.py b/tui/src/birdcage_tui/screens/console.py new file mode 100644 index 0000000..2c1e22d --- /dev/null +++ b/tui/src/birdcage_tui/screens/console.py @@ -0,0 +1,232 @@ +"""F5 Console Screen -- raw serial terminal with color-coded prompts +and command history.""" + +import re + +from textual import work +from textual.app import ComposeResult +from textual.containers import Container, Horizontal +from textual.events import Key +from textual.widgets import Button, Input, Static + +from birdcage_tui.widgets.serial_log import SerialLog + +_KNOWN_PROMPTS = [ + "TRK>", + "MOT>", + "DVB>", + "NVS>", + "A3981>", + "ADC>", + "OS>", + "STEP>", + "PEAK>", + "EE>", + "GPIO>", + "LATLON>", + "DIPSWITCH>", +] + +# Pattern to detect NVS write commands: "nvs" ... "e " +# or just "e " when already in the NVS submenu. +_NVS_WRITE_RE = re.compile(r"e\s+\d+\s+\S+") + + +def _detect_prompt(text: str) -> str | None: + """Find the last known prompt in the response text.""" + last_prompt = None + last_pos = -1 + for prompt in _KNOWN_PROMPTS: + pos = text.rfind(prompt) + if pos > last_pos: + last_pos = pos + last_prompt = prompt + return last_prompt + + +class ConsoleScreen(Container): + """F5: Raw serial console for direct firmware interaction.""" + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._device: object | None = None + self._command_history: list[str] = [] + self._history_idx: int = 0 + self._cmd_count: int = 0 + self._prompt_ctx: str = "TRK>" + self._last_dangerous_cmd: str | None = None + + def compose(self) -> ComposeResult: + with Container(classes="screen-container"): + yield SerialLog(id="serial-log") + with Horizontal(classes="console-context"): + yield Static("Context: TRK>", id="console-context") + yield Static(" Commands: 0", id="console-cmd-count") + with Horizontal(classes="console-input-area"): + yield Static("> ", classes="label") + yield Input(placeholder="Enter command...", id="console-input") + yield Button("Send", id="btn-send", variant="primary") + + def set_device(self, device: object) -> None: + """Store the device reference and show a welcome message.""" + self._device = device + + serial_log = self.query_one("#serial-log", SerialLog) + + # Determine connection description. + if hasattr(device, "demo_mode") or type(device).__name__ == "DemoDevice": + mode_label = "DEMO" + else: + mode_label = getattr(device, "firmware_name", "Live") + + port = getattr(self.app, "serial_port", "/dev/ttyUSB0") if self.app else "---" + + serial_log.append_output("Birdcage Console -- type ? for help") + serial_log.append_output(f"Connected to: {mode_label} / {port}") + + def _check_dangerous(self, cmd: str) -> str | None: + """Return a warning message if the command is dangerous, or None if safe. + + If the same dangerous command is sent twice in a row, allow it through + (the user is insisting). + """ + stripped = cmd.strip() + lower = stripped.lower() + + # Same dangerous command repeated -- user is insisting. + is_repeat = ( + self._last_dangerous_cmd is not None + and stripped == self._last_dangerous_cmd + ) + if is_repeat: + self._last_dangerous_cmd = None + return None + + warning = None + + if lower == "q" and self._prompt_ctx == "TRK>": + warning = ( + "Warning: 'q' at root kills the shell! " + "Use submenu-level 'q' to exit submenus." + ) + elif lower == "reboot": + warning = "Warning: 'reboot' will restart the dish firmware." + elif _NVS_WRITE_RE.search(lower): + warning = "Warning: NVS write detected. Are you sure?" + + if warning is not None: + self._last_dangerous_cmd = stripped + else: + self._last_dangerous_cmd = None + + return warning + + def _do_send(self, cmd_text: str) -> None: + """Validate and dispatch a command. Called on Enter or Send button.""" + cmd_text = cmd_text.strip() + if not cmd_text: + return + + # Safety gate. + warning = self._check_dangerous(cmd_text) + if warning is not None: + self.notify(warning, severity="warning", timeout=5) + return + + # Record in history. + self._command_history.append(cmd_text) + self._history_idx = len(self._command_history) + + # Show the command in the log immediately. + serial_log = self.query_one("#serial-log", SerialLog) + serial_log.append_command(cmd_text) + + # Clear input right away so the user can type while waiting. + self.query_one("#console-input", Input).value = "" + + # Dispatch to worker thread (serial I/O blocks). + self._send_command(cmd_text) + + @work(thread=True) + def _send_command(self, cmd: str) -> None: + """Send the command over serial and update the UI with the response.""" + if self._device is None: + self.app.call_from_thread( + self.notify, "No device connected", severity="error" + ) + return + + try: + response = self._device.send_raw(cmd) + except Exception as exc: + self.app.call_from_thread(self._on_response, f"ERROR: {exc}", cmd) + return + + self.app.call_from_thread(self._on_response, response, cmd) + + def _on_response(self, response: str, cmd: str) -> None: + """Process the firmware response on the main thread.""" + serial_log = self.query_one("#serial-log", SerialLog) + serial_log.append_output(response) + + # Detect prompt context from the response. + detected = _detect_prompt(response) + if detected is not None: + self._prompt_ctx = detected + ctx_label = self.query_one("#console-context", Static) + ctx_label.update(f"Context: {self._prompt_ctx}") + + # Update command count. + self._cmd_count += 1 + count_label = self.query_one("#console-cmd-count", Static) + count_label.update(f" Commands: {self._cmd_count}") + + # ------------------------------------------------------------------ + # Event handlers + # ------------------------------------------------------------------ + + def on_input_submitted(self, event: Input.Submitted) -> None: + """Handle Enter key in the command input.""" + if event.input.id == "console-input": + self._do_send(event.value) + + def on_button_pressed(self, event: Button.Pressed) -> None: + """Handle the Send button click.""" + if event.button.id == "btn-send": + cmd_input = self.query_one("#console-input", Input) + self._do_send(cmd_input.value) + + def on_key(self, event: Key) -> None: + """Handle up/down arrow keys for command history navigation.""" + cmd_input = self.query_one("#console-input", Input) + + # Only respond when the input widget has focus. + if not cmd_input.has_focus: + return + + if event.key == "up": + event.prevent_default() + event.stop() + if not self._command_history: + return + self._history_idx = max(0, self._history_idx - 1) + cmd_input.value = self._command_history[self._history_idx] + cmd_input.cursor_position = len(cmd_input.value) + + elif event.key == "down": + event.prevent_default() + event.stop() + if not self._command_history: + return + self._history_idx = min(len(self._command_history), self._history_idx + 1) + if self._history_idx >= len(self._command_history): + cmd_input.value = "" + else: + cmd_input.value = self._command_history[self._history_idx] + cmd_input.cursor_position = len(cmd_input.value) + + elif event.key == "ctrl+l": + event.prevent_default() + event.stop() + serial_log = self.query_one("#serial-log", SerialLog) + serial_log.clear() diff --git a/tui/src/birdcage_tui/screens/position.py b/tui/src/birdcage_tui/screens/position.py new file mode 100644 index 0000000..da348c2 --- /dev/null +++ b/tui/src/birdcage_tui/screens/position.py @@ -0,0 +1,282 @@ +"""F1 Position screen -- AZ/EL display, manual moves, homing, engage/release. + +Widget container for ContentSwitcher. Polls the device at 2 Hz for +position and step data, drives the compass rose, motor status panel, +and AZ/EL sparklines. Bottom row provides manual move controls. +""" + +import logging +import time + +from textual import work +from textual.app import ComposeResult +from textual.binding import Binding +from textual.containers import Container, Horizontal, Vertical +from textual.widgets import Button, Input, Static +from textual.worker import Worker + +from birdcage_tui.widgets.compass_rose import CompassRose +from birdcage_tui.widgets.motor_status import MotorStatus +from birdcage_tui.widgets.sparkline_widget import SparklineWidget + +log = logging.getLogger(__name__) + + +class PositionScreen(Container): + """F1: Position control and monitoring.""" + + can_focus = True + + BINDINGS = [ + Binding("left", "nudge_az(-1)", "AZ -1", show=False), + Binding("right", "nudge_az(1)", "AZ +1", show=False), + Binding("up", "nudge_el(1)", "EL +1", show=False), + Binding("down", "nudge_el(-1)", "EL -1", show=False), + Binding("h", "home_both", "Home Both", show=False), + Binding("e", "engage_motors", "Engage", show=False), + Binding("r", "release_motors", "Release", show=False), + ] + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._device: object = None + self._polling = False + self._engaged = False + self._poll_worker: Worker | None = None + # Track last-known position for nudge commands. + self._last_az = 180.0 + self._last_el = 45.0 + + def compose(self) -> ComposeResult: + with Container(classes="screen-container"): + with Horizontal(classes="top-row"): + yield CompassRose(id="compass") + with Vertical(classes="panel"): + yield Static("Motor Status", classes="panel-title") + yield MotorStatus(id="motor-status") + with Vertical(): + yield SparklineWidget( + max_points=80, label="AZ", color="#00d4aa", id="az-spark" + ) + yield SparklineWidget( + max_points=80, label="EL", color="#00b8c8", id="el-spark" + ) + with Horizontal(classes="bottom-controls"): + yield Static("AZ ", classes="label") + yield Input(placeholder="180.0", id="az-input", type="number") + yield Static(" EL ", classes="label") + yield Input(placeholder="45.0", id="el-input", type="number") + yield Button("Move", id="btn-move", variant="primary") + yield Button("Home AZ", id="btn-home-az") + yield Button("Home EL", id="btn-home-el") + yield Button("E/R", id="btn-engage") + + # ------------------------------------------------------------------ + # Device lifecycle + # ------------------------------------------------------------------ + + def set_device(self, device: object) -> None: + """Store the device reference and start position polling.""" + self._device = device + self._polling = True + self._poll_worker = self._do_position_poll() + + def on_show(self) -> None: + """Resume polling when this screen becomes visible.""" + if self._device is not None and not self._polling: + self._polling = True + self._poll_worker = self._do_position_poll() + + # ------------------------------------------------------------------ + # Position poll worker + # ------------------------------------------------------------------ + + @work(thread=True, exclusive=True, group="position-poll") + def _do_position_poll(self) -> None: + """Poll device at ~2 Hz for position and step data.""" + while self._polling: + if self._device is None: + time.sleep(0.5) + continue + + try: + pos = self._device.get_position() + az = pos["azimuth"] + el = pos["elevation"] + self._last_az = az + self._last_el = el + + self.app.call_from_thread(self._update_compass, az, el) + self.app.call_from_thread(self._push_sparklines, az, el) + except Exception: + log.debug("Position poll failed", exc_info=True) + + try: + steps = self._device.get_step_positions() + self.app.call_from_thread( + self._update_motor_steps, + steps["az_steps"], + steps["el_steps"], + ) + except Exception: + log.debug("Step position poll failed", exc_info=True) + + # Poll torque state from A3981 + try: + torque_resp = self._device.get_a3981_torque() + lines = torque_resp.split("\n") + az_torque = "HIGH" if "HIGH" in lines[0] else "LOW" + el_torque = "HIGH" if len(lines) > 1 and "HIGH" in lines[1] else "LOW" + self.app.call_from_thread(self._update_torque, az_torque, el_torque) + except Exception: + log.debug("Torque poll failed", exc_info=True) + + time.sleep(0.5) + + # ------------------------------------------------------------------ + # Thread-safe widget update callbacks + # ------------------------------------------------------------------ + + def _update_compass(self, az: float, el: float) -> None: + compass = self.query_one("#compass", CompassRose) + compass.azimuth = az + compass.elevation = el + + def _push_sparklines(self, az: float, el: float) -> None: + self.query_one("#az-spark", SparklineWidget).push(az) + self.query_one("#el-spark", SparklineWidget).push(el) + + def _update_motor_steps(self, az_steps: int, el_steps: int) -> None: + motor = self.query_one("#motor-status", MotorStatus) + motor.az_steps = az_steps + motor.el_steps = el_steps + + def _update_torque(self, az_torque: str, el_torque: str) -> None: + motor = self.query_one("#motor-status", MotorStatus) + motor.az_torque = az_torque + motor.el_torque = el_torque + + def _update_engaged(self, engaged: bool) -> None: + motor = self.query_one("#motor-status", MotorStatus) + motor.engaged = engaged + + # ------------------------------------------------------------------ + # Button handlers + # ------------------------------------------------------------------ + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + + if button_id == "btn-move": + self._handle_move() + elif button_id == "btn-home-az": + self._handle_home(0) + elif button_id == "btn-home-el": + self._handle_home(1) + elif button_id == "btn-engage": + self._handle_engage_toggle() + + def _handle_move(self) -> None: + """Read AZ/EL inputs and issue a move command.""" + if self._device is None: + return + + az_input = self.query_one("#az-input", Input) + el_input = self.query_one("#el-input", Input) + + try: + az = float(az_input.value) if az_input.value.strip() else self._last_az + except ValueError: + self.app.notify("Invalid AZ value", severity="warning") + return + + try: + el = float(el_input.value) if el_input.value.strip() else self._last_el + except ValueError: + self.app.notify("Invalid EL value", severity="warning") + return + + self._run_motor_command(self._device.move_to, az, el) + + def _handle_home(self, motor_id: int) -> None: + """Home a specific motor axis.""" + if self._device is None: + return + axis = "AZ" if motor_id == 0 else "EL" + self.app.notify(f"Homing {axis}...", severity="information") + self._run_motor_command(self._device.home_motor, motor_id) + + def _handle_engage_toggle(self) -> None: + """Toggle motor engage/release state.""" + if self._device is None: + return + + if self._engaged: + self._run_motor_command(self._device.release) + self._engaged = False + self._update_engaged(False) + self.app.notify("Motors released") + else: + self._run_motor_command(self._device.engage) + self._engaged = True + self._update_engaged(True) + self.app.notify("Motors engaged") + + # ------------------------------------------------------------------ + # Key binding actions + # ------------------------------------------------------------------ + + def action_nudge_az(self, delta: int) -> None: + """Nudge azimuth by delta degrees.""" + if self._device is None: + return + new_az = self._last_az + delta + self._run_motor_command(self._device.move_motor, 0, new_az) + + def action_nudge_el(self, delta: int) -> None: + """Nudge elevation by delta degrees.""" + if self._device is None: + return + new_el = self._last_el + delta + self._run_motor_command(self._device.move_motor, 1, new_el) + + def action_home_both(self) -> None: + """Home both AZ and EL motors.""" + if self._device is None: + return + self.app.notify("Homing AZ + EL...", severity="information") + self._run_motor_command(self._device.home_motor, 0) + self._run_motor_command(self._device.home_motor, 1) + + def action_engage_motors(self) -> None: + """Engage (energize) stepper motors.""" + if self._device is None: + return + self._run_motor_command(self._device.engage) + self._engaged = True + self._update_engaged(True) + self.app.notify("Motors engaged") + + def action_release_motors(self) -> None: + """Release (de-energize) stepper motors.""" + if self._device is None: + return + self._run_motor_command(self._device.release) + self._engaged = False + self._update_engaged(False) + self.app.notify("Motors released") + + # ------------------------------------------------------------------ + # Helpers + # ------------------------------------------------------------------ + + @work(thread=True, exclusive=False, group="motor-cmd") + def _run_motor_command(self, fn, *args) -> None: + """Execute a motor command in a worker thread.""" + try: + fn(*args) + except Exception: + log.exception("Motor command failed") + self.app.call_from_thread( + self.app.notify, "Motor command failed", severity="error" + ) diff --git a/tui/src/birdcage_tui/screens/scan.py b/tui/src/birdcage_tui/screens/scan.py new file mode 100644 index 0000000..a194196 --- /dev/null +++ b/tui/src/birdcage_tui/screens/scan.py @@ -0,0 +1,272 @@ +"""F3 Scan Screen -- AZ sweep heatmap, sky mapping with configurable parameters. + +Grid-based sky scan: iterates over AZ/EL range, moves the dish to each point, +reads RSSI, and paints the result into a 2D heatmap. Supports CSV export of +raw (az, el, rssi) data for offline analysis. +""" + +import csv +import logging +import time +from pathlib import Path + +from textual import work +from textual.containers import Container, Horizontal, Vertical +from textual.widgets import Button, Input, ProgressBar, Static +from textual.worker import get_current_worker + +from birdcage_tui.widgets.sky_heatmap import SkyHeatmap +from birdcage_tui.widgets.sparkline_widget import SparklineWidget + +log = logging.getLogger(__name__) + +# Type alias -- SerialBridge and DemoDevice share the same duck-typed interface. +DeviceLike = object + + +class ScanScreen(Container): + """F3: Sky scan and RF mapping.""" + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._device: DeviceLike | None = None + self._scanning = False + self._scan_data: list[tuple[float, float, float]] = [] + + def compose(self): + with Container(classes="screen-container"): + with Vertical(classes="panel"): + yield Static("Sky Scan", classes="panel-title") + yield SkyHeatmap(az_bins=40, el_bins=10, id="heatmap") + yield SparklineWidget( + max_points=80, label="Sweep RSSI", color="#00d4aa", id="sweep-spark" + ) + with Horizontal(classes="scan-status"): + yield Static("Idle", id="scan-status-text") + yield ProgressBar(id="scan-progress", total=100, show_eta=False) + with Horizontal(classes="bottom-controls"): + yield Static("AZ ", classes="label") + yield Input(value="160", id="az-start", type="number") + yield Static("-", classes="label") + yield Input(value="220", id="az-end", type="number") + yield Static(" Step ", classes="label") + yield Input(value="1.5", id="az-step", type="number") + yield Static(" EL ", classes="label") + yield Input(value="18", id="el-start", type="number") + yield Static("-", classes="label") + yield Input(value="65", id="el-end", type="number") + yield Static(" Step ", classes="label") + yield Input(value="5.0", id="el-step", type="number") + with Horizontal(classes="bottom-controls"): + yield Static("Transponders ", classes="label") + yield Input(value="3", id="xponder-input", type="integer") + yield Button("Start Scan", id="btn-start-scan", variant="primary") + yield Button("Stop", id="btn-stop-scan") + yield Button("Export CSV", id="btn-export") + + # ------------------------------------------------------------------ + # Device wiring + # ------------------------------------------------------------------ + + def set_device(self, device: DeviceLike) -> None: + """Store the device reference (SerialBridge or DemoDevice).""" + self._device = device + + # ------------------------------------------------------------------ + # Input helpers + # ------------------------------------------------------------------ + + def _read_float(self, widget_id: str, fallback: float) -> float: + """Read a float from an Input widget, returning *fallback* on parse error.""" + try: + return float(self.query_one(f"#{widget_id}", Input).value) + except (ValueError, TypeError): + return fallback + + def _read_int(self, widget_id: str, fallback: int) -> int: + """Read an int from an Input widget, returning *fallback* on parse error.""" + try: + return int(self.query_one(f"#{widget_id}", Input).value) + except (ValueError, TypeError): + return fallback + + # ------------------------------------------------------------------ + # Scan worker + # ------------------------------------------------------------------ + + @work(thread=True) + def _do_scan(self) -> None: + """Execute the AZ/EL grid scan in a background thread.""" + worker = get_current_worker() + device = self._device + if device is None: + return + + # Read scan parameters (widget access must happen via call_from_thread + # for Input.value, but Textual Input.value is a reactive that is safe + # to read from threads as a string snapshot). + az_start = self._read_float("az-start", 160.0) + az_end = self._read_float("az-end", 220.0) + az_step = self._read_float("az-step", 1.5) + el_start = self._read_float("el-start", 18.0) + el_end = self._read_float("el-end", 65.0) + el_step = self._read_float("el-step", 5.0) + iterations = self._read_int("xponder-input", 3) + + # Clamp step sizes to something sane. + if az_step <= 0: + az_step = 1.0 + if el_step <= 0: + el_step = 1.0 + + # Build the grid point list. + el_values: list[float] = [] + el = el_start + while el <= el_end + 1e-9: + el_values.append(round(el, 2)) + el += el_step + + az_values: list[float] = [] + az = az_start + while az <= az_end + 1e-9: + az_values.append(round(az, 2)) + az += az_step + + total_points = len(el_values) * len(az_values) + if total_points == 0: + self.app.call_from_thread( + self._set_status, "No grid points -- check parameters" + ) + return + + heatmap = self.query_one("#heatmap", SkyHeatmap) + spark = self.query_one("#sweep-spark", SparklineWidget) + + done = 0 + + for _el_idx, el_val in enumerate(el_values): + for _az_idx, az_val in enumerate(az_values): + if not self._scanning or worker.is_cancelled: + self.app.call_from_thread(self._set_status, "Scan stopped") + return + + # Move dish. + try: + device.move_to(az_val, el_val) + except Exception: + log.exception("move_to failed at AZ=%.2f EL=%.2f", az_val, el_val) + msg = f"Move error at AZ={az_val:.1f} EL={el_val:.1f}" + self.app.call_from_thread(self._set_status, msg) + continue + + # Settle time -- let the motor stop and vibrations damp. + time.sleep(0.3) + + # Read signal. + try: + rssi_data = device.get_rssi(iterations) + rssi = float(rssi_data.get("average", 0)) + except Exception: + log.exception("get_rssi failed at AZ=%.2f EL=%.2f", az_val, el_val) + rssi = 0.0 + + # Record raw data. + self._scan_data.append((az_val, el_val, rssi)) + + # Map to heatmap grid indices -- fit into fixed-size bins. + az_span = az_end - az_start + 1e-9 + el_span = el_end - el_start + 1e-9 + grid_az = min( + int((az_val - az_start) / az_span * heatmap.az_bins), + heatmap.az_bins - 1, + ) + grid_el = min( + int((el_val - el_start) / el_span * heatmap.el_bins), + heatmap.el_bins - 1, + ) + + # Update widgets. + self.app.call_from_thread(heatmap.set_point, grid_az, grid_el, rssi) + self.app.call_from_thread(heatmap.set_active, grid_az, grid_el) + self.app.call_from_thread(spark.push, rssi) + + done += 1 + pct = int(done * 100 / total_points) + status_text = ( + f"Scanning AZ={az_val:.1f} EL={el_val:.1f} " + f"RSSI={rssi:.0f} [{done}/{total_points}]" + ) + self.app.call_from_thread(self._set_progress, pct, status_text) + + msg = f"Scan complete -- {total_points} points" + self.app.call_from_thread(self._set_status, msg) + + # ------------------------------------------------------------------ + # Widget update helpers (called via call_from_thread) + # ------------------------------------------------------------------ + + def _set_status(self, text: str) -> None: + """Update the scan status text label.""" + self.query_one("#scan-status-text", Static).update(text) + + def _set_progress(self, pct: int, status_text: str) -> None: + """Update both progress bar and status text.""" + self.query_one("#scan-progress", ProgressBar).update(progress=pct) + self.query_one("#scan-status-text", Static).update(status_text) + + # ------------------------------------------------------------------ + # Button handlers + # ------------------------------------------------------------------ + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + + if button_id == "btn-start-scan": + self._start_scan() + elif button_id == "btn-stop-scan": + self._stop_scan() + elif button_id == "btn-export": + self._export_csv() + + def _start_scan(self) -> None: + """Clear state and kick off the scan worker.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + + if self._scanning: + self.app.notify("Scan already in progress", severity="warning") + return + + # Reset. + heatmap = self.query_one("#heatmap", SkyHeatmap) + heatmap.clear() + self._scan_data.clear() + self.query_one("#scan-progress", ProgressBar).update(progress=0) + self._set_status("Starting scan...") + + self._scanning = True + self._do_scan() + + def _stop_scan(self) -> None: + """Signal the scan worker to stop.""" + self._scanning = False + self._set_status("Stopping...") + + def _export_csv(self) -> None: + """Write scan data to /tmp/birdcage_scan.csv.""" + if not self._scan_data: + self.app.notify("No scan data to export", severity="warning") + return + + output = Path("/tmp/birdcage_scan.csv") + try: + with output.open("w", newline="") as fh: + writer = csv.writer(fh) + writer.writerow(["az", "el", "rssi"]) + for az, el, rssi in self._scan_data: + writer.writerow([f"{az:.2f}", f"{el:.2f}", f"{rssi:.1f}"]) + self.app.notify(f"Exported {len(self._scan_data)} points to {output}") + except OSError as exc: + log.exception("CSV export failed") + self.app.notify(f"Export failed: {exc}", severity="error") diff --git a/tui/src/birdcage_tui/screens/signal.py b/tui/src/birdcage_tui/screens/signal.py new file mode 100644 index 0000000..0903c0a --- /dev/null +++ b/tui/src/birdcage_tui/screens/signal.py @@ -0,0 +1,233 @@ +"""F2 Signal screen -- RSSI monitoring, sparklines, LNB control. + +Widget container for ContentSwitcher. Provides start/stop signal +monitoring with configurable iteration count and poll rate, dual +sparklines for DVB and ADC RSSI, peak tracking, and LNA toggle. +""" + +import logging +import re +import time + +from textual import work +from textual.app import ComposeResult +from textual.containers import Container, Horizontal, Vertical +from textual.widgets import Button, Input, Static +from textual.worker import Worker + +from birdcage_tui.widgets.signal_gauge import SignalGauge +from birdcage_tui.widgets.sparkline_widget import SparklineWidget + +log = logging.getLogger(__name__) + + +class SignalScreen(Container): + """F2: Signal monitoring and RSSI display.""" + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._device: object = None + self._monitoring = False + self._lna_enabled = False + self._peak_rssi = 0 + self._total_samples = 0 + self._signal_worker: Worker | None = None + + def compose(self) -> ComposeResult: + with Container(classes="screen-container"): + with Vertical(classes="panel"): + yield Static("Signal Strength", classes="panel-title") + yield SignalGauge(id="signal-gauge") + with Vertical(): + yield SparklineWidget( + max_points=80, label="DVB RSSI", color="#00d4aa", id="dvb-spark" + ) + yield SparklineWidget( + max_points=80, label="ADC RSSI", color="#2080d0", id="adc-spark" + ) + with Horizontal(classes="panel"): + yield Static("Samples: 0", id="sample-count", classes="label") + yield Static(" Peak: 0", id="peak-value", classes="label") + yield Static(" LNA: OFF", id="lna-status", classes="label") + yield Static(" Lock: NO", id="lock-status", classes="label") + with Horizontal(classes="bottom-controls"): + yield Static("Iters ", classes="label") + yield Input(value="10", id="iter-input", type="integer") + yield Static(" Rate ", classes="label") + yield Input(value="2", id="rate-input", type="integer") + yield Button("Start", id="btn-start", variant="primary") + yield Button("Stop", id="btn-stop") + yield Button("Enable LNA", id="btn-lna") + + # ------------------------------------------------------------------ + # Device lifecycle + # ------------------------------------------------------------------ + + def set_device(self, device: object) -> None: + """Store the device reference.""" + self._device = device + + def on_show(self) -> None: + """Called when this screen becomes visible.""" + pass # Monitoring is explicit via Start/Stop buttons. + + # ------------------------------------------------------------------ + # Signal poll worker + # ------------------------------------------------------------------ + + @work(thread=True, exclusive=True, group="signal-poll") + def _do_signal_poll(self) -> None: + """Poll RSSI at the configured rate while monitoring is active.""" + while self._monitoring: + if self._device is None: + time.sleep(0.5) + continue + + # Read config from inputs (safe defaults on parse failure). + try: + iterations = int( + self.app.call_from_thread(self._read_input, "iter-input") or "10" + ) + iterations = max(1, iterations) + except (ValueError, TypeError): + iterations = 10 + + try: + rate = int( + self.app.call_from_thread(self._read_input, "rate-input") or "2" + ) + rate = max(1, rate) + except (ValueError, TypeError): + rate = 2 + + # DVB RSSI (bounded, averaged) + try: + rssi = self._device.get_rssi(iterations) + rssi_avg = rssi["average"] + rssi_cur = rssi["current"] + reads = rssi["reads"] + + self._total_samples += reads + if rssi_cur > self._peak_rssi: + self._peak_rssi = rssi_cur + + self.app.call_from_thread(self._update_gauge, rssi_avg, rssi_cur, reads) + self.app.call_from_thread(self._push_dvb_spark, float(rssi_avg)) + self.app.call_from_thread(self._update_stats) + except Exception: + log.debug("DVB RSSI poll failed", exc_info=True) + + # ADC RSSI (raw single-shot) + try: + adc_resp = self._device.get_adc_rssi() + adc_match = re.search(r"(\d+)", adc_resp) + if adc_match: + adc_val = float(adc_match.group(1)) + self.app.call_from_thread(self._push_adc_spark, adc_val) + except Exception: + log.debug("ADC RSSI poll failed", exc_info=True) + + # Lock status + try: + lock_resp = self._device.get_lock_status() + lock_match = re.search(r"Lock:(\d)", lock_resp) + if lock_match: + locked = lock_match.group(1) == "1" + self.app.call_from_thread(self._update_lock, locked) + except Exception: + log.debug("Lock status poll failed", exc_info=True) + + time.sleep(1.0 / rate) + + # ------------------------------------------------------------------ + # Thread-safe widget update callbacks + # ------------------------------------------------------------------ + + def _read_input(self, input_id: str) -> str: + """Read an Input widget's value (must run on main thread).""" + return self.query_one(f"#{input_id}", Input).value + + def _update_gauge(self, rssi_avg: int, rssi_cur: int, reads: int) -> None: + gauge = self.query_one("#signal-gauge", SignalGauge) + gauge.rssi_avg = rssi_avg + gauge.rssi_cur = rssi_cur + gauge.reads = reads + + def _push_dvb_spark(self, value: float) -> None: + self.query_one("#dvb-spark", SparklineWidget).push(value) + + def _push_adc_spark(self, value: float) -> None: + self.query_one("#adc-spark", SparklineWidget).push(value) + + def _update_stats(self) -> None: + self.query_one("#sample-count", Static).update( + f"Samples: {self._total_samples}" + ) + self.query_one("#peak-value", Static).update(f" Peak: {self._peak_rssi}") + + def _update_lock(self, locked: bool) -> None: + label = "YES" if locked else "NO" + self.query_one("#lock-status", Static).update(f" Lock: {label}") + + def _update_lna_label(self) -> None: + label = "ON" if self._lna_enabled else "OFF" + self.query_one("#lna-status", Static).update(f" LNA: {label}") + + # ------------------------------------------------------------------ + # Button handlers + # ------------------------------------------------------------------ + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + + if button_id == "btn-start": + self._handle_start() + elif button_id == "btn-stop": + self._handle_stop() + elif button_id == "btn-lna": + self._handle_lna() + + def _handle_start(self) -> None: + """Start signal monitoring.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + + if self._monitoring: + return + + self._monitoring = True + self._signal_worker = self._do_signal_poll() + self.app.notify("Signal monitoring started") + + self.query_one("#btn-start", Button).variant = "default" + self.query_one("#btn-stop", Button).variant = "warning" + + def _handle_stop(self) -> None: + """Stop signal monitoring.""" + self._monitoring = False + self.app.notify("Signal monitoring stopped") + + self.query_one("#btn-start", Button).variant = "primary" + self.query_one("#btn-stop", Button).variant = "default" + + def _handle_lna(self) -> None: + """Toggle LNA enable (sends lnbdc odu to set 13V).""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + self._do_enable_lna() + + @work(thread=True, exclusive=False, group="signal-cmd") + def _do_enable_lna(self) -> None: + """Enable LNA in a worker thread (blocks on serial I/O).""" + try: + self._device.enable_lna() + self._lna_enabled = True + self.app.call_from_thread(self._update_lna_label) + self.app.call_from_thread(self.app.notify, "LNA enabled (13V ODU)") + except Exception: + log.exception("LNA enable failed") + self.app.call_from_thread( + self.app.notify, "LNA enable failed", severity="error" + ) diff --git a/tui/src/birdcage_tui/screens/system.py b/tui/src/birdcage_tui/screens/system.py new file mode 100644 index 0000000..13719a0 --- /dev/null +++ b/tui/src/birdcage_tui/screens/system.py @@ -0,0 +1,358 @@ +"""F4 System Screen -- NVS table, A3981 diagnostics, motor dynamics, firmware info. + +Aggregates hardware identity, stepper driver status, motor tuning parameters, +and the full non-volatile storage table into a single dashboard panel. All data +is fetched from the device in a background worker thread and pushed to widgets +via call_from_thread. +""" + +import json +import logging +import re +from pathlib import Path + +from rich.text import Text +from textual import work +from textual.containers import Container, Horizontal, Vertical +from textual.widgets import Button, Static +from textual.worker import get_current_worker + +from birdcage_tui.widgets.nvs_table import NvsTable + +log = logging.getLogger(__name__) + +# Type alias -- SerialBridge and DemoDevice share the same duck-typed interface. +DeviceLike = object + + +def _parse_firmware_info(raw: str) -> Text: + """Extract version, clock speed, and antenna ID from ``os > id`` output. + + Returns a styled Rich Text suitable for a Static widget. + """ + version = "?" + clock = "?" + ant_id = "?" + + m = re.search(r"Software version:\s*(\S+)", raw) + if m: + version = m.group(1) + + m = re.search(r"CCLK:\s*(\d+)", raw) + if m: + mhz = int(m.group(1)) // 1_000_000 + clock = f"{mhz}MHz" + + m = re.search(r"Ant ID:\s*(.+?)$", raw, re.MULTILINE) + if m: + ant_id = m.group(1).strip() + + result = Text() + result.append("FW: ", style="#506878") + result.append(version, style="bold #00d4aa") + result.append(" | ", style="#1a2a38") + result.append("MCU: ", style="#506878") + result.append(f"K60 {clock}", style="#c8d0d8") + result.append(" | ", style="#1a2a38") + result.append("Ant: ", style="#506878") + result.append(ant_id, style="#c8d0d8") + return result + + +def _format_a3981(diag: str, modes: dict[str, str], torque: str) -> Text: + """Combine A3981 diagnostic, mode, and torque data into styled text.""" + result = Text() + + # Diagnostics -- highlight OK in green, FAULT in red. + for line in diag.splitlines(): + line = line.strip() + if not line: + continue + if "FAULT" in line.upper(): + result.append(line, style="bold #e04040") + elif "OK" in line.upper(): + result.append(line, style="#00e060") + else: + result.append(line, style="#c8d0d8") + result.append("\n") + + # Step mode. + sm = modes.get("step_mode", "") + for line in sm.splitlines(): + line = line.strip() + if line: + result.append(line, style="#506878") + result.append("\n") + + # Current mode. + cm = modes.get("current_mode", "") + for line in cm.splitlines(): + line = line.strip() + if line: + result.append(line, style="#506878") + result.append("\n") + + # Torque -- HIGH in warm color, LOW in dim. + for line in torque.splitlines(): + line = line.strip() + if not line: + continue + if "HIGH" in line.upper(): + result.append(line, style="#e8c020") + else: + result.append(line, style="#384858") + result.append("\n") + + # Trim trailing newline. + text_str = result.plain + if text_str.endswith("\n"): + result.right_crop(1) + + return result + + +def _format_motor_dynamics( + dynamics: dict[str, float], + el_limits: dict[str, float], +) -> Text: + """Format motor velocity, acceleration, and EL limits into styled text.""" + result = Text() + + az_vel = dynamics.get("az_max_vel", 0.0) + el_vel = dynamics.get("el_max_vel", 0.0) + az_acc = dynamics.get("az_accel", 0.0) + el_acc = dynamics.get("el_accel", 0.0) + + result.append("AZ Max Vel: ", style="#506878") + result.append(f"{az_vel:.1f}", style="bold #c8d0d8") + result.append("\u00b0/s", style="#506878") + result.append(" ", style="#0e1420") + result.append("EL Max Vel: ", style="#506878") + result.append(f"{el_vel:.1f}", style="bold #c8d0d8") + result.append("\u00b0/s", style="#506878") + result.append("\n") + + result.append("AZ Accel: ", style="#506878") + result.append(f"{az_acc:.1f}", style="bold #c8d0d8") + result.append("\u00b0/s\u00b2", style="#506878") + result.append(" ", style="#0e1420") + result.append("EL Accel: ", style="#506878") + result.append(f"{el_acc:.1f}", style="bold #c8d0d8") + result.append("\u00b0/s\u00b2", style="#506878") + result.append("\n") + + result.append("Steps/Rev: ", style="#506878") + result.append("40000 / 24960", style="#c8d0d8") + + el_min = el_limits.get("min", 0.0) + el_max = el_limits.get("max", 0.0) + el_home = el_limits.get("home", 0.0) + + result.append("\n") + result.append("EL Range: ", style="#506878") + result.append(f"{el_min:.1f}", style="#c8d0d8") + result.append("\u00b0 - ", style="#506878") + result.append(f"{el_max:.1f}", style="#c8d0d8") + result.append("\u00b0", style="#506878") + result.append(" Home: ", style="#506878") + result.append(f"{el_home:.1f}", style="bold #00d4aa") + result.append("\u00b0", style="#506878") + + return result + + +class SystemScreen(Container): + """F4: System information, NVS, and diagnostics.""" + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._device: DeviceLike | None = None + self._refreshed = False + + def compose(self): + with Container(classes="screen-container"): + with Horizontal(classes="panel"): + yield Static("", id="firmware-info") + with Horizontal(classes="top-row"): + with Vertical(classes="panel"): + yield Static("A3981 Diagnostics", classes="panel-title") + yield Static("", id="a3981-diag") + with Vertical(classes="panel"): + yield Static("Motor Dynamics", classes="panel-title") + yield Static("", id="motor-dynamics") + with Vertical(classes="panel"): + yield Static("NVS Table", classes="panel-title") + yield NvsTable(id="nvs-table") + with Horizontal(classes="bottom-controls"): + yield Button("Refresh All", id="btn-refresh-all", variant="primary") + yield Button("Refresh NVS", id="btn-refresh-nvs") + yield Button("Export NVS JSON", id="btn-export-nvs") + + # ------------------------------------------------------------------ + # Device wiring + # ------------------------------------------------------------------ + + def set_device(self, device: DeviceLike) -> None: + """Store the device reference and trigger an initial refresh.""" + self._device = device + # Only auto-refresh if we're already mounted (widget tree exists). + try: + self.query_one("#firmware-info") + self._do_system_refresh() + except Exception: + # Not mounted yet -- on_show will handle it. + pass + + def on_show(self) -> None: + """Called when this screen becomes visible via ContentSwitcher.""" + if self._device is not None and not self._refreshed: + self._do_system_refresh() + + # ------------------------------------------------------------------ + # System refresh worker + # ------------------------------------------------------------------ + + @work(thread=True) + def _do_system_refresh(self) -> None: + """Fetch all system data from the device in a background thread.""" + worker = get_current_worker() + device = self._device + if device is None: + return + + # 1. Firmware identification. + try: + fw_raw = device.get_firmware_id() + fw_text = _parse_firmware_info(fw_raw) + self.app.call_from_thread( + self.query_one("#firmware-info", Static).update, fw_text + ) + except Exception: + log.exception("Failed to read firmware ID") + self.app.call_from_thread( + self.query_one("#firmware-info", Static).update, + Text("FW: error reading firmware ID", style="#e04040"), + ) + + if worker.is_cancelled: + return + + # 2. A3981 diagnostics. + try: + diag = device.get_a3981_diag() + modes = device.get_a3981_modes() + torque = device.get_a3981_torque() + a3981_text = _format_a3981(diag, modes, torque) + self.app.call_from_thread( + self.query_one("#a3981-diag", Static).update, a3981_text + ) + except Exception: + log.exception("Failed to read A3981 data") + self.app.call_from_thread( + self.query_one("#a3981-diag", Static).update, + Text("Error reading A3981 diagnostics", style="#e04040"), + ) + + if worker.is_cancelled: + return + + # 3. Motor dynamics. + try: + dynamics = device.get_motor_dynamics() + el_limits = device.get_el_limits() + motor_text = _format_motor_dynamics(dynamics, el_limits) + self.app.call_from_thread( + self.query_one("#motor-dynamics", Static).update, motor_text + ) + except Exception: + log.exception("Failed to read motor dynamics") + self.app.call_from_thread( + self.query_one("#motor-dynamics", Static).update, + Text("Error reading motor dynamics", style="#e04040"), + ) + + if worker.is_cancelled: + return + + # 4. NVS dump. + try: + nvs_text = device.nvs_dump() + nvs_table = self.query_one("#nvs-table", NvsTable) + self.app.call_from_thread(nvs_table.load_nvs, nvs_text) + except Exception: + log.exception("Failed to dump NVS") + self.app.call_from_thread( + self.app.notify, "NVS dump failed", severity="error" + ) + + self._refreshed = True + + # ------------------------------------------------------------------ + # NVS-only refresh worker + # ------------------------------------------------------------------ + + @work(thread=True) + def _do_nvs_refresh(self) -> None: + """Refresh just the NVS table without touching other panels.""" + device = self._device + if device is None: + return + + try: + nvs_text = device.nvs_dump() + nvs_table = self.query_one("#nvs-table", NvsTable) + self.app.call_from_thread(nvs_table.load_nvs, nvs_text) + self.app.call_from_thread(self.app.notify, "NVS table refreshed") + except Exception: + log.exception("Failed to refresh NVS") + self.app.call_from_thread( + self.app.notify, "NVS refresh failed", severity="error" + ) + + # ------------------------------------------------------------------ + # Button handlers + # ------------------------------------------------------------------ + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + + if button_id == "btn-refresh-all": + self._handle_refresh_all() + elif button_id == "btn-refresh-nvs": + self._handle_refresh_nvs() + elif button_id == "btn-export-nvs": + self._export_nvs_json() + + def _handle_refresh_all(self) -> None: + """Kick off a full system refresh.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + self._do_system_refresh() + + def _handle_refresh_nvs(self) -> None: + """Kick off an NVS-only refresh.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + self._do_nvs_refresh() + + def _export_nvs_json(self) -> None: + """Export parsed NVS rows to /tmp/birdcage_nvs.json.""" + nvs_table = self.query_one("#nvs-table", NvsTable) + rows = nvs_table.parsed_rows + + if not rows: + self.app.notify( + "No NVS data to export -- refresh first", severity="warning" + ) + return + + output = Path("/tmp/birdcage_nvs.json") + try: + with output.open("w") as fh: + json.dump(rows, fh, indent=2) + self.app.notify(f"Exported {len(rows)} NVS entries to {output}") + except OSError as exc: + log.exception("NVS JSON export failed") + self.app.notify(f"Export failed: {exc}", severity="error") diff --git a/tui/src/birdcage_tui/theme.tcss b/tui/src/birdcage_tui/theme.tcss new file mode 100644 index 0000000..f8f351d --- /dev/null +++ b/tui/src/birdcage_tui/theme.tcss @@ -0,0 +1,496 @@ +/* Birdcage TUI — Dark RF Theme + * Teal accent on deep blue-black. No purple. + * Signal gradient: blue > cyan > green > yellow > red + */ + +/* ── Global ────────────────────────────────────────── */ + +Screen { + background: #0a0a12; + color: #c8d0d8; +} + +Header { + background: #0e1420; + color: #00d4aa; + text-style: bold; + dock: top; + height: 1; +} + +Footer { + background: #0e1420; + color: #506878; + dock: bottom; + height: 1; +} + +/* ── Layout Containers ─────────────────────────────── */ + +#main-area { + layout: horizontal; + height: 1fr; +} + +#sidebar { + width: 26; + background: #0e1420; + border-right: solid #1a2a3a; + padding: 1 1; +} + +.sidebar-title { + color: #00d4aa; + text-style: bold; + text-align: center; + width: 100%; +} + +.sidebar-subtitle { + color: #506878; + text-align: center; + width: 100%; + margin: 0 0 1 0; +} + +#content-area { + width: 1fr; +} + +ContentSwitcher { + width: 1fr; + height: 1fr; +} + +/* ── Sidebar Buttons ───────────────────────────────── */ + +.sidebar-btn { + width: 100%; + height: 3; + margin: 0 0 1 0; + background: #121c2a; + color: #7090a8; + text-style: bold; + border: round #1a3050; + text-align: center; +} + +.sidebar-btn:hover { + background: #1a2a40; + color: #00d4aa; + border: round #00d4aa; +} + +.sidebar-btn.active { + background: #0a2a3a; + color: #00d4aa; + border: round #00d4aa; + text-style: bold; +} + +/* ── Panel / Card ──────────────────────────────────── */ + +.panel { + background: #0e1420; + border: round #1a2a3a; + padding: 1 2; + margin: 0 1 1 1; +} + +.panel-title { + color: #00d4aa; + text-style: bold; + margin-bottom: 1; +} + +/* ── Data Display ──────────────────────────────────── */ + +.value-large { + color: #00d4aa; + text-style: bold; +} + +.value-normal { + color: #c8d0d8; +} + +.label { + color: #506878; +} + +.label-dim { + color: #384858; +} + +/* ── Status Indicators ─────────────────────────────── */ + +.status-ok { + color: #00e060; +} + +.status-warn { + color: #e8a020; +} + +.status-error { + color: #e04040; +} + +.status-demo { + color: #e8a020; + text-style: italic; +} + +/* ── Input Controls ────────────────────────────────── */ + +Input { + background: #121c2a; + border: round #1a3050; + color: #c8d0d8; + padding: 0 1; +} + +Input:focus { + border: round #00d4aa; +} + +Button { + background: #1a2a40; + color: #00d4aa; + border: round #1a3050; + min-width: 10; + height: 3; +} + +Button:hover { + background: #00d4aa; + color: #0a0a12; + border: round #00d4aa; +} + +Button:focus { + border: round #00d4aa; + text-style: bold; +} + +Button.-active { + background: #0a3a3a; +} + +/* ── DataTable ─────────────────────────────────────── */ + +DataTable { + background: #0a0a12; + color: #c8d0d8; + height: 1fr; +} + +DataTable > .datatable--header { + background: #0e1420; + color: #00d4aa; + text-style: bold; +} + +DataTable > .datatable--cursor { + background: #142030; + color: #c8d0d8; +} + +DataTable > .datatable--even-row { + background: #0a0a12; +} + +DataTable > .datatable--odd-row { + background: #0c0e18; +} + +/* ── RichLog ───────────────────────────────────────── */ + +RichLog { + background: #0a0a12; + color: #c8d0d8; + border: round #1a2a3a; + scrollbar-color: #1a2a38; + scrollbar-color-active: #00d4aa; + scrollbar-color-hover: #2a4a58; + height: 1fr; +} + +/* ── Progress Bar ──────────────────────────────────── */ + +ProgressBar { + padding: 0 1; +} + +ProgressBar Bar { + color: #00d4aa; + background: #1a2a38; +} + +ProgressBar PercentageStatus { + color: #506878; + text-style: bold; +} + +/* ── Sparkline ─────────────────────────────────────── */ + +.sparkline { + height: 2; + padding: 0 1; + color: #00d4aa; + background: #0e1420; +} + +.sparkline-label { + color: #506878; + width: 14; +} + +/* ── Compass Rose ──────────────────────────────────── */ + +#compass-container { + height: auto; + min-height: 14; + padding: 1; +} + +.compass-readout { + color: #00d4aa; + text-style: bold; +} + +/* ── Signal Gauge ──────────────────────────────────── */ + +.gauge-container { + height: 3; + padding: 0 1; +} + +.gauge-bar { + height: 1; +} + +.gauge-label { + color: #506878; + width: 8; +} + +.gauge-value { + color: #c8d0d8; + width: 8; + text-align: right; +} + +/* ── Signal Colors (gradient: blue > cyan > green > yellow > red) ── */ + +.signal-cold { + color: #2080d0; +} + +.signal-cool { + color: #00b8c8; +} + +.signal-mid { + color: #00e060; +} + +.signal-warm { + color: #e8c020; +} + +.signal-hot { + color: #e04040; +} + +/* ── Sky Heatmap ───────────────────────────────────── */ + +.heatmap-container { + height: 1fr; + padding: 0; +} + +.heatmap-cell { + width: 2; + height: 1; +} + +/* ── Motor Status ──────────────────────────────────── */ + +.motor-panel { + height: auto; + padding: 1 2; + background: #0e1420; + border: round #1a2a3a; +} + +.motor-row { + layout: horizontal; + height: 1; +} + +.motor-label { + color: #506878; + width: 14; +} + +.motor-value { + color: #c8d0d8; +} + +/* ── Device Status Bar (sidebar bottom) ────────────── */ + +#device-status { + dock: bottom; + height: auto; + padding: 1; + background: #0e1420; + border-top: solid #1a2a38; +} + +.device-status-label { + color: #506878; +} + +.device-status-value { + color: #c8d0d8; +} + +.device-connected { + color: #00e060; +} + +.device-demo { + color: #e8a020; +} + +/* ── Console Screen ────────────────────────────────── */ + +.console-input-area { + dock: bottom; + height: 3; + layout: horizontal; + padding: 0 1; + background: #0e1420; + border-top: solid #1a2a38; +} + +.console-input-area Input { + width: 1fr; +} + +.console-input-area Button { + width: 10; + margin-left: 1; +} + +.console-context { + dock: bottom; + height: 1; + padding: 0 1; + background: #0e1420; + color: #506878; +} + +/* ── Prompt Colors (by submenu) ────────────────────── */ + +.prompt-trk { + color: #00d4aa; +} + +.prompt-mot { + color: #00e060; +} + +.prompt-dvb { + color: #2080d0; +} + +.prompt-nvs { + color: #e8a020; +} + +.prompt-a3981 { + color: #00b8c8; +} + +.prompt-step { + color: #40c0a0; +} + +.prompt-os { + color: #8090a0; +} + +.prompt-other { + color: #506878; +} + +/* ── Scan Screen ───────────────────────────────────── */ + +.scan-controls { + dock: bottom; + height: auto; + padding: 1; + background: #0e1420; + border-top: solid #1a2a38; +} + +.scan-status { + height: 2; + padding: 0 1; + color: #506878; +} + +/* ── Screen-Level Layouts ──────────────────────────── */ + +.screen-container { + layout: vertical; + height: 1fr; + width: 1fr; +} + +.top-row { + layout: horizontal; + height: 1fr; +} + +.bottom-controls { + dock: bottom; + height: auto; + padding: 1; + background: #0e1420; + border-top: solid #1a2a38; + layout: horizontal; +} + +.control-group { + layout: horizontal; + height: 3; + width: 1fr; +} + +.control-group Input { + width: 8; + margin-right: 1; +} + +.control-group Button { + margin-right: 1; +} + +/* ── NVS Table Highlight ───────────────────────────── */ + +.nvs-modified { + color: #e8a020; + text-style: bold; +} + +/* ── Scrollbar Styling ─────────────────────────────── */ + +* { + scrollbar-color: #1a2a38; + scrollbar-color-active: #00d4aa; + scrollbar-color-hover: #2a4a58; + scrollbar-background: #0a0a12; +} diff --git a/tui/src/birdcage_tui/widgets/__init__.py b/tui/src/birdcage_tui/widgets/__init__.py new file mode 100644 index 0000000..ea4216e --- /dev/null +++ b/tui/src/birdcage_tui/widgets/__init__.py @@ -0,0 +1,21 @@ +"""Custom widgets for the Birdcage TUI.""" + +from birdcage_tui.widgets.compass_rose import CompassRose +from birdcage_tui.widgets.device_status_bar import DeviceStatusBar +from birdcage_tui.widgets.motor_status import MotorStatus +from birdcage_tui.widgets.nvs_table import NvsTable +from birdcage_tui.widgets.serial_log import SerialLog +from birdcage_tui.widgets.signal_gauge import SignalGauge +from birdcage_tui.widgets.sky_heatmap import SkyHeatmap +from birdcage_tui.widgets.sparkline_widget import SparklineWidget + +__all__ = [ + "CompassRose", + "DeviceStatusBar", + "MotorStatus", + "NvsTable", + "SerialLog", + "SignalGauge", + "SkyHeatmap", + "SparklineWidget", +] diff --git a/tui/src/birdcage_tui/widgets/compass_rose.py b/tui/src/birdcage_tui/widgets/compass_rose.py new file mode 100644 index 0000000..a6d3c14 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/compass_rose.py @@ -0,0 +1,183 @@ +"""Compass rose widget — visual AZ/EL position display with Unicode compass dial.""" + +from rich.text import Text +from textual.reactive import reactive +from textual.widgets import Static + +# Compass grid layout: 11 columns x 7 rows. +# Positions indexed [row][col] where (0,0) is top-left. +# Cardinal/intercardinal markers are placed at fixed positions. +# The pointer occupies one of 16 perimeter slots based on azimuth. + +# 16-slot perimeter positions (clockwise from N=0): +# Each entry is (row, col) on the 11x7 grid. +_POINTER_SLOTS: list[tuple[int, int]] = [ + (0, 5), # 0: N + (0, 7), # 1: NNE + (1, 9), # 2: NE + (2, 10), # 3: ENE + (3, 10), # 4: E + (4, 10), # 5: ESE + (5, 9), # 6: SE + (6, 7), # 7: SSE + (6, 5), # 8: S + (6, 3), # 9: SSW + (5, 1), # 10: SW + (4, 0), # 11: WSW + (3, 0), # 12: W + (2, 0), # 13: WNW + (1, 1), # 14: NW + (0, 3), # 15: NNW +] + +# Fixed cardinal/intercardinal label positions: (row, col, label) +_LABELS: list[tuple[int, int, str]] = [ + (0, 5, "N"), + (3, 10, "E"), + (6, 5, "S"), + (3, 0, "W"), +] + +# Ring structure characters for the compass dial. +_RING_CHARS: dict[tuple[int, int], str] = { + # Top arc + (0, 3): ".", + (0, 4): "\u2500", + (0, 6): "\u2500", + (0, 7): ".", + # Upper sides + (1, 1): "/", + (1, 9): "\\", + # Mid-upper sides + (2, 0): "\u2502", + (2, 10): "\u2502", + # Center sides (cardinals placed separately) + # (3, 0) and (3, 10) reserved for W/E labels + # Lower-mid sides + (4, 0): "\u2502", + (4, 10): "\u2502", + # Lower sides + (5, 1): "\\", + (5, 9): "/", + # Bottom arc + (6, 3): "'", + (6, 4): "\u2500", + (6, 6): "\u2500", + (6, 7): "'", +} + + +def _azimuth_to_slot(az: float) -> int: + """Map azimuth (0-360, 0=N clockwise) to one of 16 perimeter slots.""" + normalized = az % 360.0 + slot = round(normalized / 22.5) % 16 + return slot + + +class CompassRose(Static): + """Visual compass display showing azimuth/elevation position.""" + + azimuth: reactive[float] = reactive(180.0) + elevation: reactive[float] = reactive(45.0) + + def render(self) -> Text: + result = Text() + + # Large numeric readout + az_label = Text("AZ ", style="#506878 bold") + az_value = Text(f"{self.azimuth:7.2f}\u00b0", style="#00d4aa bold") + el_label = Text(" EL ", style="#506878 bold") + el_value = Text(f"{self.elevation:6.2f}\u00b0", style="#00d4aa bold") + + result.append(az_label) + result.append(az_value) + result.append(el_label) + result.append(el_value) + result.append("\n\n") + + # Build the 7x11 compass grid + grid: list[list[tuple[str, str]]] = [ + [(" ", "#0e1420") for _ in range(11)] for _ in range(7) + ] + + # Place ring structure + for (r, c), ch in _RING_CHARS.items(): + grid[r][c] = (ch, "#c8d0d8") + + # Place cardinal labels + for r, c, label in _LABELS: + grid[r][c] = (label, "#506878 bold") + + # Center crosshair + grid[3][5] = ("\u253c", "#1a2a38") + grid[3][4] = ("\u2500", "#1a2a38") + grid[3][6] = ("\u2500", "#1a2a38") + grid[2][5] = ("\u2502", "#1a2a38") + grid[4][5] = ("\u2502", "#1a2a38") + + # Place pointer at azimuth position + slot = _azimuth_to_slot(self.azimuth) + pr, pc = _POINTER_SLOTS[slot] + # Use a filled diamond for the pointer + grid[pr][pc] = ("\u25c6", "#00d4aa bold") + + # Compute a line from center toward the pointer direction for visual clarity + # Place a dot at an intermediate position between center (3,5) and pointer + cr, cc = 3, 5 + dr = pr - cr + dc = pc - cc + if abs(dr) > 1 or abs(dc) > 1: + mr = cr + (1 if dr > 0 else (-1 if dr < 0 else 0)) + mc = cc + (1 if dc > 0 else (-1 if dc < 0 else 0)) + # Only place intermediate dot if it doesn't overwrite a label + existing_ch = grid[mr][mc][0] + if existing_ch in (" ", "\u2500", "\u2502", "\u253c"): + grid[mr][mc] = ("\u2022", "#00d4aa") + + # Render grid to text + for row_idx, row in enumerate(grid): + for _col_idx, (ch, style) in enumerate(row): + result.append(ch, style=style) + if row_idx < 6: + result.append("\n") + + # Bearing line below compass + bearing = self.azimuth % 360.0 + if bearing < 0: + bearing += 360.0 + cardinal = _bearing_to_cardinal(bearing) + result.append("\n") + result.append(f" {cardinal:>5s}", style="#506878") + result.append(f" {bearing:05.1f}\u00b0", style="#c8d0d8") + + return result + + def watch_azimuth(self, _value: float) -> None: + self.refresh() + + def watch_elevation(self, _value: float) -> None: + self.refresh() + + +def _bearing_to_cardinal(bearing: float) -> str: + """Convert bearing in degrees to 16-point cardinal abbreviation.""" + directions = [ + "N", + "NNE", + "NE", + "ENE", + "E", + "ESE", + "SE", + "SSE", + "S", + "SSW", + "SW", + "WSW", + "W", + "WNW", + "NW", + "NNW", + ] + idx = round(bearing / 22.5) % 16 + return directions[idx] diff --git a/tui/src/birdcage_tui/widgets/device_status_bar.py b/tui/src/birdcage_tui/widgets/device_status_bar.py new file mode 100644 index 0000000..7f72c29 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/device_status_bar.py @@ -0,0 +1,92 @@ +"""Device status bar widget — sidebar display of connection state and firmware info.""" + +from rich.text import Text +from textual.widgets import Static + + +class DeviceStatusBar(Static): + """Sidebar status display showing connection state and firmware info.""" + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._connected: bool = False + self._demo: bool = False + self._firmware: str = "---" + self._submenu: str = "---" + self._port: str = "---" + + def set_device(self, device: object) -> None: + """Accept a device reference and update the status display.""" + is_demo = hasattr(device, "demo_mode") or type(device).__name__ == "DemoDevice" + fw = getattr(device, "firmware_id", "02.02.48") if device else "---" + port = getattr(self.app, "serial_port", "/dev/ttyUSB0") if self.app else "---" + submenu = getattr(device, "current_menu", "TRK>") if device else "---" + connected = device is not None and not is_demo + self.update_status( + connected=connected, + demo=is_demo, + firmware=str(fw), + submenu=str(submenu), + port=str(port), + ) + + def update_status( + self, + connected: bool, + demo: bool, + firmware: str, + submenu: str, + port: str, + ) -> None: + """Update all status fields and refresh the display.""" + self._connected = connected + self._demo = demo + self._firmware = firmware + self._submenu = submenu + self._port = port + self.refresh() + + def render(self) -> Text: + result = Text() + label_w = 8 + + # Status row + result.append("Status".ljust(label_w), style="#506878") + if self._connected: + result.append("Connected", style="#00e060 bold") + elif self._demo: + result.append("Demo", style="#e8a020 italic") + else: + result.append("Offline", style="#e04040") + result.append("\n") + + # Port row + result.append("Port".ljust(label_w), style="#506878") + result.append(self._port, style="#c8d0d8") + result.append("\n") + + # Firmware row + result.append("FW".ljust(label_w), style="#506878") + result.append(self._firmware, style="#c8d0d8") + result.append("\n") + + # Menu row + result.append("Menu".ljust(label_w), style="#506878") + # Color the menu prompt with its matching prompt color + submenu_colors: dict[str, str] = { + "TRK>": "#00d4aa", + "MOT>": "#00e060", + "DVB>": "#2080d0", + "NVS>": "#e8a020", + "A3981>": "#00b8c8", + "STEP>": "#40c0a0", + "EE>": "#e8a020", + "OS>": "#8090a0", + "ADC>": "#00b8c8", + "GPIO>": "#40c0a0", + "PEAK>": "#e8c020", + } + menu_color = submenu_colors.get(self._submenu, "#c8d0d8") + result.append(self._submenu, style=f"{menu_color} bold") + + return result diff --git a/tui/src/birdcage_tui/widgets/motor_status.py b/tui/src/birdcage_tui/widgets/motor_status.py new file mode 100644 index 0000000..637622a --- /dev/null +++ b/tui/src/birdcage_tui/widgets/motor_status.py @@ -0,0 +1,76 @@ +"""Motor status widget — engagement state, torque, step counts, and EL range.""" + +from rich.text import Text +from textual.reactive import reactive +from textual.widgets import Static + + +class MotorStatus(Static): + """Panel showing motor engagement state, torque, and step counts.""" + + engaged: reactive[bool] = reactive(False) + az_torque: reactive[str] = reactive("LOW") + el_torque: reactive[str] = reactive("LOW") + az_steps: reactive[int] = reactive(0) + el_steps: reactive[int] = reactive(0) + el_min: reactive[float] = reactive(18.0) + el_max: reactive[float] = reactive(65.0) + + def render(self) -> Text: + result = Text() + label_w = 10 + + # Engaged row + result.append("Engaged".ljust(label_w), style="#506878") + if self.engaged: + result.append("YES", style="#00e060 bold") + else: + result.append("NO", style="#e04040") + result.append("\n") + + # Torque row + result.append("Torque".ljust(label_w), style="#506878") + result.append("AZ: ", style="#506878") + az_style = "#e8c020 bold" if self.az_torque == "HIGH" else "#c8d0d8" + result.append(f"{self.az_torque}", style=az_style) + result.append(" EL: ", style="#506878") + el_style = "#e8c020 bold" if self.el_torque == "HIGH" else "#c8d0d8" + result.append(f"{self.el_torque}", style=el_style) + result.append("\n") + + # Steps row + result.append("Steps".ljust(label_w), style="#506878") + result.append("AZ: ", style="#506878") + result.append(f"{self.az_steps}", style="#c8d0d8") + result.append(" EL: ", style="#506878") + result.append(f"{self.el_steps}", style="#c8d0d8") + result.append("\n") + + # EL Range row + result.append("EL Range".ljust(label_w), style="#506878") + result.append(f"{self.el_min:.1f}\u00b0", style="#c8d0d8") + result.append(" \u2013 ", style="#506878") + result.append(f"{self.el_max:.1f}\u00b0", style="#c8d0d8") + + return result + + def watch_engaged(self, _value: bool) -> None: + self.refresh() + + def watch_az_torque(self, _value: str) -> None: + self.refresh() + + def watch_el_torque(self, _value: str) -> None: + self.refresh() + + def watch_az_steps(self, _value: int) -> None: + self.refresh() + + def watch_el_steps(self, _value: int) -> None: + self.refresh() + + def watch_el_min(self, _value: float) -> None: + self.refresh() + + def watch_el_max(self, _value: float) -> None: + self.refresh() diff --git a/tui/src/birdcage_tui/widgets/nvs_table.py b/tui/src/birdcage_tui/widgets/nvs_table.py new file mode 100644 index 0000000..2fee378 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/nvs_table.py @@ -0,0 +1,93 @@ +"""NVS table widget — DataTable wrapper for non-volatile storage dump display.""" + +import re + +from textual.widgets import DataTable + +# Regex to parse NVS dump lines. +# Examples: +# 0) Log ID's 0x00000007 0x00000007 0x00000007 +# 20) Disable Tracker Proc? TRUE TRUE FALSE +# 101) Minimum Elevation Angle 18.00 18.00 18.00 +_NVS_LINE_RE = re.compile( + r"^\s*(\d+)\)\s+" # index with closing paren + r"(.+?)\s{2,}" # name (greedy until 2+ spaces) + r"(\S+)\s+" # current value + r"(\S+)\s+" # saved value + r"(\S+)\s*$" # default value +) + + +class NvsTable(DataTable): + """DataTable displaying NVS (non-volatile storage) dump data.""" + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._parsed_rows: list[dict[str, str]] = [] + self._columns_added = False + + def on_mount(self) -> None: + """Add columns when the widget is mounted.""" + if not self._columns_added: + self.add_columns("Idx", "Name", "Current", "Saved", "Default") + self._columns_added = True + + def load_nvs(self, text: str) -> list[dict[str, str]]: + """Parse NVS dump text and populate the table. + + Returns a list of dicts with keys: idx, name, current, saved, default. + Rows where current != default are marked for the screen to highlight. + """ + self.clear_table() + self._parsed_rows = [] + + for line in text.splitlines(): + line = line.rstrip() + if not line: + continue + + match = _NVS_LINE_RE.match(line) + if not match: + continue + + idx = match.group(1) + name = match.group(2).strip() + current = match.group(3) + saved = match.group(4) + default = match.group(5) + + row_data = { + "idx": idx, + "name": name, + "current": current, + "saved": saved, + "default": default, + } + self._parsed_rows.append(row_data) + + # Add row to the DataTable + modified = current != default + # Prefix the index cell to signal modification to the screen. + # The screen's CSS rule .nvs-modified handles styling. + label = f"*{idx}" if modified else idx + + self.add_row(label, name, current, saved, default, key=f"nvs-{idx}") + + return self._parsed_rows + + def clear_table(self) -> None: + """Remove all rows from the table.""" + self.clear() + self._parsed_rows = [] + + @property + def parsed_rows(self) -> list[dict[str, str]]: + """Access the most recently parsed NVS data.""" + return list(self._parsed_rows) + + @property + def modified_indices(self) -> list[str]: + """Return indices where current value differs from default.""" + return [ + row["idx"] for row in self._parsed_rows if row["current"] != row["default"] + ] diff --git a/tui/src/birdcage_tui/widgets/serial_log.py b/tui/src/birdcage_tui/widgets/serial_log.py new file mode 100644 index 0000000..55ae6c2 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/serial_log.py @@ -0,0 +1,84 @@ +"""Serial log widget — RichLog with color-coded firmware console prompts.""" + +import re + +from rich.text import Text +from textual.widgets import RichLog + +# Prompt patterns and their colors, ordered by specificity (longest match first). +_PROMPT_STYLES: list[tuple[str, str]] = [ + ("A3981>", "#00b8c8"), + ("STEP>", "#40c0a0"), + ("TRK>", "#00d4aa"), + ("MOT>", "#00e060"), + ("DVB>", "#2080d0"), + ("NVS>", "#e8a020"), + ("EE>", "#e8a020"), + ("OS>", "#8090a0"), + ("ADC>", "#00b8c8"), + ("GPIO>", "#40c0a0"), + ("PEAK>", "#e8c020"), + ("LATLON>", "#506878"), + ("DIPSWITCH>", "#506878"), +] + +# Build a regex that matches any known prompt at any position in the text. +_PROMPT_PATTERN = re.compile( + r"(" + "|".join(re.escape(p) for p, _ in _PROMPT_STYLES) + r")" +) + +# Lookup dict for color by prompt string +_PROMPT_COLOR: dict[str, str] = {p: c for p, c in _PROMPT_STYLES} + + +class SerialLog(RichLog): + """RichLog that color-codes Winegard firmware console prompts.""" + + def __init__(self, **kwargs) -> None: + super().__init__(markup=False, wrap=True, **kwargs) + + def append_output(self, text: str) -> None: + """Append firmware output with color-coded prompts. + + Each line is scanned for known prompt strings (TRK>, MOT>, etc.) + which are rendered in their assigned color. All other text uses + the default terminal color. + """ + for line in text.splitlines(): + if not line: + continue + + styled = _colorize_line(line) + self.write(styled) + + def append_command(self, cmd: str) -> None: + """Append a user-issued command, formatted with a prompt indicator.""" + styled = Text() + styled.append("> ", style="#00d4aa bold") + styled.append(cmd, style="#00d4aa") + self.write(styled) + + +def _colorize_line(line: str) -> Text: + """Parse a single line and return a Rich Text with colored prompt spans.""" + result = Text() + last_end = 0 + + for match in _PROMPT_PATTERN.finditer(line): + start, end = match.span() + prompt_str = match.group(1) + color = _PROMPT_COLOR[prompt_str] + + # Text before the prompt + if start > last_end: + result.append(line[last_end:start], style="#c8d0d8") + + # The prompt itself + result.append(prompt_str, style=f"{color} bold") + last_end = end + + # Remaining text after last prompt + if last_end < len(line): + result.append(line[last_end:], style="#c8d0d8") + + return result diff --git a/tui/src/birdcage_tui/widgets/signal_gauge.py b/tui/src/birdcage_tui/widgets/signal_gauge.py new file mode 100644 index 0000000..935ff1c --- /dev/null +++ b/tui/src/birdcage_tui/widgets/signal_gauge.py @@ -0,0 +1,90 @@ +"""Signal gauge widget — horizontal RSSI bar with color-coded thresholds.""" + +from rich.text import Text +from textual.reactive import reactive +from textual.widgets import Static + +# RSSI color thresholds (upper bound, color) +_THRESHOLDS: list[tuple[int, str]] = [ + (500, "#2080d0"), # cold — noise floor + (1000, "#00b8c8"), # cool — weak signal + (2000, "#00e060"), # mid — usable + (3000, "#e8c020"), # warm — strong + (4096, "#e04040"), # hot — saturating +] + +BAR_WIDTH = 40 +MAX_RSSI = 4096 + +# Sub-character bar fragments for smooth rendering (8 levels per cell) +_BAR_CHARS = " ▏▎▍▌▋▊▉" +_FULL = "\u2588" # █ + + +def _rssi_color(rssi: int) -> str: + """Return the color string for a given RSSI value.""" + for threshold, color in _THRESHOLDS: + if rssi <= threshold: + return color + return _THRESHOLDS[-1][1] + + +class SignalGauge(Static): + """Horizontal RSSI signal strength bar gauge.""" + + rssi_avg: reactive[int] = reactive(0) + rssi_cur: reactive[int] = reactive(0) + reads: reactive[int] = reactive(0) + + def render(self) -> Text: + result = Text() + + # Title + result.append("RSSI", style="#506878 bold") + result.append("\n") + + # Compute fill with sub-character precision (8 levels per cell = 320 positions) + clamped = max(0, min(self.rssi_cur, MAX_RSSI)) + fill_frac = clamped / MAX_RSSI * BAR_WIDTH + full_cells = int(fill_frac) + partial = fill_frac - full_cells + partial_idx = int(partial * 8) + + # Build the bar with per-character color based on position thresholds + for i in range(full_cells): + pos_rssi = round((i + 0.5) / BAR_WIDTH * MAX_RSSI) + color = _rssi_color(pos_rssi) + result.append(_FULL, style=color) + + # Partial sub-character cell + remaining = BAR_WIDTH - full_cells + if remaining > 0 and partial_idx > 0: + pos_rssi = round((full_cells + 0.5) / BAR_WIDTH * MAX_RSSI) + color = _rssi_color(pos_rssi) + result.append(_BAR_CHARS[partial_idx], style=color) + remaining -= 1 + + result.append("\u2591" * remaining, style="#1a2a38") + + # Numeric value at end of bar + result.append(f" {self.rssi_cur}", style=_rssi_color(self.rssi_cur)) + result.append("\n") + + # Label line + result.append("avg: ", style="#506878") + result.append(f"{self.rssi_avg}", style="#c8d0d8") + result.append(" cur: ", style="#506878") + result.append(f"{self.rssi_cur}", style="#c8d0d8") + result.append(" reads: ", style="#506878") + result.append(f"{self.reads}", style="#c8d0d8") + + return result + + def watch_rssi_avg(self, _value: int) -> None: + self.refresh() + + def watch_rssi_cur(self, _value: int) -> None: + self.refresh() + + def watch_reads(self, _value: int) -> None: + self.refresh() diff --git a/tui/src/birdcage_tui/widgets/sky_heatmap.py b/tui/src/birdcage_tui/widgets/sky_heatmap.py new file mode 100644 index 0000000..8287920 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/sky_heatmap.py @@ -0,0 +1,123 @@ +"""Sky heatmap widget — 2D AZ x EL grid colored by RSSI for sky scan visualization.""" + +from rich.text import Text +from textual.widgets import Static + +# RSSI color thresholds matching signal_gauge.py +_THRESHOLDS: list[tuple[float, str]] = [ + (500.0, "#2080d0"), + (1000.0, "#00b8c8"), + (2000.0, "#00e060"), + (3000.0, "#e8c020"), + (4096.0, "#e04040"), +] + +_ZERO_COLOR = "#0e1420" + + +def _rssi_color(rssi: float) -> str: + """Return the color string for a given RSSI value.""" + if rssi <= 0: + return _ZERO_COLOR + for threshold, color in _THRESHOLDS: + if rssi <= threshold: + return color + return _THRESHOLDS[-1][1] + + +class SkyHeatmap(Static): + """2D azimuth x elevation grid colored by RSSI for sky scan visualization.""" + + def __init__( + self, + az_bins: int = 40, + el_bins: int = 10, + **kwargs, + ) -> None: + super().__init__(**kwargs) + self._az_bins = az_bins + self._el_bins = el_bins + self._grid: list[list[float]] = [[0.0] * az_bins for _ in range(el_bins)] + self._active_az: int | None = None + self._active_el: int | None = None + + def set_point(self, az_idx: int, el_idx: int, rssi: float) -> None: + """Set RSSI value at a grid cell. Does not refresh — call refresh() explicitly + or batch updates and refresh once.""" + if 0 <= el_idx < self._el_bins and 0 <= az_idx < self._az_bins: + self._grid[el_idx][az_idx] = rssi + + def set_active(self, az_idx: int, el_idx: int) -> None: + """Highlight the current scan position and refresh.""" + self._active_az = az_idx + self._active_el = el_idx + self.refresh() + + def clear(self) -> None: + """Reset all RSSI values to zero and clear active position.""" + for row in self._grid: + for i in range(len(row)): + row[i] = 0.0 + self._active_az = None + self._active_el = None + self.refresh() + + def render(self) -> Text: + result = Text() + + # Column header: AZ labels (every 5 bins) + # Left gutter for EL labels + gutter = 5 + result.append(" " * gutter, style="#0e1420") + for az in range(self._az_bins): + if az % 5 == 0: + label = str(az) + result.append(label, style="#506878") + # Pad to maintain 1-char-per-bin spacing + pad = 1 - len(label) + if pad > 0: + result.append(" " * pad) + else: + result.append(" ") + result.append("\n") + + # Grid rows: highest EL at top + for el_idx in range(self._el_bins - 1, -1, -1): + # EL label + el_label = f"{el_idx:>3d} " + result.append(el_label, style="#506878") + result.append("\u2502", style="#1a2a38") + + for az_idx in range(self._az_bins): + rssi = self._grid[el_idx][az_idx] + is_active = az_idx == self._active_az and el_idx == self._active_el + + if is_active: + # Active scan position: bright white on dark background + result.append("\u2588", style="bold #ffffff on #1a2a38") + elif rssi <= 0: + # Empty cell + result.append("\u2591", style="#0e1420") + else: + color = _rssi_color(rssi) + # Use denser block for higher RSSI + ch = "\u2593" if rssi < 500 else "\u2588" + result.append(ch, style=color) + + if el_idx > 0: + result.append("\n") + + # Bottom border + result.append("\n") + result.append(" " * gutter, style="#0e1420") + result.append("\u2500" * self._az_bins, style="#1a2a38") + + return result + + @property + def az_bins(self) -> int: + return self._az_bins + + @property + def el_bins(self) -> int: + return self._el_bins diff --git a/tui/src/birdcage_tui/widgets/sparkline_widget.py b/tui/src/birdcage_tui/widgets/sparkline_widget.py new file mode 100644 index 0000000..89ad8f5 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/sparkline_widget.py @@ -0,0 +1,74 @@ +"""Sparkline widget — rolling time series using Unicode block characters.""" + +from collections import deque + +from rich.text import Text +from textual.widgets import Static + +# 8-level vertical block characters for sparkline rendering. +# Index 0 = lowest bar, index 7 = tallest bar. +_BLOCKS = "\u2581\u2582\u2583\u2584\u2585\u2586\u2587\u2588" + + +class SparklineWidget(Static): + """Rolling sparkline time series display.""" + + def __init__( + self, + max_points: int = 60, + label: str = "", + color: str = "#00d4aa", + **kwargs, + ) -> None: + super().__init__(**kwargs) + self._max_points = max_points + self._label = label + self._color = color + self._buffer: deque[float] = deque(maxlen=max_points) + + def push(self, value: float) -> None: + """Add a data point to the sparkline buffer and refresh.""" + self._buffer.append(value) + self.refresh() + + def render(self) -> Text: + result = Text() + + # Label prefix + if self._label: + result.append(f"{self._label} ", style="#506878") + + if not self._buffer: + result.append("\u2581" * self._max_points, style="#1a2a38") + return result + + values = list(self._buffer) + lo = min(values) + hi = max(values) + span = hi - lo + + for v in values: + if span <= 0: + # All values identical — render as mid-level + idx = 3 + else: + normalized = (v - lo) / span + idx = min(int(normalized * 7.999), 7) + result.append(_BLOCKS[idx], style=self._color) + + # Pad remaining width with low blocks if buffer not full + remaining = self._max_points - len(values) + if remaining > 0: + result.append(_BLOCKS[0] * remaining, style="#1a2a38") + + # Min/max annotation + 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Turn cl ## Testing No hardware-in-the-loop tests yet. Protocol implementations can be mocked for unit testing — `FirmwareProtocol` is an ABC with clear method contracts. + +## Documentation Site + +| Property | Value | +|----------|-------| +| Repo | `git@git.supported.systems:warehack.ing/birdcage-docs.git` | +| Local path | `site/` (separate git repo, not a subtree) | +| Framework | Astro + Starlight | +| Domain | `birdcage.warehack.ing` | +| Server | `warehack-ing@warehack.ing:~/birdcage-docs/` | +| Container | `birdcage-docs` (caddy:2-alpine serving static files) | + +### Workflow + +```bash +cd site/ + +# Local development with HMR +make dev # Sets APP_ENV=dev, starts Astro dev server on :4321 + +# Production build + deploy +make prod # Sets APP_ENV=prod, builds static site, serves via Caddy on :80 + +# Other commands +make logs # Tail container logs +make rebuild # Down + up with fresh build +make clean # Remove containers + images +``` + +### Make Targets + +| Target | Description | +|--------|-------------| +| `up` | Build and start container | +| `down` | Stop container | +| `logs` | Tail container logs | +| `rebuild` | Down + up with fresh build | +| `dev` | Switch to dev mode (Astro dev server + HMR) | +| `prod` | Switch to prod mode (static build + Caddy) | +| `clean` | Remove containers, images, and volumes | + +### Deploying Updates + +```bash +cd site/ +git add . && git commit -m "description" +git push origin main +ssh -A warehack-ing@warehack.ing "cd birdcage-docs && git pull && make prod" +``` + +TLS is automatic via caddy-docker-proxy (ACME + Vultr DNS challenge). New subdomains take ~2 minutes for certificate issuance. From 48746937a7320c193fca9c850f4efb14bcbbeddc Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 09:41:47 -0700 Subject: [PATCH 04/30] Fix executor shutdown warning on TUI exit Poll threads (position at 2 Hz, signal when monitoring) run while-loops with time.sleep() that never exit on app quit. Add on_unmount() to PositionScreen, SignalScreen, and BirdcageApp to clear polling flags and disconnect the device, so worker threads exit within the sleep interval instead of hitting the 300s timeout. --- tui/src/birdcage_tui/app.py | 11 +++++++++++ tui/src/birdcage_tui/screens/position.py | 4 ++++ tui/src/birdcage_tui/screens/signal.py | 4 ++++ 3 files changed, 19 insertions(+) diff --git a/tui/src/birdcage_tui/app.py b/tui/src/birdcage_tui/app.py index 1349e63..c7990d1 100644 --- a/tui/src/birdcage_tui/app.py +++ b/tui/src/birdcage_tui/app.py @@ -129,6 +129,17 @@ class BirdcageApp(App): if hasattr(screen, "on_show"): screen.on_show() + def on_unmount(self) -> None: + """Stop all polling threads and disconnect the device on shutdown.""" + for mode_key in MODES: + screen = self.query_one(f"#{mode_key}") + if hasattr(screen, "_polling"): + screen._polling = False + if hasattr(screen, "_monitoring"): + screen._monitoring = False + if self.device and hasattr(self.device, "disconnect"): + self.device.disconnect() + def action_toggle_dark(self) -> None: self.dark = not self.dark diff --git a/tui/src/birdcage_tui/screens/position.py b/tui/src/birdcage_tui/screens/position.py index da348c2..388b3c6 100644 --- a/tui/src/birdcage_tui/screens/position.py +++ b/tui/src/birdcage_tui/screens/position.py @@ -87,6 +87,10 @@ class PositionScreen(Container): self._polling = True self._poll_worker = self._do_position_poll() + def on_unmount(self) -> None: + """Stop polling thread on teardown.""" + self._polling = False + # ------------------------------------------------------------------ # Position poll worker # ------------------------------------------------------------------ diff --git a/tui/src/birdcage_tui/screens/signal.py b/tui/src/birdcage_tui/screens/signal.py index 0903c0a..9b7c7e9 100644 --- a/tui/src/birdcage_tui/screens/signal.py +++ b/tui/src/birdcage_tui/screens/signal.py @@ -71,6 +71,10 @@ class SignalScreen(Container): """Called when this screen becomes visible.""" pass # Monitoring is explicit via Start/Stop buttons. + def on_unmount(self) -> None: + """Stop monitoring thread on teardown.""" + self._monitoring = False + # ------------------------------------------------------------------ # Signal poll worker # ------------------------------------------------------------------ From ba8859cc3144894a244b0945521d77a2cfaf3f26 Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 10:21:42 -0700 Subject: [PATCH 05/30] Fix 300s executor shutdown with threading.Event Replace time.sleep() with threading.Event.wait() in all poll loops so worker threads exit immediately on shutdown instead of blocking for up to 500ms per iteration. Fixes the on_unmount crash (NoMatches from querying removed DOM nodes) by signaling the event directly rather than iterating child widgets. Three shutdown paths covered: q key (on_unmount), Ctrl+C (try/finally in main), and Textual internal shutdown. --- tui/src/birdcage_tui/app.py | 20 ++++++++++++-------- tui/src/birdcage_tui/screens/position.py | 8 ++++---- tui/src/birdcage_tui/screens/scan.py | 6 +++--- tui/src/birdcage_tui/screens/signal.py | 8 ++++---- 4 files changed, 23 insertions(+), 19 deletions(-) diff --git a/tui/src/birdcage_tui/app.py b/tui/src/birdcage_tui/app.py index c7990d1..87f03f8 100644 --- a/tui/src/birdcage_tui/app.py +++ b/tui/src/birdcage_tui/app.py @@ -6,6 +6,7 @@ device status bar, and five swappable screen panels. import argparse import logging +import threading from textual.app import App, ComposeResult from textual.binding import Binding @@ -52,6 +53,7 @@ class BirdcageApp(App): firmware_name: str = "g2" skip_init: bool = False device: object = None + shutdown_event: threading.Event = threading.Event() @property def SUB_TITLE(self) -> str: # noqa: N802 @@ -130,13 +132,8 @@ class BirdcageApp(App): screen.on_show() def on_unmount(self) -> None: - """Stop all polling threads and disconnect the device on shutdown.""" - for mode_key in MODES: - screen = self.query_one(f"#{mode_key}") - if hasattr(screen, "_polling"): - screen._polling = False - if hasattr(screen, "_monitoring"): - screen._monitoring = False + """Signal all worker threads to exit and disconnect the device.""" + self.shutdown_event.set() if self.device and hasattr(self.device, "disconnect"): self.device.disconnect() @@ -173,4 +170,11 @@ def main() -> None: app.serial_port = args.port app.firmware_name = args.firmware app.skip_init = args.skip_init - app.run() + try: + app.run() + except KeyboardInterrupt: + pass + finally: + app.shutdown_event.set() + if app.device and hasattr(app.device, "disconnect"): + app.device.disconnect() diff --git a/tui/src/birdcage_tui/screens/position.py b/tui/src/birdcage_tui/screens/position.py index 388b3c6..ca197b8 100644 --- a/tui/src/birdcage_tui/screens/position.py +++ b/tui/src/birdcage_tui/screens/position.py @@ -6,7 +6,6 @@ and AZ/EL sparklines. Bottom row provides manual move controls. """ import logging -import time from textual import work from textual.app import ComposeResult @@ -98,9 +97,10 @@ class PositionScreen(Container): @work(thread=True, exclusive=True, group="position-poll") def _do_position_poll(self) -> None: """Poll device at ~2 Hz for position and step data.""" - while self._polling: + shutdown = self.app.shutdown_event + while self._polling and not shutdown.is_set(): if self._device is None: - time.sleep(0.5) + shutdown.wait(0.5) continue try: @@ -135,7 +135,7 @@ class PositionScreen(Container): except Exception: log.debug("Torque poll failed", exc_info=True) - time.sleep(0.5) + shutdown.wait(0.5) # ------------------------------------------------------------------ # Thread-safe widget update callbacks diff --git a/tui/src/birdcage_tui/screens/scan.py b/tui/src/birdcage_tui/screens/scan.py index a194196..7be6fab 100644 --- a/tui/src/birdcage_tui/screens/scan.py +++ b/tui/src/birdcage_tui/screens/scan.py @@ -7,7 +7,6 @@ raw (az, el, rssi) data for offline analysis. import csv import logging -import time from pathlib import Path from textual import work @@ -98,6 +97,7 @@ class ScanScreen(Container): def _do_scan(self) -> None: """Execute the AZ/EL grid scan in a background thread.""" worker = get_current_worker() + shutdown = self.app.shutdown_event device = self._device if device is None: return @@ -146,7 +146,7 @@ class ScanScreen(Container): for _el_idx, el_val in enumerate(el_values): for _az_idx, az_val in enumerate(az_values): - if not self._scanning or worker.is_cancelled: + if not self._scanning or worker.is_cancelled or shutdown.is_set(): self.app.call_from_thread(self._set_status, "Scan stopped") return @@ -160,7 +160,7 @@ class ScanScreen(Container): continue # Settle time -- let the motor stop and vibrations damp. - time.sleep(0.3) + shutdown.wait(0.3) # Read signal. try: diff --git a/tui/src/birdcage_tui/screens/signal.py b/tui/src/birdcage_tui/screens/signal.py index 9b7c7e9..9a5ac27 100644 --- a/tui/src/birdcage_tui/screens/signal.py +++ b/tui/src/birdcage_tui/screens/signal.py @@ -7,7 +7,6 @@ sparklines for DVB and ADC RSSI, peak tracking, and LNA toggle. import logging import re -import time from textual import work from textual.app import ComposeResult @@ -82,9 +81,10 @@ class SignalScreen(Container): @work(thread=True, exclusive=True, group="signal-poll") def _do_signal_poll(self) -> None: """Poll RSSI at the configured rate while monitoring is active.""" - while self._monitoring: + shutdown = self.app.shutdown_event + while self._monitoring and not shutdown.is_set(): if self._device is None: - time.sleep(0.5) + shutdown.wait(0.5) continue # Read config from inputs (safe defaults on parse failure). @@ -141,7 +141,7 @@ class SignalScreen(Container): except Exception: log.debug("Lock status poll failed", exc_info=True) - time.sleep(1.0 / rate) + shutdown.wait(1.0 / rate) # ------------------------------------------------------------------ # Thread-safe widget update callbacks From 3cd6424168df8bda6393f6c73e550a965e2918f5 Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 16:40:53 -0700 Subject: [PATCH 06/30] Wire firmware-accelerated AZ sweep via azscanwxp Adds send_with_timeout() to CarryoutG2Protocol for long-running commands, and az_sweep_firmware() to both SerialBridge and DemoDevice. Sweep and Sky Map modes now try the firmware path first (single azscanwxp command, streaming results) and fall back to software step-dwell-measure on error or when "Software mode" checkbox is checked. Software sweep fixed to set EL once and move AZ only. --- src/birdcage/protocol.py | 57 +- tui/src/birdcage_tui/bridge.py | 156 ++++- tui/src/birdcage_tui/demo.py | 57 ++ tui/src/birdcage_tui/screens/signal.py | 772 +++++++++++++++++++++++-- 4 files changed, 973 insertions(+), 69 deletions(-) diff --git a/src/birdcage/protocol.py b/src/birdcage/protocol.py index c03885e..0a20d97 100644 --- a/src/birdcage/protocol.py +++ b/src/birdcage/protocol.py @@ -283,6 +283,38 @@ class CarryoutG2Protocol(FirmwareProtocol): time.sleep(0.001) # brief settle before next command return resp_data.decode("utf-8", errors="ignore") + def _probe_prompt(self) -> str: + """Send bare CR and read the prompt string. + + Returns the prompt text (e.g. ``'\\r\\nTRK>'`` or ``'\\r\\nMOT>'``). + Used to detect which submenu the firmware is in without sending + a command that could have side effects. + """ + if not self._serial: + raise RuntimeError("Not connected") + self._serial.write(b"\r") + resp = bytearray() + while True: + byte = self._serial.read(1) + if len(byte) == 0: + break # timeout — return what we have + resp.append(byte[0]) + if byte[0] == self.PROMPT_CHAR: + break + return resp.decode("utf-8", errors="ignore") + + def reset_to_root(self) -> None: + """Return to TRK> root without killing the shell. + + At TRK>, the ``q`` command terminates the UART shell entirely + (requires power cycle). This probes the current prompt first + and only sends ``q`` if we're in a submenu. + """ + prompt = self._probe_prompt() + if "TRK>" in prompt: + return # already at root + self._send("q") + def initialize(self, callback: Callable[[str], None] | None = None) -> None: """Prepare G2 for motor commands. @@ -293,22 +325,18 @@ class CarryoutG2Protocol(FirmwareProtocol): logger.info( "Initializing Carryout G2 (tracker must be pre-disabled via NVS 20)" ) - self._send("q") + self.reset_to_root() self.enter_motor_menu() logger.info("Carryout G2 initialized and ready") def enter_motor_menu(self) -> None: - self._send("q") + self.reset_to_root() self._send(self.MOTOR_COMMAND) def kill_search(self) -> None: """No-op — G2 search is disabled permanently via NVS index 20.""" logger.debug("G2 search kill is a no-op (NVS 20 disables tracker)") - def reset_to_root(self) -> None: - """Return to the firmware root menu.""" - self._send("q") - def get_position(self) -> Position: """Query dish position. @@ -351,7 +379,7 @@ class CarryoutG2Protocol(FirmwareProtocol): def enter_dvb_menu(self) -> None: """Enter DVB signal analysis submenu (must be at root menu).""" - self._send("q") # ensure root + self.reset_to_root() self._send("dvb") def enable_lna(self) -> None: @@ -392,6 +420,21 @@ class CarryoutG2Protocol(FirmwareProtocol): raise ValueError(f"Could not parse RSSI from: {response!r}") + def send_with_timeout(self, cmd: str, timeout: float = 90) -> str: + """Send a command with a custom serial timeout. + + Used for long-running firmware commands (azscanwxp, azscan) that stream + output over tens of seconds before the final prompt. + """ + if not self._serial: + raise RuntimeError("Not connected") + original = self._serial.timeout + self._serial.timeout = timeout + try: + return self._send(cmd) + finally: + self._serial.timeout = original + def send_raw(self, cmd: str) -> str: """Send arbitrary command, return raw prompt-terminated response.""" return self._send(cmd) diff --git a/tui/src/birdcage_tui/bridge.py b/tui/src/birdcage_tui/bridge.py index a90e218..6ab4a4d 100644 --- a/tui/src/birdcage_tui/bridge.py +++ b/tui/src/birdcage_tui/bridge.py @@ -66,6 +66,32 @@ class SerialBridge: self._menu = Menu.UNKNOWN self._connected = False + # ------------------------------------------------------------------ + # Menu prompt → string mapping for status display + # ------------------------------------------------------------------ + + _MENU_PROMPTS: dict[Menu, str] = { + Menu.ROOT: "TRK>", + Menu.MOT: "MOT>", + Menu.DVB: "DVB>", + Menu.NVS: "NVS>", + Menu.A3981: "A3981>", + Menu.ADC: "ADC>", + Menu.OS: "OS>", + Menu.STEP: "STEP>", + Menu.PEAK: "PEAK>", + Menu.EEPROM: "EE>", + Menu.GPIO: "GPIO>", + Menu.LATLON: "LATLON>", + Menu.DIPSWITCH: "DIPSWITCH>", + Menu.UNKNOWN: "???", + } + + @property + def current_menu(self) -> str: + """Current firmware prompt string for status display.""" + return self._MENU_PROMPTS.get(self._menu, "???") + # ------------------------------------------------------------------ # Internal helpers # ------------------------------------------------------------------ @@ -82,6 +108,21 @@ class SerialBridge: self._proto.reset_to_root() self._menu = Menu.ROOT + def _detect_menu(self) -> Menu: + """Probe firmware prompt and return the corresponding Menu enum. + + Caller must hold ``_lock``. + """ + prompt = self._proto._probe_prompt() + upper = prompt.upper() + # Check against known prompt strings (handles EE> vs EEPROM>, etc.) + for menu, prompt_str in self._MENU_PROMPTS.items(): + if menu == Menu.UNKNOWN: + continue + if prompt_str.upper() in upper: + return menu + return Menu.UNKNOWN + def _ensure_menu(self, target: Menu) -> None: """Navigate to *target* submenu if not already there. @@ -114,7 +155,7 @@ class SerialBridge: with self._lock: self._proto.connect(port, baudrate) self._connected = True - self._menu = Menu.UNKNOWN + self._menu = self._detect_menu() def disconnect(self) -> None: """Close the serial connection.""" @@ -139,7 +180,8 @@ class SerialBridge: with self._lock: if not skip_init: self._proto.initialize() - self._menu = Menu.MOT # initialize() ends in MOT> + self._menu = Menu.MOT # initialize() ends in MOT> + # else: leave _menu as whatever connect() detected # ------------------------------------------------------------------ # Motor (MOT>) @@ -296,6 +338,116 @@ class SerialBridge: return result + def get_pid_gains(self) -> dict[str, dict[str, float]]: + """Read PID gains for both motor axes. + + Firmware returns: ``Kp=600 Kv=60 Ki=1`` per motor. + + Returns: + ``{"az": {"kp": 600, "kv": 60, "ki": 1}, + "el": {"kp": 250, "kv": 50, "ki": 1}}`` + """ + with self._lock: + self._ensure_menu(Menu.MOT) + response = self._send("pid") + + # Parse "Kp=600 Kv=60 Ki=1" patterns. The pid command without args + # shows both motors. We look for two sets of Kp/Kv/Ki values. + kp_matches = re.findall(r"Kp[=:]?\s*(\d+)", response) + kv_matches = re.findall(r"Kv[=:]?\s*(\d+)", response) + ki_matches = re.findall(r"Ki[=:]?\s*(\d+)", response) + + result = { + "az": {"kp": 600.0, "kv": 60.0, "ki": 1.0}, + "el": {"kp": 250.0, "kv": 50.0, "ki": 1.0}, + } + + if len(kp_matches) >= 2: + result["az"]["kp"] = float(kp_matches[0]) + result["el"]["kp"] = float(kp_matches[1]) + elif len(kp_matches) == 1: + result["az"]["kp"] = float(kp_matches[0]) + + if len(kv_matches) >= 2: + result["az"]["kv"] = float(kv_matches[0]) + result["el"]["kv"] = float(kv_matches[1]) + elif len(kv_matches) == 1: + result["az"]["kv"] = float(kv_matches[0]) + + if len(ki_matches) >= 2: + result["az"]["ki"] = float(ki_matches[0]) + result["el"]["ki"] = float(ki_matches[1]) + elif len(ki_matches) == 1: + result["az"]["ki"] = float(ki_matches[0]) + + return result + + def set_pid_gains(self, motor_id: int, kp: float, kv: float, ki: float) -> None: + """Write PID gains for a single motor axis. + + Args: + motor_id: 0 for AZ, 1 for EL. + kp: Proportional gain. + kv: Velocity gain. + ki: Integral gain. + """ + with self._lock: + self._ensure_menu(Menu.MOT) + self._send(f"pid {motor_id} {int(kp)} {int(kv)} {int(ki)}") + + def az_sweep_firmware( + self, + start_az: float, + span: float, + step_cdeg: int, + num_xponders: int, + timeout: float = 120, + ) -> list[dict[str, float]]: + """Execute a firmware-accelerated AZ sweep via azscanwxp. + + Moves to *start_az* first, then runs the firmware sweep command which + handles motor movement and RSSI measurement atomically — no per-point + serial round-trips. + + Args: + start_az: Starting azimuth in degrees. + span: Total sweep width in degrees. + step_cdeg: Step size in centidegrees (100 = 1.00°). + num_xponders: Number of transponders to cycle per position. + timeout: Serial read timeout for the long-running command. + + Returns: + List of dicts with keys: az, rssi, lock, snr. + """ + with self._lock: + self._ensure_menu(Menu.MOT) + # Move to start position and wait for prompt. + self._send(f"a 0 {start_az}") + # Execute firmware sweep with extended timeout. + response = self._proto.send_with_timeout( + f"azscanwxp 0 {span} {step_cdeg} {num_xponders}", + timeout=timeout, + ) + + # Parse streaming output lines. + # Motor: Angle: RSSI: Lock:<0/1> SNR: + results: list[dict[str, float]] = [] + for match in re.finditer( + r"Angle:(-?\d+)\s+RSSI:(\d+)\s+Lock:(\d)\s+SNR:(-?\d+\.?\d*)", + response, + ): + results.append( + { + "az": int(match.group(1)) / 100.0, + "rssi": float(match.group(2)), + "lock": float(match.group(3)), + "snr": float(match.group(4)), + } + ) + + logger.info("Firmware sweep returned %d points", len(results)) + return results + # ------------------------------------------------------------------ # Signal (DVB>) # ------------------------------------------------------------------ diff --git a/tui/src/birdcage_tui/demo.py b/tui/src/birdcage_tui/demo.py index e86ab88..62f6e60 100644 --- a/tui/src/birdcage_tui/demo.py +++ b/tui/src/birdcage_tui/demo.py @@ -333,6 +333,53 @@ class DemoDevice: "el_steps": int(self._el * 24960 / 360), } + def get_pid_gains(self) -> dict[str, dict[str, float]]: + return { + "az": {"kp": 600.0, "kv": 60.0, "ki": 1.0}, + "el": {"kp": 250.0, "kv": 50.0, "ki": 1.0}, + } + + def set_pid_gains(self, motor_id: int, kp: float, kv: float, ki: float) -> None: + pass # No-op in demo mode. + + def az_sweep_firmware( + self, + start_az: float, + span: float, + step_cdeg: int, + num_xponders: int, + timeout: float = 120, + ) -> list[dict[str, float]]: + """Simulate a firmware azscanwxp sweep with Gaussian signal peak.""" + step_deg = step_cdeg / 100.0 + if step_deg <= 0: + step_deg = 1.0 + + results: list[dict[str, float]] = [] + az = start_az + end_az = start_az + span + while az <= end_az + 1e-9: + dist_sq = (az - _SAT_AZ) ** 2 + (self._el - _SAT_EL) ** 2 + signal = _RSSI_PEAK * math.exp(-dist_sq / _RSSI_BEAM_WIDTH) + rssi = _RSSI_NOISE_FLOOR + signal + random.gauss(0.0, 30.0) + locked = 1 if rssi > 1500 else 0 + snr = max(0.0, (rssi - _RSSI_NOISE_FLOOR) / 50.0) + random.gauss(0.0, 0.5) + results.append( + { + "az": round(az, 2), + "rssi": round(rssi), + "lock": float(locked), + "snr": round(max(0.0, snr), 1), + } + ) + az += step_deg + + # Brief delay to simulate firmware execution time. + time.sleep(0.5) + self._target_az = end_az + self._last_move_time = time.monotonic() + return results + # ------------------------------------------------------------------ # Signal (DVB>) # ------------------------------------------------------------------ @@ -530,6 +577,16 @@ class DemoDevice: az_steps = int(self._az * 40000 / 360) el_steps = int(self._el * 24960 / 360) return f"Position[0] = {az_steps} Position[1] = {el_steps}\nMOT>" + if cmd == "pid" or cmd.startswith("pid "): + parts = cmd.split() + if len(parts) == 1: + return ( + "Motor 0: Kp=600 Kv=60 Ki=1\nMotor 1: Kp=250 Kv=50 Ki=1\nMOT>" + ) + elif len(parts) >= 4: + motor_id = parts[1] + return f"PID set for motor {motor_id}\nMOT>" + return "Usage: pid [motor] [Kp] [Kv] [Ki]\nMOT>" return f"Unknown command: {cmd}\nMOT>" def _handle_dvb(self, cmd: str) -> str: diff --git a/tui/src/birdcage_tui/screens/signal.py b/tui/src/birdcage_tui/screens/signal.py index 9a5ac27..44e859e 100644 --- a/tui/src/birdcage_tui/screens/signal.py +++ b/tui/src/birdcage_tui/screens/signal.py @@ -1,83 +1,261 @@ -"""F2 Signal screen -- RSSI monitoring, sparklines, LNB control. +"""F3 Signal screen -- Find and Measure. -Widget container for ContentSwitcher. Provides start/stop signal -monitoring with configurable iteration count and poll rate, dual -sparklines for DVB and ADC RSSI, peak tracking, and LNA toggle. +Three sub-modes via ModeBar + ContentSwitcher: + + Monitor -- RSSI monitoring with dual sparklines, signal gauge, receiver info + Sweep -- 1D azimuth-vs-RSSI bar chart across an AZ range at fixed EL + Sky Map -- 2D AZ x EL grid scan with heatmap visualization and CSV export + +Merges the old Signal + Scan screens into a single tab. """ +import contextlib +import csv import logging import re +from pathlib import Path from textual import work from textual.app import ComposeResult from textual.containers import Container, Horizontal, Vertical -from textual.widgets import Button, Input, Static -from textual.worker import Worker +from textual.widgets import ( + Button, + Checkbox, + ContentSwitcher, + Input, + ProgressBar, + Static, +) +from textual.worker import Worker, get_current_worker +from birdcage_tui.widgets.mode_bar import ModeBar +from birdcage_tui.widgets.receiver_info import ReceiverInfo from birdcage_tui.widgets.signal_gauge import SignalGauge +from birdcage_tui.widgets.sky_heatmap import SkyHeatmap from birdcage_tui.widgets.sparkline_widget import SparklineWidget +from birdcage_tui.widgets.status_strip import StatusStrip +from birdcage_tui.widgets.sweep_plot import SweepPlot log = logging.getLogger(__name__) +# Type alias -- SerialBridge and DemoDevice share the same duck-typed interface. +DeviceLike = object + class SignalScreen(Container): - """F2: Signal monitoring and RSSI display.""" + """F3: Find and Measure -- signal monitoring, sweep, and sky mapping.""" def __init__(self, **kwargs) -> None: super().__init__(**kwargs) - self._device: object = None + self._device: DeviceLike | None = None + + # Monitor state self._monitoring = False self._lna_enabled = False self._peak_rssi = 0 self._total_samples = 0 self._signal_worker: Worker | None = None + self._receiver_loaded = False + + # Sweep state + self._sweeping = False + self._sweep_data: list[tuple[float, float]] = [] + + # Sky Map state + self._scanning = False + self._scan_data: list[tuple[float, float, float]] = [] + + # ------------------------------------------------------------------ + # Compose + # ------------------------------------------------------------------ def compose(self) -> ComposeResult: with Container(classes="screen-container"): - with Vertical(classes="panel"): - yield Static("Signal Strength", classes="panel-title") - yield SignalGauge(id="signal-gauge") - with Vertical(): - yield SparklineWidget( - max_points=80, label="DVB RSSI", color="#00d4aa", id="dvb-spark" - ) - yield SparklineWidget( - max_points=80, label="ADC RSSI", color="#2080d0", id="adc-spark" - ) - with Horizontal(classes="panel"): - yield Static("Samples: 0", id="sample-count", classes="label") - yield Static(" Peak: 0", id="peak-value", classes="label") - yield Static(" LNA: OFF", id="lna-status", classes="label") - yield Static(" Lock: NO", id="lock-status", classes="label") - with Horizontal(classes="bottom-controls"): - yield Static("Iters ", classes="label") - yield Input(value="10", id="iter-input", type="integer") - yield Static(" Rate ", classes="label") - yield Input(value="2", id="rate-input", type="integer") - yield Button("Start", id="btn-start", variant="primary") - yield Button("Stop", id="btn-stop") - yield Button("Enable LNA", id="btn-lna") + yield ModeBar( + modes={ + "monitor": "Monitor", + "sweep": "Sweep", + "skymap": "Sky Map", + }, + initial="monitor", + classes="mode-bar", + ) + with ContentSwitcher(id="signal-modes", initial="monitor"): + # -- Monitor mode ----------------------------------------- + with Container(id="monitor"): + with Horizontal(classes="top-row"): + with Vertical(classes="panel"): + yield Static("Signal Strength", classes="panel-title") + yield SignalGauge(id="signal-gauge") + yield SparklineWidget( + max_points=80, + label="DVB RSSI", + color="#00d4aa", + id="dvb-spark", + ) + yield SparklineWidget( + max_points=80, + label="ADC RSSI", + color="#2080d0", + id="adc-spark", + ) + with Vertical(classes="panel"): + yield Static("Receiver", classes="panel-title") + yield ReceiverInfo(id="receiver-info") + with Horizontal(classes="panel"): + yield Static("Samples: 0", id="sample-count", classes="label") + yield Static(" Peak: 0", id="peak-value", classes="label") + yield Static(" LNA: OFF", id="lna-status", classes="label") + yield Static(" Lock: NO", id="lock-status", classes="label") + with Horizontal(classes="bottom-controls"): + yield Static("Iters ", classes="label") + yield Input(value="10", id="iter-input", type="integer") + yield Static(" Rate ", classes="label") + yield Input(value="2", id="rate-input", type="integer") + yield Static(" Hz", classes="label") + yield Button("Start", id="btn-start", variant="primary") + yield Button("Stop", id="btn-stop") + yield Button("Enable LNA", id="btn-lna") + yield Button("Reset Peak", id="btn-reset-peak") + + # -- Sweep mode ------------------------------------------- + with Container(id="sweep"): + with Vertical(classes="panel"): + yield Static("AZ Sweep", classes="panel-title") + yield SweepPlot(id="sweep-plot") + with Horizontal(classes="scan-status"): + yield Static("Idle", id="sweep-status-text") + yield ProgressBar( + id="sweep-progress", total=100, show_eta=False + ) + with Horizontal(classes="bottom-controls"): + yield Static("AZ Start ", classes="label") + yield Input(value="160", id="sweep-az-start", type="number") + yield Static(" AZ End ", classes="label") + yield Input(value="220", id="sweep-az-end", type="number") + yield Static(" Step ", classes="label") + yield Input(value="1.5", id="sweep-az-step", type="number") + yield Static(" EL (fixed) ", classes="label") + yield Input(value="38.0", id="sweep-el-fixed", type="number") + yield Static(" Iters ", classes="label") + yield Input(value="10", id="sweep-iters", type="integer") + with Horizontal(classes="bottom-controls"): + yield Button( + "Start Sweep", id="btn-start-sweep", variant="primary" + ) + yield Button("Stop", id="btn-stop-sweep") + yield Button("Export CSV", id="btn-export-sweep") + yield Checkbox( + "Software mode", + id="sweep-software-mode", + value=False, + ) + + # -- Sky Map mode ----------------------------------------- + with Container(id="skymap"): + with Vertical(classes="panel"): + yield Static("Sky Scan", classes="panel-title") + yield SkyHeatmap(az_bins=40, el_bins=10, id="heatmap") + yield SparklineWidget( + max_points=80, + label="Sweep RSSI", + color="#00d4aa", + id="scan-spark", + ) + with Horizontal(classes="scan-status"): + yield Static("Idle", id="scan-status-text") + yield ProgressBar(id="scan-progress", total=100, show_eta=False) + with Horizontal(classes="bottom-controls"): + yield Static("AZ ", classes="label") + yield Input(value="160", id="scan-az-start", type="number") + yield Static("-", classes="label") + yield Input(value="220", id="scan-az-end", type="number") + yield Static(" Step ", classes="label") + yield Input(value="1.5", id="scan-az-step", type="number") + yield Static(" EL ", classes="label") + yield Input(value="18", id="scan-el-start", type="number") + yield Static("-", classes="label") + yield Input(value="65", id="scan-el-end", type="number") + yield Static(" Step ", classes="label") + yield Input(value="5.0", id="scan-el-step", type="number") + with Horizontal(classes="bottom-controls"): + yield Static("Transponders ", classes="label") + yield Input(value="3", id="xponder-input", type="integer") + yield Button( + "Start Scan", id="btn-start-scan", variant="primary" + ) + yield Button("Stop", id="btn-stop-scan") + yield Button("Export CSV", id="btn-export-scan") + yield Checkbox( + "Software mode", + id="scan-software-mode", + value=False, + ) # ------------------------------------------------------------------ # Device lifecycle # ------------------------------------------------------------------ - def set_device(self, device: object) -> None: + def set_device(self, device: DeviceLike) -> None: """Store the device reference.""" self._device = device def on_show(self) -> None: - """Called when this screen becomes visible.""" - pass # Monitoring is explicit via Start/Stop buttons. + """Load receiver info on first show (requires device).""" + if not self._receiver_loaded and self._device is not None: + self._load_receiver_info() + + def on_position_update(self, az: float, el: float) -> None: + """Called by app-level position poll. Signal screen doesn't use this.""" def on_unmount(self) -> None: - """Stop monitoring thread on teardown.""" + """Stop all workers on teardown.""" self._monitoring = False + self._sweeping = False + self._scanning = False # ------------------------------------------------------------------ - # Signal poll worker + # ModeBar switching # ------------------------------------------------------------------ + def on_mode_bar_mode_changed(self, event: ModeBar.ModeChanged) -> None: + """Switch ContentSwitcher when ModeBar selection changes.""" + switcher = self.query_one("#signal-modes", ContentSwitcher) + switcher.current = event.mode + + def switch_mode(self, mode_key: str) -> None: + """Programmatic mode switch (called by app.py for QuickActions).""" + switcher = self.query_one("#signal-modes", ContentSwitcher) + switcher.current = mode_key + # Update the ModeBar visual state to match. + mode_bar = self.query_one(ModeBar) + for btn in mode_bar.query(".mode-btn"): + btn.remove_class("active") + with contextlib.suppress(Exception): + mode_bar.query_one(f"#mode-{mode_key}").add_class("active") + + # ------------------------------------------------------------------ + # Input helpers + # ------------------------------------------------------------------ + + def _read_float(self, widget_id: str, fallback: float) -> float: + """Read a float from an Input widget, returning *fallback* on error.""" + try: + return float(self.query_one(f"#{widget_id}", Input).value) + except (ValueError, TypeError): + return fallback + + def _read_int(self, widget_id: str, fallback: int) -> int: + """Read an int from an Input widget, returning *fallback* on error.""" + try: + return int(self.query_one(f"#{widget_id}", Input).value) + except (ValueError, TypeError): + return fallback + + # ================================================================== + # MONITOR MODE + # ================================================================== + @work(thread=True, exclusive=True, group="signal-poll") def _do_signal_poll(self) -> None: """Poll RSSI at the configured rate while monitoring is active.""" @@ -117,7 +295,8 @@ class SignalScreen(Container): self.app.call_from_thread(self._update_gauge, rssi_avg, rssi_cur, reads) self.app.call_from_thread(self._push_dvb_spark, float(rssi_avg)) - self.app.call_from_thread(self._update_stats) + self.app.call_from_thread(self._update_monitor_stats) + self.app.call_from_thread(self._update_status_strip_rssi, rssi_avg) except Exception: log.debug("DVB RSSI poll failed", exc_info=True) @@ -143,9 +322,7 @@ class SignalScreen(Container): shutdown.wait(1.0 / rate) - # ------------------------------------------------------------------ - # Thread-safe widget update callbacks - # ------------------------------------------------------------------ + # -- Monitor thread-safe callbacks -- def _read_input(self, input_id: str) -> str: """Read an Input widget's value (must run on main thread).""" @@ -163,7 +340,7 @@ class SignalScreen(Container): def _push_adc_spark(self, value: float) -> None: self.query_one("#adc-spark", SparklineWidget).push(value) - def _update_stats(self) -> None: + def _update_monitor_stats(self) -> None: self.query_one("#sample-count", Static).update( f"Samples: {self._total_samples}" ) @@ -177,26 +354,17 @@ class SignalScreen(Container): label = "ON" if self._lna_enabled else "OFF" self.query_one("#lna-status", Static).update(f" LNA: {label}") - # ------------------------------------------------------------------ - # Button handlers - # ------------------------------------------------------------------ + def _update_status_strip_rssi(self, rssi_avg: int) -> None: + """Push RSSI to the app-level StatusStrip.""" + with contextlib.suppress(Exception): + self.app.query_one("#status-strip", StatusStrip).rssi = rssi_avg - def on_button_pressed(self, event: Button.Pressed) -> None: - button_id = event.button.id or "" + # -- Monitor button handlers -- - if button_id == "btn-start": - self._handle_start() - elif button_id == "btn-stop": - self._handle_stop() - elif button_id == "btn-lna": - self._handle_lna() - - def _handle_start(self) -> None: - """Start signal monitoring.""" + def _handle_monitor_start(self) -> None: if self._device is None: self.app.notify("No device connected", severity="warning") return - if self._monitoring: return @@ -207,8 +375,7 @@ class SignalScreen(Container): self.query_one("#btn-start", Button).variant = "default" self.query_one("#btn-stop", Button).variant = "warning" - def _handle_stop(self) -> None: - """Stop signal monitoring.""" + def _handle_monitor_stop(self) -> None: self._monitoring = False self.app.notify("Signal monitoring stopped") @@ -216,7 +383,6 @@ class SignalScreen(Container): self.query_one("#btn-stop", Button).variant = "default" def _handle_lna(self) -> None: - """Toggle LNA enable (sends lnbdc odu to set 13V).""" if self._device is None: self.app.notify("No device connected", severity="warning") return @@ -224,7 +390,6 @@ class SignalScreen(Container): @work(thread=True, exclusive=False, group="signal-cmd") def _do_enable_lna(self) -> None: - """Enable LNA in a worker thread (blocks on serial I/O).""" try: self._device.enable_lna() self._lna_enabled = True @@ -235,3 +400,490 @@ class SignalScreen(Container): self.app.call_from_thread( self.app.notify, "LNA enable failed", severity="error" ) + + def _handle_reset_peak(self) -> None: + self._peak_rssi = 0 + self._total_samples = 0 + self._update_monitor_stats() + self.app.notify("Peak and sample counters reset") + + @work(thread=True, exclusive=False, group="signal-cmd") + def _load_receiver_info(self) -> None: + """Fetch channel params and DVB config in a worker thread.""" + if self._device is None: + return + try: + channel = self._device.get_channel_params() + config = self._device.get_dvb_config() + self._receiver_loaded = True + self.app.call_from_thread(self._apply_receiver_info, channel, config) + except Exception: + log.debug("Receiver info load failed", exc_info=True) + + def _apply_receiver_info(self, channel: str, config: str) -> None: + self.query_one("#receiver-info", ReceiverInfo).load_data(channel, config) + + # ================================================================== + # SWEEP MODE (1D AZ scan) + # ================================================================== + + @work(thread=True) + def _do_sweep(self) -> None: + """Execute a 1D AZ sweep -- firmware-accelerated or software fallback.""" + device = self._device + if device is None: + return + + # Check if user forced software mode. + force_software = self.query_one("#sweep-software-mode", Checkbox).value + + if not force_software and hasattr(device, "az_sweep_firmware"): + try: + self._do_sweep_firmware(device) + return + except Exception: + log.warning( + "Firmware sweep failed, falling back to software", + exc_info=True, + ) + self.app.call_from_thread( + self._set_sweep_status, "Firmware sweep failed -- falling back..." + ) + + self._do_sweep_software(device) + + def _do_sweep_firmware(self, device: DeviceLike) -> None: + """Firmware-accelerated sweep via azscanwxp (runs in worker thread).""" + shutdown = self.app.shutdown_event + + az_start = self._read_float("sweep-az-start", 160.0) + az_end = self._read_float("sweep-az-end", 220.0) + az_step = self._read_float("sweep-az-step", 1.5) + el_fixed = self._read_float("sweep-el-fixed", 38.0) + iterations = self._read_int("sweep-iters", 10) + + span = az_end - az_start + if span <= 0 or az_step <= 0: + self.app.call_from_thread( + self._set_sweep_status, "Invalid sweep range -- check parameters" + ) + return + + step_cdeg = max(1, int(az_step * 100)) + + # Set EL once. + self.app.call_from_thread(self._set_sweep_status, "Setting elevation...") + device.move_motor(1, el_fixed) + + # Let EL settle briefly. + shutdown.wait(0.5) + if not self._sweeping or shutdown.is_set(): + return + + self.app.call_from_thread( + self._set_sweep_status, "Firmware scan in progress..." + ) + self.app.call_from_thread( + self._set_sweep_progress, 10, "Firmware scan in progress..." + ) + + results = device.az_sweep_firmware( + start_az=az_start, + span=span, + step_cdeg=step_cdeg, + num_xponders=iterations, + ) + + if not results: + self.app.call_from_thread( + self._set_sweep_status, "Firmware sweep returned no data" + ) + return + + # Populate the plot with all points at once. + sweep_plot = self.query_one("#sweep-plot", SweepPlot) + for pt in results: + az_val = pt["az"] + rssi = pt["rssi"] + self._sweep_data.append((az_val, rssi)) + self.app.call_from_thread(sweep_plot.add_point, az_val, rssi) + + total = len(results) + msg = f"Sweep complete -- {total} points (firmware)" + self.app.call_from_thread(self._set_sweep_progress, 100, msg) + self.app.call_from_thread( + self._set_sweep_status, f"Sweep complete -- {total} points (firmware)" + ) + + def _do_sweep_software(self, device: DeviceLike) -> None: + """Software step-dwell-measure sweep (runs in worker thread).""" + worker = get_current_worker() + shutdown = self.app.shutdown_event + + az_start = self._read_float("sweep-az-start", 160.0) + az_end = self._read_float("sweep-az-end", 220.0) + az_step = self._read_float("sweep-az-step", 1.5) + el_fixed = self._read_float("sweep-el-fixed", 38.0) + iterations = self._read_int("sweep-iters", 10) + + if az_step <= 0: + az_step = 1.0 + + # Build AZ point list. + az_values: list[float] = [] + az = az_start + while az <= az_end + 1e-9: + az_values.append(round(az, 2)) + az += az_step + + total = len(az_values) + if total == 0: + self.app.call_from_thread( + self._set_sweep_status, "No sweep points -- check parameters" + ) + return + + sweep_plot = self.query_one("#sweep-plot", SweepPlot) + + # Set EL once at start, then only move AZ per point. + try: + device.move_motor(1, el_fixed) + except Exception: + log.exception("EL move failed") + + for idx, az_val in enumerate(az_values): + if not self._sweeping or worker.is_cancelled or shutdown.is_set(): + self.app.call_from_thread(self._set_sweep_status, "Sweep stopped") + return + + # Move AZ only (EL already set). + try: + device.move_motor(0, az_val) + except Exception: + log.exception("AZ move failed at %.2f", az_val) + msg = f"Move error at AZ={az_val:.1f}" + self.app.call_from_thread(self._set_sweep_status, msg) + continue + + # Settle time. + shutdown.wait(0.3) + + # Read signal. + try: + rssi_data = device.get_rssi(iterations) + rssi = float(rssi_data.get("average", 0)) + except Exception: + log.exception("get_rssi failed at AZ=%.2f", az_val) + rssi = 0.0 + + self._sweep_data.append((az_val, rssi)) + + # Update widgets. + self.app.call_from_thread(sweep_plot.add_point, az_val, rssi) + self.app.call_from_thread(sweep_plot.set_active, az_val) + + done = idx + 1 + pct = int(done * 100 / total) + status = f"AZ={az_val:.1f} RSSI={rssi:.0f} [{done}/{total}]" + self.app.call_from_thread(self._set_sweep_progress, pct, status) + + self.app.call_from_thread( + self._set_sweep_status, f"Sweep complete -- {total} points" + ) + + # -- Sweep thread-safe callbacks -- + + def _set_sweep_status(self, text: str) -> None: + self.query_one("#sweep-status-text", Static).update(text) + + def _set_sweep_progress(self, pct: int, status_text: str) -> None: + self.query_one("#sweep-progress", ProgressBar).update(progress=pct) + self.query_one("#sweep-status-text", Static).update(status_text) + + # -- Sweep button handlers -- + + def _handle_sweep_start(self) -> None: + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + if self._sweeping: + self.app.notify("Sweep already in progress", severity="warning") + return + + sweep_plot = self.query_one("#sweep-plot", SweepPlot) + sweep_plot.clear() + self._sweep_data.clear() + self.query_one("#sweep-progress", ProgressBar).update(progress=0) + self._set_sweep_status("Starting sweep...") + + self._sweeping = True + self._do_sweep() + + def _handle_sweep_stop(self) -> None: + self._sweeping = False + self._set_sweep_status("Stopping...") + + def _export_sweep_csv(self) -> None: + if not self._sweep_data: + self.app.notify("No sweep data to export", severity="warning") + return + + output = Path("/tmp/birdcage_sweep.csv") + try: + with output.open("w", newline="") as fh: + writer = csv.writer(fh) + writer.writerow(["az", "rssi"]) + for az, rssi in self._sweep_data: + writer.writerow([f"{az:.2f}", f"{rssi:.1f}"]) + self.app.notify(f"Exported {len(self._sweep_data)} points to {output}") + except OSError as exc: + log.exception("Sweep CSV export failed") + self.app.notify(f"Export failed: {exc}", severity="error") + + # ================================================================== + # SKY MAP MODE (2D AZ x EL scan) + # ================================================================== + + @work(thread=True) + def _do_scan(self) -> None: + """Execute the AZ/EL grid scan in a background thread.""" + worker = get_current_worker() + shutdown = self.app.shutdown_event + device = self._device + if device is None: + return + + az_start = self._read_float("scan-az-start", 160.0) + az_end = self._read_float("scan-az-end", 220.0) + az_step = self._read_float("scan-az-step", 1.5) + el_start = self._read_float("scan-el-start", 18.0) + el_end = self._read_float("scan-el-end", 65.0) + el_step = self._read_float("scan-el-step", 5.0) + iterations = self._read_int("xponder-input", 3) + + if az_step <= 0: + az_step = 1.0 + if el_step <= 0: + el_step = 1.0 + + # Build the grid point lists. + el_values: list[float] = [] + el = el_start + while el <= el_end + 1e-9: + el_values.append(round(el, 2)) + el += el_step + + az_values: list[float] = [] + az = az_start + while az <= az_end + 1e-9: + az_values.append(round(az, 2)) + az += az_step + + total_points = len(el_values) * len(az_values) + if total_points == 0: + self.app.call_from_thread( + self._set_scan_status, "No grid points -- check parameters" + ) + return + + heatmap = self.query_one("#heatmap", SkyHeatmap) + spark = self.query_one("#scan-spark", SparklineWidget) + + force_software = self.query_one("#scan-software-mode", Checkbox).value + use_firmware = not force_software and hasattr(device, "az_sweep_firmware") + + done = 0 + az_span_grid = az_end - az_start + 1e-9 + el_span_grid = el_end - el_start + 1e-9 + span_deg = az_end - az_start + step_cdeg = max(1, int(az_step * 100)) + + for _el_idx, el_val in enumerate(el_values): + if not self._scanning or worker.is_cancelled or shutdown.is_set(): + self.app.call_from_thread(self._set_scan_status, "Scan stopped") + return + + # Try firmware sweep for this EL row. + if use_firmware: + try: + device.move_motor(1, el_val) + shutdown.wait(0.3) + + status = f"EL={el_val:.1f} Firmware sweep..." + self.app.call_from_thread(self._set_scan_status, status) + + results = device.az_sweep_firmware( + start_az=az_start, + span=span_deg, + step_cdeg=step_cdeg, + num_xponders=iterations, + ) + + for pt in results: + az_val = pt["az"] + rssi = pt["rssi"] + self._scan_data.append((az_val, el_val, rssi)) + + grid_az = min( + int((az_val - az_start) / az_span_grid * heatmap.az_bins), + heatmap.az_bins - 1, + ) + grid_el = min( + int((el_val - el_start) / el_span_grid * heatmap.el_bins), + heatmap.el_bins - 1, + ) + self.app.call_from_thread( + heatmap.set_point, grid_az, grid_el, rssi + ) + self.app.call_from_thread(spark.push, rssi) + + done += len(az_values) + pct = min(int(done * 100 / total_points), 100) + status = ( + f"EL={el_val:.1f} {len(results)} pts (firmware) " + f"[{done}/{total_points}]" + ) + self.app.call_from_thread(self._set_scan_progress, pct, status) + continue + + except Exception: + log.warning( + "Firmware sweep failed at EL=%.1f, falling back", + el_val, + exc_info=True, + ) + use_firmware = False # Don't retry firmware for remaining rows. + + # Software fallback: point-by-point for this EL row. + try: + device.move_motor(1, el_val) + except Exception: + log.exception("EL move failed at EL=%.2f", el_val) + + for _az_idx, az_val in enumerate(az_values): + if not self._scanning or worker.is_cancelled or shutdown.is_set(): + self.app.call_from_thread(self._set_scan_status, "Scan stopped") + return + + try: + device.move_motor(0, az_val) + except Exception: + log.exception("AZ move failed at AZ=%.2f EL=%.2f", az_val, el_val) + continue + + shutdown.wait(0.3) + + try: + rssi_data = device.get_rssi(iterations) + rssi = float(rssi_data.get("average", 0)) + except Exception: + log.exception("get_rssi failed at AZ=%.2f EL=%.2f", az_val, el_val) + rssi = 0.0 + + self._scan_data.append((az_val, el_val, rssi)) + + grid_az = min( + int((az_val - az_start) / az_span_grid * heatmap.az_bins), + heatmap.az_bins - 1, + ) + grid_el = min( + int((el_val - el_start) / el_span_grid * heatmap.el_bins), + heatmap.el_bins - 1, + ) + + self.app.call_from_thread(heatmap.set_point, grid_az, grid_el, rssi) + self.app.call_from_thread(heatmap.set_active, grid_az, grid_el) + self.app.call_from_thread(spark.push, rssi) + + done += 1 + pct = int(done * 100 / total_points) + status_text = ( + f"AZ={az_val:.1f} EL={el_val:.1f} " + f"RSSI={rssi:.0f} [{done}/{total_points}]" + ) + self.app.call_from_thread(self._set_scan_progress, pct, status_text) + + msg = f"Scan complete -- {total_points} points" + self.app.call_from_thread(self._set_scan_status, msg) + + # -- Scan thread-safe callbacks -- + + def _set_scan_status(self, text: str) -> None: + self.query_one("#scan-status-text", Static).update(text) + + def _set_scan_progress(self, pct: int, status_text: str) -> None: + self.query_one("#scan-progress", ProgressBar).update(progress=pct) + self.query_one("#scan-status-text", Static).update(status_text) + + # -- Scan button handlers -- + + def _handle_scan_start(self) -> None: + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + if self._scanning: + self.app.notify("Scan already in progress", severity="warning") + return + + heatmap = self.query_one("#heatmap", SkyHeatmap) + heatmap.clear() + self._scan_data.clear() + self.query_one("#scan-progress", ProgressBar).update(progress=0) + self._set_scan_status("Starting scan...") + + self._scanning = True + self._do_scan() + + def _handle_scan_stop(self) -> None: + self._scanning = False + self._set_scan_status("Stopping...") + + def _export_scan_csv(self) -> None: + if not self._scan_data: + self.app.notify("No scan data to export", severity="warning") + return + + output = Path("/tmp/birdcage_scan.csv") + try: + with output.open("w", newline="") as fh: + writer = csv.writer(fh) + writer.writerow(["az", "el", "rssi"]) + for az, el, rssi in self._scan_data: + writer.writerow([f"{az:.2f}", f"{el:.2f}", f"{rssi:.1f}"]) + self.app.notify(f"Exported {len(self._scan_data)} points to {output}") + except OSError as exc: + log.exception("Scan CSV export failed") + self.app.notify(f"Export failed: {exc}", severity="error") + + # ================================================================== + # Unified button dispatcher + # ================================================================== + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + + # Monitor buttons + if button_id == "btn-start": + self._handle_monitor_start() + elif button_id == "btn-stop": + self._handle_monitor_stop() + elif button_id == "btn-lna": + self._handle_lna() + elif button_id == "btn-reset-peak": + self._handle_reset_peak() + + # Sweep buttons + elif button_id == "btn-start-sweep": + self._handle_sweep_start() + elif button_id == "btn-stop-sweep": + self._handle_sweep_stop() + elif button_id == "btn-export-sweep": + self._export_sweep_csv() + + # Sky Map buttons + elif button_id == "btn-start-scan": + self._handle_scan_start() + elif button_id == "btn-stop-scan": + self._handle_scan_stop() + elif button_id == "btn-export-scan": + self._export_scan_csv() From 2ee2f472758f6849ed392faf0da2abb45f8cf84d Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 16:50:08 -0700 Subject: [PATCH 07/30] Fix sweep/scan Stop button and state cleanup _sweeping/_scanning flags were never reset when workers finished, leaving the UI stuck in "Stopping..." forever. Both _do_sweep and _do_scan now use try/finally to always clear state and reset button styles. Firmware sweep checks the flag after the blocking serial call returns and discards results if Stop was pressed mid-execution. --- tui/src/birdcage_tui/screens/signal.py | 71 ++++++++++++++++++++------ 1 file changed, 54 insertions(+), 17 deletions(-) diff --git a/tui/src/birdcage_tui/screens/signal.py b/tui/src/birdcage_tui/screens/signal.py index 44e859e..1a5ab17 100644 --- a/tui/src/birdcage_tui/screens/signal.py +++ b/tui/src/birdcage_tui/screens/signal.py @@ -434,23 +434,28 @@ class SignalScreen(Container): if device is None: return - # Check if user forced software mode. - force_software = self.query_one("#sweep-software-mode", Checkbox).value + try: + # Check if user forced software mode. + force_software = self.query_one("#sweep-software-mode", Checkbox).value - if not force_software and hasattr(device, "az_sweep_firmware"): - try: - self._do_sweep_firmware(device) - return - except Exception: - log.warning( - "Firmware sweep failed, falling back to software", - exc_info=True, - ) - self.app.call_from_thread( - self._set_sweep_status, "Firmware sweep failed -- falling back..." - ) + if not force_software and hasattr(device, "az_sweep_firmware"): + try: + self._do_sweep_firmware(device) + return + except Exception: + log.warning( + "Firmware sweep failed, falling back to software", + exc_info=True, + ) + self.app.call_from_thread( + self._set_sweep_status, + "Firmware sweep failed -- falling back...", + ) - self._do_sweep_software(device) + self._do_sweep_software(device) + finally: + self._sweeping = False + self.app.call_from_thread(self._reset_sweep_buttons) def _do_sweep_firmware(self, device: DeviceLike) -> None: """Firmware-accelerated sweep via azscanwxp (runs in worker thread).""" @@ -494,6 +499,11 @@ class SignalScreen(Container): num_xponders=iterations, ) + # Check if Stop was pressed while firmware was executing. + if not self._sweeping or shutdown.is_set(): + self.app.call_from_thread(self._set_sweep_status, "Sweep stopped") + return + if not results: self.app.call_from_thread( self._set_sweep_status, "Firmware sweep returned no data" @@ -600,6 +610,11 @@ class SignalScreen(Container): self.query_one("#sweep-progress", ProgressBar).update(progress=pct) self.query_one("#sweep-status-text", Static).update(status_text) + def _reset_sweep_buttons(self) -> None: + """Restore sweep button styles to idle state (main thread).""" + self.query_one("#btn-start-sweep", Button).variant = "primary" + self.query_one("#btn-stop-sweep", Button).variant = "default" + # -- Sweep button handlers -- def _handle_sweep_start(self) -> None: @@ -616,12 +631,16 @@ class SignalScreen(Container): self.query_one("#sweep-progress", ProgressBar).update(progress=0) self._set_sweep_status("Starting sweep...") + self.query_one("#btn-start-sweep", Button).variant = "default" + self.query_one("#btn-stop-sweep", Button).variant = "warning" + self._sweeping = True self._do_sweep() def _handle_sweep_stop(self) -> None: self._sweeping = False self._set_sweep_status("Stopping...") + self._reset_sweep_buttons() def _export_sweep_csv(self) -> None: if not self._sweep_data: @@ -647,12 +666,21 @@ class SignalScreen(Container): @work(thread=True) def _do_scan(self) -> None: """Execute the AZ/EL grid scan in a background thread.""" - worker = get_current_worker() - shutdown = self.app.shutdown_event device = self._device if device is None: return + try: + self._do_scan_inner(device) + finally: + self._scanning = False + self.app.call_from_thread(self._reset_scan_buttons) + + def _do_scan_inner(self, device: DeviceLike) -> None: + """Inner scan logic (called from _do_scan worker thread).""" + worker = get_current_worker() + shutdown = self.app.shutdown_event + az_start = self._read_float("scan-az-start", 160.0) az_end = self._read_float("scan-az-end", 220.0) az_step = self._read_float("scan-az-step", 1.5) @@ -815,6 +843,11 @@ class SignalScreen(Container): self.query_one("#scan-progress", ProgressBar).update(progress=pct) self.query_one("#scan-status-text", Static).update(status_text) + def _reset_scan_buttons(self) -> None: + """Restore scan button styles to idle state (main thread).""" + self.query_one("#btn-start-scan", Button).variant = "primary" + self.query_one("#btn-stop-scan", Button).variant = "default" + # -- Scan button handlers -- def _handle_scan_start(self) -> None: @@ -831,12 +864,16 @@ class SignalScreen(Container): self.query_one("#scan-progress", ProgressBar).update(progress=0) self._set_scan_status("Starting scan...") + self.query_one("#btn-start-scan", Button).variant = "default" + self.query_one("#btn-stop-scan", Button).variant = "warning" + self._scanning = True self._do_scan() def _handle_scan_stop(self) -> None: self._scanning = False self._set_scan_status("Stopping...") + self._reset_scan_buttons() def _export_scan_csv(self) -> None: if not self._scan_data: From c6ac958ee8eff180ff7c367d20c9c28014b5c14b Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 16:56:14 -0700 Subject: [PATCH 08/30] Make firmware sweep cancellable to prevent shutdown deadlock send_with_timeout now uses a 2s per-byte timeout with a deadline loop instead of one long blocking read, checking a cancel event between reads. SerialBridge.disconnect() sets the cancel event before acquiring the lock, so a blocked firmware sweep aborts within ~2s and releases the lock for clean port shutdown. --- src/birdcage/protocol.py | 52 ++++++++++++++++++++++++++++------ tui/src/birdcage_tui/bridge.py | 12 +++++++- 2 files changed, 55 insertions(+), 9 deletions(-) diff --git a/src/birdcage/protocol.py b/src/birdcage/protocol.py index 0a20d97..55be998 100644 --- a/src/birdcage/protocol.py +++ b/src/birdcage/protocol.py @@ -10,6 +10,7 @@ from __future__ import annotations import logging import re +import threading import time from abc import ABC, abstractmethod from collections.abc import Callable @@ -420,20 +421,55 @@ class CarryoutG2Protocol(FirmwareProtocol): raise ValueError(f"Could not parse RSSI from: {response!r}") - def send_with_timeout(self, cmd: str, timeout: float = 90) -> str: - """Send a command with a custom serial timeout. + def send_with_timeout( + self, + cmd: str, + timeout: float = 90, + cancel: threading.Event | None = None, + ) -> str: + """Send a command with a deadline-based timeout and optional cancellation. - Used for long-running firmware commands (azscanwxp, azscan) that stream - output over tens of seconds before the final prompt. + Uses a short per-byte read timeout (2s) so the cancel event can be + checked between reads. The overall deadline limits total wall-clock + time. Used for long-running firmware commands (azscanwxp, azscan) + that stream output before the final prompt. + + Args: + cmd: Command string to send. + timeout: Maximum wall-clock seconds to wait for the prompt. + cancel: Optional event; if set, the read aborts immediately. + + Raises: + InterruptedError: If *cancel* is set during the read. + TimeoutError: If the prompt is not received within *timeout*. """ if not self._serial: raise RuntimeError("Not connected") - original = self._serial.timeout - self._serial.timeout = timeout + + original_timeout = self._serial.timeout + self._serial.timeout = 2.0 # short per-byte timeout for cancel checks try: - return self._send(cmd) + self._serial.write(f"{cmd}\r".encode("ascii")) + + resp_data = bytearray() + deadline = time.monotonic() + timeout + while time.monotonic() < deadline: + if cancel and cancel.is_set(): + raise InterruptedError(f"Cancelled during: {cmd!r}") + + byte = self._serial.read(1) + if len(byte) == 0: + continue # short timeout expired, loop and check again + resp_data.append(byte[0]) + if byte[0] == self.PROMPT_CHAR: + break + else: + raise TimeoutError(f"No prompt after {timeout}s for: {cmd!r}") + + time.sleep(0.001) + return resp_data.decode("utf-8", errors="ignore") finally: - self._serial.timeout = original + self._serial.timeout = original_timeout def send_raw(self, cmd: str) -> str: """Send arbitrary command, return raw prompt-terminated response.""" diff --git a/tui/src/birdcage_tui/bridge.py b/tui/src/birdcage_tui/bridge.py index 6ab4a4d..cb126b8 100644 --- a/tui/src/birdcage_tui/bridge.py +++ b/tui/src/birdcage_tui/bridge.py @@ -63,6 +63,7 @@ class SerialBridge: def __init__(self, protocol: CarryoutG2Protocol) -> None: self._proto = protocol self._lock = threading.Lock() + self._cancel = threading.Event() self._menu = Menu.UNKNOWN self._connected = False @@ -158,13 +159,20 @@ class SerialBridge: self._menu = self._detect_menu() def disconnect(self) -> None: - """Close the serial connection.""" + """Close the serial connection. + + Signals cancellation first to unblock any long-running serial + reads (e.g. firmware sweep), then acquires the lock to close + the port cleanly. + """ + self._cancel.set() with self._lock: with contextlib.suppress(Exception): self._go_to_root() self._proto.disconnect() self._connected = False self._menu = Menu.UNKNOWN + self._cancel.clear() # reset for potential reconnect @property def is_connected(self) -> bool: @@ -424,9 +432,11 @@ class SerialBridge: # Move to start position and wait for prompt. self._send(f"a 0 {start_az}") # Execute firmware sweep with extended timeout. + # Pass cancel event so disconnect() can interrupt the read. response = self._proto.send_with_timeout( f"azscanwxp 0 {span} {step_cdeg} {num_xponders}", timeout=timeout, + cancel=self._cancel, ) # Parse streaming output lines. From 972c26b22f343bbd434c507b3a5bbd27f9b4fce8 Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 16:58:21 -0700 Subject: [PATCH 09/30] Guard finally blocks against app teardown during Ctrl+C The sweep/scan finally blocks call self.app.call_from_thread() to reset button state, but self.app raises NoActiveAppError if the Textual context is already torn down during Ctrl+C shutdown. Wrap with contextlib.suppress so the flag reset still happens. --- tui/src/birdcage_tui/screens/signal.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/tui/src/birdcage_tui/screens/signal.py b/tui/src/birdcage_tui/screens/signal.py index 1a5ab17..591db54 100644 --- a/tui/src/birdcage_tui/screens/signal.py +++ b/tui/src/birdcage_tui/screens/signal.py @@ -447,15 +447,17 @@ class SignalScreen(Container): "Firmware sweep failed, falling back to software", exc_info=True, ) - self.app.call_from_thread( - self._set_sweep_status, - "Firmware sweep failed -- falling back...", - ) + with contextlib.suppress(Exception): + self.app.call_from_thread( + self._set_sweep_status, + "Firmware sweep failed -- falling back...", + ) self._do_sweep_software(device) finally: self._sweeping = False - self.app.call_from_thread(self._reset_sweep_buttons) + with contextlib.suppress(Exception): + self.app.call_from_thread(self._reset_sweep_buttons) def _do_sweep_firmware(self, device: DeviceLike) -> None: """Firmware-accelerated sweep via azscanwxp (runs in worker thread).""" @@ -674,7 +676,8 @@ class SignalScreen(Container): self._do_scan_inner(device) finally: self._scanning = False - self.app.call_from_thread(self._reset_scan_buttons) + with contextlib.suppress(Exception): + self.app.call_from_thread(self._reset_scan_buttons) def _do_scan_inner(self, device: DeviceLike) -> None: """Inner scan logic (called from _do_scan worker thread).""" From e7e71c47d7a9933d6b9debeece5b333dc7e1ad18 Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 17:12:11 -0700 Subject: [PATCH 10/30] Wire Stop button to cancel blocked firmware sweeps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop handler now calls cancel_operation() on the device bridge, which sets a threading.Event that interrupts the 2s-timeout serial read loop in send_with_timeout(). InterruptedError is caught separately to prevent falling back to software sweep on cancel. disconnect() uses acquire(timeout=5) with force-close fallback instead of blocking lock acquisition — prevents deadlock when a stuck worker holds the serial lock during shutdown. Add 3 Textual async tests (pytest-asyncio) to verify Stop behavior: firmware sweep stop, software sweep stop, and sweep restart. --- tui/src/birdcage_tui/bridge.py | 29 ++++- tui/src/birdcage_tui/demo.py | 6 + tui/src/birdcage_tui/screens/signal.py | 17 +++ tui/tests/__init__.py | 0 tui/tests/test_sweep_stop.py | 154 +++++++++++++++++++++++++ 5 files changed, 204 insertions(+), 2 deletions(-) create mode 100644 tui/tests/__init__.py create mode 100644 tui/tests/test_sweep_stop.py diff --git a/tui/src/birdcage_tui/bridge.py b/tui/src/birdcage_tui/bridge.py index cb126b8..6998403 100644 --- a/tui/src/birdcage_tui/bridge.py +++ b/tui/src/birdcage_tui/bridge.py @@ -158,6 +158,18 @@ class SerialBridge: self._connected = True self._menu = self._detect_menu() + def cancel_operation(self) -> None: + """Signal any in-progress long-running operation to abort. + + Safe to call from any thread. The cancel event is checked every + ~2 seconds by ``send_with_timeout``. + """ + self._cancel.set() + + def clear_cancel(self) -> None: + """Reset the cancel event so future operations proceed normally.""" + self._cancel.clear() + def disconnect(self) -> None: """Close the serial connection. @@ -166,13 +178,26 @@ class SerialBridge: the port cleanly. """ self._cancel.set() - with self._lock: + if not self._lock.acquire(timeout=5): + # Lock held by dead/stuck worker — force-close the port + # so the blocked serial read raises an exception. + logger.warning("Lock acquisition timed out, force-closing port") + with contextlib.suppress(Exception): + self._proto.disconnect() + self._connected = False + self._menu = Menu.UNKNOWN + self._cancel.clear() + return + + try: with contextlib.suppress(Exception): self._go_to_root() self._proto.disconnect() self._connected = False self._menu = Menu.UNKNOWN - self._cancel.clear() # reset for potential reconnect + self._cancel.clear() + finally: + self._lock.release() @property def is_connected(self) -> bool: diff --git a/tui/src/birdcage_tui/demo.py b/tui/src/birdcage_tui/demo.py index 62f6e60..eb56673 100644 --- a/tui/src/birdcage_tui/demo.py +++ b/tui/src/birdcage_tui/demo.py @@ -261,6 +261,12 @@ class DemoDevice: self._connected = True self._menu = _DemoMenu.ROOT + def cancel_operation(self) -> None: + pass # Demo operations are instant, nothing to cancel. + + def clear_cancel(self) -> None: + pass # No cancel state in demo mode. + def disconnect(self) -> None: self._connected = False self._menu = _DemoMenu.ROOT diff --git a/tui/src/birdcage_tui/screens/signal.py b/tui/src/birdcage_tui/screens/signal.py index 591db54..a0d1d3a 100644 --- a/tui/src/birdcage_tui/screens/signal.py +++ b/tui/src/birdcage_tui/screens/signal.py @@ -442,11 +442,18 @@ class SignalScreen(Container): try: self._do_sweep_firmware(device) return + except InterruptedError: + # User cancelled via Stop or app shutdown — don't retry. + log.info("Firmware sweep cancelled") + return except Exception: log.warning( "Firmware sweep failed, falling back to software", exc_info=True, ) + # Only fall through to software if still active. + if not self._sweeping: + return with contextlib.suppress(Exception): self.app.call_from_thread( self._set_sweep_status, @@ -456,6 +463,9 @@ class SignalScreen(Container): self._do_sweep_software(device) finally: self._sweeping = False + # Clear cancel so the next sweep doesn't immediately abort. + if self._device and hasattr(self._device, "clear_cancel"): + self._device.clear_cancel() with contextlib.suppress(Exception): self.app.call_from_thread(self._reset_sweep_buttons) @@ -641,6 +651,9 @@ class SignalScreen(Container): def _handle_sweep_stop(self) -> None: self._sweeping = False + # Cancel any blocked serial operation (firmware sweep). + if self._device and hasattr(self._device, "cancel_operation"): + self._device.cancel_operation() self._set_sweep_status("Stopping...") self._reset_sweep_buttons() @@ -676,6 +689,8 @@ class SignalScreen(Container): self._do_scan_inner(device) finally: self._scanning = False + if self._device and hasattr(self._device, "clear_cancel"): + self._device.clear_cancel() with contextlib.suppress(Exception): self.app.call_from_thread(self._reset_scan_buttons) @@ -875,6 +890,8 @@ class SignalScreen(Container): def _handle_scan_stop(self) -> None: self._scanning = False + if self._device and hasattr(self._device, "cancel_operation"): + self._device.cancel_operation() self._set_scan_status("Stopping...") self._reset_scan_buttons() diff --git a/tui/tests/__init__.py b/tui/tests/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/tui/tests/test_sweep_stop.py b/tui/tests/test_sweep_stop.py new file mode 100644 index 0000000..479207a --- /dev/null +++ b/tui/tests/test_sweep_stop.py @@ -0,0 +1,154 @@ +"""Test that the sweep Stop button actually stops a sweep. + +Uses Textual's run_test() and pilot to drive the TUI in demo mode, +start a sweep, click Stop, and verify the sweep terminates. +""" + +import asyncio + +import pytest +from textual.widgets import Button + +from birdcage_tui.app import BirdcageApp + + +@pytest.mark.asyncio +async def test_sweep_stop_firmware(): + """Stop button should abort a firmware sweep and reset UI state.""" + app = BirdcageApp() + app.demo_mode = True + + async with app.run_test(size=(120, 40)) as pilot: + # Wait for app to fully mount. + await pilot.pause() + + # Navigate to Signal screen (F3). + await pilot.press("f3") + await pilot.pause() + + # Switch to Sweep mode via the mode bar. + signal = app.query_one("SignalScreen") + signal.switch_mode("sweep") + await pilot.pause() + + # Click Start Sweep. + start_btn = app.query_one("#btn-start-sweep", Button) + await pilot.click(start_btn) + + # Give the firmware sweep worker time to start and complete + # (demo mode takes ~0.5s). + await asyncio.sleep(1.0) + + # Click Stop. + stop_btn = app.query_one("#btn-stop-sweep", Button) + await pilot.click(stop_btn) + await pilot.pause() + + # Verify: _sweeping should be False. + assert not signal._sweeping, "_sweeping should be False after Stop" + + # Verify: Start button should have primary variant (ready for new sweep). + assert start_btn.variant == "primary", ( + f"Start button variant should be 'primary', got {start_btn.variant!r}" + ) + + # Take a screenshot for visual inspection. + app.save_screenshot("/tmp/birdcage_sweep_stop_test.svg") + + +@pytest.mark.asyncio +async def test_sweep_stop_during_software(): + """Stop button should abort a software sweep mid-execution.""" + app = BirdcageApp() + app.demo_mode = True + + async with app.run_test(size=(120, 40)) as pilot: + await pilot.pause() + await pilot.press("f3") + await pilot.pause() + + signal = app.query_one("SignalScreen") + signal.switch_mode("sweep") + await pilot.pause() + + # Check the "Software mode" checkbox to force slow path. + from textual.widgets import Checkbox + + sw_checkbox = app.query_one("#sweep-software-mode", Checkbox) + sw_checkbox.value = True + await pilot.pause() + + # Start sweep (software mode — takes longer per point). + start_btn = app.query_one("#btn-start-sweep", Button) + await pilot.click(start_btn) + + # Brief pause to let the worker start, but not finish. + await asyncio.sleep(0.3) + + # Click Stop while the software sweep is in progress. + stop_btn = app.query_one("#btn-stop-sweep", Button) + await pilot.click(stop_btn) + + # Wait for the worker to notice the stop flag. + await asyncio.sleep(1.0) + + # Verify: sweep stopped. + assert not signal._sweeping, "_sweeping should be False after Stop" + assert start_btn.variant == "primary" + + app.save_screenshot("/tmp/birdcage_sweep_stop_sw_test.svg") + + +@pytest.mark.asyncio +async def test_sweep_restart_after_stop(): + """After stopping, a new sweep should start without errors.""" + app = BirdcageApp() + app.demo_mode = True + + async with app.run_test(size=(120, 40)) as pilot: + await pilot.pause() + await pilot.press("f3") + await pilot.pause() + + signal = app.query_one("SignalScreen") + signal.switch_mode("sweep") + await pilot.pause() + + # Verify device is available. + assert signal._device is not None, "Device should be set after mount" + + # First sweep -- click Start and wait for completion. + start_btn = app.query_one("#btn-start-sweep", Button) + await pilot.click(start_btn) + + # Give the worker time to start. + await asyncio.sleep(0.5) + + # Poll until sweep completes. + for _ in range(40): + await asyncio.sleep(0.2) + if not signal._sweeping: + # Give one more beat for call_from_thread callbacks. + await asyncio.sleep(0.3) + break + + assert not signal._sweeping, "Sweep still running after polling" + assert len(signal._sweep_data) > 0, ( + f"First sweep should have data; " + f"device type={type(signal._device).__name__}" + ) + + # Second sweep. + await pilot.click(start_btn) + await asyncio.sleep(0.5) + + for _ in range(40): + await asyncio.sleep(0.2) + if not signal._sweeping: + await asyncio.sleep(0.3) + break + + assert not signal._sweeping + assert len(signal._sweep_data) > 0, "Second sweep should have data" + + app.save_screenshot("/tmp/birdcage_sweep_restart_test.svg") From 145763fcfb70490635842869f9da61dfa9abbf9e Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 18:04:50 -0700 Subject: [PATCH 11/30] Rebuild TUI as 4-tab layout with 10 new widgets Replace sidebar + 5-screen layout with horizontal tab bar (F1-F4) and persistent StatusStrip. Consolidate Position + Scan screens into Signal (F3) with Monitor/Sweep/Sky Map sub-modes via ModeBar. Screens: - F1 Dashboard: system health, tracking panel, quick actions, presets - F2 Control: motor tuning, compass rose, preset management - F3 Signal: RSSI monitor, 1D sweep (SweepPlot), 2D sky map (heatmap) - F4 System: NVS editor with regex filter, EEPROM, firmware info - F5 Console: push/pop overlay (no longer a tab) New widgets: StatusStrip, ModeBar, SweepPlot, QuickActions, PresetList, ReceiverInfo, MotorTuning, NvsFilter, SystemHealth, TrackingPanel. Removed: PositionScreen, ScanScreen, DeviceStatusBar (functionality absorbed into new screens and StatusStrip). App-level position poll feeds StatusStrip and active screen at ~2 Hz. Fix shared threading.Event across instances (class-level mutable default). --- tui/pyproject.toml | 68 +-- tui/src/birdcage_tui/app.py | 252 ++++++++-- tui/src/birdcage_tui/screens/console.py | 98 ++-- tui/src/birdcage_tui/screens/control.py | 451 ++++++++++++++++++ tui/src/birdcage_tui/screens/dashboard.py | 153 ++++++ tui/src/birdcage_tui/screens/position.py | 286 ----------- tui/src/birdcage_tui/screens/scan.py | 272 ----------- tui/src/birdcage_tui/screens/system.py | 271 ++++++++++- tui/src/birdcage_tui/theme.tcss | 300 +++++++++--- tui/src/birdcage_tui/widgets/__init__.py | 22 +- .../birdcage_tui/widgets/device_status_bar.py | 92 ---- tui/src/birdcage_tui/widgets/mode_bar.py | 72 +++ tui/src/birdcage_tui/widgets/motor_tuning.py | 130 +++++ tui/src/birdcage_tui/widgets/nvs_filter.py | 72 +++ tui/src/birdcage_tui/widgets/preset_list.py | 216 +++++++++ tui/src/birdcage_tui/widgets/quick_actions.py | 48 ++ tui/src/birdcage_tui/widgets/receiver_info.py | 156 ++++++ tui/src/birdcage_tui/widgets/status_strip.py | 111 +++++ tui/src/birdcage_tui/widgets/sweep_plot.py | 157 ++++++ tui/src/birdcage_tui/widgets/system_health.py | 195 ++++++++ .../birdcage_tui/widgets/tracking_panel.py | 164 +++++++ tui/tests/test_sweep_stop.py | 3 +- tui/uv.lock | 72 ++- 23 files changed, 2796 insertions(+), 865 deletions(-) create mode 100644 tui/src/birdcage_tui/screens/control.py create mode 100644 tui/src/birdcage_tui/screens/dashboard.py delete mode 100644 tui/src/birdcage_tui/screens/position.py delete mode 100644 tui/src/birdcage_tui/screens/scan.py delete mode 100644 tui/src/birdcage_tui/widgets/device_status_bar.py create mode 100644 tui/src/birdcage_tui/widgets/mode_bar.py create mode 100644 tui/src/birdcage_tui/widgets/motor_tuning.py create mode 100644 tui/src/birdcage_tui/widgets/nvs_filter.py create mode 100644 tui/src/birdcage_tui/widgets/preset_list.py create mode 100644 tui/src/birdcage_tui/widgets/quick_actions.py create mode 100644 tui/src/birdcage_tui/widgets/receiver_info.py create mode 100644 tui/src/birdcage_tui/widgets/status_strip.py create mode 100644 tui/src/birdcage_tui/widgets/sweep_plot.py create mode 100644 tui/src/birdcage_tui/widgets/system_health.py create mode 100644 tui/src/birdcage_tui/widgets/tracking_panel.py diff --git a/tui/pyproject.toml b/tui/pyproject.toml index 85f6d7e..1e7dab8 100644 --- a/tui/pyproject.toml +++ b/tui/pyproject.toml @@ -1,31 +1,37 @@ -[build-system] -requires = ["hatchling"] -build-backend = "hatchling.build" - -[project] -name = "birdcage-tui" -version = "2026.02.13" -description = "Textual TUI for Winegard Carryout G2 satellite dish control" -license = "MIT" -requires-python = ">=3.11" -authors = [{name = "Ryan Malloy", email = "ryan@supported.systems"}] -dependencies = [ - "birdcage", - "textual>=1.0.0", -] - -[project.scripts] -birdcage-tui = "birdcage_tui.app:main" - -[tool.uv.sources] -birdcage = { path = ".." } - -[tool.ruff] -target-version = "py311" -src = ["src"] - -[tool.ruff.lint] -select = ["E", "F", "I", "UP", "B", "SIM"] - -[tool.hatch.build.targets.wheel] -packages = ["src/birdcage_tui"] +[build-system] +requires = ["hatchling"] +build-backend = "hatchling.build" + +[project] +name = "birdcage-tui" +version = "2026.02.13" +description = "Textual TUI for Winegard Carryout G2 satellite dish control" +license = "MIT" +requires-python = ">=3.11" +authors = [{name = "Ryan Malloy", email = "ryan@supported.systems"}] +dependencies = [ + "birdcage", + "textual>=1.0.0", +] + +[project.scripts] +birdcage-tui = "birdcage_tui.app:main" + +[tool.uv.sources] +birdcage = { path = "..", editable = true } + +[tool.ruff] +target-version = "py311" +src = ["src"] + +[tool.ruff.lint] +select = ["E", "F", "I", "UP", "B", "SIM"] + +[tool.hatch.build.targets.wheel] +packages = ["src/birdcage_tui"] + +[dependency-groups] +dev = [ + "pytest>=9.0.2", + "pytest-asyncio>=1.3.0", +] diff --git a/tui/src/birdcage_tui/app.py b/tui/src/birdcage_tui/app.py index 87f03f8..07a2650 100644 --- a/tui/src/birdcage_tui/app.py +++ b/tui/src/birdcage_tui/app.py @@ -1,33 +1,35 @@ """Birdcage TUI — main application shell. -ContentSwitcher-based layout with sidebar navigation (F1-F5), -device status bar, and five swappable screen panels. +Horizontal tab bar (F1-F4) with persistent StatusStrip, ContentSwitcher +for four task-oriented screens, and F5 console overlay. App-level position +polling feeds the StatusStrip regardless of which tab is active. """ import argparse +import contextlib import logging import threading +from textual import work from textual.app import App, ComposeResult from textual.binding import Binding -from textual.containers import Horizontal, Vertical -from textual.widgets import Button, ContentSwitcher, Footer, Header, Static +from textual.containers import Horizontal +from textual.widgets import Button, ContentSwitcher, Footer, Header -from birdcage_tui.screens.console import ConsoleScreen -from birdcage_tui.screens.position import PositionScreen -from birdcage_tui.screens.scan import ScanScreen +from birdcage_tui.screens.console import ConsoleOverlay +from birdcage_tui.screens.control import ControlScreen +from birdcage_tui.screens.dashboard import DashboardScreen from birdcage_tui.screens.signal import SignalScreen from birdcage_tui.screens.system import SystemScreen -from birdcage_tui.widgets.device_status_bar import DeviceStatusBar +from birdcage_tui.widgets.status_strip import StatusStrip log = logging.getLogger(__name__) -MODES: dict[str, tuple[str, type]] = { - "position": ("F1 Position", PositionScreen), - "signal": ("F2 Signal", SignalScreen), - "scan": ("F3 Scan", ScanScreen), +TABS: dict[str, tuple[str, type]] = { + "dashboard": ("F1 Dashboard", DashboardScreen), + "control": ("F2 Control", ControlScreen), + "signal": ("F3 Signal", SignalScreen), "system": ("F4 System", SystemScreen), - "console": ("F5 Console", ConsoleScreen), } @@ -38,11 +40,11 @@ class BirdcageApp(App): CSS_PATH = "theme.tcss" BINDINGS = [ - Binding("f1", "switch_mode('position')", "Position"), - Binding("f2", "switch_mode('signal')", "Signal"), - Binding("f3", "switch_mode('scan')", "Scan"), - Binding("f4", "switch_mode('system')", "System"), - Binding("f5", "switch_mode('console')", "Console"), + Binding("f1", "switch_tab('dashboard')", "Dashboard"), + Binding("f2", "switch_tab('control')", "Control"), + Binding("f3", "switch_tab('signal')", "Signal"), + Binding("f4", "switch_tab('system')", "System"), + Binding("f5", "toggle_console", "Console"), Binding("q", "quit", "Quit"), Binding("d", "toggle_dark", "Dark"), ] @@ -55,6 +57,13 @@ class BirdcageApp(App): device: object = None shutdown_event: threading.Event = threading.Event() + # App-level position cache (updated by background poll). + _current_az: float = 0.0 + _current_el: float = 0.0 + _prev_az: float = 0.0 + _prev_el: float = 0.0 + _console_visible: bool = False + @property def SUB_TITLE(self) -> str: # noqa: N802 if self.demo_mode: @@ -63,22 +72,25 @@ class BirdcageApp(App): def compose(self) -> ComposeResult: yield Header() - with Horizontal(id="main-area"): - with Vertical(id="sidebar"): - yield Static("\U0001f6f0\ufe0f Birdcage", classes="sidebar-title") - yield Static("Carryout G2", classes="sidebar-subtitle") - for mode_key, (label, _) in MODES.items(): - yield Button(label, id=f"btn-{mode_key}", classes="sidebar-btn") - yield DeviceStatusBar(id="device-status") - with ContentSwitcher(id="content-area", initial="position"): - for mode_key, (_, screen_cls) in MODES.items(): - yield screen_cls(id=mode_key) + yield StatusStrip(id="status-strip") + with Horizontal(id="tab-bar"): + for tab_key, (label, _) in TABS.items(): + yield Button(label, id=f"tab-{tab_key}", classes="tab-btn") + with ContentSwitcher(id="content-area", initial="dashboard"): + for tab_key, (_, screen_cls) in TABS.items(): + yield screen_cls(id=tab_key) yield Footer() def on_mount(self) -> None: - self.query_one("#btn-position").add_class("active") + # Fresh event per instance — class-level default is shared across instances. + self.shutdown_event = threading.Event() + self.query_one("#tab-dashboard").add_class("active") self._setup_device() + # ------------------------------------------------------------------ + # Device lifecycle + # ------------------------------------------------------------------ + def _setup_device(self) -> None: """Create device (demo or real) and hand it to each screen.""" if self.demo_mode: @@ -98,6 +110,9 @@ class BirdcageApp(App): self.run_worker(self._initialize_device, thread=True) self._distribute_device() + self._update_status_strip_connection() + self._install_console() + self._start_position_poll() async def _initialize_device(self) -> None: """Run device init in a worker thread (blocks on serial I/O).""" @@ -109,44 +124,176 @@ class BirdcageApp(App): def _distribute_device(self) -> None: """Pass the device reference to every screen that wants it.""" - for mode_key in MODES: - screen = self.query_one(f"#{mode_key}") + for tab_key in TABS: + screen = self.query_one(f"#{tab_key}") if hasattr(screen, "set_device"): screen.set_device(self.device) - status_bar = self.query_one("#device-status", DeviceStatusBar) - if hasattr(status_bar, "set_device"): - status_bar.set_device(self.device) + def _update_status_strip_connection(self) -> None: + """Set the status strip's connection info from current device.""" + strip = self.query_one("#status-strip", StatusStrip) + is_demo = type(self.device).__name__ == "DemoDevice" if self.device else False + strip.demo = is_demo or self.demo_mode + strip.connected = ( + self.device is not None + and getattr(self.device, "is_connected", False) + and not strip.demo + ) + strip.port = self.serial_port - def action_switch_mode(self, mode: str) -> None: - """Switch the content area to *mode* and update sidebar highlight.""" + def _install_console(self) -> None: + """Pre-install the console overlay so it persists across open/close.""" + self.install_screen(ConsoleOverlay(), name="console-overlay") + + # ------------------------------------------------------------------ + # App-level position poll + # ------------------------------------------------------------------ + + @work(thread=True, exclusive=True, group="app-position-poll") + def _start_position_poll(self) -> None: + """Poll device at ~2 Hz for position, update StatusStrip globally.""" + shutdown = self.shutdown_event + while not shutdown.is_set(): + if self.device is None: + shutdown.wait(0.5) + continue + + try: + pos = self.device.get_position() + az = pos["azimuth"] + el = pos["elevation"] + self._current_az = az + self._current_el = el + self.call_from_thread(self._update_position, az, el) + except Exception: + log.debug("App position poll failed", exc_info=True) + + shutdown.wait(0.5) + + def _update_position(self, az: float, el: float) -> None: + """Push position to StatusStrip and active screen.""" + strip = self.query_one("#status-strip", StatusStrip) + strip.azimuth = az + strip.elevation = el + + # Detect movement from position delta + delta = abs(az - self._prev_az) + abs(el - self._prev_el) + if delta > 0.05: + strip.motor_state = "MOVING" + else: + strip.motor_state = "IDLE" + self._prev_az = az + self._prev_el = el + + # Notify active screen switcher = self.query_one("#content-area", ContentSwitcher) - switcher.current = mode + if switcher.current: + try: + active = self.query_one(f"#{switcher.current}") + if hasattr(active, "on_position_update"): + active.on_position_update(az, el) + except Exception: + pass - for btn in self.query(".sidebar-btn"): + # ------------------------------------------------------------------ + # Tab switching + # ------------------------------------------------------------------ + + def action_switch_tab(self, tab: str) -> None: + """Switch the content area to *tab* and update tab bar highlight.""" + switcher = self.query_one("#content-area", ContentSwitcher) + switcher.current = tab + + for btn in self.query(".tab-btn"): btn.remove_class("active") - self.query_one(f"#btn-{mode}").add_class("active") + self.query_one(f"#tab-{tab}").add_class("active") - screen = self.query_one(f"#{mode}") + screen = self.query_one(f"#{tab}") if hasattr(screen, "on_show"): screen.on_show() + # ------------------------------------------------------------------ + # Console overlay + # ------------------------------------------------------------------ + + def action_toggle_console(self) -> None: + """Push or pop the console overlay.""" + if self._console_visible: + # Pop the console -- dismiss triggers the callback + try: + self.pop_screen() + except Exception: + self._console_visible = False + else: + self.push_screen("console-overlay", callback=self._on_console_dismissed) + self._console_visible = True + + def _on_console_dismissed(self, _result=None) -> None: + """Called when the console overlay is dismissed.""" + self._console_visible = False + + # ------------------------------------------------------------------ + # Tab bar button handling + # ------------------------------------------------------------------ + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + if button_id.startswith("tab-"): + tab = button_id.removeprefix("tab-") + if tab in TABS: + self.action_switch_tab(tab) + + # ------------------------------------------------------------------ + # QuickActions navigation (from Dashboard) + # ------------------------------------------------------------------ + + def on_quick_actions_action_selected(self, event) -> None: + """Handle navigation requests from the Dashboard's quick actions.""" + action = event.action + if action == "point": + self.action_switch_tab("control") + elif action == "monitor": + self.action_switch_tab("signal") + elif action == "scan": + self.action_switch_tab("signal") + # Tell the signal screen to switch to skymap mode + try: + signal_screen = self.query_one("#signal") + if hasattr(signal_screen, "switch_mode"): + signal_screen.switch_mode("skymap") + except Exception: + pass + elif action == "stow": + self._do_stow() + + def _do_stow(self) -> None: + """Move dish to stow position (0, 65).""" + if self.device is None: + self.notify("No device connected", severity="warning") + return + self.notify("Stowing dish to AZ=0 EL=65...", severity="information") + self._run_stow() + + @work(thread=True) + def _run_stow(self) -> None: + """Execute stow in a worker thread.""" + try: + self.device.move_to(0.0, 65.0) + self.call_from_thread(self.notify, "Stow command sent") + except Exception: + log.exception("Stow failed") + self.call_from_thread(self.notify, "Stow failed", severity="error") + + # ------------------------------------------------------------------ + # Lifecycle + # ------------------------------------------------------------------ + def on_unmount(self) -> None: """Signal all worker threads to exit and disconnect the device.""" self.shutdown_event.set() if self.device and hasattr(self.device, "disconnect"): self.device.disconnect() - def action_toggle_dark(self) -> None: - self.dark = not self.dark - - def on_button_pressed(self, event: Button.Pressed) -> None: - button_id = event.button.id or "" - if button_id.startswith("btn-"): - mode = button_id.removeprefix("btn-") - if mode in MODES: - self.action_switch_mode(mode) - def main() -> None: parser = argparse.ArgumentParser( @@ -176,5 +323,6 @@ def main() -> None: pass finally: app.shutdown_event.set() - if app.device and hasattr(app.device, "disconnect"): - app.device.disconnect() + with contextlib.suppress(Exception): + if app.device and hasattr(app.device, "disconnect"): + app.device.disconnect() diff --git a/tui/src/birdcage_tui/screens/console.py b/tui/src/birdcage_tui/screens/console.py index 2c1e22d..2f4d213 100644 --- a/tui/src/birdcage_tui/screens/console.py +++ b/tui/src/birdcage_tui/screens/console.py @@ -1,12 +1,17 @@ -"""F5 Console Screen -- raw serial terminal with color-coded prompts -and command history.""" +"""Console overlay -- raw serial terminal as a slide-up ModalScreen. + +Pushed via F5, dismissed via Escape or F5 again. Preserves command +history across open/close cycles when installed via install_screen(). +""" import re from textual import work from textual.app import ComposeResult +from textual.binding import Binding from textual.containers import Container, Horizontal from textual.events import Key +from textual.screen import ModalScreen from textual.widgets import Button, Input, Static from birdcage_tui.widgets.serial_log import SerialLog @@ -27,8 +32,7 @@ _KNOWN_PROMPTS = [ "DIPSWITCH>", ] -# Pattern to detect NVS write commands: "nvs" ... "e " -# or just "e " when already in the NVS submenu. +# Pattern to detect NVS write commands. _NVS_WRITE_RE = re.compile(r"e\s+\d+\s+\S+") @@ -44,20 +48,29 @@ def _detect_prompt(text: str) -> str | None: return last_prompt -class ConsoleScreen(Container): - """F5: Raw serial console for direct firmware interaction.""" +class ConsoleOverlay(ModalScreen): + """F5: Raw serial console as a slide-up overlay. - def __init__(self, **kwargs) -> None: - super().__init__(**kwargs) - self._device: object | None = None + Slides up from the bottom of the terminal, taking ~50% of the viewport. + The active screen remains visible (dimmed) above. Dismissed by Escape or F5. + """ + + BINDINGS = [ + Binding("escape", "dismiss_overlay", "Close", priority=True), + Binding("f5", "dismiss_overlay", "Close", priority=True), + ] + + def __init__(self) -> None: + super().__init__() self._command_history: list[str] = [] self._history_idx: int = 0 self._cmd_count: int = 0 self._prompt_ctx: str = "TRK>" self._last_dangerous_cmd: str | None = None + self._welcomed = False def compose(self) -> ComposeResult: - with Container(classes="screen-container"): + with Container(id="console-overlay"): yield SerialLog(id="serial-log") with Horizontal(classes="console-context"): yield Static("Context: TRK>", id="console-context") @@ -67,29 +80,43 @@ class ConsoleScreen(Container): yield Input(placeholder="Enter command...", id="console-input") yield Button("Send", id="btn-send", variant="primary") - def set_device(self, device: object) -> None: - """Store the device reference and show a welcome message.""" - self._device = device + def on_mount(self) -> None: + """Show welcome message on first mount.""" + if not self._welcomed: + self._show_welcome() + self._welcomed = True + self.query_one("#console-input", Input).focus() + def on_screen_resume(self) -> None: + """Re-focus input when the overlay is re-opened.""" + self.query_one("#console-input", Input).focus() + + def _show_welcome(self) -> None: + """Display connection info in the serial log.""" serial_log = self.query_one("#serial-log", SerialLog) + device = self.app.device if hasattr(self.app, "device") else None - # Determine connection description. - if hasattr(device, "demo_mode") or type(device).__name__ == "DemoDevice": - mode_label = "DEMO" + if device is not None: + is_demo = type(device).__name__ == "DemoDevice" + mode_label = "DEMO" if is_demo else "Live" else: - mode_label = getattr(device, "firmware_name", "Live") + mode_label = "No device" - port = getattr(self.app, "serial_port", "/dev/ttyUSB0") if self.app else "---" + port = getattr(self.app, "serial_port", "---") serial_log.append_output("Birdcage Console -- type ? for help") serial_log.append_output(f"Connected to: {mode_label} / {port}") - def _check_dangerous(self, cmd: str) -> str | None: - """Return a warning message if the command is dangerous, or None if safe. + def action_dismiss_overlay(self) -> None: + """Close the console overlay.""" + self.dismiss() - If the same dangerous command is sent twice in a row, allow it through - (the user is insisting). - """ + # ------------------------------------------------------------------ + # Safety checks + # ------------------------------------------------------------------ + + def _check_dangerous(self, cmd: str) -> str | None: + """Return a warning if the command is dangerous, or None if safe.""" stripped = cmd.strip() lower = stripped.lower() @@ -121,8 +148,12 @@ class ConsoleScreen(Container): return warning + # ------------------------------------------------------------------ + # Command dispatch + # ------------------------------------------------------------------ + def _do_send(self, cmd_text: str) -> None: - """Validate and dispatch a command. Called on Enter or Send button.""" + """Validate and dispatch a command.""" cmd_text = cmd_text.strip() if not cmd_text: return @@ -141,23 +172,24 @@ class ConsoleScreen(Container): serial_log = self.query_one("#serial-log", SerialLog) serial_log.append_command(cmd_text) - # Clear input right away so the user can type while waiting. + # Clear input. self.query_one("#console-input", Input).value = "" - # Dispatch to worker thread (serial I/O blocks). + # Dispatch to worker thread. self._send_command(cmd_text) @work(thread=True) def _send_command(self, cmd: str) -> None: """Send the command over serial and update the UI with the response.""" - if self._device is None: + device = self.app.device if hasattr(self.app, "device") else None + if device is None: self.app.call_from_thread( self.notify, "No device connected", severity="error" ) return try: - response = self._device.send_raw(cmd) + response = device.send_raw(cmd) except Exception as exc: self.app.call_from_thread(self._on_response, f"ERROR: {exc}", cmd) return @@ -176,6 +208,15 @@ class ConsoleScreen(Container): ctx_label = self.query_one("#console-context", Static) ctx_label.update(f"Context: {self._prompt_ctx}") + # Update the app-level StatusStrip menu indicator + from birdcage_tui.widgets.status_strip import StatusStrip + + try: + strip = self.app.query_one("#status-strip", StatusStrip) + strip.fw_menu = self._prompt_ctx + except Exception: + pass + # Update command count. self._cmd_count += 1 count_label = self.query_one("#console-cmd-count", Static) @@ -200,7 +241,6 @@ class ConsoleScreen(Container): """Handle up/down arrow keys for command history navigation.""" cmd_input = self.query_one("#console-input", Input) - # Only respond when the input widget has focus. if not cmd_input.has_focus: return diff --git a/tui/src/birdcage_tui/screens/control.py b/tui/src/birdcage_tui/screens/control.py new file mode 100644 index 0000000..c8e32e5 --- /dev/null +++ b/tui/src/birdcage_tui/screens/control.py @@ -0,0 +1,451 @@ +"""F2 Control screen -- Point My Dish with Manual, Presets, and Track sub-modes. + +Three-mode layout driven by a ModeBar and ContentSwitcher. Manual mode provides +compass rose, motor status, sparklines, and move/home/engage controls. Presets +mode manages saved AZ/EL targets. Track mode wraps the rotctld server lifecycle. +""" + +import contextlib +import logging + +from textual import work +from textual.app import ComposeResult +from textual.binding import Binding +from textual.containers import Container, Horizontal, Vertical +from textual.widgets import Button, ContentSwitcher, Input, Static +from textual.worker import Worker + +from birdcage_tui.widgets.compass_rose import CompassRose +from birdcage_tui.widgets.mode_bar import ModeBar +from birdcage_tui.widgets.motor_status import MotorStatus +from birdcage_tui.widgets.preset_list import PresetList +from birdcage_tui.widgets.sparkline_widget import SparklineWidget +from birdcage_tui.widgets.tracking_panel import TrackingPanel + +log = logging.getLogger(__name__) + + +class ControlScreen(Container): + """F2: Point My Dish -- Manual / Presets / Track sub-modes.""" + + can_focus = True + + BINDINGS = [ + Binding("left", "nudge_az(-1)", "AZ -1", show=False), + Binding("right", "nudge_az(1)", "AZ +1", show=False), + Binding("up", "nudge_el(1)", "EL +1", show=False), + Binding("down", "nudge_el(-1)", "EL -1", show=False), + Binding("h", "home_both", "Home Both", show=False), + Binding("e", "engage_motors", "Engage", show=False), + Binding("r", "release_motors", "Release", show=False), + ] + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._device: object = None + self._polling = False + self._engaged = False + self._poll_worker: Worker | None = None + self._last_az = 180.0 + self._last_el = 45.0 + + # ------------------------------------------------------------------ + # Compose + # ------------------------------------------------------------------ + + def compose(self) -> ComposeResult: + with Container(classes="screen-container"): + yield ModeBar( + modes={ + "manual": "Manual", + "presets": "Presets", + "track": "Track", + }, + initial="manual", + classes="mode-bar", + ) + with ContentSwitcher(id="control-modes", initial="manual"): + # -- Manual mode -- + with Container(id="manual"): + with Horizontal(classes="top-row"): + yield CompassRose(id="ctrl-compass") + with Vertical(classes="panel"): + yield Static("Motor Status", classes="panel-title") + yield MotorStatus(id="ctrl-motor-status") + with Vertical(): + yield SparklineWidget( + max_points=80, + label="AZ", + color="#00d4aa", + id="ctrl-az-spark", + ) + yield SparklineWidget( + max_points=80, + label="EL", + color="#00b8c8", + id="ctrl-el-spark", + ) + with Horizontal(classes="bottom-controls"): + yield Static("AZ ", classes="label") + yield Input( + placeholder="180.0", + id="ctrl-az-input", + type="number", + ) + yield Static(" EL ", classes="label") + yield Input( + placeholder="45.0", + id="ctrl-el-input", + type="number", + ) + yield Button("Move", id="btn-ctrl-move", variant="primary") + with Horizontal(classes="bottom-controls"): + yield Button("Home AZ", id="btn-ctrl-home-az") + yield Button("Home EL", id="btn-ctrl-home-el") + yield Button("E/R", id="btn-ctrl-engage") + + # -- Presets mode -- + with Container(id="presets"), Horizontal(classes="top-row"): + yield PresetList(id="ctrl-preset-list") + with Vertical(classes="panel"): + yield Static("Current Position", classes="panel-title") + yield CompassRose(id="ctrl-preset-compass") + + # -- Track mode -- + with Container(id="track"), Vertical(classes="panel"): + yield Static("Satellite Tracking", classes="panel-title") + yield TrackingPanel(id="ctrl-tracking-panel") + + # ------------------------------------------------------------------ + # Device lifecycle + # ------------------------------------------------------------------ + + def set_device(self, device: object) -> None: + """Store the device reference and start the data poll.""" + self._device = device + self._start_data_poll() + + def on_show(self) -> None: + """Resume polling when this screen becomes visible.""" + if self._device is not None and not self._polling: + self._start_data_poll() + + def on_unmount(self) -> None: + """Stop polling thread on teardown.""" + self._polling = False + + # ------------------------------------------------------------------ + # Mode switching + # ------------------------------------------------------------------ + + def on_mode_bar_mode_changed(self, event: ModeBar.ModeChanged) -> None: + """Switch the ContentSwitcher when the ModeBar selection changes.""" + switcher = self.query_one("#control-modes", ContentSwitcher) + switcher.current = event.mode + + def switch_mode(self, mode_key: str) -> None: + """Programmatically switch to a sub-mode (called by app.py).""" + switcher = self.query_one("#control-modes", ContentSwitcher) + switcher.current = mode_key + # Update ModeBar button highlight + mode_bar = self.query_one(ModeBar) + for btn in mode_bar.query(".mode-btn"): + btn.remove_class("active") + with contextlib.suppress(Exception): + mode_bar.query_one(f"#mode-{mode_key}").add_class("active") + + # ------------------------------------------------------------------ + # Position updates (called by app-level poll) + # ------------------------------------------------------------------ + + def on_position_update(self, az: float, el: float) -> None: + """Push position to compass roses, sparklines, and internal cache.""" + self._last_az = az + self._last_el = el + + # Manual mode compass + try: + compass = self.query_one("#ctrl-compass", CompassRose) + compass.azimuth = az + compass.elevation = el + except Exception: + pass + + # Presets mode compass + try: + preset_compass = self.query_one("#ctrl-preset-compass", CompassRose) + preset_compass.azimuth = az + preset_compass.elevation = el + except Exception: + pass + + # Sparklines + try: + self.query_one("#ctrl-az-spark", SparklineWidget).push(az) + self.query_one("#ctrl-el-spark", SparklineWidget).push(el) + except Exception: + pass + + # ------------------------------------------------------------------ + # Data poll worker (step positions + torque) + # ------------------------------------------------------------------ + + def _start_data_poll(self) -> None: + """Kick off the background data poll for motor status.""" + self._polling = True + self._poll_worker = self._do_data_poll() + + @work(thread=True, exclusive=True, group="control-data-poll") + def _do_data_poll(self) -> None: + """Poll step positions and torque at ~2 Hz while active.""" + shutdown = self.app.shutdown_event + while self._polling and not shutdown.is_set(): + if self._device is None: + shutdown.wait(0.5) + continue + + # Step positions + try: + steps = self._device.get_step_positions() + self.app.call_from_thread( + self._update_motor_steps, + steps["az_steps"], + steps["el_steps"], + ) + except Exception: + log.debug("Step position poll failed", exc_info=True) + + # Torque state from A3981 + try: + torque_resp = self._device.get_a3981_torque() + az_torque = "HIGH" if "AZ Torq:HIGH" in torque_resp else "LOW" + el_torque = "HIGH" if "EL Torq:HIGH" in torque_resp else "LOW" + self.app.call_from_thread(self._update_torque, az_torque, el_torque) + except Exception: + log.debug("Torque poll failed", exc_info=True) + + shutdown.wait(0.5) + + # ------------------------------------------------------------------ + # Thread-safe widget update callbacks + # ------------------------------------------------------------------ + + def _update_motor_steps(self, az_steps: int, el_steps: int) -> None: + try: + motor = self.query_one("#ctrl-motor-status", MotorStatus) + motor.az_steps = az_steps + motor.el_steps = el_steps + except Exception: + pass + + def _update_torque(self, az_torque: str, el_torque: str) -> None: + try: + motor = self.query_one("#ctrl-motor-status", MotorStatus) + motor.az_torque = az_torque + motor.el_torque = el_torque + except Exception: + pass + + def _update_engaged(self, engaged: bool) -> None: + try: + motor = self.query_one("#ctrl-motor-status", MotorStatus) + motor.engaged = engaged + except Exception: + pass + + # ------------------------------------------------------------------ + # Button handlers + # ------------------------------------------------------------------ + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + + if button_id == "btn-ctrl-move": + self._handle_move() + elif button_id == "btn-ctrl-home-az": + self._handle_home(0) + elif button_id == "btn-ctrl-home-el": + self._handle_home(1) + elif button_id == "btn-ctrl-engage": + self._handle_engage_toggle() + + def _handle_move(self) -> None: + """Read AZ/EL inputs and issue a move command.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + + az_input = self.query_one("#ctrl-az-input", Input) + el_input = self.query_one("#ctrl-el-input", Input) + + try: + az = float(az_input.value) if az_input.value.strip() else self._last_az + except ValueError: + self.app.notify("Invalid AZ value", severity="warning") + return + + try: + el = float(el_input.value) if el_input.value.strip() else self._last_el + except ValueError: + self.app.notify("Invalid EL value", severity="warning") + return + + self.app.notify(f"Moving to AZ={az:.1f} EL={el:.1f}", severity="information") + self._run_motor_command(self._device.move_to, az, el) + + def _handle_home(self, motor_id: int) -> None: + """Home a specific motor axis.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + axis = "AZ" if motor_id == 0 else "EL" + self.app.notify(f"Homing {axis}...", severity="information") + self._run_motor_command(self._device.home_motor, motor_id) + + def _handle_engage_toggle(self) -> None: + """Toggle motor engage/release state.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + + if self._engaged: + self._run_motor_command(self._device.release) + self._engaged = False + self._update_engaged(False) + self.app.notify("Motors released") + else: + self._run_motor_command(self._device.engage) + self._engaged = True + self._update_engaged(True) + self.app.notify("Motors engaged") + + # ------------------------------------------------------------------ + # Preset handlers + # ------------------------------------------------------------------ + + def on_preset_list_go_to_preset(self, event: PresetList.GoToPreset) -> None: + """Move dish to the selected preset's AZ/EL.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + + az = event.az if event.az is not None else self._last_az + el = event.el + self.app.notify( + f"Moving to preset AZ={az:.1f} EL={el:.1f}", + severity="information", + ) + self._run_motor_command(self._device.move_to, az, el) + + def on_preset_list_save_requested(self, _event: PresetList.SaveRequested) -> None: + """Save the current position as a new preset.""" + preset_list = self.query_one("#ctrl-preset-list", PresetList) + name_input = preset_list.query_one("#preset-name-input", Input) + name = name_input.value.strip() + + if not name: + self.app.notify("Enter a preset name first", severity="warning") + return + + preset_list.save_preset(name, self._last_az, self._last_el) + name_input.value = "" + self.app.notify( + f"Saved preset '{name}' at AZ={self._last_az:.1f} EL={self._last_el:.1f}" + ) + + # ------------------------------------------------------------------ + # Tracking handlers + # ------------------------------------------------------------------ + + def on_tracking_panel_start_requested( + self, event: TrackingPanel.StartRequested + ) -> None: + """Handle rotctld start request (placeholder for Phase 6).""" + log.info( + "Tracking start requested: %s:%d min_el=%.1f", + event.host, + event.port, + event.min_el, + ) + panel = self.query_one("#ctrl-tracking-panel", TrackingPanel) + panel.set_status(state="LISTENING") + self.app.notify( + f"Tracking server listening on {event.host}:{event.port}", + severity="information", + ) + + def on_tracking_panel_stop_requested( + self, _event: TrackingPanel.StopRequested + ) -> None: + """Handle rotctld stop request (placeholder for Phase 6).""" + log.info("Tracking stop requested") + panel = self.query_one("#ctrl-tracking-panel", TrackingPanel) + panel.set_status(state="STOPPED") + self.app.notify("Tracking server stopped") + + # ------------------------------------------------------------------ + # Key binding actions + # ------------------------------------------------------------------ + + def _is_manual_active(self) -> bool: + """Check if Manual mode is the currently visible sub-mode.""" + try: + switcher = self.query_one("#control-modes", ContentSwitcher) + return switcher.current == "manual" + except Exception: + return False + + def action_nudge_az(self, delta: int) -> None: + """Nudge azimuth by delta degrees.""" + if not self._is_manual_active() or self._device is None: + return + new_az = self._last_az + delta + self._run_motor_command(self._device.move_motor, 0, new_az) + + def action_nudge_el(self, delta: int) -> None: + """Nudge elevation by delta degrees.""" + if not self._is_manual_active() or self._device is None: + return + new_el = self._last_el + delta + self._run_motor_command(self._device.move_motor, 1, new_el) + + def action_home_both(self) -> None: + """Home both AZ and EL motors.""" + if not self._is_manual_active() or self._device is None: + return + self.app.notify("Homing AZ + EL...", severity="information") + self._run_motor_command(self._device.home_motor, 0) + self._run_motor_command(self._device.home_motor, 1) + + def action_engage_motors(self) -> None: + """Engage (energize) stepper motors.""" + if not self._is_manual_active() or self._device is None: + return + self._run_motor_command(self._device.engage) + self._engaged = True + self._update_engaged(True) + self.app.notify("Motors engaged") + + def action_release_motors(self) -> None: + """Release (de-energize) stepper motors.""" + if not self._is_manual_active() or self._device is None: + return + self._run_motor_command(self._device.release) + self._engaged = False + self._update_engaged(False) + self.app.notify("Motors released") + + # ------------------------------------------------------------------ + # Motor command worker + # ------------------------------------------------------------------ + + @work(thread=True, exclusive=False, group="motor-cmd") + def _run_motor_command(self, fn, *args) -> None: + """Execute a motor command in a worker thread.""" + try: + fn(*args) + except Exception: + log.exception("Motor command failed") + self.app.call_from_thread( + self.app.notify, "Motor command failed", severity="error" + ) diff --git a/tui/src/birdcage_tui/screens/dashboard.py b/tui/src/birdcage_tui/screens/dashboard.py new file mode 100644 index 0000000..f8a0bd4 --- /dev/null +++ b/tui/src/birdcage_tui/screens/dashboard.py @@ -0,0 +1,153 @@ +"""F1 Dashboard screen -- at-a-glance status and quick actions. + +Home base for the Birdcage TUI. Shows a compass rose with live AZ/EL +position, a signal gauge with RSSI sparkline, quick-action buttons for +common tasks, and a system health summary pulled from firmware on mount. +""" + +import logging + +from textual import work +from textual.app import ComposeResult +from textual.containers import Container, Horizontal, Vertical +from textual.widgets import Static + +from birdcage_tui.widgets.compass_rose import CompassRose +from birdcage_tui.widgets.quick_actions import QuickActions +from birdcage_tui.widgets.signal_gauge import SignalGauge +from birdcage_tui.widgets.sparkline_widget import SparklineWidget +from birdcage_tui.widgets.system_health import SystemHealthPanel + +log = logging.getLogger(__name__) + +DeviceLike = object + + +class DashboardScreen(Container): + """F1: At-a-glance status overview with quick actions.""" + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._device: DeviceLike | None = None + self._health_loaded = False + + def compose(self) -> ComposeResult: + with Container(classes="screen-container"): + with Horizontal(classes="top-row"): + with Vertical(classes="panel"): + yield Static("Position", classes="panel-title") + yield CompassRose(id="dash-compass") + with Vertical(classes="panel"): + yield Static("Signal", classes="panel-title") + yield SignalGauge(id="dash-signal") + yield SparklineWidget( + max_points=80, + label="DVB RSSI", + color="#00d4aa", + id="dash-rssi-spark", + ) + yield QuickActions(classes="quick-actions") + with Vertical(classes="system-health"): + yield Static("System Health", classes="panel-title") + yield SystemHealthPanel(id="dash-health") + + # ------------------------------------------------------------------ + # Device lifecycle + # ------------------------------------------------------------------ + + def set_device(self, device: object) -> None: + """Store the device reference and kick off health data load.""" + self._device = device + self._load_health_data() + + def on_show(self) -> None: + """Load health data on first activation if not yet fetched.""" + if not self._health_loaded and self._device is not None: + self._load_health_data() + + # ------------------------------------------------------------------ + # Position updates (called by app-level 2 Hz poll) + # ------------------------------------------------------------------ + + def on_position_update(self, az: float, el: float) -> None: + """Push live AZ/EL into the compass rose.""" + compass = self.query_one("#dash-compass", CompassRose) + compass.azimuth = az + compass.elevation = el + + # ------------------------------------------------------------------ + # System health loader + # ------------------------------------------------------------------ + + @work(thread=True, exclusive=True, group="dash-health") + def _load_health_data(self) -> None: + """Fetch hardware diagnostics from firmware and populate the panel.""" + if self._device is None: + return + + shutdown = getattr(self.app, "shutdown_event", None) + if shutdown is not None and shutdown.is_set(): + return + + diag = "" + torque = "" + fw_id = "" + motor_life = "" + el_limits: dict[str, float] = {"min": 0.0, "max": 0.0, "home": 0.0} + + try: + diag = self._device.get_a3981_diag() + except Exception: + log.debug("Dashboard: failed to fetch A3981 diag", exc_info=True) + + try: + torque = self._device.get_a3981_torque() + except Exception: + log.debug("Dashboard: failed to fetch A3981 torque", exc_info=True) + + try: + fw_id = self._device.get_firmware_id() + except Exception: + log.debug("Dashboard: failed to fetch firmware ID", exc_info=True) + + try: + motor_life = self._device.get_motor_life() + except Exception: + log.debug("Dashboard: failed to fetch motor life", exc_info=True) + + try: + el_limits = self._device.get_el_limits() + except Exception: + log.debug("Dashboard: failed to fetch EL limits", exc_info=True) + + self._health_loaded = True + + try: + self.app.call_from_thread( + self._apply_health_data, + diag, + torque, + fw_id, + motor_life, + el_limits, + ) + except Exception: + log.debug("Dashboard: failed to push health data to UI", exc_info=True) + + def _apply_health_data( + self, + diag: str, + torque: str, + fw_id: str, + motor_life: str, + el_limits: dict[str, float], + ) -> None: + """Update the SystemHealthPanel on the main thread.""" + panel = self.query_one("#dash-health", SystemHealthPanel) + panel.load_data( + diag=diag, + torque=torque, + fw_id=fw_id, + motor_life=motor_life, + el_limits=el_limits, + ) diff --git a/tui/src/birdcage_tui/screens/position.py b/tui/src/birdcage_tui/screens/position.py deleted file mode 100644 index ca197b8..0000000 --- a/tui/src/birdcage_tui/screens/position.py +++ /dev/null @@ -1,286 +0,0 @@ -"""F1 Position screen -- AZ/EL display, manual moves, homing, engage/release. - -Widget container for ContentSwitcher. Polls the device at 2 Hz for -position and step data, drives the compass rose, motor status panel, -and AZ/EL sparklines. Bottom row provides manual move controls. -""" - -import logging - -from textual import work -from textual.app import ComposeResult -from textual.binding import Binding -from textual.containers import Container, Horizontal, Vertical -from textual.widgets import Button, Input, Static -from textual.worker import Worker - -from birdcage_tui.widgets.compass_rose import CompassRose -from birdcage_tui.widgets.motor_status import MotorStatus -from birdcage_tui.widgets.sparkline_widget import SparklineWidget - -log = logging.getLogger(__name__) - - -class PositionScreen(Container): - """F1: Position control and monitoring.""" - - can_focus = True - - BINDINGS = [ - Binding("left", "nudge_az(-1)", "AZ -1", show=False), - Binding("right", "nudge_az(1)", "AZ +1", show=False), - Binding("up", "nudge_el(1)", "EL +1", show=False), - Binding("down", "nudge_el(-1)", "EL -1", show=False), - Binding("h", "home_both", "Home Both", show=False), - Binding("e", "engage_motors", "Engage", show=False), - Binding("r", "release_motors", "Release", show=False), - ] - - def __init__(self, **kwargs) -> None: - super().__init__(**kwargs) - self._device: object = None - self._polling = False - self._engaged = False - self._poll_worker: Worker | None = None - # Track last-known position for nudge commands. - self._last_az = 180.0 - self._last_el = 45.0 - - def compose(self) -> ComposeResult: - with Container(classes="screen-container"): - with Horizontal(classes="top-row"): - yield CompassRose(id="compass") - with Vertical(classes="panel"): - yield Static("Motor Status", classes="panel-title") - yield MotorStatus(id="motor-status") - with Vertical(): - yield SparklineWidget( - max_points=80, label="AZ", color="#00d4aa", id="az-spark" - ) - yield SparklineWidget( - max_points=80, label="EL", color="#00b8c8", id="el-spark" - ) - with Horizontal(classes="bottom-controls"): - yield Static("AZ ", classes="label") - yield Input(placeholder="180.0", id="az-input", type="number") - yield Static(" EL ", classes="label") - yield Input(placeholder="45.0", id="el-input", type="number") - yield Button("Move", id="btn-move", variant="primary") - yield Button("Home AZ", id="btn-home-az") - yield Button("Home EL", id="btn-home-el") - yield Button("E/R", id="btn-engage") - - # ------------------------------------------------------------------ - # Device lifecycle - # ------------------------------------------------------------------ - - def set_device(self, device: object) -> None: - """Store the device reference and start position polling.""" - self._device = device - self._polling = True - self._poll_worker = self._do_position_poll() - - def on_show(self) -> None: - """Resume polling when this screen becomes visible.""" - if self._device is not None and not self._polling: - self._polling = True - self._poll_worker = self._do_position_poll() - - def on_unmount(self) -> None: - """Stop polling thread on teardown.""" - self._polling = False - - # ------------------------------------------------------------------ - # Position poll worker - # ------------------------------------------------------------------ - - @work(thread=True, exclusive=True, group="position-poll") - def _do_position_poll(self) -> None: - """Poll device at ~2 Hz for position and step data.""" - shutdown = self.app.shutdown_event - while self._polling and not shutdown.is_set(): - if self._device is None: - shutdown.wait(0.5) - continue - - try: - pos = self._device.get_position() - az = pos["azimuth"] - el = pos["elevation"] - self._last_az = az - self._last_el = el - - self.app.call_from_thread(self._update_compass, az, el) - self.app.call_from_thread(self._push_sparklines, az, el) - except Exception: - log.debug("Position poll failed", exc_info=True) - - try: - steps = self._device.get_step_positions() - self.app.call_from_thread( - self._update_motor_steps, - steps["az_steps"], - steps["el_steps"], - ) - except Exception: - log.debug("Step position poll failed", exc_info=True) - - # Poll torque state from A3981 - try: - torque_resp = self._device.get_a3981_torque() - lines = torque_resp.split("\n") - az_torque = "HIGH" if "HIGH" in lines[0] else "LOW" - el_torque = "HIGH" if len(lines) > 1 and "HIGH" in lines[1] else "LOW" - self.app.call_from_thread(self._update_torque, az_torque, el_torque) - except Exception: - log.debug("Torque poll failed", exc_info=True) - - shutdown.wait(0.5) - - # ------------------------------------------------------------------ - # Thread-safe widget update callbacks - # ------------------------------------------------------------------ - - def _update_compass(self, az: float, el: float) -> None: - compass = self.query_one("#compass", CompassRose) - compass.azimuth = az - compass.elevation = el - - def _push_sparklines(self, az: float, el: float) -> None: - self.query_one("#az-spark", SparklineWidget).push(az) - self.query_one("#el-spark", SparklineWidget).push(el) - - def _update_motor_steps(self, az_steps: int, el_steps: int) -> None: - motor = self.query_one("#motor-status", MotorStatus) - motor.az_steps = az_steps - motor.el_steps = el_steps - - def _update_torque(self, az_torque: str, el_torque: str) -> None: - motor = self.query_one("#motor-status", MotorStatus) - motor.az_torque = az_torque - motor.el_torque = el_torque - - def _update_engaged(self, engaged: bool) -> None: - motor = self.query_one("#motor-status", MotorStatus) - motor.engaged = engaged - - # ------------------------------------------------------------------ - # Button handlers - # ------------------------------------------------------------------ - - def on_button_pressed(self, event: Button.Pressed) -> None: - button_id = event.button.id or "" - - if button_id == "btn-move": - self._handle_move() - elif button_id == "btn-home-az": - self._handle_home(0) - elif button_id == "btn-home-el": - self._handle_home(1) - elif button_id == "btn-engage": - self._handle_engage_toggle() - - def _handle_move(self) -> None: - """Read AZ/EL inputs and issue a move command.""" - if self._device is None: - return - - az_input = self.query_one("#az-input", Input) - el_input = self.query_one("#el-input", Input) - - try: - az = float(az_input.value) if az_input.value.strip() else self._last_az - except ValueError: - self.app.notify("Invalid AZ value", severity="warning") - return - - try: - el = float(el_input.value) if el_input.value.strip() else self._last_el - except ValueError: - self.app.notify("Invalid EL value", severity="warning") - return - - self._run_motor_command(self._device.move_to, az, el) - - def _handle_home(self, motor_id: int) -> None: - """Home a specific motor axis.""" - if self._device is None: - return - axis = "AZ" if motor_id == 0 else "EL" - self.app.notify(f"Homing {axis}...", severity="information") - self._run_motor_command(self._device.home_motor, motor_id) - - def _handle_engage_toggle(self) -> None: - """Toggle motor engage/release state.""" - if self._device is None: - return - - if self._engaged: - self._run_motor_command(self._device.release) - self._engaged = False - self._update_engaged(False) - self.app.notify("Motors released") - else: - self._run_motor_command(self._device.engage) - self._engaged = True - self._update_engaged(True) - self.app.notify("Motors engaged") - - # ------------------------------------------------------------------ - # Key binding actions - # ------------------------------------------------------------------ - - def action_nudge_az(self, delta: int) -> None: - """Nudge azimuth by delta degrees.""" - if self._device is None: - return - new_az = self._last_az + delta - self._run_motor_command(self._device.move_motor, 0, new_az) - - def action_nudge_el(self, delta: int) -> None: - """Nudge elevation by delta degrees.""" - if self._device is None: - return - new_el = self._last_el + delta - self._run_motor_command(self._device.move_motor, 1, new_el) - - def action_home_both(self) -> None: - """Home both AZ and EL motors.""" - if self._device is None: - return - self.app.notify("Homing AZ + EL...", severity="information") - self._run_motor_command(self._device.home_motor, 0) - self._run_motor_command(self._device.home_motor, 1) - - def action_engage_motors(self) -> None: - """Engage (energize) stepper motors.""" - if self._device is None: - return - self._run_motor_command(self._device.engage) - self._engaged = True - self._update_engaged(True) - self.app.notify("Motors engaged") - - def action_release_motors(self) -> None: - """Release (de-energize) stepper motors.""" - if self._device is None: - return - self._run_motor_command(self._device.release) - self._engaged = False - self._update_engaged(False) - self.app.notify("Motors released") - - # ------------------------------------------------------------------ - # Helpers - # ------------------------------------------------------------------ - - @work(thread=True, exclusive=False, group="motor-cmd") - def _run_motor_command(self, fn, *args) -> None: - """Execute a motor command in a worker thread.""" - try: - fn(*args) - except Exception: - log.exception("Motor command failed") - self.app.call_from_thread( - self.app.notify, "Motor command failed", severity="error" - ) diff --git a/tui/src/birdcage_tui/screens/scan.py b/tui/src/birdcage_tui/screens/scan.py deleted file mode 100644 index 7be6fab..0000000 --- a/tui/src/birdcage_tui/screens/scan.py +++ /dev/null @@ -1,272 +0,0 @@ -"""F3 Scan Screen -- AZ sweep heatmap, sky mapping with configurable parameters. - -Grid-based sky scan: iterates over AZ/EL range, moves the dish to each point, -reads RSSI, and paints the result into a 2D heatmap. Supports CSV export of -raw (az, el, rssi) data for offline analysis. -""" - -import csv -import logging -from pathlib import Path - -from textual import work -from textual.containers import Container, Horizontal, Vertical -from textual.widgets import Button, Input, ProgressBar, Static -from textual.worker import get_current_worker - -from birdcage_tui.widgets.sky_heatmap import SkyHeatmap -from birdcage_tui.widgets.sparkline_widget import SparklineWidget - -log = logging.getLogger(__name__) - -# Type alias -- SerialBridge and DemoDevice share the same duck-typed interface. -DeviceLike = object - - -class ScanScreen(Container): - """F3: Sky scan and RF mapping.""" - - def __init__(self, **kwargs) -> None: - super().__init__(**kwargs) - self._device: DeviceLike | None = None - self._scanning = False - self._scan_data: list[tuple[float, float, float]] = [] - - def compose(self): - with Container(classes="screen-container"): - with Vertical(classes="panel"): - yield Static("Sky Scan", classes="panel-title") - yield SkyHeatmap(az_bins=40, el_bins=10, id="heatmap") - yield SparklineWidget( - max_points=80, label="Sweep RSSI", color="#00d4aa", id="sweep-spark" - ) - with Horizontal(classes="scan-status"): - yield Static("Idle", id="scan-status-text") - yield ProgressBar(id="scan-progress", total=100, show_eta=False) - with Horizontal(classes="bottom-controls"): - yield Static("AZ ", classes="label") - yield Input(value="160", id="az-start", type="number") - yield Static("-", classes="label") - yield Input(value="220", id="az-end", type="number") - yield Static(" Step ", classes="label") - yield Input(value="1.5", id="az-step", type="number") - yield Static(" EL ", classes="label") - yield Input(value="18", id="el-start", type="number") - yield Static("-", classes="label") - yield Input(value="65", id="el-end", type="number") - yield Static(" Step ", classes="label") - yield Input(value="5.0", id="el-step", type="number") - with Horizontal(classes="bottom-controls"): - yield Static("Transponders ", classes="label") - yield Input(value="3", id="xponder-input", type="integer") - yield Button("Start Scan", id="btn-start-scan", variant="primary") - yield Button("Stop", id="btn-stop-scan") - yield Button("Export CSV", id="btn-export") - - # ------------------------------------------------------------------ - # Device wiring - # ------------------------------------------------------------------ - - def set_device(self, device: DeviceLike) -> None: - """Store the device reference (SerialBridge or DemoDevice).""" - self._device = device - - # ------------------------------------------------------------------ - # Input helpers - # ------------------------------------------------------------------ - - def _read_float(self, widget_id: str, fallback: float) -> float: - """Read a float from an Input widget, returning *fallback* on parse error.""" - try: - return float(self.query_one(f"#{widget_id}", Input).value) - except (ValueError, TypeError): - return fallback - - def _read_int(self, widget_id: str, fallback: int) -> int: - """Read an int from an Input widget, returning *fallback* on parse error.""" - try: - return int(self.query_one(f"#{widget_id}", Input).value) - except (ValueError, TypeError): - return fallback - - # ------------------------------------------------------------------ - # Scan worker - # ------------------------------------------------------------------ - - @work(thread=True) - def _do_scan(self) -> None: - """Execute the AZ/EL grid scan in a background thread.""" - worker = get_current_worker() - shutdown = self.app.shutdown_event - device = self._device - if device is None: - return - - # Read scan parameters (widget access must happen via call_from_thread - # for Input.value, but Textual Input.value is a reactive that is safe - # to read from threads as a string snapshot). - az_start = self._read_float("az-start", 160.0) - az_end = self._read_float("az-end", 220.0) - az_step = self._read_float("az-step", 1.5) - el_start = self._read_float("el-start", 18.0) - el_end = self._read_float("el-end", 65.0) - el_step = self._read_float("el-step", 5.0) - iterations = self._read_int("xponder-input", 3) - - # Clamp step sizes to something sane. - if az_step <= 0: - az_step = 1.0 - if el_step <= 0: - el_step = 1.0 - - # Build the grid point list. - el_values: list[float] = [] - el = el_start - while el <= el_end + 1e-9: - el_values.append(round(el, 2)) - el += el_step - - az_values: list[float] = [] - az = az_start - while az <= az_end + 1e-9: - az_values.append(round(az, 2)) - az += az_step - - total_points = len(el_values) * len(az_values) - if total_points == 0: - self.app.call_from_thread( - self._set_status, "No grid points -- check parameters" - ) - return - - heatmap = self.query_one("#heatmap", SkyHeatmap) - spark = self.query_one("#sweep-spark", SparklineWidget) - - done = 0 - - for _el_idx, el_val in enumerate(el_values): - for _az_idx, az_val in enumerate(az_values): - if not self._scanning or worker.is_cancelled or shutdown.is_set(): - self.app.call_from_thread(self._set_status, "Scan stopped") - return - - # Move dish. - try: - device.move_to(az_val, el_val) - except Exception: - log.exception("move_to failed at AZ=%.2f EL=%.2f", az_val, el_val) - msg = f"Move error at AZ={az_val:.1f} EL={el_val:.1f}" - self.app.call_from_thread(self._set_status, msg) - continue - - # Settle time -- let the motor stop and vibrations damp. - shutdown.wait(0.3) - - # Read signal. - try: - rssi_data = device.get_rssi(iterations) - rssi = float(rssi_data.get("average", 0)) - except Exception: - log.exception("get_rssi failed at AZ=%.2f EL=%.2f", az_val, el_val) - rssi = 0.0 - - # Record raw data. - self._scan_data.append((az_val, el_val, rssi)) - - # Map to heatmap grid indices -- fit into fixed-size bins. - az_span = az_end - az_start + 1e-9 - el_span = el_end - el_start + 1e-9 - grid_az = min( - int((az_val - az_start) / az_span * heatmap.az_bins), - heatmap.az_bins - 1, - ) - grid_el = min( - int((el_val - el_start) / el_span * heatmap.el_bins), - heatmap.el_bins - 1, - ) - - # Update widgets. - self.app.call_from_thread(heatmap.set_point, grid_az, grid_el, rssi) - self.app.call_from_thread(heatmap.set_active, grid_az, grid_el) - self.app.call_from_thread(spark.push, rssi) - - done += 1 - pct = int(done * 100 / total_points) - status_text = ( - f"Scanning AZ={az_val:.1f} EL={el_val:.1f} " - f"RSSI={rssi:.0f} [{done}/{total_points}]" - ) - self.app.call_from_thread(self._set_progress, pct, status_text) - - msg = f"Scan complete -- {total_points} points" - self.app.call_from_thread(self._set_status, msg) - - # ------------------------------------------------------------------ - # Widget update helpers (called via call_from_thread) - # ------------------------------------------------------------------ - - def _set_status(self, text: str) -> None: - """Update the scan status text label.""" - self.query_one("#scan-status-text", Static).update(text) - - def _set_progress(self, pct: int, status_text: str) -> None: - """Update both progress bar and status text.""" - self.query_one("#scan-progress", ProgressBar).update(progress=pct) - self.query_one("#scan-status-text", Static).update(status_text) - - # ------------------------------------------------------------------ - # Button handlers - # ------------------------------------------------------------------ - - def on_button_pressed(self, event: Button.Pressed) -> None: - button_id = event.button.id or "" - - if button_id == "btn-start-scan": - self._start_scan() - elif button_id == "btn-stop-scan": - self._stop_scan() - elif button_id == "btn-export": - self._export_csv() - - def _start_scan(self) -> None: - """Clear state and kick off the scan worker.""" - if self._device is None: - self.app.notify("No device connected", severity="warning") - return - - if self._scanning: - self.app.notify("Scan already in progress", severity="warning") - return - - # Reset. - heatmap = self.query_one("#heatmap", SkyHeatmap) - heatmap.clear() - self._scan_data.clear() - self.query_one("#scan-progress", ProgressBar).update(progress=0) - self._set_status("Starting scan...") - - self._scanning = True - self._do_scan() - - def _stop_scan(self) -> None: - """Signal the scan worker to stop.""" - self._scanning = False - self._set_status("Stopping...") - - def _export_csv(self) -> None: - """Write scan data to /tmp/birdcage_scan.csv.""" - if not self._scan_data: - self.app.notify("No scan data to export", severity="warning") - return - - output = Path("/tmp/birdcage_scan.csv") - try: - with output.open("w", newline="") as fh: - writer = csv.writer(fh) - writer.writerow(["az", "el", "rssi"]) - for az, el, rssi in self._scan_data: - writer.writerow([f"{az:.2f}", f"{el:.2f}", f"{rssi:.1f}"]) - self.app.notify(f"Exported {len(self._scan_data)} points to {output}") - except OSError as exc: - log.exception("CSV export failed") - self.app.notify(f"Export failed: {exc}", severity="error") diff --git a/tui/src/birdcage_tui/screens/system.py b/tui/src/birdcage_tui/screens/system.py index 13719a0..31d20e8 100644 --- a/tui/src/birdcage_tui/screens/system.py +++ b/tui/src/birdcage_tui/screens/system.py @@ -1,8 +1,7 @@ -"""F4 System Screen -- NVS table, A3981 diagnostics, motor dynamics, firmware info. +"""F4 System Screen -- hardware info, motor tuning, NVS configuration. -Aggregates hardware identity, stepper driver status, motor tuning parameters, -and the full non-volatile storage table into a single dashboard panel. All data -is fetched from the device in a background worker thread and pushed to widgets +Three sub-modes via ModeBar: Hardware, Motors, NVS Config. All data is +fetched from the device in background worker threads and pushed to widgets via call_from_thread. """ @@ -13,10 +12,14 @@ from pathlib import Path from rich.text import Text from textual import work +from textual.app import ComposeResult from textual.containers import Container, Horizontal, Vertical -from textual.widgets import Button, Static +from textual.widgets import Button, ContentSwitcher, Static from textual.worker import get_current_worker +from birdcage_tui.widgets.mode_bar import ModeBar +from birdcage_tui.widgets.motor_tuning import MotorTuning +from birdcage_tui.widgets.nvs_filter import NvsFilter from birdcage_tui.widgets.nvs_table import NvsTable log = logging.getLogger(__name__) @@ -162,31 +165,70 @@ def _format_motor_dynamics( class SystemScreen(Container): - """F4: System information, NVS, and diagnostics.""" + """F4: System hardware, motor tuning, and NVS configuration.""" def __init__(self, **kwargs) -> None: super().__init__(**kwargs) self._device: DeviceLike | None = None self._refreshed = False + self._nvs_raw: str = "" + self._nvs_parsed: list[dict[str, str]] = [] - def compose(self): + def compose(self) -> ComposeResult: with Container(classes="screen-container"): - with Horizontal(classes="panel"): - yield Static("", id="firmware-info") - with Horizontal(classes="top-row"): - with Vertical(classes="panel"): - yield Static("A3981 Diagnostics", classes="panel-title") - yield Static("", id="a3981-diag") - with Vertical(classes="panel"): - yield Static("Motor Dynamics", classes="panel-title") - yield Static("", id="motor-dynamics") - with Vertical(classes="panel"): - yield Static("NVS Table", classes="panel-title") - yield NvsTable(id="nvs-table") - with Horizontal(classes="bottom-controls"): - yield Button("Refresh All", id="btn-refresh-all", variant="primary") - yield Button("Refresh NVS", id="btn-refresh-nvs") - yield Button("Export NVS JSON", id="btn-export-nvs") + yield ModeBar( + modes={ + "hardware": "Hardware", + "motors": "Motors", + "nvs": "NVS Config", + }, + initial="hardware", + classes="mode-bar", + ) + with ContentSwitcher(id="system-modes", initial="hardware"): + # -- Hardware sub-mode -- + with Container(id="hardware"): + with Vertical(classes="panel"): + yield Static("Firmware", classes="panel-title") + yield Static("", id="firmware-info") + with Vertical(classes="panel"): + yield Static("A3981 Stepper Drivers", classes="panel-title") + yield Static("", id="a3981-diag") + with Horizontal(classes="bottom-controls"): + yield Button( + "Refresh All", + id="btn-refresh-all", + variant="primary", + ) + yield Button("Reset A3981 Faults", id="btn-reset-a3981") + + # -- Motors sub-mode -- + with Container(id="motors"): + with Vertical(classes="panel"): + yield Static("Motor Dynamics", classes="panel-title") + yield Static("", id="motor-dynamics") + yield MotorTuning(id="motor-tuning", classes="motor-tuning") + + # -- NVS Config sub-mode -- + with Container(id="nvs"): + yield NvsFilter(id="nvs-filter", classes="nvs-filter") + with Vertical(classes="panel"): + yield NvsTable(id="nvs-table") + with Horizontal(classes="bottom-controls"): + yield Button( + "Refresh NVS", + id="btn-refresh-nvs", + variant="primary", + ) + yield Button("Export NVS JSON", id="btn-export-nvs") + + # ------------------------------------------------------------------ + # Mode switching + # ------------------------------------------------------------------ + + def on_mode_bar_mode_changed(self, event: ModeBar.ModeChanged) -> None: + """Switch the system sub-mode ContentSwitcher.""" + self.query_one("#system-modes", ContentSwitcher).current = event.mode # ------------------------------------------------------------------ # Device wiring @@ -208,8 +250,11 @@ class SystemScreen(Container): if self._device is not None and not self._refreshed: self._do_system_refresh() + def on_position_update(self, az: float, el: float) -> None: + """System screen does not need position updates.""" + # ------------------------------------------------------------------ - # System refresh worker + # System refresh worker (all panels) # ------------------------------------------------------------------ @work(thread=True) @@ -271,14 +316,34 @@ class SystemScreen(Container): Text("Error reading motor dynamics", style="#e04040"), ) + # 3b. PID gains (populate the tuning widget). + try: + gains = device.get_pid_gains() + az_g = gains.get("az", {}) + el_g = gains.get("el", {}) + self.app.call_from_thread( + self._apply_pid_gains, + az_g.get("kp", 600), + az_g.get("kv", 60), + az_g.get("ki", 1), + el_g.get("kp", 250), + el_g.get("kv", 50), + el_g.get("ki", 1), + ) + except Exception: + log.debug("PID gain read failed", exc_info=True) + if worker.is_cancelled: return # 4. NVS dump. try: nvs_text = device.nvs_dump() + self._nvs_raw = nvs_text nvs_table = self.query_one("#nvs-table", NvsTable) self.app.call_from_thread(nvs_table.load_nvs, nvs_text) + # Cache parsed rows for filtering. + self.app.call_from_thread(self._cache_nvs_rows) except Exception: log.exception("Failed to dump NVS") self.app.call_from_thread( @@ -287,6 +352,24 @@ class SystemScreen(Container): self._refreshed = True + def _apply_pid_gains( + self, + az_kp: float, + az_kv: float, + az_ki: float, + el_kp: float, + el_kv: float, + el_ki: float, + ) -> None: + """Push device-reported PID gains into the MotorTuning widget inputs.""" + tuning = self.query_one("#motor-tuning", MotorTuning) + tuning.load_gains(az_kp, az_kv, az_ki, el_kp, el_kv, el_ki) + + def _cache_nvs_rows(self) -> None: + """Snapshot parsed NVS rows from the table for filter operations.""" + nvs_table = self.query_one("#nvs-table", NvsTable) + self._nvs_parsed = nvs_table.parsed_rows + # ------------------------------------------------------------------ # NVS-only refresh worker # ------------------------------------------------------------------ @@ -300,8 +383,10 @@ class SystemScreen(Container): try: nvs_text = device.nvs_dump() + self._nvs_raw = nvs_text nvs_table = self.query_one("#nvs-table", NvsTable) self.app.call_from_thread(nvs_table.load_nvs, nvs_text) + self.app.call_from_thread(self._cache_nvs_rows) self.app.call_from_thread(self.app.notify, "NVS table refreshed") except Exception: log.exception("Failed to refresh NVS") @@ -309,6 +394,78 @@ class SystemScreen(Container): self.app.notify, "NVS refresh failed", severity="error" ) + # ------------------------------------------------------------------ + # A3981 fault reset worker + # ------------------------------------------------------------------ + + @work(thread=True) + def _do_a3981_reset(self) -> None: + """Reset A3981 fault flags via the A3981 submenu.""" + device = self._device + if device is None: + return + + try: + device.send_raw("a3981") + device.send_raw("reset") + device.send_raw("q") + self.app.call_from_thread(self.app.notify, "A3981 faults reset") + # Re-read diagnostics after reset. + try: + diag = device.get_a3981_diag() + modes = device.get_a3981_modes() + torque = device.get_a3981_torque() + a3981_text = _format_a3981(diag, modes, torque) + self.app.call_from_thread( + self.query_one("#a3981-diag", Static).update, a3981_text + ) + except Exception: + log.debug("A3981 re-read after reset failed", exc_info=True) + except Exception: + log.exception("A3981 fault reset failed") + self.app.call_from_thread( + self.app.notify, "A3981 reset failed", severity="error" + ) + + # ------------------------------------------------------------------ + # NVS filter handler + # ------------------------------------------------------------------ + + def on_nvs_filter_filter_changed(self, event: NvsFilter.FilterChanged) -> None: + """Re-filter the NVS table based on search text and modified toggle.""" + self._apply_nvs_filter(event.text, event.modified_only) + + def _apply_nvs_filter(self, text: str, modified_only: bool) -> None: + """Clear the NVS DataTable and re-add only matching rows.""" + nvs_table = self.query_one("#nvs-table", NvsTable) + nvs_table.clear() + + needle = text.strip().lower() + + for row in self._nvs_parsed: + # Modified-only filter: skip rows where current == default. + if modified_only and row["current"] == row["default"]: + continue + + # Text filter: match against index or name (case-insensitive). + if needle: + idx_match = needle in row["idx"].lower() + name_match = needle in row["name"].lower() + if not (idx_match or name_match): + continue + + # Row passes all filters -- add it to the table. + modified = row["current"] != row["default"] + label = f"*{row['idx']}" if modified else row["idx"] + nvs_table.add_row( + label, + row["name"], + row["current"], + row["saved"], + row["default"], + key=f"nvs-{row['idx']}", + ) + # ------------------------------------------------------------------ # Button handlers # ------------------------------------------------------------------ @@ -322,12 +479,15 @@ class SystemScreen(Container): self._handle_refresh_nvs() elif button_id == "btn-export-nvs": self._export_nvs_json() + elif button_id == "btn-reset-a3981": + self._handle_reset_a3981() def _handle_refresh_all(self) -> None: """Kick off a full system refresh.""" if self._device is None: self.app.notify("No device connected", severity="warning") return + self._refreshed = False self._do_system_refresh() def _handle_refresh_nvs(self) -> None: @@ -337,10 +497,16 @@ class SystemScreen(Container): return self._do_nvs_refresh() + def _handle_reset_a3981(self) -> None: + """Reset A3981 stepper driver fault flags.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + self._do_a3981_reset() + def _export_nvs_json(self) -> None: """Export parsed NVS rows to /tmp/birdcage_nvs.json.""" - nvs_table = self.query_one("#nvs-table", NvsTable) - rows = nvs_table.parsed_rows + rows = self._nvs_parsed if not rows: self.app.notify( @@ -356,3 +522,56 @@ class SystemScreen(Container): except OSError as exc: log.exception("NVS JSON export failed") self.app.notify(f"Export failed: {exc}", severity="error") + + # ------------------------------------------------------------------ + # Motor tuning handler + # ------------------------------------------------------------------ + + def on_motor_tuning_apply_requested( + self, event: MotorTuning.ApplyRequested + ) -> None: + """Handle PID gain apply request from the MotorTuning widget.""" + if self._device is None: + self.app.notify("No device connected", severity="warning") + return + log.info( + "PID apply requested: AZ(%.0f/%.0f/%.0f) EL(%.0f/%.0f/%.0f)", + event.az_kp, + event.az_kv, + event.az_ki, + event.el_kp, + event.el_kv, + event.el_ki, + ) + self._do_pid_write( + event.az_kp, + event.az_kv, + event.az_ki, + event.el_kp, + event.el_kv, + event.el_ki, + ) + + @work(thread=True) + def _do_pid_write( + self, + az_kp: float, + az_kv: float, + az_ki: float, + el_kp: float, + el_kv: float, + el_ki: float, + ) -> None: + """Write PID gains to both motor axes in a worker thread.""" + device = self._device + if device is None: + return + try: + device.set_pid_gains(0, az_kp, az_kv, az_ki) + device.set_pid_gains(1, el_kp, el_kv, el_ki) + self.app.call_from_thread(self.app.notify, "PID gains applied to AZ + EL") + except Exception: + log.exception("PID write failed") + self.app.call_from_thread( + self.app.notify, "PID write failed", severity="error" + ) diff --git a/tui/src/birdcage_tui/theme.tcss b/tui/src/birdcage_tui/theme.tcss index f8f351d..3f32a6a 100644 --- a/tui/src/birdcage_tui/theme.tcss +++ b/tui/src/birdcage_tui/theme.tcss @@ -1,6 +1,8 @@ /* Birdcage TUI — Dark RF Theme * Teal accent on deep blue-black. No purple. * Signal gradient: blue > cyan > green > yellow > red + * + * Layout: Header / StatusStrip / TabBar / ContentSwitcher / Footer */ /* ── Global ────────────────────────────────────────── */ @@ -25,49 +27,31 @@ Footer { height: 1; } -/* ── Layout Containers ─────────────────────────────── */ +/* ── Status Strip ─────────────────────────────────── */ -#main-area { - layout: horizontal; - height: 1fr; -} - -#sidebar { - width: 26; +#status-strip { + dock: top; + height: 1; background: #0e1420; - border-right: solid #1a2a3a; - padding: 1 1; + color: #c8d0d8; + border-bottom: solid #1a2a3a; + padding: 0 1; } -.sidebar-title { - color: #00d4aa; - text-style: bold; - text-align: center; - width: 100%; -} +/* ── Tab Bar ──────────────────────────────────────── */ -.sidebar-subtitle { - color: #506878; - text-align: center; - width: 100%; - margin: 0 0 1 0; -} - -#content-area { - width: 1fr; -} - -ContentSwitcher { - width: 1fr; - height: 1fr; -} - -/* ── Sidebar Buttons ───────────────────────────────── */ - -.sidebar-btn { - width: 100%; +#tab-bar { + dock: top; height: 3; - margin: 0 0 1 0; + background: #0a0a12; + padding: 0 1; + layout: horizontal; +} + +.tab-btn { + min-width: 16; + height: 3; + margin: 0 0 0 0; background: #121c2a; color: #7090a8; text-style: bold; @@ -75,19 +59,84 @@ ContentSwitcher { text-align: center; } -.sidebar-btn:hover { +.tab-btn:hover { background: #1a2a40; color: #00d4aa; border: round #00d4aa; } -.sidebar-btn.active { +.tab-btn.active { background: #0a2a3a; color: #00d4aa; border: round #00d4aa; text-style: bold; } +/* ── Mode Bar (within-screen sub-mode toggle) ─────── */ + +.mode-bar { + height: 3; + background: #0a0a12; + padding: 0 1; + layout: horizontal; + dock: top; +} + +.mode-btn { + min-width: 14; + height: 3; + margin: 0 0 0 0; + background: #0e1420; + color: #506878; + text-style: bold; + border: round #1a2a3a; + text-align: center; +} + +.mode-btn:hover { + background: #1a2a40; + color: #00d4aa; + border: round #00d4aa; +} + +.mode-btn.active { + background: #0a2a3a; + color: #00d4aa; + border: round #00d4aa; + text-style: bold; +} + +/* ── Content Area ─────────────────────────────────── */ + +#content-area { + width: 1fr; + height: 1fr; +} + +ContentSwitcher { + width: 1fr; + height: 1fr; +} + +/* ── Console Overlay (ModalScreen) ────────────────── */ + +ConsoleOverlay { + background: rgba(10, 10, 18, 0.6); +} + +#console-overlay { + dock: bottom; + height: 50%; + width: 100%; + background: #0a0a12; + border-top: double #00d4aa; + padding: 0; +} + +#console-overlay #serial-log { + height: 1fr; +} + /* ── Panel / Card ──────────────────────────────────── */ .panel { @@ -177,6 +226,18 @@ Button.-active { background: #0a3a3a; } +/* ── Checkbox ──────────────────────────────────────── */ + +Checkbox { + background: transparent; + color: #c8d0d8; + padding: 0 1; +} + +Checkbox:focus { + color: #00d4aa; +} + /* ── DataTable ─────────────────────────────────────── */ DataTable { @@ -338,44 +399,23 @@ ProgressBar PercentageStatus { color: #c8d0d8; } -/* ── Device Status Bar (sidebar bottom) ────────────── */ - -#device-status { - dock: bottom; - height: auto; - padding: 1; - background: #0e1420; - border-top: solid #1a2a38; -} - -.device-status-label { - color: #506878; -} - -.device-status-value { - color: #c8d0d8; -} - -.device-connected { - color: #00e060; -} - -.device-demo { - color: #e8a020; -} - -/* ── Console Screen ────────────────────────────────── */ +/* ── Console Input Area ───────────────────────────── */ .console-input-area { dock: bottom; - height: 3; + height: auto; + width: 100%; layout: horizontal; padding: 0 1; background: #0e1420; border-top: solid #1a2a38; } -.console-input-area Input { +.console-input-area .label { + width: auto; +} + +#console-input { width: 1fr; } @@ -426,7 +466,125 @@ ProgressBar PercentageStatus { color: #506878; } -/* ── Scan Screen ───────────────────────────────────── */ +/* ── Quick Actions (Dashboard) ────────────────────── */ + +.quick-actions { + height: auto; + layout: horizontal; + padding: 0 1; +} + +.quick-action-btn { + min-width: 16; + height: 3; + margin: 0 1 0 0; + background: #1a2a40; + color: #00d4aa; + border: round #1a3050; + text-style: bold; +} + +.quick-action-btn:hover { + background: #00d4aa; + color: #0a0a12; + border: round #00d4aa; +} + +/* ── System Health (Dashboard) ────────────────────── */ + +.system-health { + height: auto; + padding: 1 2; + background: #0e1420; + border: round #1a2a3a; + margin: 0 1; +} + +/* ── Preset List ──────────────────────────────────── */ + +.preset-controls { + height: auto; + layout: horizontal; + padding: 0 1; + dock: bottom; +} + +.preset-controls Button { + margin-right: 1; +} + +/* ── Tracking Panel ───────────────────────────────── */ + +.tracking-panel { + height: auto; + padding: 1 2; + background: #0e1420; + border: round #1a2a3a; +} + +.tracking-status { + color: #506878; +} + +/* ── Receiver Info ────────────────────────────────── */ + +.receiver-info { + height: auto; + padding: 1 2; + background: #0e1420; + border: round #1a2a3a; +} + +/* ── Sweep Plot ───────────────────────────────────── */ + +.sweep-plot { + height: auto; + min-height: 8; + padding: 1 2; + background: #0e1420; + border: round #1a2a3a; +} + +/* ── NVS Filter ───────────────────────────────────── */ + +.nvs-filter { + height: auto; + layout: horizontal; + padding: 0 1; + dock: top; + background: #0e1420; + border-bottom: solid #1a2a3a; +} + +.nvs-filter Input { + width: 1fr; + margin-right: 1; +} + +/* ── Motor Tuning (PID editor) ────────────────────── */ + +.motor-tuning { + height: auto; + padding: 1 2; + background: #0e1420; + border: round #1a2a3a; +} + +.pid-row { + layout: horizontal; + height: 3; +} + +.pid-row .label { + width: 4; +} + +.pid-row Input { + width: 8; + margin-right: 1; +} + +/* ── Scan Controls ────────────────────────────────── */ .scan-controls { dock: bottom; @@ -446,8 +604,8 @@ ProgressBar PercentageStatus { .screen-container { layout: vertical; - height: 1fr; - width: 1fr; + height: 100%; + width: 100%; } .top-row { diff --git a/tui/src/birdcage_tui/widgets/__init__.py b/tui/src/birdcage_tui/widgets/__init__.py index ea4216e..5e7dcf0 100644 --- a/tui/src/birdcage_tui/widgets/__init__.py +++ b/tui/src/birdcage_tui/widgets/__init__.py @@ -1,21 +1,39 @@ """Custom widgets for the Birdcage TUI.""" from birdcage_tui.widgets.compass_rose import CompassRose -from birdcage_tui.widgets.device_status_bar import DeviceStatusBar +from birdcage_tui.widgets.mode_bar import ModeBar from birdcage_tui.widgets.motor_status import MotorStatus +from birdcage_tui.widgets.motor_tuning import MotorTuning +from birdcage_tui.widgets.nvs_filter import NvsFilter from birdcage_tui.widgets.nvs_table import NvsTable +from birdcage_tui.widgets.preset_list import PresetList +from birdcage_tui.widgets.quick_actions import QuickActions +from birdcage_tui.widgets.receiver_info import ReceiverInfo from birdcage_tui.widgets.serial_log import SerialLog from birdcage_tui.widgets.signal_gauge import SignalGauge from birdcage_tui.widgets.sky_heatmap import SkyHeatmap from birdcage_tui.widgets.sparkline_widget import SparklineWidget +from birdcage_tui.widgets.status_strip import StatusStrip +from birdcage_tui.widgets.sweep_plot import SweepPlot +from birdcage_tui.widgets.system_health import SystemHealthPanel +from birdcage_tui.widgets.tracking_panel import TrackingPanel __all__ = [ "CompassRose", - "DeviceStatusBar", + "ModeBar", "MotorStatus", + "MotorTuning", + "NvsFilter", "NvsTable", + "PresetList", + "QuickActions", + "ReceiverInfo", "SerialLog", "SignalGauge", "SkyHeatmap", "SparklineWidget", + "StatusStrip", + "SweepPlot", + "SystemHealthPanel", + "TrackingPanel", ] diff --git a/tui/src/birdcage_tui/widgets/device_status_bar.py b/tui/src/birdcage_tui/widgets/device_status_bar.py deleted file mode 100644 index 7f72c29..0000000 --- a/tui/src/birdcage_tui/widgets/device_status_bar.py +++ /dev/null @@ -1,92 +0,0 @@ -"""Device status bar widget — sidebar display of connection state and firmware info.""" - -from rich.text import Text -from textual.widgets import Static - - -class DeviceStatusBar(Static): - """Sidebar status display showing connection state and firmware info.""" - - def __init__(self, **kwargs) -> None: - super().__init__(**kwargs) - self._connected: bool = False - self._demo: bool = False - self._firmware: str = "---" - self._submenu: str = "---" - self._port: str = "---" - - def set_device(self, device: object) -> None: - """Accept a device reference and update the status display.""" - is_demo = hasattr(device, "demo_mode") or type(device).__name__ == "DemoDevice" - fw = getattr(device, "firmware_id", "02.02.48") if device else "---" - port = getattr(self.app, "serial_port", "/dev/ttyUSB0") if self.app else "---" - submenu = getattr(device, "current_menu", "TRK>") if device else "---" - connected = device is not None and not is_demo - self.update_status( - connected=connected, - demo=is_demo, - firmware=str(fw), - submenu=str(submenu), - port=str(port), - ) - - def update_status( - self, - connected: bool, - demo: bool, - firmware: str, - submenu: str, - port: str, - ) -> None: - """Update all status fields and refresh the display.""" - self._connected = connected - self._demo = demo - self._firmware = firmware - self._submenu = submenu - self._port = port - self.refresh() - - def render(self) -> Text: - result = Text() - label_w = 8 - - # Status row - result.append("Status".ljust(label_w), style="#506878") - if self._connected: - result.append("Connected", style="#00e060 bold") - elif self._demo: - result.append("Demo", style="#e8a020 italic") - else: - result.append("Offline", style="#e04040") - result.append("\n") - - # Port row - result.append("Port".ljust(label_w), style="#506878") - result.append(self._port, style="#c8d0d8") - result.append("\n") - - # Firmware row - result.append("FW".ljust(label_w), style="#506878") - result.append(self._firmware, style="#c8d0d8") - result.append("\n") - - # Menu row - result.append("Menu".ljust(label_w), style="#506878") - # Color the menu prompt with its matching prompt color - submenu_colors: dict[str, str] = { - "TRK>": "#00d4aa", - "MOT>": "#00e060", - "DVB>": "#2080d0", - "NVS>": "#e8a020", - "A3981>": "#00b8c8", - "STEP>": "#40c0a0", - "EE>": "#e8a020", - "OS>": "#8090a0", - "ADC>": "#00b8c8", - "GPIO>": "#40c0a0", - "PEAK>": "#e8c020", - } - menu_color = submenu_colors.get(self._submenu, "#c8d0d8") - result.append(self._submenu, style=f"{menu_color} bold") - - return result diff --git a/tui/src/birdcage_tui/widgets/mode_bar.py b/tui/src/birdcage_tui/widgets/mode_bar.py new file mode 100644 index 0000000..995393a --- /dev/null +++ b/tui/src/birdcage_tui/widgets/mode_bar.py @@ -0,0 +1,72 @@ +"""Mode bar widget -- button bar for ContentSwitcher sub-modes.""" + +from textual.app import ComposeResult +from textual.containers import Horizontal +from textual.message import Message +from textual.widgets import Button + + +class ModeBar(Horizontal): + """Horizontal bar of toggle buttons that switch a ContentSwitcher. + + Used inside screens to switch between sub-modes (e.g., Manual/Presets/Track + within the Control screen, or Monitor/Sweep/SkyMap within Signal). + + Posts a ``ModeBar.ModeChanged`` message when the active mode changes. + The parent screen should watch for this and update its ContentSwitcher. + """ + + class ModeChanged(Message): + """Posted when the user selects a different mode.""" + + def __init__(self, mode: str) -> None: + super().__init__() + self.mode = mode + + def __init__( + self, + modes: dict[str, str], + initial: str | None = None, + **kwargs, + ) -> None: + """Create a mode bar. + + Args: + modes: Mapping of mode_key -> display label. + initial: Which mode to highlight initially. Defaults to the first key. + """ + super().__init__(**kwargs) + self._modes = modes + self._initial = initial or next(iter(modes)) + + def compose(self) -> ComposeResult: + for key, label in self._modes.items(): + btn = Button(label, id=f"mode-{key}", classes="mode-btn") + if key == self._initial: + btn.add_class("active") + yield btn + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + if not button_id.startswith("mode-"): + return + + mode = button_id.removeprefix("mode-") + if mode not in self._modes: + return + + # Update button highlight + for btn in self.query(".mode-btn"): + btn.remove_class("active") + event.button.add_class("active") + + self.post_message(self.ModeChanged(mode)) + event.stop() + + @property + def active_mode(self) -> str: + """Return the currently active mode key.""" + for btn in self.query(".mode-btn.active"): + btn_id = btn.id or "" + return btn_id.removeprefix("mode-") + return self._initial diff --git a/tui/src/birdcage_tui/widgets/motor_tuning.py b/tui/src/birdcage_tui/widgets/motor_tuning.py new file mode 100644 index 0000000..db77577 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/motor_tuning.py @@ -0,0 +1,130 @@ +"""Motor tuning widget -- PID gain editor for AZ and EL motor control loops.""" + +from textual.app import ComposeResult +from textual.containers import Container, Horizontal, Vertical +from textual.message import Message +from textual.widgets import Button, Input, Static + + +class MotorTuning(Container): + """PID gain editor for AZ and EL motor control loops. + + Displays two rows of labeled inputs (Kp, Kv, Ki for each axis) and an + Apply button. The button uses ``variant="warning"`` because writing PID + gains takes effect immediately on the live motor control loop. + + The parent screen should confirm the action before sending the values + to the firmware via ``mot pid ``. + """ + + class ApplyRequested(Message): + """Posted when the user clicks Apply PID. + + The parent screen should validate and confirm before writing to + the firmware, since PID changes affect motor behavior immediately. + """ + + def __init__( + self, + az_kp: float, + az_kv: float, + az_ki: float, + el_kp: float, + el_kv: float, + el_ki: float, + ) -> None: + super().__init__() + self.az_kp = az_kp + self.az_kv = az_kv + self.az_ki = az_ki + self.el_kp = el_kp + self.el_kv = el_kv + self.el_ki = el_ki + + def compose(self) -> ComposeResult: + yield Static("PID Tuning", classes="panel-title") + + with Vertical(): + # AZ row + with Horizontal(classes="pid-row"): + yield Static("AZ", classes="pid-axis-label") + yield Static("Kp:", classes="pid-gain-label") + yield Input(value="600", id="pid-az-kp", type="number") + yield Static("Kv:", classes="pid-gain-label") + yield Input(value="60", id="pid-az-kv", type="number") + yield Static("Ki:", classes="pid-gain-label") + yield Input(value="1", id="pid-az-ki", type="number") + + # EL row + with Horizontal(classes="pid-row"): + yield Static("EL", classes="pid-axis-label") + yield Static("Kp:", classes="pid-gain-label") + yield Input(value="250", id="pid-el-kp", type="number") + yield Static("Kv:", classes="pid-gain-label") + yield Input(value="50", id="pid-el-kv", type="number") + yield Static("Ki:", classes="pid-gain-label") + yield Input(value="1", id="pid-el-ki", type="number") + + # Button row + with Horizontal(classes="pid-button-row"): + yield Button( + "Apply PID", + id="pid-apply", + variant="warning", + ) + + def load_gains( + self, + az_kp: float, + az_kv: float, + az_ki: float, + el_kp: float, + el_kv: float, + el_ki: float, + ) -> None: + """Populate all input fields from device-reported PID gains. + + Args: + az_kp: Azimuth proportional gain. + az_kv: Azimuth velocity gain. + az_ki: Azimuth integral gain. + el_kp: Elevation proportional gain. + el_kv: Elevation velocity gain. + el_ki: Elevation integral gain. + """ + self.query_one("#pid-az-kp", Input).value = str(int(az_kp)) + self.query_one("#pid-az-kv", Input).value = str(int(az_kv)) + self.query_one("#pid-az-ki", Input).value = str(int(az_ki)) + self.query_one("#pid-el-kp", Input).value = str(int(el_kp)) + self.query_one("#pid-el-kv", Input).value = str(int(el_kv)) + self.query_one("#pid-el-ki", Input).value = str(int(el_ki)) + + def on_button_pressed(self, event: Button.Pressed) -> None: + """Handle the Apply PID button press.""" + if event.button.id != "pid-apply": + return + + try: + az_kp = float(self.query_one("#pid-az-kp", Input).value) + az_kv = float(self.query_one("#pid-az-kv", Input).value) + az_ki = float(self.query_one("#pid-az-ki", Input).value) + el_kp = float(self.query_one("#pid-el-kp", Input).value) + el_kv = float(self.query_one("#pid-el-kv", Input).value) + el_ki = float(self.query_one("#pid-el-ki", Input).value) + except ValueError: + # Non-numeric input -- do not post the message. + # The Input widget's type="number" constraint should prevent this + # in normal usage, but guard against edge cases. + return + + self.post_message( + self.ApplyRequested( + az_kp=az_kp, + az_kv=az_kv, + az_ki=az_ki, + el_kp=el_kp, + el_kv=el_kv, + el_ki=el_ki, + ) + ) + event.stop() diff --git a/tui/src/birdcage_tui/widgets/nvs_filter.py b/tui/src/birdcage_tui/widgets/nvs_filter.py new file mode 100644 index 0000000..66d3721 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/nvs_filter.py @@ -0,0 +1,72 @@ +"""NVS filter widget -- text search and modified-only toggle for NVS table filtering.""" + +from textual.app import ComposeResult +from textual.containers import Horizontal +from textual.message import Message +from textual.widgets import Checkbox, Input, Static + + +class NvsFilter(Horizontal): + """Filter bar for the NVS table: text search + show-modified-only toggle. + + Composes a label, text input for searching NVS entries by name or index, + and a checkbox to restrict display to entries where current != default. + + Posts ``NvsFilter.FilterChanged`` when either control changes, so the + parent screen can re-filter the NVS DataTable rows. + """ + + class FilterChanged(Message): + """Posted when the filter text or modified-only toggle changes.""" + + def __init__(self, text: str, modified_only: bool) -> None: + super().__init__() + self.text = text + self.modified_only = modified_only + + def compose(self) -> ComposeResult: + yield Static("Filter: ", classes="label") + yield Input( + placeholder="search by name or index...", + id="nvs-filter-input", + ) + yield Checkbox( + "Modified only", + id="nvs-filter-modified", + value=False, + ) + + def on_input_changed(self, event: Input.Changed) -> None: + """Re-post filter state when search text changes.""" + if event.input.id != "nvs-filter-input": + return + self._post_filter() + event.stop() + + def on_checkbox_changed(self, event: Checkbox.Changed) -> None: + """Re-post filter state when the modified-only toggle changes.""" + if event.checkbox.id != "nvs-filter-modified": + return + self._post_filter() + event.stop() + + def _post_filter(self) -> None: + """Read current control values and post a FilterChanged message.""" + text_input = self.query_one("#nvs-filter-input", Input) + checkbox = self.query_one("#nvs-filter-modified", Checkbox) + self.post_message( + self.FilterChanged( + text=text_input.value, + modified_only=checkbox.value, + ) + ) + + @property + def filter_text(self) -> str: + """Current text in the search input.""" + return self.query_one("#nvs-filter-input", Input).value + + @property + def modified_only(self) -> bool: + """Whether the modified-only checkbox is checked.""" + return self.query_one("#nvs-filter-modified", Checkbox).value diff --git a/tui/src/birdcage_tui/widgets/preset_list.py b/tui/src/birdcage_tui/widgets/preset_list.py new file mode 100644 index 0000000..0c6193b --- /dev/null +++ b/tui/src/birdcage_tui/widgets/preset_list.py @@ -0,0 +1,216 @@ +"""Preset list widget -- saved AZ/EL target presets backed by JSON file.""" + +import json +import logging +from pathlib import Path + +from textual.app import ComposeResult +from textual.containers import Container, Horizontal +from textual.message import Message +from textual.widgets import Button, DataTable, Input + +log = logging.getLogger(__name__) + +PRESETS_PATH = Path.home() / ".config" / "birdcage" / "presets.json" + + +class PresetList(Container): + """DataTable of saved AZ/EL presets with save/go/delete actions. + + File format:: + + { + "targets": [ + {"name": "Zenith", "az": null, "el": 65.0, "notes": "EL-only"}, + {"name": "South", "az": 180.0, "el": 45.0, "notes": ""} + ] + } + + An ``az`` value of ``null`` means "don't move AZ" (EL-only targets). + """ + + class GoToPreset(Message): + """Posted when the user presses Go on a selected preset.""" + + def __init__(self, az: float | None, el: float) -> None: + super().__init__() + self.az = az + self.el = el + + class SaveRequested(Message): + """Posted when the user presses Save Current. + + The parent screen should read the current position and call + ``save_preset()`` with a name and the current AZ/EL. + """ + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._presets: list[dict] = [] + self._table_ready = False + + def compose(self) -> ComposeResult: + yield DataTable(id="preset-table") + with Horizontal(classes="preset-controls"): + yield Input(placeholder="Preset name", id="preset-name-input") + yield Button("Save Current", id="btn-preset-save") + yield Button("Go", id="btn-preset-go") + yield Button("Delete", id="btn-preset-delete") + + def on_mount(self) -> None: + """Add columns and load presets when mounted.""" + table = self.query_one("#preset-table", DataTable) + table.add_columns("Name", "AZ", "EL", "Notes") + table.cursor_type = "row" + self._table_ready = True + self.load_presets() + + # ------------------------------------------------------------------ + # Persistence + # ------------------------------------------------------------------ + + def load_presets(self) -> None: + """Read presets from the JSON file and populate the table.""" + self._presets = [] + + if PRESETS_PATH.exists(): + try: + data = json.loads(PRESETS_PATH.read_text(encoding="utf-8")) + self._presets = data.get("targets", []) + except (json.JSONDecodeError, KeyError): + log.warning("Failed to parse presets file: %s", PRESETS_PATH) + + self._rebuild_table() + + def _write_presets(self) -> None: + """Write the current presets list to the JSON file.""" + PRESETS_PATH.parent.mkdir(parents=True, exist_ok=True) + data = {"targets": self._presets} + PRESETS_PATH.write_text( + json.dumps(data, indent=2, ensure_ascii=False) + "\n", + encoding="utf-8", + ) + + def _rebuild_table(self) -> None: + """Clear and repopulate the DataTable from the in-memory presets list.""" + if not self._table_ready: + return + + table = self.query_one("#preset-table", DataTable) + table.clear() + + for idx, preset in enumerate(self._presets): + name = preset.get("name", f"preset-{idx}") + az = preset.get("az") + el = preset.get("el", 0.0) + notes = preset.get("notes", "") + + az_str = f"{az:.1f}" if az is not None else "---" + el_str = f"{el:.1f}" + + table.add_row(name, az_str, el_str, notes, key=f"preset-{idx}") + + # ------------------------------------------------------------------ + # Public API + # ------------------------------------------------------------------ + + def save_preset( + self, + name: str, + az: float | None, + el: float, + notes: str = "", + ) -> None: + """Append a new preset and persist to disk. + + Args: + name: Human-readable label for this target. + az: Azimuth in degrees, or None for EL-only targets. + el: Elevation in degrees. + notes: Optional description. + """ + entry: dict = { + "name": name, + "az": az, + "el": el, + "notes": notes, + } + self._presets.append(entry) + self._write_presets() + self._rebuild_table() + + def delete_selected(self) -> None: + """Remove the currently highlighted preset row.""" + table = self.query_one("#preset-table", DataTable) + if table.row_count == 0: + return + + row_key = table.cursor_row + if row_key < 0 or row_key >= len(self._presets): + return + + self._presets.pop(row_key) + self._write_presets() + self._rebuild_table() + + def _get_selected_preset(self) -> dict | None: + """Return the preset dict for the currently highlighted row.""" + table = self.query_one("#preset-table", DataTable) + if table.row_count == 0: + return None + + row_key = table.cursor_row + if row_key < 0 or row_key >= len(self._presets): + return None + + return self._presets[row_key] + + @property + def presets(self) -> list[dict]: + """Access the current in-memory presets list.""" + return list(self._presets) + + # ------------------------------------------------------------------ + # Button handlers + # ------------------------------------------------------------------ + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + + if button_id == "btn-preset-save": + self._handle_save() + elif button_id == "btn-preset-go": + self._handle_go() + elif button_id == "btn-preset-delete": + self._handle_delete() + + def _handle_save(self) -> None: + """Read the name input and post a SaveRequested message.""" + name_input = self.query_one("#preset-name-input", Input) + name = name_input.value.strip() + if not name: + self.app.notify("Enter a preset name first", severity="warning") + return + self.post_message(self.SaveRequested()) + + def _handle_go(self) -> None: + """Post a GoToPreset message for the selected row.""" + preset = self._get_selected_preset() + if preset is None: + self.app.notify("No preset selected", severity="warning") + return + + az = preset.get("az") + el = preset.get("el", 0.0) + self.post_message(self.GoToPreset(az=az, el=float(el))) + + def _handle_delete(self) -> None: + """Delete the selected preset.""" + preset = self._get_selected_preset() + if preset is None: + self.app.notify("No preset selected", severity="warning") + return + + name = preset.get("name", "?") + self.delete_selected() + self.app.notify(f"Deleted preset: {name}") diff --git a/tui/src/birdcage_tui/widgets/quick_actions.py b/tui/src/birdcage_tui/widgets/quick_actions.py new file mode 100644 index 0000000..a9186f0 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/quick_actions.py @@ -0,0 +1,48 @@ +"""Quick actions widget -- grid of task-oriented action buttons for the Dashboard.""" + +from textual.app import ComposeResult +from textual.containers import Container, Horizontal +from textual.message import Message +from textual.widgets import Button + + +class QuickActions(Container): + """Grid of buttons navigating to relevant screens/modes. + + Posts an ``ActionSelected`` message when a button is pressed. + The parent screen or app handles the actual navigation or confirmation + (e.g., stow requires user confirmation before moving). + """ + + class ActionSelected(Message): + """Posted when the user selects a quick action.""" + + def __init__(self, action: str) -> None: + super().__init__() + self.action = action + + # Action definitions: (id_suffix, label, description) + _ACTIONS: list[tuple[str, str]] = [ + ("point", "Point Dish"), + ("monitor", "Monitor Signal"), + ("scan", "Scan Sky"), + ("stow", "Stow"), + ] + + def compose(self) -> ComposeResult: + with Horizontal(classes="quick-action-row"): + for action_id, label in self._ACTIONS: + yield Button( + label, + id=f"qa-{action_id}", + classes="quick-action-btn", + ) + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + if not button_id.startswith("qa-"): + return + + action = button_id.removeprefix("qa-") + self.post_message(self.ActionSelected(action)) + event.stop() diff --git a/tui/src/birdcage_tui/widgets/receiver_info.py b/tui/src/birdcage_tui/widgets/receiver_info.py new file mode 100644 index 0000000..3d86151 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/receiver_info.py @@ -0,0 +1,156 @@ +"""Receiver info widget -- parsed DVB/RF receiver parameters display.""" + +import re + +from rich.text import Text +from textual.widgets import Static + + +class ReceiverInfo(Static): + """Displays parsed DVB receiver parameters from bridge channel/config queries. + + Call ``load_data(channel_params_text, dvb_config_text)`` to update. + Parses the firmware's ``dis`` and ``config`` command output into a + compact, color-coded summary of receiver state. + """ + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._freq: str = "---" + self._symrate: str = "---" + self._lnb: str = "---" + self._lock: str = "NO" + self._bcm_id: str = "---" + self._bcm_rev: str = "" + self._bcm_fw: str = "" + + def load_data( + self, + channel_params: str = "", + dvb_config: str = "", + ) -> None: + """Parse raw firmware responses and refresh the display. + + Args: + channel_params: Raw output from DVB ``dis`` command (channel + parameter table with Parameter/Current columns). + dvb_config: Raw output from DVB ``config`` command (BCM + hardware/firmware identification). + """ + self._parse_channel_params(channel_params) + self._parse_dvb_config(dvb_config) + self.refresh() + + def _parse_channel_params(self, text: str) -> None: + """Extract frequency, symbol rate, LNB state, and lock from dis output. + + The ``dis`` command returns a table-formatted output with + "Parameter" and "Current" columns. We extract key-value pairs + by matching known parameter names. + """ + if not text: + return + + # Frequency (kHz) + freq_match = re.search( + r"(?:freq|frequency)\s*[:\|]?\s*(\d+)", text, re.IGNORECASE + ) + if freq_match: + self._freq = f"{freq_match.group(1)} kHz" + + # Symbol rate + sym_match = re.search( + r"(?:sym(?:bol)?[\s_]*rate|ksps)\s*[:\|]?\s*(\S+)", text, re.IGNORECASE + ) + if sym_match: + val = sym_match.group(1) + # May be "blind" for blind scan mode, or a numeric value + if val.lower() in ("blind", "blind_scan", "auto"): + self._symrate = "blind scan" + else: + self._symrate = f"{val} ksps" + + # LNB voltage / polarity + lnb_match = re.search( + r"(?:lnb|polarity|lnbdc)\s*[:\|]?\s*(.+?)(?:\r?\n|$)", text, re.IGNORECASE + ) + if lnb_match: + raw = lnb_match.group(1).strip() + # Interpret voltage as polarity + if "13" in raw: + self._lnb = "ODU 13V (V-pol)" + elif "18" in raw: + self._lnb = "ODU 18V (H-pol)" + elif raw: + self._lnb = raw + + # Lock status + lock_match = re.search(r"lock\s*[:\|]?\s*(\S+)", text, re.IGNORECASE) + if lock_match: + val = lock_match.group(1).upper() + if val in ("1", "YES", "TRUE", "LOCKED"): + self._lock = "YES" + else: + self._lock = "NO" + + def _parse_dvb_config(self, text: str) -> None: + """Extract BCM chip ID, revision, and firmware version from config output. + + The ``config`` command returns lines like: + BCM4515 ID 0x4515 Rev B0 + FW v113.37 + """ + if not text: + return + + # BCM chip ID (e.g., "0x4515") + id_match = re.search(r"(?:ID|BCM)\s*(0x[0-9a-fA-F]+)", text) + if id_match: + self._bcm_id = id_match.group(1) + + # Revision (e.g., "Rev B0") + rev_match = re.search(r"Rev\s+(\S+)", text, re.IGNORECASE) + if rev_match: + self._bcm_rev = rev_match.group(1) + + # Firmware version (e.g., "FW v113.37" or "v113.37") + fw_match = re.search(r"(?:FW\s+)?v(\d+\.\d+)", text) + if fw_match: + self._bcm_fw = f"v{fw_match.group(1)}" + + def render(self) -> Text: + result = Text() + label_w = 10 + + # Frequency + result.append("Freq".ljust(label_w), style="#506878") + result.append(self._freq, style="#c8d0d8") + result.append("\n") + + # Symbol rate + result.append("SymRate".ljust(label_w), style="#506878") + result.append(self._symrate, style="#c8d0d8") + result.append("\n") + + # LNB state + result.append("LNB".ljust(label_w), style="#506878") + result.append(self._lnb, style="#c8d0d8") + result.append("\n") + + # Lock status + result.append("Lock".ljust(label_w), style="#506878") + if self._lock == "YES": + result.append("YES", style="#00e060 bold") + else: + result.append("NO", style="#e04040") + result.append("\n") + + # BCM identification + result.append("BCM".ljust(label_w), style="#506878") + result.append(self._bcm_id, style="#00d4aa") + if self._bcm_rev: + result.append(f" Rev {self._bcm_rev}", style="#c8d0d8") + if self._bcm_fw: + result.append(f" FW {self._bcm_fw}", style="#c8d0d8") + + return result diff --git a/tui/src/birdcage_tui/widgets/status_strip.py b/tui/src/birdcage_tui/widgets/status_strip.py new file mode 100644 index 0000000..ebcd64f --- /dev/null +++ b/tui/src/birdcage_tui/widgets/status_strip.py @@ -0,0 +1,111 @@ +"""Status strip -- persistent 1-row connection/position/signal bar.""" + +from rich.text import Text +from textual.reactive import reactive +from textual.widgets import Static + +# Firmware prompt → display color mapping. +_MENU_COLORS: dict[str, str] = { + "TRK>": "#00d4aa", + "MOT>": "#00e060", + "DVB>": "#2080d0", + "NVS>": "#e8a020", + "A3981>": "#00b8c8", + "STEP>": "#40c0a0", + "EE>": "#e8a020", + "OS>": "#8090a0", + "ADC>": "#00b8c8", + "GPIO>": "#40c0a0", + "PEAK>": "#e8c020", +} + + +class StatusStrip(Static): + """Persistent status bar showing connection, position, signal, and motor state. + + Docked below the header on every screen. Updated by the app-level + position poll and signal monitors. + """ + + connected: reactive[bool] = reactive(False) + demo: reactive[bool] = reactive(False) + port: reactive[str] = reactive("/dev/ttyUSB0") + azimuth: reactive[float] = reactive(0.0) + elevation: reactive[float] = reactive(0.0) + rssi: reactive[int] = reactive(-1) # -1 means no data + motor_state: reactive[str] = reactive("IDLE") + fw_menu: reactive[str] = reactive("TRK>") + + def render(self) -> Text: + result = Text() + sep = Text(" \u2502 ", style="#1a2a38") + + # Connection status + if self.demo: + result.append(" DEMO", style="#e8a020 bold italic") + elif self.connected: + result.append(" CONNECTED", style="#00e060 bold") + result.append(f" {self.port}", style="#506878") + else: + result.append(" OFFLINE", style="#e04040 bold") + + result.append_text(sep) + + # Position + result.append("AZ ", style="#506878") + result.append(f"{self.azimuth:7.2f}", style="#00d4aa bold") + result.append(" EL ", style="#506878") + result.append(f"{self.elevation:6.2f}", style="#00d4aa bold") + + result.append_text(sep) + + # Signal (RSSI) + if self.rssi >= 0: + result.append("RSSI ", style="#506878") + result.append(f"{self.rssi}", style="#00b8c8 bold") + else: + result.append("RSSI ", style="#384858") + result.append("---", style="#384858") + + result.append_text(sep) + + # Motor state + state = self.motor_state + if state == "MOVING": + result.append(state, style="#e8c020 bold") + elif state == "ENGAGED": + result.append(state, style="#00e060") + else: + result.append(state, style="#506878") + + result.append_text(sep) + + # Firmware context + menu_color = _MENU_COLORS.get(self.fw_menu, "#506878") + result.append(self.fw_menu, style=f"{menu_color}") + + return result + + def watch_connected(self, _value: bool) -> None: + self.refresh() + + def watch_demo(self, _value: bool) -> None: + self.refresh() + + def watch_port(self, _value: str) -> None: + self.refresh() + + def watch_azimuth(self, _value: float) -> None: + self.refresh() + + def watch_elevation(self, _value: float) -> None: + self.refresh() + + def watch_rssi(self, _value: int) -> None: + self.refresh() + + def watch_motor_state(self, _value: str) -> None: + self.refresh() + + def watch_fw_menu(self, _value: str) -> None: + self.refresh() diff --git a/tui/src/birdcage_tui/widgets/sweep_plot.py b/tui/src/birdcage_tui/widgets/sweep_plot.py new file mode 100644 index 0000000..a64bf5f --- /dev/null +++ b/tui/src/birdcage_tui/widgets/sweep_plot.py @@ -0,0 +1,157 @@ +"""Sweep plot widget -- 1D azimuth-vs-RSSI bar chart for signal sweep visualization.""" + +from collections import deque + +from rich.text import Text +from textual.widgets import Static + +# 8-level vertical block characters for bar rendering. +# Index 0 = lowest bar, index 7 = tallest bar. +_BLOCKS = "\u2581\u2582\u2583\u2584\u2585\u2586\u2587\u2588" + +# RSSI color thresholds matching signal_gauge.py / sky_heatmap.py +_THRESHOLDS: list[tuple[float, str]] = [ + (500.0, "#2080d0"), # cold -- noise floor + (1000.0, "#00b8c8"), # cool -- weak signal + (2000.0, "#00e060"), # mid -- usable + (3000.0, "#e8c020"), # warm -- strong + (4096.0, "#e04040"), # hot -- saturating +] + +# Maximum display width in columns. AZ range is mapped to fit within this. +MAX_DISPLAY_WIDTH = 60 + + +def _rssi_color(rssi: float) -> str: + """Return the color string for a given RSSI value.""" + if rssi <= 0: + return "#1a2a38" + for threshold, color in _THRESHOLDS: + if rssi <= threshold: + return color + return _THRESHOLDS[-1][1] + + +class SweepPlot(Static): + """1D vertical bar chart showing RSSI at each AZ position. + + X-axis = azimuth positions, Y-axis = RSSI intensity (8-level Unicode blocks). + Similar to a spectrum analyzer display but in angular domain. + + Each column represents one azimuth measurement point, rendered as a stacked + block character whose height encodes RSSI strength and whose color encodes + the signal gradient (blue < cyan < green < yellow < red). + + Methods: + clear: Reset all measurement data. + add_point: Add an AZ/RSSI measurement point. + set_active: Highlight the current sweep position. + """ + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + # Ordered measurement data: (az, rssi) pairs + self._points: deque[tuple[float, float]] = deque(maxlen=MAX_DISPLAY_WIDTH) + self._active_az: float | None = None + + def clear(self) -> None: + """Reset all data and clear the active position.""" + self._points.clear() + self._active_az = None + self.refresh() + + def add_point(self, az: float, rssi: float) -> None: + """Add a measurement point and refresh the display. + + Args: + az: Azimuth angle in degrees. + rssi: Raw RSSI ADC count (0-4096). + """ + self._points.append((az, rssi)) + self.refresh() + + def set_active(self, az: float) -> None: + """Highlight the current sweep position and refresh. + + Args: + az: Azimuth angle in degrees of the active scan position. + """ + self._active_az = az + self.refresh() + + def render(self) -> Text: + result = Text() + + # Title line + result.append("AZ Sweep", style="#506878 bold") + + if not self._points: + result.append("\n") + result.append(_BLOCKS[0] * MAX_DISPLAY_WIDTH, style="#1a2a38") + result.append("\n") + result.append("no data", style="#384858") + return result + + points = list(self._points) + rssi_values = [rssi for _, rssi in points] + az_values = [az for az, _ in points] + + # Find peak + peak_rssi = max(rssi_values) + peak_idx = rssi_values.index(peak_rssi) + peak_az = az_values[peak_idx] + + # Normalize RSSI to 0-7 block index range + lo = min(rssi_values) + hi = max(rssi_values) + span = hi - lo + + # Render the bar chart row + result.append("\n") + for az, rssi in points: + is_active = self._active_az is not None and abs(az - self._active_az) < 0.05 + + if is_active: + # Active position: bright white marker + result.append(_BLOCKS[7], style="#ffffff bold") + else: + # Compute block level from RSSI + if span <= 0: + idx = 3 + else: + normalized = (rssi - lo) / span + idx = min(int(normalized * 7.999), 7) + color = _rssi_color(rssi) + result.append(_BLOCKS[idx], style=color) + + # Pad remaining width with low blocks if fewer points than max width + remaining = MAX_DISPLAY_WIDTH - len(points) + if remaining > 0: + result.append(_BLOCKS[0] * remaining, style="#1a2a38") + + # AZ axis labels + result.append("\n") + if len(az_values) >= 2: + az_lo = az_values[0] + az_hi = az_values[-1] + lo_label = f"{az_lo:.1f}\u00b0" + hi_label = f"{az_hi:.1f}\u00b0" + gap = MAX_DISPLAY_WIDTH - len(lo_label) - len(hi_label) + result.append(lo_label, style="#506878") + if gap > 0: + result.append(" " * gap) + result.append(hi_label, style="#506878") + elif len(az_values) == 1: + result.append(f"{az_values[0]:.1f}\u00b0", style="#506878") + + # Peak indicator line + result.append("\n") + result.append("Peak at ", style="#506878") + result.append(f"AZ={peak_az:.1f}", style="#00d4aa bold") + result.append(" RSSI=", style="#506878") + result.append(f"{peak_rssi:.0f}", style=_rssi_color(peak_rssi)) + + # Point count + result.append(f" ({len(points)} pts)", style="#384858") + + return result diff --git a/tui/src/birdcage_tui/widgets/system_health.py b/tui/src/birdcage_tui/widgets/system_health.py new file mode 100644 index 0000000..6e545c3 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/system_health.py @@ -0,0 +1,195 @@ +"""System health panel widget -- compact multi-line diagnostics for the Dashboard.""" + +import re + +from rich.text import Text +from textual.widgets import Static + + +class SystemHealthPanel(Static): + """Multi-line styled text showing A3981 diag, firmware ID, motor life. + + Populated by calling ``load_data()`` with raw firmware response strings. + Parses and formats hardware diagnostics into a compact, color-coded + summary suitable for the Dashboard overview. + """ + + def __init__(self, **kwargs) -> None: + super().__init__(**kwargs) + self._diag: str = "" + self._torque: str = "" + self._fw_id: str = "" + self._motor_life: str = "" + self._el_limits: dict[str, float] = {"min": 0.0, "max": 0.0} + + def load_data( + self, + diag: str = "", + torque: str = "", + fw_id: str = "", + motor_life: str = "", + el_limits: dict[str, float] | None = None, + ) -> None: + """Update all health fields from raw firmware responses and refresh. + + Args: + diag: Raw A3981 ``diag`` response (e.g., "AZ DIAG: OK EL DIAG: OK"). + torque: Raw A3981 ``st`` response (e.g., "AZ Torq:LOW EL Torq:LOW"). + fw_id: Raw OS ``id`` response with NVS version, system ID, chip info. + motor_life: Raw MOT ``life`` response with usage statistics. + el_limits: Parsed EL limits dict with "min" and "max" keys (degrees). + """ + self._diag = diag + self._torque = torque + self._fw_id = fw_id + self._motor_life = motor_life + if el_limits is not None: + self._el_limits = el_limits + self.refresh() + + def render(self) -> Text: + result = Text() + label_w = 10 + + # A3981 diagnostic row + result.append("A3981".ljust(label_w), style="#506878") + az_diag, el_diag = _parse_diag(self._diag) + result.append("AZ ", style="#506878") + result.append(az_diag, style=_diag_style(az_diag)) + result.append(" EL ", style="#506878") + result.append(el_diag, style=_diag_style(el_diag)) + result.append("\n") + + # Torque row + result.append("Torque".ljust(label_w), style="#506878") + az_torque, el_torque = _parse_torque(self._torque) + result.append("AZ ", style="#506878") + result.append(az_torque, style=_torque_style(az_torque)) + result.append(" EL ", style="#506878") + result.append(el_torque, style=_torque_style(el_torque)) + result.append("\n") + + # Firmware identification row + fw_ver, mcu, ant_id = _parse_fw_id(self._fw_id) + result.append("FW".ljust(label_w), style="#506878") + result.append(fw_ver, style="#c8d0d8") + if mcu: + result.append(" MCU: ", style="#506878") + result.append(mcu, style="#c8d0d8") + if ant_id: + result.append(" Ant: ", style="#506878") + result.append(ant_id, style="#c8d0d8") + result.append("\n") + + # EL range + motor life row + result.append("EL Range".ljust(label_w), style="#506878") + el_min = self._el_limits.get("min", 0.0) + el_max = self._el_limits.get("max", 0.0) + result.append(f"{el_min:.1f}\u00b0", style="#c8d0d8") + result.append(" \u2013 ", style="#506878") + result.append(f"{el_max:.1f}\u00b0", style="#c8d0d8") + + az_life, el_life = _parse_motor_life(self._motor_life) + if az_life or el_life: + result.append(" Life: ", style="#506878") + result.append(f"AZ {az_life}", style="#c8d0d8") + result.append(f" EL {el_life}", style="#c8d0d8") + + return result + + +def _parse_diag(text: str) -> tuple[str, str]: + """Extract AZ and EL diagnostic status from A3981 diag response.""" + az = "---" + el = "---" + if not text: + return az, el + + az_match = re.search(r"AZ\s+DIAG:\s*(\w+)", text, re.IGNORECASE) + el_match = re.search(r"EL\s+DIAG:\s*(\w+)", text, re.IGNORECASE) + if az_match: + az = az_match.group(1).upper() + if el_match: + el = el_match.group(1).upper() + return az, el + + +def _parse_torque(text: str) -> tuple[str, str]: + """Extract AZ and EL torque levels from A3981 st response.""" + az = "---" + el = "---" + if not text: + return az, el + + az_match = re.search(r"AZ\s+Torq:(\w+)", text, re.IGNORECASE) + el_match = re.search(r"EL\s+Torq:(\w+)", text, re.IGNORECASE) + if az_match: + az = az_match.group(1).upper() + if el_match: + el = el_match.group(1).upper() + return az, el + + +def _parse_fw_id(text: str) -> tuple[str, str, str]: + """Extract firmware version, MCU type, and antenna ID from OS id response. + + The ``id`` command returns multi-line output including NVS version, + System ID, and chip details. We extract the most relevant fields. + """ + fw_ver = "---" + mcu = "" + ant_id = "" + if not text: + return fw_ver, mcu, ant_id + + # Firmware / NVS version (e.g., "02.02.48" or "NVS Ver: 02.02.48") + ver_match = re.search(r"(\d{2}\.\d{2}\.\d{2,3})", text) + if ver_match: + fw_ver = ver_match.group(1) + + # MCU identification (e.g., "K60" or "Kinetis") + if "K60" in text or "Kinetis" in text: + mcu = "K60 96MHz" + + # Antenna ID (e.g., "12-IN G2" or "Ant ID") + ant_match = re.search(r"Ant\s+ID\s*[-:]\s*(.+?)(?:\r?\n|$)", text, re.IGNORECASE) + if ant_match: + ant_id = ant_match.group(1).strip() + + return fw_ver, mcu, ant_id + + +def _parse_motor_life(text: str) -> tuple[str, str]: + """Extract AZ and EL motor life counters from MOT life response.""" + az = "" + el = "" + if not text: + return az, el + + # Motor life output varies by firmware. Look for numeric counters + # associated with motor 0 (AZ) and motor 1 (EL). + az_match = re.search(r"(?:Motor\s*\[?0\]?|AZ)\D+(\d+)", text, re.IGNORECASE) + el_match = re.search(r"(?:Motor\s*\[?1\]?|EL)\D+(\d+)", text, re.IGNORECASE) + if az_match: + az = az_match.group(1) + if el_match: + el = el_match.group(1) + return az, el + + +def _diag_style(value: str) -> str: + """Return Rich style string for a diagnostic status value.""" + if value == "OK": + return "#00e060 bold" + if value == "FAULT": + return "#e04040 bold" + return "#506878" + + +def _torque_style(value: str) -> str: + """Return Rich style string for a torque level value.""" + if value == "HIGH": + return "#e8c020 bold" + if value == "LOW": + return "#c8d0d8" + return "#506878" diff --git a/tui/src/birdcage_tui/widgets/tracking_panel.py b/tui/src/birdcage_tui/widgets/tracking_panel.py new file mode 100644 index 0000000..1f4a208 --- /dev/null +++ b/tui/src/birdcage_tui/widgets/tracking_panel.py @@ -0,0 +1,164 @@ +"""Tracking panel widget -- rotctld server lifecycle control for satellite tracking.""" + +from rich.text import Text +from textual.app import ComposeResult +from textual.containers import Container, Horizontal +from textual.message import Message +from textual.reactive import reactive +from textual.widgets import Button, Input, Static + + +class TrackingPanel(Container): + """Panel wrapping the RotctldServer lifecycle UI for satellite tracking. + + Displays server status, bind address, client info, move statistics, + and leapfrog state. The actual rotctld server is started and managed + by the parent screen -- this widget is purely the control surface. + """ + + class StartRequested(Message): + """Posted when the user presses Start Server.""" + + def __init__(self, host: str, port: int, min_el: float) -> None: + super().__init__() + self.host = host + self.port = port + self.min_el = min_el + + class StopRequested(Message): + """Posted when the user presses Stop.""" + + def compose(self) -> ComposeResult: + yield TrackingStatus(id="tracking-status") + with Horizontal(classes="tracking-controls"): + yield Button("Start Server", id="btn-track-start", variant="primary") + yield Button("Stop", id="btn-track-stop") + yield Static(" Bind: ", classes="label") + yield Input(value="127.0.0.1", id="track-host-input") + yield Static(":", classes="label") + yield Input(value="4533", id="track-port-input", type="integer") + yield Static(" Min EL: ", classes="label") + yield Input(value="18.0", id="track-minel-input", type="number") + + # ------------------------------------------------------------------ + # Status updates (called by parent screen) + # ------------------------------------------------------------------ + + def set_status( + self, + state: str = "STOPPED", + client: str = "", + moves: int = 0, + rate: float = 0.0, + leapfrog: bool = True, + ) -> None: + """Update the tracking status display. + + Args: + state: One of "STOPPED", "LISTENING", "CONNECTED". + client: Client identification string (e.g., "Gpredict"). + moves: Total move commands received. + rate: Move command rate in commands per second. + leapfrog: Whether leapfrog predictive compensation is active. + """ + status = self.query_one("#tracking-status", TrackingStatus) + status.state = state + status.client = client + status.moves = moves + status.rate = rate + status.leapfrog = leapfrog + + # ------------------------------------------------------------------ + # Button handlers + # ------------------------------------------------------------------ + + def on_button_pressed(self, event: Button.Pressed) -> None: + button_id = event.button.id or "" + + if button_id == "btn-track-start": + self._handle_start() + elif button_id == "btn-track-stop": + self._handle_stop() + + def _handle_start(self) -> None: + """Read bind parameters and post a StartRequested message.""" + host = self.query_one("#track-host-input", Input).value.strip() + if not host: + host = "127.0.0.1" + + try: + port = int(self.query_one("#track-port-input", Input).value) + except ValueError: + self.app.notify("Invalid port number", severity="warning") + return + + try: + min_el = float(self.query_one("#track-minel-input", Input).value) + except ValueError: + min_el = 18.0 + + self.post_message(self.StartRequested(host, port, min_el)) + + def _handle_stop(self) -> None: + """Post a StopRequested message.""" + self.post_message(self.StopRequested()) + + +class TrackingStatus(Static): + """Rich text display of rotctld server state and tracking statistics.""" + + state: reactive[str] = reactive("STOPPED") + client: reactive[str] = reactive("") + moves: reactive[int] = reactive(0) + rate: reactive[float] = reactive(0.0) + leapfrog: reactive[bool] = reactive(True) + + def render(self) -> Text: + result = Text() + label_w = 10 + + # Status row + result.append("Status".ljust(label_w), style="#506878") + if self.state == "CONNECTED": + result.append("CONNECTED", style="#00e060 bold") + elif self.state == "LISTENING": + result.append("LISTENING", style="#e8a020 bold") + else: + result.append("STOPPED", style="#e04040") + result.append("\n") + + # Bind address row (shown as part of status context) + result.append("Client".ljust(label_w), style="#506878") + if self.client: + result.append(self.client, style="#c8d0d8") + else: + result.append("(none)", style="#384858") + result.append("\n") + + # Move statistics row + result.append("Moves".ljust(label_w), style="#506878") + result.append(f"{self.moves}", style="#c8d0d8") + result.append(" Rate: ", style="#506878") + result.append(f"{self.rate:.1f}/s", style="#c8d0d8") + result.append(" Leapfrog: ", style="#506878") + if self.leapfrog: + result.append("ON", style="#00e060 bold") + else: + result.append("OFF", style="#506878") + + return result + + def watch_state(self, _value: str) -> None: + self.refresh() + + def watch_client(self, _value: str) -> None: + self.refresh() + + def watch_moves(self, _value: int) -> None: + self.refresh() + + def watch_rate(self, _value: float) -> None: + self.refresh() + + def watch_leapfrog(self, _value: bool) -> None: + self.refresh() diff --git a/tui/tests/test_sweep_stop.py b/tui/tests/test_sweep_stop.py index 479207a..5bed8a5 100644 --- a/tui/tests/test_sweep_stop.py +++ b/tui/tests/test_sweep_stop.py @@ -134,8 +134,7 @@ async def test_sweep_restart_after_stop(): assert not signal._sweeping, "Sweep still running after polling" assert len(signal._sweep_data) > 0, ( - f"First sweep should have data; " - f"device type={type(signal._device).__name__}" + f"First sweep should have data; device type={type(signal._device).__name__}" ) # Second sweep. diff --git a/tui/uv.lock b/tui/uv.lock index 7e82e23..d6918f4 100644 --- a/tui/uv.lock +++ b/tui/uv.lock @@ -5,7 +5,7 @@ requires-python = ">=3.11" [[package]] name = "birdcage" version = "2026.2.12.1" -source = { directory = "../" } +source = { editable = "../" } dependencies = [ { name = "click" }, { name = "pyserial" }, @@ -26,12 +26,24 @@ dependencies = [ { name = "textual" }, ] +[package.dev-dependencies] +dev = [ + { name = "pytest" }, + { name = "pytest-asyncio" }, +] + [package.metadata] requires-dist = [ - { name = "birdcage", directory = "../" }, + { name = "birdcage", editable = "../" }, { name = "textual", specifier = ">=1.0.0" }, ] +[package.metadata.requires-dev] +dev = [ + { name = "pytest", specifier = ">=9.0.2" }, + { name = "pytest-asyncio", specifier = ">=1.3.0" }, +] + [[package]] name = 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identifying initialized vs. uninitialized (0x10101 sentinel) entries. --- scripts/boot_baud_probe.py | 197 +++++++++++++++++++++++++++++++ scripts/boot_capture.py | 229 +++++++++++++++++++++++++++++++++++++ scripts/ee_dump.py | 76 ++++++++++++ 3 files changed, 502 insertions(+) create mode 100644 scripts/boot_baud_probe.py create mode 100644 scripts/boot_capture.py create mode 100644 scripts/ee_dump.py diff --git a/scripts/boot_baud_probe.py b/scripts/boot_baud_probe.py new file mode 100644 index 0000000..a2c8695 --- /dev/null +++ b/scripts/boot_baud_probe.py @@ -0,0 +1,197 @@ +#!/usr/bin/env python3 +"""Probe G2 bootloader at different baud rates and try interrupt sequences. + +The bootloader phase is <50ms. This script: +1. Shows the raw hex of the garbage bytes after "Application is running..." +2. Tries rebooting at different baud rates to decode the bootloader's native rate +3. Tries sending interrupt sequences during the bootloader window + +Usage: + uv run scripts/boot_baud_probe.py +""" + +import time + +import serial + +PORT = "/dev/ttyUSB2" +APP_BAUD = 115200 + + +def reboot_and_capture( + port: str, + capture_baud: int, + duration: float = 5.0, + pre_interrupt: bytes | None = None, + interrupt_delay: float = 0.01, +) -> bytes: + """Reboot at app baud, optionally switch to capture_baud, read everything.""" + + # Open at application baud rate to send reboot command + ser = serial.Serial(port, APP_BAUD, timeout=0.5) + ser.reset_input_buffer() + + # Make sure we're at a prompt — send CR + ser.write(b"\r") + time.sleep(0.3) + resp = ser.read(4096).decode("utf-8", errors="replace") + + if "OS>" not in resp: + if "TRK>" in resp: + ser.write(b"os\r") + time.sleep(0.3) + ser.read(4096) + else: + ser.write(b"q\r") + time.sleep(0.3) + ser.read(4096) + ser.write(b"os\r") + time.sleep(0.3) + ser.read(4096) + + ser.reset_input_buffer() + ser.write(b"reboot\r") + + # If we need to switch baud rate, do it immediately + if capture_baud != APP_BAUD: + time.sleep(0.01) # tiny delay for reboot cmd to be sent + ser.baudrate = capture_baud + + # Send interrupt if requested + if pre_interrupt: + time.sleep(interrupt_delay) + if pre_interrupt == b"BREAK": + ser.send_break(duration=0.25) + else: + ser.write(pre_interrupt) + + # Capture everything + buf = bytearray() + start = time.monotonic() + ser.timeout = 0.05 + while time.monotonic() - start < duration: + data = ser.read(4096) + if data: + buf.extend(data) + + ser.close() + return bytes(buf) + + +def hex_dump(data: bytes, prefix: str = " ") -> None: + """Print hex dump with ASCII sidebar.""" + for i in range(0, len(data), 16): + chunk = data[i : i + 16] + hex_part = " ".join(f"{b:02x}" for b in chunk) + ascii_part = "".join(chr(b) if 32 <= b < 127 else "." for b in chunk) + print(f"{prefix}{i:04x}: {hex_part:<48s} {ascii_part}") + + +def main(): + print("=" * 70) + print("G2 BOOTLOADER BAUD RATE PROBE") + print("=" * 70) + + # --- Phase 1: Capture raw boot at 115200 and show hex --- + print("\n--- Phase 1: Raw boot capture at 115200 (hex dump) ---\n") + data = reboot_and_capture(PORT, APP_BAUD, duration=2.0) + print(f"Captured {len(data)} bytes:\n") + hex_dump(data) + + # Find the garbage bytes between "running..." and "Application Starting" + idx1 = data.find(b"running...") + idx2 = data.find(b"Application Starting") + if idx1 >= 0 and idx2 >= 0: + between = data[idx1 + len(b"running...") : idx2] + print("\nBytes between 'running...' and 'Application Starting':") + print(f" Raw: {between!r}") + print(f" Hex: {between.hex(' ')}") + print(f" Len: {len(between)}") + + # Wait for boot to complete + print("\n Waiting for boot to complete...") + time.sleep(12) + + # --- Phase 2: Try different baud rates during bootloader --- + test_bauds = [9600, 19200, 38400, 57600, 115200, 230400, 460800] + + print("\n--- Phase 2: Bootloader at different baud rates ---\n") + for baud in test_bauds: + print(f"\n Trying {baud} baud...") + data = reboot_and_capture(PORT, baud, duration=2.0) + + # Filter to just the first ~200 bytes (bootloader phase) + preview = data[:200] + # Check if it looks like readable ASCII + ascii_count = sum(1 for b in preview if 32 <= b < 127 or b in (10, 13)) + ratio = ascii_count / max(len(preview), 1) + + print(f" Captured {len(data)} bytes, ASCII ratio: {ratio:.0%}") + if ratio > 0.5: + text = preview.decode("utf-8", errors="replace") + print(f" Preview: {text[:120]!r}") + else: + if preview: + print(f" Hex: {preview[:32].hex(' ')}") + + # Wait for boot + time.sleep(12) + + # --- Phase 3: Try interrupt sequences at 115200 --- + print("\n--- Phase 3: Interrupt sequences at 115200 ---\n") + + interrupts = [ + (0.005, "5ms CR", b"\r\r\r\r\r"), + (0.005, "5ms ESC", b"\x1b\x1b\x1b"), + (0.005, "5ms BREAK", b"BREAK"), + (0.005, "5ms 0x55 autobaud", b"\x55\x55\x55\x55\x55"), + (0.005, "5ms 0x7F (DEL)", b"\x7f\x7f\x7f"), + (0.005, "5ms 'bl'", b"bl\r"), + (0.01, "10ms CR burst", b"\r" * 20), + (0.02, "20ms '?' burst", b"?\r?\r?\r"), + (0.03, "30ms CR", b"\r\r\r"), + ] + + for delay, desc, payload in interrupts: + print(f"\n [{desc}] (delay={delay}s)") + data = reboot_and_capture( + PORT, APP_BAUD, duration=3.0, pre_interrupt=payload, interrupt_delay=delay + ) + + text = data.decode("utf-8", errors="replace") + + # Look for anything unusual (not normal boot) + normal_markers = ["Application Starting", "MotorInit", "BCM4515"] + unusual = False + + # Check if we got a response BEFORE normal boot messages + bl_idx = text.find("Bootloader version") + app_idx = text.find("Application Starting") + + if bl_idx >= 0 and app_idx >= 0: + between = text[bl_idx:app_idx] + if len(between) > 80: # more than just "Bootloader version: 1.01\r\n..." + unusual = True + print(" *** EXTRA DATA in bootloader phase! ***") + print(f" Between BL and App: {between!r}") + + if "BL>" in text or "CMD>" in text or "download" in text.lower(): + unusual = True + print(" *** BOOTLOADER PROMPT DETECTED ***") + + if not unusual: + # Check if boot proceeded normally + if any(m in text for m in normal_markers): + print(" Normal boot (no intercept)") + else: + print(f" Unexpected: {text[:150]!r}") + + time.sleep(12) + + print("\n" + "=" * 70) + print("PROBE COMPLETE") + print("=" * 70) + + +if __name__ == "__main__": + main() diff --git a/scripts/boot_capture.py b/scripts/boot_capture.py new file mode 100644 index 0000000..0a72703 --- /dev/null +++ b/scripts/boot_capture.py @@ -0,0 +1,229 @@ +#!/usr/bin/env python3 +"""Reboot G2 firmware and capture boot output with timestamps. + +Pass 1: Observe boot sequence timing. +Pass 2: Try interrupt sequences during bootloader phase. + +Usage: + uv run scripts/boot_capture.py [--interrupt] +""" + +import argparse +import time + +import serial + +PORT = "/dev/ttyUSB2" +BAUD = 115200 +BOOT_CAPTURE_SECS = 30 # how long to capture after reboot + + +def timestamp() -> str: + return f"{time.monotonic():.4f}" + + +def capture_boot(ser: serial.Serial, duration: float) -> list[tuple[float, bytes]]: + """Read all data for `duration` seconds, returning (time, data) pairs.""" + chunks = [] + start = time.monotonic() + ser.timeout = 0.05 # 50ms polling + while time.monotonic() - start < duration: + data = ser.read(4096) + if data: + chunks.append((time.monotonic() - start, data)) + return chunks + + +def enter_os_and_reboot(ser: serial.Serial) -> None: + """Navigate to OS menu and send reboot command.""" + ser.reset_input_buffer() + + # We left the port in the OS> menu before closing mcserial. + # But the port close/reopen may have reset state. Try sending + # a bare CR first to see where we are. + ser.write(b"\r") + time.sleep(0.3) + response = ser.read(4096) + decoded = response.decode("utf-8", errors="replace") + print(f" Prompt check: {decoded.strip()!r}") + + if "OS>" in decoded: + print(" Already in OS menu.") + elif "TRK>" in decoded: + print(" At root prompt, entering OS menu...") + ser.write(b"os\r") + time.sleep(0.3) + ser.read(4096) # consume echo + elif "MOT>" in decoded or "DVB>" in decoded: + print(" In a submenu, exiting to root first...") + ser.write(b"q\r") + time.sleep(0.3) + ser.read(4096) + ser.write(b"os\r") + time.sleep(0.3) + ser.read(4096) + else: + # Unknown state — try brute force: q to root, then os + print(" Unknown state, trying q -> os...") + ser.write(b"q\r") + time.sleep(0.3) + ser.read(4096) + ser.write(b"os\r") + time.sleep(0.3) + ser.read(4096) + + # Flush buffer + ser.reset_input_buffer() + + print(" Sending 'reboot' command...") + ser.write(b"reboot\r") + + +def pass1_observe(ser: serial.Serial) -> list[tuple[float, bytes]]: + """Reboot and passively observe boot output.""" + print("\n=== PASS 1: OBSERVE BOOT SEQUENCE ===\n") + enter_os_and_reboot(ser) + + print(f" Capturing for {BOOT_CAPTURE_SECS}s...\n") + chunks = capture_boot(ser, BOOT_CAPTURE_SECS) + + print("--- Boot Output (with timestamps) ---\n") + full_output = bytearray() + for t, data in chunks: + full_output.extend(data) + text = ( + data.decode("utf-8", errors="replace") + .replace("\r\n", "\n") + .replace("\r", "\n") + ) + for line in text.split("\n"): + if line.strip(): + print(f" [{t:7.3f}s] {line}") + + print(f"\n--- Total: {len(full_output)} bytes in {len(chunks)} chunks ---") + return chunks + + +def pass2_interrupt(ser: serial.Serial) -> None: + """Reboot and try interrupt sequences during bootloader phase.""" + print("\n=== PASS 2: INTERRUPT BOOT ===\n") + + # Interrupt sequences to try, with timing (seconds after reboot) + interrupts = [ + # (delay_after_reboot, description, bytes_to_send) + (0.05, "immediate CR", b"\r"), + (0.05, "immediate ESC", b"\x1b"), + (0.05, "immediate BREAK", "BREAK"), # special handling + (0.05, "immediate 0x55 (autobaud)", b"\x55\x55\x55\x55\x55"), + (0.05, "immediate space", b" "), + (0.1, "100ms CR", b"\r"), + (0.1, "100ms ESC", b"\x1b"), + (0.2, "200ms CR", b"\r"), + (0.5, "500ms CR+ESC", b"\r\x1b\r"), + (1.0, "1s CR", b"\r"), + (1.0, "1s 'bl'", b"bl\r"), + (1.0, "1s 'boot'", b"boot\r"), + (2.0, "2s CR", b"\r"), + (2.0, "2s '?'", b"?\r"), + ] + + for delay, desc, payload in interrupts: + print(f"\n--- Trying: {desc} (at +{delay}s) ---") + enter_os_and_reboot(ser) + + # Wait for the specified delay + time.sleep(delay) + + # Send the interrupt + if payload == "BREAK": + ser.send_break(duration=0.25) + print(" Sent BREAK signal (250ms)") + else: + ser.write(payload) + print(f" Sent: {payload!r}") + + # Capture response for 5 seconds + chunks = capture_boot(ser, 8) + + full = bytearray() + for _, data in chunks: + full.extend(data) + text = full.decode("utf-8", errors="replace") + + # Check for interesting responses + interesting = False + for keyword in [ + "boot", + "loader", + "BL>", + "CMD>", + ">>", + "ready", + "download", + "upload", + "flash", + "update", + "xmodem", + "ymodem", + "zmodem", + "srec", + "hex", + "binary", + ]: + if keyword.lower() in text.lower(): + interesting = True + break + + if interesting: + print(" *** INTERESTING RESPONSE ***") + for t, data in chunks: + line = data.decode("utf-8", errors="replace").strip() + if line: + print(f" [{t:7.3f}s] {line}") + else: + # Print condensed summary + lines = [ln.strip() for ln in text.split("\n") if ln.strip()] + if lines: + print(f" Response: {len(full)} bytes, first: {lines[0][:80]!r}") + if len(lines) > 1: + print(f" last: {lines[-1][:80]!r}") + else: + print(f" No response ({len(full)} bytes)") + + # Wait for boot to complete before next attempt + print(" Waiting for full boot...") + time.sleep(max(0, BOOT_CAPTURE_SECS - 8 - delay)) + ser.reset_input_buffer() + + +def main(): + parser = argparse.ArgumentParser(description="G2 bootloader capture") + parser.add_argument( + "--interrupt", action="store_true", help="Pass 2: try interrupt sequences" + ) + parser.add_argument("--port", default=PORT) + parser.add_argument("--baud", type=int, default=BAUD) + args = parser.parse_args() + + print(f"Opening {args.port} @ {args.baud}...") + ser = serial.Serial(args.port, args.baud, timeout=1) + ser.reset_input_buffer() + + try: + pass1_observe(ser) + + if args.interrupt: + # Wait for boot to fully complete + print("\n Waiting for boot to settle...") + time.sleep(5) + ser.reset_input_buffer() + pass2_interrupt(ser) + except KeyboardInterrupt: + print("\n\nInterrupted by user.") + finally: + ser.close() + print("\nPort closed.") + + +if __name__ == "__main__": + main() diff --git a/scripts/ee_dump.py b/scripts/ee_dump.py new file mode 100644 index 0000000..6f3bace --- /dev/null +++ b/scripts/ee_dump.py @@ -0,0 +1,76 @@ +#!/usr/bin/env python3 +"""Dump all EEPROM indices from Winegard G2 firmware via RS-422.""" + +import re +import sys +import time + +import serial + +PORT = "/dev/ttyUSB2" +BAUD = 115200 +PROMPT = b">" +MAX_INDEX = 100 # scan up to this index + + +def send_cmd(ser: serial.Serial, cmd: str) -> str: + """Send command + CR, read until prompt '>'.""" + ser.reset_input_buffer() + ser.write(f"{cmd}\r".encode("ascii")) + buf = bytearray() + while True: + b = ser.read(1) + if len(b) == 0: + break # timeout + buf.append(b[0]) + if b[0] == ord(">"): + break + return buf.decode("utf-8", errors="ignore") + + +def main(): + ser = serial.Serial(PORT, BAUD, timeout=3) + time.sleep(0.1) + + # Navigate to EE submenu + send_cmd(ser, "q") # ensure root + resp = send_cmd(ser, "eeprom") + if "EE>" not in resp: + print(f"Failed to enter EEPROM menu: {resp!r}", file=sys.stderr) + ser.close() + sys.exit(1) + + print(f"{'Index':>5} {'Decimal':>10} {'Hex':>10} Status") + print("-" * 50) + + valid_count = 0 + for idx in range(MAX_INDEX + 1): + resp = send_cmd(ser, f"ee {idx}") + + # Parse response + if "Read value" in resp: + match = re.search(r"Read value = (\d+)", resp) + if match: + val = int(match.group(1)) + print(f"{idx:>5} {val:>10} 0x{val:08X} OK") + valid_count += 1 + elif "Failed to read" in resp: + match = re.search(r"val:(\d+)", resp) + val_str = match.group(1) if match else "?" + val = int(val_str) if val_str != "?" else 0 + print(f"{idx:>5} {val:>10} 0x{val:08X} INVALID") + else: + # Unknown response - might be end of range + clean = resp.strip().replace("\r\n", " | ") + print(f"{idx:>5} {'':>10} {'':>10} ERROR: {clean}") + + print("-" * 50) + print(f"Valid entries: {valid_count} / {MAX_INDEX + 1}") + + # Return to root + send_cmd(ser, "q") + ser.close() + + +if __name__ == "__main__": + main() From 1c27a8d15d595a0d756d7d0305b16922dfd7c165 Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 18:05:15 -0700 Subject: [PATCH 13/30] Add console-probe package for firmware console discovery Automated deep probe of Winegard firmware console interfaces. Discovers available commands via help parsing, submenu probing, and wordlist brute-force. Handles prompt-terminated serial I/O with the > character termination strategy. Modules: serial_io (prompt-aware I/O), discovery (auto-discovery), profile (DeviceProfile dataclass), report (JSON output), cli (argparse). --- src/console_probe/__init__.py | 1 + src/console_probe/cli.py | 362 ++++++++++++++ src/console_probe/discovery.py | 847 +++++++++++++++++++++++++++++++++ src/console_probe/profile.py | 34 ++ src/console_probe/report.py | 105 ++++ src/console_probe/serial_io.py | 105 ++++ 6 files changed, 1454 insertions(+) create mode 100644 src/console_probe/__init__.py create mode 100644 src/console_probe/cli.py create mode 100644 src/console_probe/discovery.py create mode 100644 src/console_probe/profile.py create mode 100644 src/console_probe/report.py create mode 100644 src/console_probe/serial_io.py diff --git a/src/console_probe/__init__.py b/src/console_probe/__init__.py new file mode 100644 index 0000000..6b661e6 --- /dev/null +++ b/src/console_probe/__init__.py @@ -0,0 +1 @@ +"""Generic embedded console command prober.""" diff --git a/src/console_probe/cli.py b/src/console_probe/cli.py new file mode 100644 index 0000000..13491af --- /dev/null +++ b/src/console_probe/cli.py @@ -0,0 +1,362 @@ +"""CLI entry point for the embedded console probe.""" + +from __future__ import annotations + +import argparse +import sys +from pathlib import Path + +import serial # pyright: ignore[reportMissingImports] + +from console_probe.discovery import ( + auto_discover, + discover_submenu_help, + enter_submenu, + generate_candidates, + navigate_to_root, + parse_help_output, + probe_commands, +) +from console_probe.profile import DeviceProfile +from console_probe.report import write_json_report +from console_probe.serial_io import send_cmd + +LINE_ENDINGS = {"cr": "\r", "lf": "\n", "crlf": "\r\n"} + + +def parse_args() -> argparse.Namespace: + parser = argparse.ArgumentParser( + description="Probe for hidden commands on an embedded console", + formatter_class=argparse.RawDescriptionHelpFormatter, + epilog="""\ +examples: + %(prog)s --port /dev/ttyUSB2 --baud 115200 + %(prog)s --deep + %(prog)s --discover-only --json /tmp/discover.json + %(prog)s --submenu mot + %(prog)s --wordlist scripts/wordlists/winegard.txt + %(prog)s --prompt "U-Boot>" --error "Unknown command" +""", + ) + + conn = parser.add_argument_group("connection") + conn.add_argument( + "--port", default="/dev/ttyUSB0", help="Serial port (default: /dev/ttyUSB0)" + ) + conn.add_argument( + "--baud", type=int, default=115200, help="Baud rate (default: 115200)" + ) + conn.add_argument( + "--line-ending", + choices=LINE_ENDINGS, + default="cr", + help="Line ending to send (default: cr)", + ) + + disc = parser.add_argument_group("discovery overrides") + disc.add_argument( + "--prompt", default=None, help="Override auto-detected root prompt" + ) + disc.add_argument( + "--error", default=None, help="Override auto-detected error string" + ) + disc.add_argument( + "--help-cmd", default="?", help="Command to request help (default: ?)" + ) + disc.add_argument( + "--exit-cmd", default="q", help="Command to exit submenu (default: q)" + ) + + probe = parser.add_argument_group("probing") + probe.add_argument( + "--discover-only", + action="store_true", + help="Discover commands via help only (no brute-force probing)", + ) + probe.add_argument( + "--deep", action="store_true", help="Probe all discovered submenus" + ) + probe.add_argument( + "--submenu", type=str, default=None, help="Probe a single submenu by name" + ) + probe.add_argument( + "--timeout", + type=float, + default=0.5, + help="Per-command timeout in seconds (default: 0.5)", + ) + probe.add_argument( + "--blocklist", + default="reboot,stow,def,q,Q", + help="Comma-separated commands to never send (default: reboot,stow,def,q,Q)", + ) + probe.add_argument( + "--wordlist", + action="append", + default=None, + metavar="FILE", + help="Extra candidate words file (one per line, repeatable)", + ) + probe.add_argument( + "--bundled", + action="append", + default=None, + metavar="FILE", + help="Bundled wordlist file (alias for --wordlist, repeatable)", + ) + + output = parser.add_argument_group("output") + output.add_argument( + "--json", metavar="FILE", default=None, help="Write results as JSON to FILE" + ) + + return parser.parse_args() + + +def _run_discover_only( + ser: serial.Serial, + profile: DeviceProfile, + help_cmd: str, +) -> dict[str, list[tuple[str, str]]]: + """Discover commands via submenu help only (no brute-force). + + Enters each discovered submenu, queries help, stores results in + ``profile.submenu_help``, and prints a summary. + + Returns an empty results dict (no probe hits). + """ + all_results: dict[str, list[tuple[str, str]]] = {} + total_commands = 0 + + submenus = list(profile.submenus) + if not submenus: + print(" No submenus to discover. Use --deep for brute-force probing.") + return all_results + + print(f"\nPhase 2: Discovering commands in {len(submenus)} submenus...\n") + + for menu in submenus: + label = menu.upper() + sub_prompt = enter_submenu(ser, menu, profile) + print(f" [{label}] Prompt: {sub_prompt}") + + entries = discover_submenu_help(ser, menu, profile, help_cmd=help_cmd) + profile.submenu_help[label] = entries + total_commands += len(entries) + + if entries: + print(f" [{label}] Found {len(entries)} commands:") + for entry in entries: + params = f" {entry.params}" if entry.params else "" + desc = f" -- {entry.description}" if entry.description else "" + print(f" {entry.name}{params}{desc}") + else: + print(f" [{label}] No commands found in help output.") + + # Empty probe results for this menu (discover-only) + all_results[label] = [] + + navigate_to_root(ser, profile) + print() + + print( + f"Discovery complete: {total_commands} commands across {len(submenus)} submenus" + ) + return all_results + + +def _run_deep_probe( + ser: serial.Serial, + profile: DeviceProfile, + candidates: list[str], + submenus_to_probe: list[str], + help_cmd: str, + timeout: float, +) -> dict[str, list[tuple[str, str]]]: + """Run submenu help discovery, then brute-force probe. + + For each submenu: discover help first, then probe candidates. + This populates both ``profile.submenu_help`` and the probe results, + enabling the report to show ``undiscovered`` commands (probe-only). + """ + all_results: dict[str, list[tuple[str, str]]] = {} + + for menu in submenus_to_probe: + label = menu.upper() + print(f"\n=== {label} submenu ===\n") + sub_prompt = enter_submenu(ser, menu, profile) + print(f" Prompt: {sub_prompt}") + + # Step 1: Discover via help + print(" Querying help...") + entries = discover_submenu_help(ser, menu, profile, help_cmd=help_cmd) + profile.submenu_help[label] = entries + help_names = {e.name for e in entries} + names_str = ", ".join(sorted(help_names)) + print(f" Help discovered {len(entries)} commands: {names_str}") + + # Step 2: Brute-force probe + print(f" Probing {len(candidates)} candidates...") + sub_hits = probe_commands( + ser, candidates, sub_prompt, label, profile, timeout=timeout + ) + all_results[label] = sub_hits + + # Classify + undiscovered = [ + (cmd, resp) for cmd, resp in sub_hits if cmd.lower() not in help_names + ] + + print(f"\n--- {label} Results ---") + print(f" Help commands: {len(entries)}") + print(f" Probe hits: {len(sub_hits)}") + print(f" Undiscovered (probe-only): {len(undiscovered)}") + for cmd, resp in undiscovered: + print(f" '{cmd}' -> {resp}") + + navigate_to_root(ser, profile) + + return all_results + + +def main() -> None: + args = parse_args() + + profile = DeviceProfile( + port=args.port, + baud=args.baud, + line_ending=LINE_ENDINGS[args.line_ending], + exit_cmd=args.exit_cmd, + ) + + if args.prompt: + profile.root_prompt = args.prompt + profile.prompts = [args.prompt] + if args.error: + profile.error_string = args.error + + # Merge --bundled into --wordlist + wordlist_raw = (args.wordlist or []) + (args.bundled or []) + wordlist_paths = [Path(p) for p in wordlist_raw] if wordlist_raw else None + + # Build candidates (skip if discover-only) + blocklist = {w.strip() for w in args.blocklist.split(",") if w.strip()} + if not args.discover_only: + candidates = generate_candidates(blocklist, wordlist_paths) + print(f"Generated {len(candidates)} candidate commands\n") + else: + candidates = [] + + # Open serial + ser = serial.Serial(profile.port, profile.baud, timeout=1) + ser.reset_input_buffer() + + all_results: dict[str, list[tuple[str, str]]] = {} + + try: + # Auto-discovery + if not profile.root_prompt or not profile.error_string: + profile = auto_discover(ser, profile) + else: + print("Using overrides:") + print(f" Root prompt: {profile.root_prompt}") + print(f' Error string: "{profile.error_string}"') + + print(f" Sending help command: {args.help_cmd}") + help_resp = send_cmd(ser, args.help_cmd, profile, timeout=2.0) + commands, submenus = parse_help_output(help_resp, profile) + profile.known_commands = commands + if not profile.submenus: + profile.submenus = submenus + for sub in profile.submenus: + sub_prompt = f"{sub.upper()}>" + if sub_prompt not in profile.prompts: + profile.prompts.append(sub_prompt) + + if commands: + print( + f" Known commands ({len(commands)}): {', '.join(sorted(commands))}" + ) + if submenus: + print(f" Submenus ({len(submenus)}): {', '.join(submenus)}") + print() + + if not profile.root_prompt: + print( + "ERROR: Could not determine root prompt. Use --prompt to specify.", + file=sys.stderr, + ) + sys.exit(1) + + prompt = navigate_to_root(ser, profile) + print(f"Starting at: {prompt}\n") + + # --- Discover-only mode --- + if args.discover_only: + all_results = _run_discover_only(ser, profile, args.help_cmd) + + if args.json: + write_json_report(Path(args.json), profile, all_results) + return + + # --- Standard probing --- + root_label = profile.root_prompt.rstrip(">$#").strip() or "ROOT" + print( + f"=== Probing {profile.root_prompt} (root) " + f"-- {len(candidates)} candidates ===\n" + ) + + root_hits = probe_commands( + ser, + candidates, + profile.root_prompt, + root_label, + profile, + timeout=args.timeout, + ) + all_results[root_label] = root_hits + + unknown_hits = [ + (cmd, resp) + for cmd, resp in root_hits + if cmd.lower() not in profile.known_commands + ] + known_count = len(root_hits) - len(unknown_hits) + + print("\n--- Root Results ---") + print(f" Total hits: {len(root_hits)}") + print(f" Known commands: {known_count}") + print(f" UNKNOWN commands: {len(unknown_hits)}") + for cmd, resp in unknown_hits: + print(f" '{cmd}' -> {resp}") + + # Submenu probing + submenus_to_probe: list[str] = [] + if args.submenu: + submenus_to_probe.append(args.submenu) + elif args.deep: + submenus_to_probe = list(profile.submenus) + + if submenus_to_probe: + sub_results = _run_deep_probe( + ser, + profile, + candidates, + submenus_to_probe, + args.help_cmd, + args.timeout, + ) + all_results.update(sub_results) + + if args.json: + write_json_report(Path(args.json), profile, all_results) + + except KeyboardInterrupt: + print("\n\nInterrupted.") + finally: + ser.close() + print("\nPort closed.") + + +if __name__ == "__main__": + main() diff --git a/src/console_probe/discovery.py b/src/console_probe/discovery.py new file mode 100644 index 0000000..25fd847 --- /dev/null +++ b/src/console_probe/discovery.py @@ -0,0 +1,847 @@ +"""Auto-discovery, help parsing, navigation, and probing for embedded consoles.""" + +from __future__ import annotations + +import re +import sys +import time + +import serial # pyright: ignore[reportMissingImports] + +from console_probe.profile import DeviceProfile, HelpEntry +from console_probe.serial_io import PROMPT_RE, detect_prompt, send_cmd + +# --------------------------------------------------------------------------- +# Help output parsing +# --------------------------------------------------------------------------- + +# Common parameter placeholder names that should never be treated as commands. +# These appear in help text like ``help []`` or ``set ``. +_PARAM_PLACEHOLDERS: set[str] = { + "command", + "commands", + "parameter", + "parameters", + "value", + "values", + "index", + "name", + "arg", + "args", + "argument", + "arguments", + "option", + "options", + "number", + "string", + "text", + "file", + "path", + "addr", + "address", + "size", + "count", + "offset", + "length", + "data", + "byte", + "bytes", + "word", + "type", + "mode", + "level", + "pin", + "port", + "id", + "key", +} + + +def _inside_brackets(text: str, pos: int) -> bool: + """Return True if *pos* falls inside ``[...]`` in *text*. + + Counts unmatched ``[`` characters before *pos*. If the count is odd, + the position is inside brackets (parameter syntax). + """ + depth = 0 + for i in range(pos): + ch = text[i] + if ch == "[": + depth += 1 + elif ch == "]": + depth = max(0, depth - 1) + return depth > 0 + + +# Shared regex patterns for help parsing +_CMD_DASH_RE = re.compile(r"^\s*(\w[\w.]*)\s+[-\u2014]\s+") +_CMD_SPACES_RE = re.compile(r"^\s{0,4}(\w[\w.]*)\s{2,}") +_BARE_CMD_RE = re.compile(r"^\s{0,4}(\w[\w.]*)\s*$") +_BRACKET_RE = re.compile(r"<(\w[\w.]*)>") +_ENTER_RE = re.compile(r"[Ee]nter\s+?", re.IGNORECASE) +_MENU_RE = re.compile(r"(\w+)\s+[Mm]enu") +_SUBMENU_RE = re.compile(r"(\w+)\s+[Ss]ub-?[Mm]enu") + + +def parse_help_output( + help_text: str, + profile: DeviceProfile, +) -> tuple[set[str], list[str]]: + """Parse help output for command names and submenu hints. + + Returns (known_commands, submenu_names). + """ + commands: set[str] = set() + submenus: list[str] = [] + + for line in help_text.split("\n"): + stripped = line.strip() + if not stripped: + continue + if PROMPT_RE.fullmatch(stripped): + continue + + # Try angle-bracket commands first (e.g. "Enter - ...") + bracket_match = _BRACKET_RE.search(stripped) + if bracket_match: + cmd_name = bracket_match.group(1).lower() + # Reject if inside [...] brackets or is a known placeholder + if ( + len(cmd_name) <= 20 + and not _inside_brackets(stripped, bracket_match.start()) + and cmd_name not in _PARAM_PLACEHOLDERS + ): + commands.add(cmd_name) + else: + # Fall back to generic patterns + for pat in (_CMD_DASH_RE, _CMD_SPACES_RE, _BARE_CMD_RE): + m = pat.match(stripped) + if m: + cmd_name = m.group(1).lower() + if len(cmd_name) <= 20: + commands.add(cmd_name) + break + + # Look for submenu hints + enter_match = _ENTER_RE.search(stripped) + if enter_match: + sub = enter_match.group(1).lower() + if sub not in submenus and len(sub) <= 20: + submenus.append(sub) + else: + for pat in (_SUBMENU_RE, _MENU_RE): + m = pat.search(stripped) + if m: + sub = m.group(1).lower() + if sub not in submenus and len(sub) <= 20: + submenus.append(sub) + break + + return commands, submenus + + +def parse_help_structured( + help_text: str, + profile: DeviceProfile, +) -> list[HelpEntry]: + """Parse help output into structured entries with descriptions and params. + + Same regex logic as ``parse_help_output`` but captures description text + (everything after `` - `` or double-space separator) and parameter syntax + (text in ``[...]`` / ``<...>``). + """ + entries: list[HelpEntry] = [] + seen: set[str] = set() + + # Extended patterns that capture descriptions + # "command - description" or "command --- description" + cmd_desc_re = re.compile(r"^\s*(\w[\w.]*)\s+[-\u2014]+\s+(.*)") + # "command Description text" (2+ spaces after command) + cmd_space_desc_re = re.compile(r"^\s{0,4}(\w[\w.]*)\s{2,}(\S.*)") + + # Parameter syntax: text in [...] or <...> on the same line as the command + param_re = re.compile(r"(\[.*?\]|<\w[\w.]*>)") + + for line in help_text.split("\n"): + stripped = line.strip() + if not stripped: + continue + if PROMPT_RE.fullmatch(stripped): + continue + + cmd_name: str | None = None + description = "" + + # Try angle-bracket commands: "Enter - Motor driver" + bracket_match = _BRACKET_RE.search(stripped) + if bracket_match: + candidate = bracket_match.group(1).lower() + if ( + len(candidate) <= 20 + and not _inside_brackets(stripped, bracket_match.start()) + and candidate not in _PARAM_PLACEHOLDERS + ): + cmd_name = candidate + # Description is everything after the bracket match + separator + rest = stripped[bracket_match.end() :] + desc_m = re.match(r"\s*[-\u2014]+\s*(.*)", rest) + if desc_m: + description = desc_m.group(1).strip() + elif rest.strip(): + description = rest.strip() + + if not cmd_name: + # "command - description" + m = cmd_desc_re.match(stripped) + if m: + cmd_name = m.group(1).lower() + description = m.group(2).strip() + else: + # "command Description" + m = cmd_space_desc_re.match(stripped) + if m: + cmd_name = m.group(1).lower() + description = m.group(2).strip() + else: + # Bare command name + m = _BARE_CMD_RE.match(stripped) + if m: + cmd_name = m.group(1).lower() + + if cmd_name and len(cmd_name) <= 20 and cmd_name not in seen: + # Extract parameter syntax from the full line + params_parts = param_re.findall(stripped) + # Filter out parts that are just the command name in brackets + params = " ".join( + p for p in params_parts if p.strip("[]<>").lower() != cmd_name + ) + + seen.add(cmd_name) + entries.append( + HelpEntry( + name=cmd_name, + description=description, + params=params, + ) + ) + + return entries + + +# --------------------------------------------------------------------------- +# Submenu help discovery +# --------------------------------------------------------------------------- + + +def discover_submenu_help( + ser: serial.Serial, + menu: str, + profile: DeviceProfile, + help_cmd: str = "?", + extra_help_cmds: list[str] | None = None, +) -> list[HelpEntry]: + """Query help in the current submenu and parse structured entries. + + Assumes the caller has already navigated into the submenu. + + Sends *help_cmd* (default ``?``), then tries *extra_help_cmds* + (default ``["man"]``) for firmware with paginated help (e.g. DVB submenu). + Merges results from all help commands, deduplicating by command name. + """ + if extra_help_cmds is None: + extra_help_cmds = ["man"] + + # Primary help + help_resp = send_cmd(ser, help_cmd, profile, timeout=3.0) + entries = parse_help_structured(help_resp, profile) + + # Try extra help commands for multi-page help + seen_names = {e.name for e in entries} + for extra_cmd in extra_help_cmds: + extra_resp = send_cmd(ser, extra_cmd, profile, timeout=3.0) + extra_entries = parse_help_structured(extra_resp, profile) + + # Only merge if the response looks like real help output + # (at least 3 entries and has new commands) + new_entries = [e for e in extra_entries if e.name not in seen_names] + if len(extra_entries) >= 3 and new_entries: + entries.extend(new_entries) + seen_names.update(e.name for e in new_entries) + + return entries + + +# --------------------------------------------------------------------------- +# Error string detection +# --------------------------------------------------------------------------- + + +def detect_error_string(ser: serial.Serial, profile: DeviceProfile) -> str | None: + """Send a garbage command and extract the error message template.""" + resp = send_cmd(ser, "__xyzzy_probe__", profile, timeout=1.0) + + # Strip the echo of our command and any prompt + lines = resp.replace("__xyzzy_probe__", "").strip().split("\n") + content_lines = [] + for line in lines: + stripped = line.strip() + if not stripped: + continue + if PROMPT_RE.fullmatch(stripped): + continue + stripped = PROMPT_RE.sub("", stripped).strip() + if stripped: + content_lines.append(stripped) + + if content_lines: + return content_lines[0].strip() + return None + + +# --------------------------------------------------------------------------- +# Auto-discovery +# --------------------------------------------------------------------------- + + +def auto_discover(ser: serial.Serial, profile: DeviceProfile) -> DeviceProfile: + """Run the discovery sequence and populate the profile.""" + print("Phase 1: Auto-discovering device console...\n") + + prompt = detect_prompt(ser, profile) + if prompt: + profile.root_prompt = prompt + profile.prompts = [prompt] + print(f" Root prompt: {prompt}") + else: + print(" WARNING: Could not detect root prompt.") + print(" Use --prompt to specify manually.") + + err = detect_error_string(ser, profile) + if err: + profile.error_string = err + print(f' Error string: "{err}"') + else: + print(" WARNING: Could not detect error string.") + print(" Use --error to specify manually.") + + print(" Sending help command: ?") + help_resp = send_cmd(ser, "?", profile, timeout=2.0) + + commands, submenus = parse_help_output(help_resp, profile) + if commands: + profile.known_commands = commands + print(f" Known commands ({len(commands)}): {', '.join(sorted(commands))}") + else: + print(" No commands parsed from help output.") + + if submenus: + profile.submenus = submenus + print(f" Detected submenus ({len(submenus)}): {', '.join(submenus)}") + else: + print(" No submenus detected from help output.") + + # Build prompt list from submenus + for sub in profile.submenus: + sub_prompt = f"{sub.upper()}>" + if sub_prompt not in profile.prompts: + profile.prompts.append(sub_prompt) + + print() + return profile + + +# --------------------------------------------------------------------------- +# Navigation +# --------------------------------------------------------------------------- + + +def navigate_to_root(ser: serial.Serial, profile: DeviceProfile) -> str: + """Send exit command until we're at the root prompt.""" + # Check if already at root (bare CR won't kill anything) + resp = send_cmd(ser, "", profile) + if profile.root_prompt and profile.root_prompt in resp: + return profile.root_prompt + + for _ in range(5): + resp = send_cmd(ser, profile.exit_cmd, profile) + if profile.root_prompt and profile.root_prompt in resp: + return profile.root_prompt + last_line = resp.strip().split("\n")[-1].strip() + m = PROMPT_RE.search(last_line) + if m: + detected = m.group(1) + if not profile.root_prompt: + profile.root_prompt = detected + if detected == profile.root_prompt: + return detected + + # Last resort + resp = send_cmd(ser, "", profile) + last_line = resp.strip().split("\n")[-1].strip() + return last_line + + +def enter_submenu(ser: serial.Serial, menu: str, profile: DeviceProfile) -> str: + """Enter a submenu and return the prompt we land on.""" + navigate_to_root(ser, profile) + resp = send_cmd(ser, menu, profile) + lines = resp.strip().split("\n") + last = lines[-1].strip() if lines else "" + + m = PROMPT_RE.search(last) + if m: + new_prompt = m.group(1) + if new_prompt not in profile.prompts: + profile.prompts.append(new_prompt) + return new_prompt + return last + + +# --------------------------------------------------------------------------- +# Response cleaning +# --------------------------------------------------------------------------- + + +def clean_response( + resp: str, + cmd: str, + profile: DeviceProfile, +) -> str: + """Strip echo, prompts, and whitespace from a response.""" + clean = resp + + for suffix in ("\r\n", "\r", "\n", ""): + clean = clean.replace(f"{cmd}{suffix}", "", 1) + + clean = clean.strip() + + for p in profile.prompts: + clean = clean.replace(p, "") + + clean = PROMPT_RE.sub("", clean) + return clean.strip() + + +# --------------------------------------------------------------------------- +# Probing +# --------------------------------------------------------------------------- + + +def probe_commands( + ser: serial.Serial, + candidates: list[str], + prompt: str, + label: str, + profile: DeviceProfile, + timeout: float = 0.5, +) -> list[tuple[str, str]]: + """Probe candidates at the current menu level. Returns (cmd, preview) hits.""" + hits = [] + total = len(candidates) + + for i, cmd in enumerate(candidates): + if (i + 1) % 50 == 0: + print(f" [{label}] Progress: {i + 1}/{total}...", flush=True) + + resp = send_cmd(ser, cmd, profile, timeout=timeout) + clean = clean_response(resp, cmd, profile) + + is_error = profile.error_string and profile.error_string in resp + if not is_error and clean: + preview = clean[:100].replace("\r\n", " | ").replace("\n", " | ") + hits.append((cmd, preview)) + print(f" *** HIT: '{cmd}' -> {preview}", flush=True) + + # Recover from submenu exits + if "Terminating shell" in resp or "exiting" in resp.lower(): + if profile.root_prompt and prompt != profile.root_prompt: + print(f" ('{cmd}' exited submenu, re-entering...)") + menu_name = prompt.replace(">", "").strip().lower() + enter_submenu(ser, menu_name, profile) + else: + print(f" ('{cmd}' terminated shell, waiting for restart...)") + time.sleep(1.0) + check = send_cmd(ser, "", profile) + if profile.root_prompt and profile.root_prompt not in check: + print( + " WARNING: Shell did not restart. Remaining " + "results may be incomplete.", + flush=True, + ) + + return hits + + +# --------------------------------------------------------------------------- +# Candidate generation +# --------------------------------------------------------------------------- + + +def generate_candidates( + blocklist: set[str], + wordlist_paths: list | None = None, +) -> list[str]: + """Build the candidate command list. + + Includes generic embedded debug commands + single chars + two-letter combos. + Merges in any external wordlist files. Applies blocklist last. + """ + import string + from pathlib import Path + + candidates: list[str] = [] + + # Single characters + candidates.extend(list(string.ascii_lowercase)) + candidates.extend(list(string.ascii_uppercase)) + candidates.extend(list(string.digits)) + + # Generic embedded debug commands + generic = [ + # Memory access + "md", + "mw", + "mm", + "mr", + "mem", + "peek", + "poke", + "rd", + "wr", + "read", + "write", + "dump", + "load", + "save", + "md.b", + "md.w", + "md.l", + "x", + "xx", + "xd", + # Flash + "flash", + "fl", + "erase", + "program", + "verify", + "protect", + "flinfo", + "fldump", + "flashdump", + # Boot / system + "boot", + "reboot", + "reset", + "go", + "run", + "exec", + "jump", + "bootd", + "bootm", + "bootp", + "version", + "ver", + "info", + "about", + "sysinfo", + "uptime", + "date", + "time", + "clk", + "clock", + # Debug + "debug", + "dbg", + "trace", + "log", + "print", + "echo", + "test", + "diag", + "selftest", + "bist", + "bench", + "assert", + "crash", + "fault", + "panic", + # Shell / OS + "sh", + "shell", + "cmd", + "command", + "cli", + "task", + "tasks", + "ps", + "top", + "threads", + "kill", + "suspend", + "resume", + "heap", + "stack", + "free", + "malloc", + "meminfo", + "cpu", + "cpuinfo", + "temp", + "temperature", + # Network / comms + "ping", + "net", + "ifconfig", + "ip", + "mac", + "uart", + "serial", + "spi", + "i2c", + "can", + # Service / factory + "factory", + "service", + "mfg", + "production", + "prod", + "cal", + "calibrate", + "calibration", + "config", + "cfg", + "setup", + "settings", + "hidden", + "secret", + "admin", + "su", + "root", + "login", + "password", + "passwd", + "auth", + "unlock", + # Update + "update", + "upgrade", + "firmware", + "fw", + "ota", + "download", + "upload", + "xmodem", + "ymodem", + "zmodem", + "tftp", + "ftp", + # Generic hardware + "sw", + "hw", + "id", + "sn", + "help", + "man", + "usage", + # Two-letter combos + "bl", + "bt", + "db", + "dm", + "dp", + "ds", + "dt", + "eb", + "ed", + "ee", + "ef", + "em", + "en", + "ep", + "er", + "es", + "et", + "fa", + "fb", + "fc", + "fd", + "fe", + "ff", + "fg", + "fh", + "fi", + "fj", + "ga", + "gb", + "gc", + "gd", + "ge", + "gf", + "gg", + "gh", + "gi", + "gj", + "ha", + "hb", + "hc", + "hd", + "he", + "hf", + "hg", + "hh", + "hi", + "hj", + "ia", + "ib", + "ic", + "io", + "ir", + "ka", + "kb", + "kc", + "kd", + "ke", + "la", + "lb", + "lc", + "ld", + "le", + "lf", + "lg", + "lh", + "li", + "lj", + "ma", + "mb", + "mc", + "me", + "mf", + "mg", + "mh", + "mi", + "mj", + "na", + "nb", + "nc", + "nd", + "ne", + "nf", + "ng", + "nh", + "ni", + "nj", + "oa", + "ob", + "oc", + "od", + "oe", + "of", + "og", + "oh", + "oi", + "oj", + "pa", + "pb", + "pc", + "pd", + "pe", + "pf", + "pg", + "ph", + "pi", + "pj", + "ra", + "rb", + "rc", + "re", + "rf", + "rg", + "rh", + "ri", + "rj", + "sa", + "sb", + "sc", + "sd", + "se", + "sf", + "sg", + "si", + "sj", + "ta", + "tb", + "tc", + "td", + "te", + "tf", + "tg", + "th", + "ti", + "tj", + "ua", + "ub", + "uc", + "ud", + "ue", + "uf", + "ug", + "uh", + "ui", + "uj", + "va", + "vb", + "vc", + "vd", + "ve", + "vf", + "vg", + "vh", + "vi", + "vj", + "wa", + "wb", + "wc", + "wd", + "we", + "wf", + "wg", + "wh", + "wi", + "wj", + "za", + "zb", + "zc", + "zd", + "ze", + "zf", + ] + candidates.extend(generic) + + # Merge external wordlists + if wordlist_paths: + for wl_path in wordlist_paths: + p = Path(wl_path) if not isinstance(wl_path, Path) else wl_path + try: + text = p.read_text() + for line in text.split("\n"): + word = line.strip() + if word and not word.startswith("#"): + candidates.append(word) + except OSError as exc: + print( + f"WARNING: Could not read wordlist {p}: {exc}", + file=sys.stderr, + ) + + # Deduplicate preserving order + seen: set[str] = set() + unique: list[str] = [] + for c in candidates: + if c not in seen: + seen.add(c) + unique.append(c) + + # Apply blocklist + unique = [c for c in unique if c not in blocklist] + return unique diff --git a/src/console_probe/profile.py b/src/console_probe/profile.py new file mode 100644 index 0000000..a878660 --- /dev/null +++ b/src/console_probe/profile.py @@ -0,0 +1,34 @@ +"""Device profile and data structures for console probing.""" + +from __future__ import annotations + +from dataclasses import dataclass, field + + +@dataclass +class HelpEntry: + """A single command parsed from firmware help output. + + Captures the command name, any parameter syntax shown in brackets/angles, + and the description text (everything after the separator). + """ + + name: str # command name (lowercase) + description: str = "" # help description text + params: str = "" # parameter syntax from brackets, e.g. "[ [angle]]" + + +@dataclass +class DeviceProfile: + """Everything we know (or detected) about the attached console.""" + + port: str = "/dev/ttyUSB0" + baud: int = 115200 + root_prompt: str = "" # e.g. "TRK>" + prompts: list[str] = field(default_factory=list) # all known prompts + error_string: str = "" # e.g. "Invalid command." + known_commands: set[str] = field(default_factory=set) # from help output + submenus: list[str] = field(default_factory=list) # detected submenu names + exit_cmd: str = "q" + line_ending: str = "\r" + submenu_help: dict[str, list[HelpEntry]] = field(default_factory=dict) diff --git a/src/console_probe/report.py b/src/console_probe/report.py new file mode 100644 index 0000000..e28b9f1 --- /dev/null +++ b/src/console_probe/report.py @@ -0,0 +1,105 @@ +"""JSON report generation for console probe results.""" + +from __future__ import annotations + +import json +from pathlib import Path + +from console_probe.profile import DeviceProfile + +FORMAT_VERSION = 2 + + +def build_report( + profile: DeviceProfile, + results: dict[str, list[tuple[str, str]]], +) -> dict: + """Build the full JSON report structure. + + ``results`` maps menu labels (e.g. "TRK", "MOT") to lists of + ``(cmd, preview)`` probe hits. + + When ``profile.submenu_help`` is populated, the report includes a + ``menus`` section with per-submenu ``help_commands``, ``probe_hits``, + ``undiscovered`` (probe-only commands not in help), and stats. + """ + report: dict = { + "format_version": FORMAT_VERSION, + "device": {"port": profile.port, "baud": profile.baud}, + "detected": { + "root_prompt": profile.root_prompt, + "error_string": profile.error_string, + "known_commands": sorted(profile.known_commands), + "submenus": profile.submenus, + }, + } + + # Per-submenu structured output + if profile.submenu_help: + menus: dict = {} + for label, help_entries in profile.submenu_help.items(): + help_names = {e.name for e in help_entries} + + # Probe hits for this menu (may be empty if --discover-only) + probe_hits = results.get(label, []) + + # Undiscovered = probe hits whose names are NOT in help output + undiscovered = [ + {"cmd": cmd, "response": resp} + for cmd, resp in probe_hits + if cmd.lower() not in help_names + ] + + menus[label] = { + "prompt": f"{label}>", + "help_commands": [ + { + "cmd": e.name, + "description": e.description, + "params": e.params, + } + for e in help_entries + ], + "probe_hits": [ + {"cmd": cmd, "response": resp} for cmd, resp in probe_hits + ], + "undiscovered": undiscovered, + "stats": { + "help_count": len(help_entries), + "probe_count": len(probe_hits), + "undiscovered_count": len(undiscovered), + }, + } + + report["menus"] = menus + + # Legacy results section (backward compat) + report["results"] = {} + for label, hits in results.items(): + known_hits = [ + (cmd, resp) for cmd, resp in hits if cmd.lower() in profile.known_commands + ] + unknown_hits = [ + (cmd, resp) + for cmd, resp in hits + if cmd.lower() not in profile.known_commands + ] + report["results"][label] = { + "total_hits": len(hits), + "known": len(known_hits), + "unknown": len(unknown_hits), + "hits": [{"cmd": cmd, "response": resp} for cmd, resp in hits], + } + + return report + + +def write_json_report( + path: Path, + profile: DeviceProfile, + results: dict[str, list[tuple[str, str]]], +) -> None: + """Write machine-readable JSON probe report.""" + report = build_report(profile, results) + path.write_text(json.dumps(report, indent=2) + "\n") + print(f"\nJSON report written to {path}") diff --git a/src/console_probe/serial_io.py b/src/console_probe/serial_io.py new file mode 100644 index 0000000..e499b20 --- /dev/null +++ b/src/console_probe/serial_io.py @@ -0,0 +1,105 @@ +"""Serial I/O for prompt-terminated embedded consoles.""" + +from __future__ import annotations + +import re +import time + +import serial # pyright: ignore[reportMissingImports] + +from console_probe.profile import DeviceProfile + +PROMPT_RE = re.compile(r"(\S+[>$#])\s*$") + + +def _is_prompt_terminated(text: str, profile: DeviceProfile) -> bool: + """Check if *text* ends with a firmware prompt (not parameter syntax). + + When ``profile.prompts`` is populated, checks whether the last line ends + with one of the known prompt strings. Also accepts any PROMPT_RE match + on the last line **if** that line contains no ``[`` bracket (which would + indicate parameter syntax like ``[]``). + + When ``profile.prompts`` is empty (initial discovery phase), falls back + to the original heuristic: ``stripped.endswith(">")``. + """ + stripped = text.rstrip() + if not stripped: + return False + + last_line = stripped.split("\n")[-1] + + if profile.prompts: + # Check known prompts first (fast path) + last_stripped = last_line.rstrip() + for p in profile.prompts: + if last_stripped.endswith(p): + return True + + # Accept a PROMPT_RE match only if no brackets on that line + if "[" not in last_line: + m = PROMPT_RE.search(last_line) + if m: + return True + + return False + + # No known prompts yet — fallback to bare > check + return stripped.endswith(">") + + +def send_cmd( + ser: serial.Serial, + cmd: str, + profile: DeviceProfile, + timeout: float = 1.0, +) -> str: + """Send *cmd* + line-ending, read until a known prompt or timeout.""" + ser.reset_input_buffer() + ser.write(f"{cmd}{profile.line_ending}".encode("ascii", errors="replace")) + ser.timeout = timeout + + buf = bytearray() + deadline = time.monotonic() + timeout + while time.monotonic() < deadline: + chunk = ser.read(4096) + if chunk: + buf.extend(chunk) + text = buf.decode("utf-8", errors="replace") + if _is_prompt_terminated(text, profile): + break + elif buf: + text = buf.decode("utf-8", errors="replace") + if _is_prompt_terminated(text, profile): + break + + return buf.decode("utf-8", errors="replace") + + +def detect_prompt(ser: serial.Serial, profile: DeviceProfile) -> str | None: + """Send a bare line-ending and extract the prompt from the response.""" + ser.reset_input_buffer() + ser.write(profile.line_ending.encode("ascii")) + ser.timeout = 2.0 + + buf = bytearray() + deadline = time.monotonic() + 2.0 + while time.monotonic() < deadline: + chunk = ser.read(4096) + if chunk: + buf.extend(chunk) + text = buf.decode("utf-8", errors="replace") + tail = text.rstrip() + if tail.endswith((">", "#", "$")): + break + elif buf: + break + + text = buf.decode("utf-8", errors="replace").strip() + if not text: + return None + + # Take the last line, look for a prompt-like token + last_line = text.split("\n")[-1].strip() + m = PROMPT_RE.search(last_line) + return m.group(1) if m else (last_line if last_line else None) From bbdd406bca08f58f9ab3129ba28c366f5424c13f Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 18:36:23 -0700 Subject: [PATCH 14/30] Configure git-lfs for binary assets Track PDFs, images (PNG/JPG), SVGs, and 3D models (STEP/WRL) via git-lfs to keep repo clone size manageable as datasheets and extracted page images accumulate. --- .gitattributes | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 .gitattributes diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..e46ee45 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,7 @@ +*.png filter=lfs diff=lfs merge=lfs -text +*.jpg filter=lfs diff=lfs merge=lfs -text +*.jpeg filter=lfs diff=lfs merge=lfs -text +*.svg filter=lfs diff=lfs merge=lfs -text +*.step filter=lfs diff=lfs merge=lfs -text +*.wrl filter=lfs diff=lfs merge=lfs -text +*.pdf filter=lfs diff=lfs merge=lfs -text From 5252d1d73c1506b74b4874b19b1ee4a33e9a15b6 Mon Sep 17 00:00:00 2001 From: Ryan Malloy Date: Sat, 14 Feb 2026 18:36:42 -0700 Subject: [PATCH 15/30] Add hardware reference docs (A3981, K60, RYS352A) Allegro A3981 stepper motor driver: datasheet, KiCad symbols/footprint, 3D model (TSSOP-28). Two per G2 board, SPI-controlled, AUTO microstep. NXP MK60DN512VLQ10 (Kinetis K60): datasheet and 1300-page reference manual. Cortex-M4 96MHz MCU running the G2 firmware. Reyax RYS352A GPS module: datasheet and PAIR command guide. GPS receiver on the G2 board (used for auto-location/satellite lookup). All extracted as markdown + page images + vector SVGs for LLM context. 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mode 100644 docs/RYS352x_PAIR_Command_Guide.md create mode 100644 docs/RYS352x_PAIR_Command_Guide.pdf diff --git a/docs/A3981-datasheet.md b/docs/A3981-datasheet.md new file mode 100644 index 0000000..6c0cdba --- /dev/null +++ b/docs/A3981-datasheet.md @@ -0,0 +1,6095 @@ +# Document Metadata +**Format:** PDF 1.4 +**Creator:** Adobe InDesign 19.0 (Windows) +**Producer:** Adobe PDF Library 17.0 +**Creation Date:** D:20240711085554-04'00' +**Mod Date:** D:20240711085620-04'00' + +--- + +## Page 1 + +The A3981 is a flexible microstepping motor driver with built-in +translator for easy operation. It is a single-chip solution, designed +to operate bipolar stepper motors in full-, half-, quarter- and +sixteenth-step modes, at up to 28 V and ±1.4 A. The A3981 +can be controlled by simple Step and Direction inputs, or +through the SPI-compatible serial interface that also can be +used to program many of the integrated features and to read +diagnostic information. +The current regulator can be programmed to operate in fixed +off-time or fixed frequency PWM, with several decay modes +to reduce audible motor noise and increase step accuracy. +In addition the phase current tables can be programmed via +the serial interface to create unique microstep current profiles +to further improve motor performance for specific applications. +The current in each phase of the motor is controlled through a +DMOS full bridge, using synchronous rectification to improve +power dissipation. Internal circuits and timers prevent cross- +conduction and shoot-through, when switching between high- +side and low-side drives. +The outputs are protected from short circuits, and features +for low load current and stalled rotor detection are included. +Chip-level protection includes hot and cold thermal warnings, +overtemperature shutdown, and overvoltage and undervoltage +lockout. +The A3981 is supplied in a 28-pin TSSOP power package with +an exposed thermal pad (package type LP). This package is +lead (Pb) free with 100% matte-tin leadframe plating. +A3981-DS, Rev. 9 +MCO-0000738 +• Peak motor current up to ±1.4 A, 28 V +• Low RDS(on) outputs, 0.5 Ω source and sink, typical +• Automatic current decay mode detection/selection +• Mixed, Fast, and Slow current decay modes +• Synchronous rectification for low power dissipation +• Internal OVLO, UVLO, and Thermal Shutdown circuitry +• Crossover-current protection +• Short-circuit and open-load diagnostics +• Hot and cold thermal warning +• Stall detect features +• SPI-compatible or simple Step and Direction motion +control +• Highly configurable via SPI-compatible serial interface +APPLICATIONS +• Automotive stepper motors +• Engine management +• Headlamp positioning +Automotive Programmable Stepper Driver +PACKAGE: +28-Pin TSSOP with Exposed Thermal Pad +(suffix LP) +Typical Applications +Not to scale +A3981 +Automotive +12V Power Net +Logic +Supply +Serial Interface Control +Micro- +controller +or +ECU +OAP +PGND +VBB +OSC +OAM +OBP +OBM +Stepper +Motor +AGND +VCP +STEP +DIR +MS0 +MS1 +ENABLE +RESETn +SDI +SDO +SCK +STRn +VDD +DIAG +SENSA +SENSB +REF +VREG +CP1 CP2 +Parallel Control +Automotive +12V Power Net +Logic +Supply +or +ECU +OAP +PGND +VBB +OSC +OAM +OBP +OBM +Stepper +Motor +AGND +VCP +STEP +DIR +MS0 +MS1 +ENABLE +RESETn +SDI +SDO +SCK +STRn +VDD +DIAG +SENSA +SENSB +REF +VREG +CP1 CP2 +Micro- +controller +FEATURES AND BENEFITS +DESCRIPTION +July 11, 2024 + +![Image 1 from page 1](pdf-image://page_1_img_1) + +![Image 2 from page 1](pdf-image://page_1_img_2) + +## Page 2 + +Automotive Programmable Stepper Driver +A3981 +2 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +SELECTION GUIDE +Part Number +Packing\* +A3981KLPTR-T +4000 pieces per reel +4.4 mm × 9.7 mm, 1.2 mm nominal height TSSOP with +exposed thermal pad +\*Contact Allegro™ for additional packing information. +ABSOLUTE MAXIMUM RATINGS with respect to GND +Characteristic +Symbol +Notes +Rating +Unit +Load Supply Voltage +VBBx +Applies to VBBA and VBBB +–0.3 to 50 +V +Logic Supply Voltage +VDD +–0.3 to 6 +V +Pin CP1 +–0.3 to VBB +V +Pins CP2, VCP +–0.3 to VBB+8 +V +Pins STEP, DIR, ENABLE, DIAG +–0.3 to 6 +V +Pin VREG +–0.3 to 8.5 +V +Pin RESETn +Can be pulled to VBB with 38 kΩ +–0.3 to 6 +V +Pin OSC +–0.3 to 6 +V +Pins MS0, MS1 +–0.3 to 6 +V +Pins SDI, SDO, SCK, STRn +–0.3 to 6 +V +Pin REF +–0.3 to 6 +V +Pins OAP, OAM, OBP, OBM +–0.3 to VBB +V +Pins SENSA, SENSB +–0.3 to 1 +V +Ambient Operating Temperature +Range +TA +Range K; limited by power dissipation +–40 to 150 +°C +Maximum Continuous Junction +Temperature +TJ(max) +150 +°C +Transient Junction Temperature +TtJ +Overtemperature event not exceeding 10 s, lifetime +duration not exceeding 10 hours, guaranteed by design and +characterization +175 +°C +Storage Temperature Range +Tstg +–55 to 150 +°C +THERMAL CHARACTERISTICS: May require derating at maximum conditions +Characteristic +Symbol +Test Conditions\* +Value +Unit +Package Thermal Resistance +(Junction to Ambient) +RθJA +4-layer PCB based on JEDEC standard +28 +°C/W +2-layer PCB with 24.52 cm2 of copper area each side +32 +°C/W +Package Thermal Resistance +(Junction to Pad) +RθJP +2 +°C/W +\*Additional thermal information available on the Allegro website +SPECIFICATIONS + +![Image 1 from page 2](pdf-image://page_2_img_1) + +## Page 3 + +Automotive Programmable Stepper Driver +A3981 +3 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +DMOS Full Bridge +DMOS Full Bridge +Gate +Drive +Charge +Pump +STEP +REF +6-bit +DAC +6-bit +DAC +Oscillator ++ +- ++ +- +SENSB +SENSA +VCP +VBBA +OAP +OAM +SENSA +VBBB +OBP +OBM +SENSB +DIR +RESETn +ENABLE +VDD +DIAG +REF +3.3V +VBAT +VBAT +SDI +SDO +SCK +STRn +DAC +REF +PWM +Control +Bridge +Control +Logic +PWM +Control +Translator +Serial Interface +System +Control +and +Registers +Undervoltage, Overvoltage +Cold Warning, Hot Warning, Overtemperature +Short Detect, Open Load Detect +Stall Detect +D +N +G +P +D +N +G +A +Regulator +OSC +VREG +PAD +CP2 +CP1 +MS1 +MS0 +Functional Block Diagram + +![Image 1 from page 3](pdf-image://page_3_img_1) + +## Page 4 + +Automotive Programmable Stepper Driver +A3981 +4 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Pinout Diagram +Terminal List Table +Name +Number +Description +AGND +7 +Analog reference ground +CP1 +23 +Charge pump capacitor terminal +CP2 +24 +Charge pump capacitor terminal +DIAG +16 +Diagnostic output +DIR +3 +Direction select input +ENABLE +26 +Bridge enable input +MS0 +13 +Microstep select input +MS1 +12 +Microstep select input +OAM +25 +Bridge A negative output +OAP +4 +Bridge A positive output +OBM +18 +Bridge B negative output +OBP +11 +Bridge B positive output +OSC +5 +Oscillator input +PAD +– +Connect exposed tab to ground +Name +Number +Description +PGND +21 +Power Ground +REF +8 +Reference input voltage +RESETn +27 +Chip reset +SCK +9 +Serial data clock +SDI +6 +Serial data input +SDO +17 +Serial data output +SENSA +1 +Current sense node – bridge A +SENSB +14 +Current sense node – bridge B +STEP +19 +Step input +STRn +2 +Serial data strobe +VBBA +28 +Motor supply – bridge A +VBBB +15 +Motor supply – bridge B +VCP +22 +Above supply voltage +VDD +10 +Logic Supply +VREG +20 +Regulated voltage +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +I/O & Control +Timer +Reg +Ref +VDD +SENSA +STRn +DIR +OAP +AGND +REF +VDD +OBP +SENSB +VBBA +RESETn +ENABLE +OAM +VCP +PGND +VREG +STEP +OBM +DIAG +VBBB +2 +P +C +C +S +O +SDI +SCK +CP1 +MS1 +MS0 +SDO +Charge +Pump +Pinout Diagram and Terminal List Table + +![Image 1 from page 4](pdf-image://page_4_img_1) + +## Page 5 + +Automotive Programmable Stepper Driver +A3981 +5 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +ELECTRICAL CHARACTERISTICS [1][2]: Valid at TJ = –40°C to 150°C, VBB = 7 to 28 V, VDD = 3 to 5.5 V, unless otherwise noted +Characteristics +Symbol +Test Conditions +Min. +Typ. +Max. +Unit +SUPPLIES +Load Supply Voltage Range [3] +VBB +Functional +0 +– +50 +V +Outputs Driving +7 +– +VBBOV +V +Load Supply Quiescent Current +IBBQ +ENABLE = 0 +– +– +4 +mA +Sleep mode +– +1 +10 +µA +Logic Supply Voltage Range +VDD +3 +– +5.5 +V +Logic Supply Quiescent Current +IDDQ +ENABLE = 0 +– +– +5 +mA +ENABLE=0, VDD > 5 V +– +– +5.5 +mA +Sleep mode, VDD = 3.3 V +– +4 +15 +µA +Sleep mode, VDD = 5 V +– +– +25 +µA +Charge Pump Voltage +VCP +With repect to VBB, VBB >7.5 V, ENABLE = 0, +RESETn = 1 +– +6.7 +– +V +Internal Regulator Voltage +VREG +ENABLE = 0, RESETn = 1, VBB > 7.5 V +– +7.2 +– +V +Internal Regulator Dropout Voltage +VREGDO +ENABLE = 0, RESETn = 1, VBB > 5.6 V +– +100 +200 +mV +MOTOR BRIDGE OUTPUT +High-Side On-Resistance +RONH +VBB = 13.5 V, IOUT = –1 A, TJ = 25°C +– +500 +600 +mΩ +VBB = 13.5 V, IOUT = –1 A, TJ = 150°C +– +900 +1100 +mΩ +VBB = 7 V, IOUT = –1 A, TJ = 25°C +– +625 +750 +mΩ +High-Side Body Diode Forward +Voltage +VFH +IF = 1 A +– +– +1.4 +V +Low-Side On-Resistance +RONL +VBB = 13.5 V, IOUT = 1 A, TJ = 25°C +– +500 +600 +mΩ +VBB = 13.5 V, IOUT = 1 A, TJ = 150°C +– +900 +1100 +mΩ +VBB = 7 V, IOUT = 1 A, TJ = 25°C +– +625 +750 +mΩ +Low-Side Body Diode Forward +Voltage +VFL +IF = –1 A +– +– +1.4 +V +Output Leakage Current +ILO +ENABLE = 0, RESETn = 1, VO = VBB +–120 +–65 +– +µA +ENABLE = 0, RESETn = 1, VO = 0 V +–200 +–120 +– +µA +ENABLE = 0, RESETn = 0, VO = VBB +– +<1.0 +20 +µA +ENABLE = 0, RESETn = 0, VO = 0 V +–20 +<1.0 +– +µA +CURRENT CONTROL +Internal Oscillator Frequency +fOSC +OSC = AGND +3.2 +4 +4.8 +MHz +51 kΩ from OSC to VDD +3.6 +– +4.4 +MHz +External Oscillator Frequency Range +fEXT +3 +– +5 +MHz +Blank Time [4] +tBLANK +Default Blank-Time +– +1500 +– +ns +Off-Time (In Fixed Off-Time Mode) [4] +tOFF +Default Off-Time +– +44 +– +µs +PWM Frequency (In Fixed Frequency +Mode) [4] +fPWM +Default PWM Frequency +– +16.7 +– +kHz +Continued on the next page… + +![Image 1 from page 5](pdf-image://page_5_img_1) + +## Page 6 + +Automotive Programmable Stepper Driver +A3981 +6 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Continued on the next page… +ELECTRICAL CHARACTERISTICS [1][2] (continued): Valid at TJ = –40°C to 150°C, VBB = 7 to 28 V, VDD = 3 to 5.5 V, +unless otherwise noted +Characteristics +Symbol +Test Conditions +Min. +Typ. +Max. +Unit +CURRENT CONTROL (continued) +Fast Decay Time [4] +tFAST +Default Fast Decay Time +– +8 +– +µs +Reference Input Voltage +VREF +0.8 +– +2 +V +Internal Reference Voltage +VREFint +REF tied to VDD +1.1 +1.2 +1.3 +V +Reference Input Current +IREF +–3 +0 +3 +µA +Maximum Sense Voltage +VSMAX +– +125 +– +mV +Current Trip Point Error [5] +EITrip +VREF = 2 V, MXI0 = MXI1 = 1 +– +– +±5 +% +LOGIC INPUT AND OUTPUT – DC PARAMETERS +Input Low Voltage +VIL +– +– +0.3 × VDD +V +VDD > 4.5 V +– +– +0.28 × VDD +V +Input High Voltage +VIH +0.7 × VDD +– +– +V +Input Hysteresis +VIhys +250 +500 +– +mV +Input Current (Except RESETn) +IIN +0 V < VIN < VDD +–1 +– +1 +µA +Input Pull-Down Resistor (RESETn) +RPD +– +50 +– +kΩ +Output Low Voltage +VOL +IOL = 2 mA +– +0.2 +0.4 +V +Output High Voltage +VOH +IOL = –2 mA +VDD–0.4 +VDD–0.2 +– +V +Output Leakage (SDO) +IO +0 V < VO < VDD, STRn = 1 +–1 +– +1 +µA +LOGIC INPUT AND OUTPUT – DYNAMIC PARAMETERS +Reset Pulse Width +tRST +0.2 +– +4.5 +µs +Reset Shutdown Width +tRSD +10 +– +– +µs +Input Pulse Filter Time (STEP, DIR) +tPIN +– +35 +– +ns +Clock High Time +tSCKH +A in figure 1 +50 +– +– +ns +Clock Low Time +tSCKL +B in figure 1 +50 +– +– +ns +Strobe Lead Time +tSTLD +C in figure 1 +30 +– +– +ns +Strobe Lag Time +tSTLG +D in figure 1 +30 +– +– +ns +Strobe High Time +tSTRH +E in figure 1 +300 +– +– +ns +Data Out Enable Time +tSDOE +F in figure 1 +– +– +40 +ns +Data Out Disable Time +tSDOD +G in figure 1 +– +– +30 +ns +Data Out Valid Time from Clock +Falling +tSDOV +H in figure 1 +– +– +40 +ns +Data Out Hold Time from Clock +Falling +tSDOH +I in figure 1 +5 +– +– +ns +Data In Set-Up Time to Clock Rising +tSDIS +J in figure 1 +15 +– +– +ns +Data In Hold Time From Clock Rising +tSDIH +K in figure 1 +10 +– +– +ns +STEP Rising to STRn Rising +Setup Time +tSPS +L in figure 1, only when D15 = 1 and D14 = 0 +100 +– +– +ns +STEP Rising from STRn Rising +Hold Time +tSPH +M in figure 1, only when D15 = 1 and D14 = 0 +300 +– +– +ns + +![Image 1 from page 6](pdf-image://page_6_img_1) + +## Page 7 + +Automotive Programmable Stepper Driver +A3981 +7 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Characteristics +Symbol +Test Conditions +Min. +Typ. +Max. +Unit +LOGIC INPUT AND OUTPUT – DYNAMIC PARAMETERS (continued) +Step Low Time +tSTPH +1 +– +– +µs +Setup Time Control Input Change +to STEP +tSU +MS1, MS2, DIR +200 +– +– +ns +Hold Time Control Input Change +from STEP +tH +MS1, MS2, DIR +200 +– +– +ns +Wake-Up from RESET +tEN +– +– +1 +ms +DIAGNOSTICS AND PROTECTION +VBB Overvoltage Threshold +VBBOV +VBB rising +32 +34 +36 +V +VBB Overvoltage Hysteresis +VBBOVHys +2 +– +4 +V +VREG Undervoltage Threshold +VREGUV +VREG falling +5.1 +– +5.4 +V +VREG Undervoltage Hysteresis +VRGUVHys +– +1 +– +V +VDD Undervoltage Threshold +VDDUV +VDD falling +2.6 +– +2.9 +V +VDD Undervoltage Hysteresis +VDDUVHys +50 +100 +– +mV +VDD Power-On Reset Threshold6 +VDDPOR +VDD falling +0.8 +– +1.5 +V +OSC Timeout +tWD +Bit 13 = 1 +0.5 +1 +1.5 +µs +High-Side Overcurrent Threshold +IOCH +Sampled after tSCT +1.4 +2.05 +2.65 +A +High-Side Current Limit +ILIMH +Active during tSCT +3 +5.5 +8 +A +Low-Side Overcurrent Sense Voltage +VOCL +Sampled after tSCT +210 +250 +290 +mV +Overcurrent Fault Delay +tSCT +Default Fault Delay +1500 +2000 +2700 +ns +Open Load Current Threshold Error +EIOC +VREF = 2 V, MXI0 = MXI1 = 1 +– +– +±10 +% +Temperature Voltage Output Offset +VTO +Temperature output selected on DIAG pin +– +1440 +– +mV +Temperature Voltage Output Slope +AT +– +–3.92 +– +mV/°C +Cold Temperature Warning Threshold +TJWC +Temperature decreasing +–20 +–10 +0 +°C +Cold Temperature Warning Hysteresis +TJWChys +– +15 +– +°C +Hot Temperature Warning Threshold +TJWH +Temperature increasing +125 +135 +145 +°C +Hot Temperature Warning Hysteresis +TJWHhys +– +15 +– +°C +Overtemperature Shutdown Threshold +TJF +Temperature increasing +155 +170 +– +°C +Overtemperature Hysteresis +TJhys +Recovery = TJF – TJhys +– +15 +– +°C +[1] For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin. +[2] All references to “VBB” apply to VBBA and VBBB. +[3] Function is correct but parameters are not guaranteed above or below the general limits (7 to 28 V). Outputs not operational above VBBOV or below VREGUV . +[4] Assumes a 4 MHz clock. +[5] Current Trip Point Error is the difference between actual current trip point and the target current trip point, referred to maximum full scale (100%) current: EItrip = 100 × +[ItripActual – ItripTarget ] / IFullScale (%). +[6] Ensured by design and characterization. +ELECTRICAL CHARACTERISTICS [1][2] (continued): Valid at TJ = –40°C to 150°C, VBB = 7 to 28 V, VDD = 3 to 5.5 V, +unless otherwise noted + +![Image 1 from page 7](pdf-image://page_7_img_1) + +## Page 8 + +Automotive Programmable Stepper Driver +A3981 +8 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Figure 1: Serial Interface Timing Diagram +Figure 2: Control Input Interface Timing Diagram +C +A +B +D +E +J +K +F +I +G +0 +D +4 +1 +D +5 +1 +D +'0 +D +'4 +1 +D +'5 +1 +D +STRn +SCK +SDI +SDO +H +Z +STEP +L +M +No rise when +D15=1 and D14=0 +Z +X +X +X +X +Key +Characteristic +Key +Characteristic +A +Clock High Time +H +Data Out Valid Time from Clock Falling +B +Clock Low Time +I +Data Out Hold Time from Clock Falling +C +Strobe Lead Time +J +Data In Set-Up Time to Clock Rising +D +Strobe Lag Time +K +Data In Hold Time From Clock Rising +E +Strobe High Time +L +STEP Rising to STRn Rising Setup Time +F +Data Out Enable Time +M +STEP Rising from STRn Rising Hold Time +G +Data Out Disable Time +X +“Don’t care” +Z +High-impedance (tristate) +STEP +DIR, MS0, MS1 +tSTPL +tSTPH +tH +tSU +RESETn +tEN +ENABLE\* +* ENABLE(Pin) OR RUN[EN] bit + +![Image 1 from page 8](pdf-image://page_8_img_1) + +## Page 9 + +Automotive Programmable Stepper Driver +A3981 +9 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +FUNCTIONAL DESCRIPTION +The A3981 is an automotive stepper motor driver suitable for +high-temperature applications such as headlamp bending and +leveling, throttle control, and gas recirculation control. It is also +suitable for other low-current stepper applications such as air +conditioning and venting. It provides a highly flexible microstep­ +ping motor driver that can be configured via the SPI-compatible +serial interface. It can be controlled with simple Step and Direc­ +tion inputs, for high-speed stepping applications, or directly +through the serial interface by writing a step change value. +The two DMOS full bridges are capable of driving bipolar step­ +per motors in full-, half-, quarter-, eighth- and sixteenth-step +modes, at up to 28 V and ±1.4 A. The current in each phase of the +stepper motor is regulated by a peak detect PWM current control +scheme that can be programmed to operate in fixed off-time or +fixed frequency. Several decay modes can be selected to reduce +audible motor noise and increase step accuracy. In addition the +phase current tables, which default to a sinusoidal current profile, +can be programmed via the serial interface to create unique mic­ +rostep current profiles to further improve motor performance for +specific applications. +The outputs are protected from short circuits, and features for +open load and stalled rotor detection are included. Chip level pro­ +tection includes hot and cold thermal warning, overtemperature +shutdown, and overvoltage and undervoltage lockout. +Pin Functions +VBBA, VBBB. Main motor supply and chip supply for internal +regulators and charge pump. VBBA and VBBB should be con­ +nected together and each decoupled to ground with a low ESR +electrolytic capacitor and a good ceramic capacitor. +Note: Any reference to “VBB” in this specification is defined as +applying to both VBBA and VBBB. +CP1, CP2. Pump capacitor connection for charge pump. Con­ +nect a 100 nF (50 V) ceramic capacitor between CP1 and CP2. +VCP. Above-supply voltage for high-side drive. A 100 nF (16 V) +ceramic capacitor should be connected between VCP and VBB to +provide the pump storage reservoir. +VDD. Logic supply. Compatible with 3.3 V and 5 V logic. Should +be decoupled to ground with a 100 nF (10 V) ceramic capacitor. +VREG. Regulated supply for bridge gate drive. Should be +decoupled to ground with a 220 nF (10 V) ceramic capacitor. +AGND. Analog reference ground. Quiet return for measurement +and input references. Connect to PGND (see Layout section). +PGND. Digital and power ground. Connect to supply ground and +AGND (see Layout section). +OAP, OAM. Motor connection for phase A. Positive motor phase +current direction is defined as flowing from OAM to OAP. +OBP, OBM. Motor connection for phase B. Positive motor phase +current direction is defined as flowing from OBM to OBP. +SENSA. Phase A current sense. Connect sense resistor between +SENSA and PGND. +SENSB. Phase B current sense. Connect sense resistor between +SENSB and PGND. +REF. Reference input to set absolute maximum current level for +both phases. Defaults to internal reference when tied to VDD. +STEP. Step logic input. Motor advances on rising edge. Filtered +input with hysteresis. +DIR. Direction logic input. Direction changes on the next STEP +rising edge. When high, the Phase Angle Number is increased +on the rising edge of STEP. Has no effect when using the serial +interface. Filtered input with hysteresis. +MS0. Microstep resolution select input. +MS1. Microstep resolution select input. +RESETn. Resets faults when pulsed low. Forces low-power +shutdown (sleep) when held low for more than the Reset Shut­ +down Width, tRSD . Can be pulled to VBB with 30 kΩ resistor. +ENABLE. Controls activity of bridge outputs. When held low, +deactivates the outputs, that is, turns off all output bridge FETs. +Internal logic continues to follow input commands. +SDI. Serial data input. 16-bit serial word input MSB first. +SDO. Serial data output. High impedance when STRn is high. +Outputs bit 15 of the diagnostic registers (Fault Register 0 and Fault +Register 1), the Fault Register flag, as soon as STRn goes low. +SCK. Serial interface clock. Data is latched in from SDI on the +rising edge of the SCK clock signal. There must be 16 rising +edges per write and SCK must be held high when STRn changes. +STRn. Serial data strobe and serial access enable. When STRn +is high any activity on SCK or SDI is ignored, and SDO is high +impedance allowing multiple SDI slaves to have common SDI, +SCK, and SDO connections. + +![Image 1 from page 9](pdf-image://page_9_img_1) + +## Page 10 + +Automotive Programmable Stepper Driver +A3981 +10 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +DIAG. Diagnostic output. Function selected via the serial inter­ +face, setting Configuration Register 1. Default is Fault output. +OSC. With bit 13 in Configuration Register 1 set to 0, either con­ +nect this pin to AGND to use the internal oscillator running at the +default frequency of 4 MHz, or connect a resistor to VDD to set +the internal oscillator frequency. ( The approximate frequency is +calculated from: +fOSC = 10 000 / (48 ROSC – 20) +where fOSC is the internal oscillator frequency in MHz, and ROSC +is the value, in kΩ of the resistor between OSC and VDD.) +If bit 13 in Configuration Register 1 is set to 1, then OSC is the +input for an external system clock, which must have a frequency +between 3 and 5 MHz. In this mode a watchdog is provided to +detect loss of the system clock. If the OSC pin remains high or +low for more than the watchdog time, tWD , 1 µs typical, then the +Fault Register flag (bit 15 in the diagnostic registers) is set and +the outputs are disabled until the clock restarts. +Driving a Stepper Motor +A two-phase stepper motor is made to rotate by sequencing +the relative currents in each phase. In its simplest form, each +phase is simply fully energized in turn by applying a voltage to +the winding. For more precise control of the motor torque over +temperature and voltage ranges, current control is required. For +efficiency this is usually accomplished using pulse width modula­ +tion (PWM) techniques. In addition current control also allows +the relative current in each phase to be controlled, providing more +precise control over the motor movement and hence improve­ +ments in torque ripple and mechanical noise. Further details of +stepper motor control are provided in Appendix A. +For bipolar stepper motors the current direction is significant, +so the voltage applied to each phase must be reversible. This +requires the use of a full bridge (also known as an H-bridge) +which can switch each phase connection to supply or to ground. +PHASE CURRENT CONTROL +In the A3981, current to each phase of the two-phase bipolar +stepper motor is controlled through a low impedance N-channel +DMOS full bridge. This allows efficient and precise control of +the phase current using PWM switching. The full-bridge con­ +figuration provides full control over the current direction during +the PWM on-time, and over the current decay mode during the +PWM off-time. Due to the flexibility of the A3981 these control +techniques can be completely transparent to the user or can be +partially- or fully-programmed through the serial interface. +Each leg (high-side, low-side pair) of a bridge is protected from +shoot-through by a fixed dead time. This is the time between +switching off one FET and switching on the complementary FET. +Cross-conduction is prevented by lock-out logic in each driver pair. +The phase currents and in particular the relative phase currents +are defined in the Phase Current table (table 7). This table defines +the two phase currents at each microstep position. For each of the +two phases, the currents are measured using a sense resistor, RS, +with voltage feedback to the respective SENSx pin. The target +current level is defined by the voltage from the digital-to-analog +converter (DAC) for that phase. The sense voltage is amplified by +a fixed gain and compared to the output of the DAC. +There are two types of maximum current: the absolute maximum, +ISMAX , the maximum possible current defined by the sense resis­ +tor and the reference input; and the phase maximum, IPMAX , the +maximum current delivered to a motor phase. +The absolute maximum current, ISMAX, is defined as: +ISMAX = VREF / (16 × RS ) +where VREF is the voltage at the REF pin, and RS is the sense +resistor value. +The phase maximum, IPMAX , is the 100% reference level for the +phase current table and may be a fraction of the absolute maxi­ +mum current, ISMAX , depending on the value of the MXI0 and +MXI1 bits in Configuration Register 0. +For example: +• if RS = 180 mΩ and VREF = 2 V, then ISMAX = 694 mA +• if MXI1= 1 and MXI0 = 0, then IPMAX = 520 mA +The actual current delivered to each phase at each Step Angle +Number is determined by the value of IPMAX and the contents +of the Phase Current table. For each phase, the value in the table +is passed to the DAC, which uses IPMAX as the reference 100% +level (code 63) and reduces the current target depending on the +DAC code. The output from the DAC is used as the input to the +current comparators. +The current comparison is ignored at the start of the PWM +on‑time for a duration referred to as the blank time. The blank +time is necessary to prevent any capacitive switching currents +from causing a peak current detection. + +![Image 1 from page 10](pdf-image://page_10_img_1) + +## Page 11 + +Automotive Programmable Stepper Driver +A3981 +11 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +The PWM on-time starts at the beginning of each PWM period. +The current rises in the phase winding until the sense voltage +reaches the required current level. At this point the PWM off-time +starts and the bridge is switched into one of two decay modes, +slow decay or fast decay: +• Slow decay is most effective when the current is rising +from step to step, and it occurs when the phase winding is +effectively shorted by switching-on either both high-side FETs +or both low-side FETs in the full bridge. +• Fast decay is most effective when the current is falling from +step to step, and it occurs when the voltage on the phase is +reversed. +One disadvantage of fast decay is the increased current ripple in +the phase winding. However, this can be reduced while main­ +taining good current control, by using a short time of fast decay +followed by slow decay for the remainder of the PWM off-time. +This technique is commonly referred to as mixed decay. +The A3981 provides two methods to determine the PWM +frequency: fixed off-time and fixed frequency. At power-up the +default mode is fixed off-time. Fixed frequency can be selected +through the serial interface. Fixed off-time provides a marginal +improvement in current accuracy over a wide range of current +levels. Fixed frequency provides a fixed fundamental frequency +to allow more precise supply filtering for EMC reduction. In both +cases the PWM off-time will not be present if the peak current +limit is not attained during the PWM on-time. +PHASE CURRENT TABLE +The relative phase currents are defined by the Phase Current table +(Table 7). This table contains 64 lines and is addressed by the +Step Angle Number, where Step Angle Number 0 corresponds to +0° or 360°. The Step Angle Number is generated internally by the +step sequencer, which is controlled either by the STEP and DIR +inputs or by the step change value from the serial input. The Step +Angle Number determines the motor position within the 360° +electrical cycle and a sequence of Step Angle Numbers deter­ +mines the motor movement. Note that there are four full mechani­ +cal steps per 360° electrical cycle. +Each line of the Phase Current table (Table 7) has a 6-bit value +per phase to set the DAC level for that phase, plus an additional +bit per phase to determine the current direction for that phase. +The Step Angle Number sets the electrical angle of the stepper +motor in one-sixteenth microsteps, approximately equivalent to +electrical steps of 5.625°. +On first power-up or after a VDD power-on reset, the Phase Cur­ +rent table values are reset to define a sinusoidal current profile +and the Step Angle Number is set to 8, equivalent to the electri­ +cal cycle 45° position. This position is defined as the “home” +position. The maximum current in each phase, IPMAX , is defined +by the sense resistor and the Maximum Current setting (bits +MXI[0..1]) in Configuration Register 0. The phase currents for +each entry in the Phase Current table are expressed as a percent­ +age of this maximum phase current. +When using the STEP and DIR inputs to control the stepper +motor, the A3981 automatically increases or decreases the Step +Angle Number according to the step sequence associated with +the selected step mode. The default step mode, reset at power- +up or after a power on reset, is full step. Half-, quarter-, and +sixteenth‑step sequences are also available when using the STEP +and DIR inputs, and are selected using the logical OR of the MS0 +and MS1 inputs and the MS0 and MS1 bits in Configuration Reg­ +ister 0. The eighth-step sequence is shown in the Phase Current +table for reference only. +When using the serial interface to control the stepper motor, a +step change value (6-bit) is input through the serial interface to +increase or decrease the Step Angle Number. The step change +value is a two’s complement (2’sC) number, where a positive +value increases the step angle and a negative value decreases +the step angle. A single step change in the Step Angle Number is +equivalent to a single one-sixteenth microstep. Therefore, for cor­ +rect motor movement, the step change value should be restricted +to no greater than 16 steps, positive or negative. +This facility enables full control of the stepper motor at any +microstep resolution up to and including sixteenth‑step, plus +the ability to change microstep resolution “on-the-fly” from one +microstep to the next. +In both control input method cases, the resulting Step Angle +Number is used to determine the phase current value and current +direction for each phase, based on the Phase Current table. The +decay mode is determined by the position in the Phase Current +table and the intended direction of rotation of the motor. +Diagnostics +The A3981 integrates a number of diagnostic features to protect +the driver and load as far as possible from fault conditions and +extreme operating environments. At the system level the supply + +![Image 1 from page 11](pdf-image://page_11_img_1) + +## Page 12 + +Automotive Programmable Stepper Driver +A3981 +12 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +voltages and the chip temperature are monitored. A number of +these features automatically disable the current drive to protect +the outputs and the load. Others only provide an indication of +the likely fault status, as shown in the Fault table (Table 1). A +single diagnostic output pin (DIAG) can be programmed through +the serial interface to provide several different internal signals. +At power-up, or after a power-on-reset the DIAG pin outputs a +simple Fault Output flag which will be low if a fault is present. +The Fault Output flag remains low while the fault is present or if +one of the latched faults (for example, a bridge short circuit) has +been detected and the outputs disabled. +Alternative to the Fault Output flag, the DIAG output can be pro­ +grammed via the serial interface to output: the stall detect signal, +which goes low when a stall is detected; the phase A PWM-on +signal, which is high during the phase A PWM on-time; or an +analog signal indicating the silicon temperature. +If required, specific fault information can be determined by read­ +ing the diagnostic registers (see Serial Interface section). +The first bit (bit 15) in both diagnostic registers contains a com­ +mon Fault Register flag which will be high if any of the fault bits +in either register has been set. This allows a fault condition to be +detected using the serial interface, by simply taking STRn low. +As soon as STRn goes low the fist bit in the diagnostic registers +can be read to determine if a fault has been detected at any time +since the last diagnostic registers reset. In all cases the fault bits +in the diagnostic registers are latched and only cleared after a +diagnostic registers reset. +Note that the Fault Register flag in the diagnostic registers, does +not provide the same function as the Fault Output flag on the +DIAG pin. The Fault Output flag on the DIAG pin provides an +indication that either a fault is present or the outputs have been +disabled due to a short circuit fault. The Fault Register flag sim­ +ply provides an indication that a fault has occurred since the last +diagnostic registers reset and has been latched. +At the system level the supply voltages and chip temperature are +monitored. +SUPPLY VOLTAGE MONITORS +The logic supply, the motor supply, and the regulator output are +monitored: the motor supply for overvoltage, and the regulator +output and logic supply for undervoltage. +• If the motor supply voltage, VBBA and VBBB , goes above +the VBB overvoltage threshold, the A3981 will disable the +outputs and indicate the fault. When the motor supply voltage +goes below the VBB overvoltage threshold, the outputs will +be re-enabled and the fault flag removed. The fault bits in the +diagnostic registers remain set until cleared by a diagnostic +registers reset. +• If the output of the internal regulator, VREG , goes below the +VREG undervoltage threshold, the A3981 will disable the +outputs and indicate the fault. When the regulator output rises +above the VREG undervoltage threshold, the outputs will be +re-enabled and the fault flag removed. The fault bits in the +diagnostic registers remain set until cleared by a diagnostic +registers reset. +• If the logic supply voltage, VDD , goes below the VDD +undervoltage threshold, then the outputs will be immediately +disabled. When the logic supply rises above the VDD +undervoltage threshold, the outputs will be enabled. +• If the logic supply voltage, VDD , goes below the VDD +power–on reset threshold, a power-on reset will take place and +all registers will be reset to their default state. The fault bits in +the diagnostic registers remain set until cleared by a diagnostic +registers reset. +TEMPERATURE MONITORS +Three specific temperature thresholds are provided: a hot +warning, a cold warning, and an overtemperature shutdown. In +addition, the analog internal signal used to determine the chip +temperature can be selected in Configuration Register 1 as the +Table 1: Fault Table +Diagnostic +Action +Latched +VBB Overvoltage +Disable outputs, set Fault +Register flag +No +VREG Undervoltage +Disable outputs, set Fault +Register flag +No +VDD Undervoltage +Disable outputs +No +Temperature Warning +Set Fault Register flag +No +Overtemperature +Disable outputs, set Fault +Register flag +No +Bridge Short +Disable outputs, set Fault +Register flag +Yes +Bridge Open +Set Fault Register flag +No +Stall Detect +Set ST flag +No + +![Image 1 from page 12](pdf-image://page_12_img_1) + +## Page 13 + +Automotive Programmable Stepper Driver +A3981 +13 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +output on the DIAG pin through the serial interface. The analog +scale is TJ ≈ (VDIAG – VTO ) / AT  . +Hot Warning If the chip temperature rises above the Hot Tem­ +perature Warning Threshold, TJWH , the Fault flag will go low and +the Hot Warning bits will be set in the diagnostic registers. No +action will be taken by the A3981. When the temperature drops +below the Hot Temperature Warning Threshold, the Fault flag +will go high but the Hot Warning bits remain set in the diagnostic +registers until reset. +Cold Warning If the chip temperature falls below the Cold +Temperature Warning Threshold, TJWC , the Fault flag will go low +and the Cold Warning bits will be set in the diagnostic registers. +No action will be taken by the A3981. When the temperature rises +above the Cold Temperature Warning Threshold, the Fault flag +will go high but the Cold Warning bits remain set in the diagnos­ +tic registers until reset. +Overtemperature Shutdown If the chip temperature rises +above the Overtemperature Shutdown Threshold, TJF , the Fault +flag will go low and the Thermal Shutdown bits will be set in the +diagnostic registers. The A3981 will disable the outputs to try to +prevent a further increase in the chip temperature. When the tem­ +perature drops below the Overtemperature Shutdown Threshold, +the Fault flag will go high but the Thermal Shutdown bits remain +set in the diagnostic registers until reset. +BRIDGE AND OUTPUT DIAGNOSTICS +The A3981 includes monitors that can detect a short to supply or +a short to ground at the motor phase connections. These condi­ +tions are detected by monitoring the current from the motor +phase connections through the bridge to the motor supply and to +ground. +Low current comparators and timers are provided to help detect +possible open load conditions. +Short to Supply A short from any of the motor connections to +the motor supply (VBBA or VBBB) is detected by monitoring the +voltage across the low-side current sense resistor in each bridge. +This gives a direct measurement of the current through the low +side of the bridge. +When a low-side FET is in the On state, the voltage across the +sense resistor, under normal operating conditions, should never +be more than the Maximum Sense Voltage, VSMAX. In this state, +an overcurrent is determined to exist when the voltage across the +sense resistor exceeds the Low-Side Overcurrent Sense Voltage, +VOCL , typically 2 × VSMAX . This overcurrent must be continu­ +ously present for at least the Overcurrent Fault Delay, tSCT , +before the short fault is confirmed by setting the relevant bit in +FAULT0 and driving the DIAG output low if the Fault Output +flag is selected. The output is switched off and remains off until a +fault reset occurs. +Note that the sense resistor cannot distinguish which low-side +FET is in an overcurrent state. So, if more than one low-side FET +is active when the fault is detected, for example during low-side +recirculation with synchronous rectification, then the shorted con­ +nection is determined from the internal PWM state. +The actual overcurrent that VOCL represents is determined by the +value of the sense resistor and is typically 2 × ISMAX . +Short to Ground A short from any of the motor connections +to ground is detected by directly monitoring the current through +each of the high-side FETs in each bridge. +When a high-side FET is in the On state the maximum current +is typically always less than 1 A. In this state, an overcurrent is +determined to exist when the current through the active high-side +FET exceeds the High-Side Overcurrent Threshold, IOCH . +This overcurrent must be present for at least the Overcurrent +Fault Delay, tSCT , before the short fault is confirmed by setting +the relevant bit in FAULT0 and driving the DIAG output low if +the Fault Output flag is selected. The output is switched off and +remains off until a fault reset occurs. +Note that when a short to ground is present the current through +the high-side FET is limited to the High-Side Current Limit, +ILIMH , during the Overcurrent Fault Delay, tSCT  . This prevents +large negative transients at the phase output pins when the out­ +puts are switched off. +Shorted Load A short across the load is indicated by concurrent +short faults on both high side and low side. +Short Fault Blanking All overcurrent conditions are ignored +for the duration of the Overcurrent Fault Delay, tSCT . The short +detection delay timer is started when an overcurrent first occurs. +If the overcurrent is still present at the end of the short detection +delay time then a short fault will be generated and latched. If the +overcurrent goes away before the short detection delay time is +complete, then the timer is reset and no fault is generated. +This prevents false short detection caused by supply and load + +![Image 1 from page 13](pdf-image://page_13_img_1) + +## Page 14 + +Automotive Programmable Stepper Driver +A3981 +14 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Figure 3. Effect of stall condition on current rise +transients. It also prevents false short detections resulting from +current transients generated by the motor or wiring capacitance +when a FET is first switched on. +Short Fault Reset and Retry When a short circuit has been +detected all outputs for the faulty phase are disabled until the +next occurrence of: the next rising edge on the STEP input, the +RESETn input is pulsed low, or until the diagnostic registers +are reset by writing to one of the registers through the serial +interface. At the next STEP command or after a fault reset, the +Fault Register flag is cleared, the outputs are re-enabled, and the +voltage across the FET is resampled. Note that the diagnostic +registers are not cleared by the rising edge of the STEP input. +While the fault persists the A3981 will continue this cycle, +enabling the outputs for a short period then disabling the out­ +puts. This allows the A3981 to handle a continuous short circuit +without damage. If, while stepping rapidly, a short circuit appears +and no action is taken, the repeated short circuit current pulses +will eventually cause the temperature of the A3981 to rise and an +overtemperature fault will occur. +Open Load Detection Open load conditions are detected +by monitoring the phase current when the phase DAC value +is greater than 31. The Open Load Current Threshold, IOL , is +defined by the OL0 and OL1 bits in the Run register as a percent­ +age of the maximum (100%) phase current, IPMAX , defined in the +Phase Current table. The 100% level in the Phase Current table is +defined by the sense resistor value and the contents of the MXI0 +and MXI1 bits in Configuration Register 0. +For example: +• if RS = 180 mΩ and VREF = 2 V, then ISMAX = 694 mA +• if MXI1 = 1 and MXI0 = 0, then IPMAX = 520 mA +• if OL1=0 and OL0=1, then IOL = 156 mA +The open load current monitor is only active after a blank +time from the start of a PWM cycle. An open load can only be +detected if the DAC value for the phase is greater than 31 and the +current has not exceeded the Open Load Current Threshold for +more than 15 PWM cycles. +The A3981 continues to drive the bridge outputs under an open +load condition and clears the Fault Register flag as soon as the +phase current exceeds the Open Load Current Threshold or the +DAC value is less than 32. The diagnostic registers retain the +open load fault bits, OLA and OLB, and will not be cleared until +RESETn is pulsed low or one of the diagnostic registers is written +through the serial interface. +Stall Detection For all motors it is possible to determine the +mechanical state of the motor by monitoring the back-EMF +(BEMF) generated in the motor phase windings. A stalled motor +condition is when the phase currents are being sequenced to step +the motor but the motor remains stationary. This can be due to +a mechanical blockage such as an end stop or the step sequence +exceeding the motor capability for the attached load. +A PWM monitor feature is included in the A3981 to assist in +detecting the stall condition of the stepper motor. This feature +uses the effect of the BEMF on the current rise time by compar­ +ing the PWM count during the current rise quadrant to determine +the point at which a stall occurs. Reliable stall detection in a +simple stepper driver is only possible by combining the PWM +monitor with a continuous step sequence at a sufficiently high +step rate. +When a motor is running normally, at speed, the BEMF, gen­ +erated by the magnetic poles in the motor passing the phase +windings, acts against the supply voltage and reduces the rise +rate of the phase current, as shown in Figure 3. The PWM current +control does not activate until the current reaches the set trip level +for the microstep position. When a motor is stopped, as in a stall +Effect of stall +condition +Normal running +condition +Increased number of +PWM cycles at each +microstep + +![Image 1 from page 14](pdf-image://page_14_img_1) + +![Image 2 from page 14](pdf-image://page_14_img_2) + +## Page 15 + +Automotive Programmable Stepper Driver +A3981 +15 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +condition, the BEMF is reduced. This allows the current to rise to +the limit faster and the PWM current control to activate sooner. +Assuming a constant step rate and motor load this results in an +increase in the number of PWM cycles for each step of the motor. +The A3981 uses this difference to detect a motor changing from +continuous stepping to a stalled condition. +The PWM monitor feature assumes the following factors: +• The motor must be stepping fast enough for the BEMF to +reduce the phase current slew rate. Stall detection reliability +improves as the current slew rate reduces. +• The motor is not being stepped in full step mode. +Although stall detection cannot be guaranteed when using the +integrated features of the A3981, good stall detection reliability +can be achieved by careful selection of motor winding resistance +and inductance, motor speed, count difference, stall detection +scheme, and by conforming to the above requirements. +The A3981 includes circuits to allow the PWM monitor to oper­ +ate in two ways: compare opposite phases and compare each +phase. +Stall Detection Scheme: Compare Opposite Phases +The default stall detection scheme in the A3981, selected when +STS[1..0] = 00, is the compare opposite phases scheme. +When this scheme is selected, two PWM counters, one for each +phase, accumulate the number of PWM cycles when the phase +current is stepped from zero to full-scale current. At the end of +each phase current rise, the counter for that phase is compared +to the count result for the previous current rise in the opposite +phase, as shown in Figure 4. If the difference is greater than the +PWM count difference in the CONFIG1 register (CD[7:0]), then +the ST bit in the diagnostic registers is set. In addition, if the ST +signal is selected as the output on the DIAG pin, then the pin will +go low. +Figure 4: Stall Detect by PWM Count Comparing Opposite Phases, STS[1..0] = 00 + +![Image 1 from page 15](pdf-image://page_15_img_1) + +![Image 2 from page 15](pdf-image://page_15_img_2) + +## Page 16 + +Automotive Programmable Stepper Driver +A3981 +16 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Stall Detection Scheme: Compare Each Phase +In some motors the winding differences can cause false stall +detection. This can be overcome by changing the comparison cir­ +cuits to operate on each phase independently. The compare each +phase scheme is selected when STS[1..0] = 01. +When this scheme is selected, two PWM counters, one for each +phase, accumulate the number of PWM cycles when the phase +current is stepped from zero to full-scale current. At the end of +each phase current rise, the counter for that phase is compared to +the count result for the previous current rise in the same phase, +as shown in Figure 5. If the difference is greater than the PWM +count difference in the CONFIG1 register (CD[7:0]), then the ST +bit in the diagnostic registers is set. In addition, if the ST signal is +selected as the output on the DIAG pin, then the pin will go low. +In addition to using the integrated features of the A3981, it is +also possible to perform stall detection by examining the PWM +on-time for a single phase using an external microcontroller. In +the A3981 the PWM-on signal for phase A can be selected as the +output on the DIAG pin by using the serial interface. +Figure 5: Stall Detect by PWM Count Comparing Each Phase Independently, STS[1..0] = 01 + +![Image 1 from page 16](pdf-image://page_16_img_1) + +![Image 2 from page 16](pdf-image://page_16_img_2) + +## Page 17 + +Automotive Programmable Stepper Driver +A3981 +17 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +SERIAL INTERFACE DESCRIPTION +A three wire synchronous serial interface, compatible with +SPI, can be used to configure and control all the features of the +A3981. A fourth wire can be used to provide diagnostic feedback. +The registers that are accessible through the serial interface are +defined in Table 2. +The A3981 can be operated without using the serial interface, +by using the default configuration and control register settings +and the STEP and DIR logic inputs for motor control. However, +application-specific configurations are only possible by setting +the appropriate register bits through the serial interface. In addi­ +tion to setting the configuration bits, the serial interface can also +be used to control the motor directly. +The serial interface timing requirements are specified in the Elec­ +trical Characteristics table, and illustrated in Figure 1. +Writing to Configuration and Control Regis­ +ters +When writing to the serial register, data is received on the SDI +pin and clocked through a shift register on the rising edge of the +clock signal input on the SCK pin. STRn is normally held high, +and is only brought low to initiate a serial transfer. No data is +clocked through the shift register when STRn is high, thus allow­ +ing multiple SDI slave units to use common SDI, SCK, and SDO +connections. Each independent slave requires a dedicated STRn +connection. +The serial data word has 16 bits, MSB input first. After 16 data +bits have been clocked into the shift register, STRn must be taken +high to latch the data into the selected register. When this occurs, +the internal control circuits act on the new configuration and +control data, and the diagnostic registers are reset. +Table 2. Serial Register Definition\* +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Configuration and Control Registers (Write) +Configuration +Register 0 +(CONFIG0) +0 +0 +SYR +MS1 +MS0 +MXI1 +MXI0 +PFD2 +PFD1 +PFD0 +TBK1 +TBK0 +TOF2 +TOF1 +TOF0 +PWM +FRQ2 +FRQ1 +FRQ0 +1 +0 +0 +1 +1 +1 +0 +0 +0 +1 +1 +1 +0 +0 +Configuration +Register 1 +(CONFIG1) +0 +1 +OSC +TSC1 +TSC0 +CD7 +CD6 +CD5 +CD4 +CD3 +CD2 +CD1 +CD0 +DIAG1 +DIAG0 +0 +1 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +0 +Run Register +(RUN) +1 +0 +EN +OL1 +OL0 +HLR +SLEW +BRK +DCY1 +DCY0 +SC5 +SC4 +SC3 +SC2 +SC1 +SC0 +0 +0 +1 +0 +1 +0 +0 +1 +0 +0 +0 +0 +0 +0 +Table Load +Register +(TBLLD) +1 +1 +STS1 +STS1 +PTP +PT5 +PT4 +PT3 +PT2 +PT1 +PT0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +1 +0 +1 +Diagnostic Registers (Read) +Fault Register +0 (FAULT0) +FF +TW1 +TW0 +OV +UV +ST +OLB +OLA +BML +BMH +BPL +BPH +AML +AMH +APL +APH +Fault +Register 1 +(FAULT1) +FF +TW1 +TW0 +OV +UV +ST +OLB +OLA +0 +0 +SA5 +SA4 +SA3 +SA2 +SA1 +SA0 +\*Power-on reset value shown below each input register bit. + +![Image 1 from page 17](pdf-image://page_17_img_1) + +## Page 18 + +Automotive Programmable Stepper Driver +A3981 +18 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +If there are more than 16 rising edges on SCK, or if STRn goes +high and there are fewer than 16 rising edges on SCK, the write +will be cancelled without writing data to the configuration and +control registers. In addition the diagnostic registers will not be +reset. Instead the FF bit will be set to 1 in the diagnostic registers, +to indicate a data transfer error. +The first two bits of the serial word are used to select the register +to be written. This provides access to four writable registers: +• The Configuration registers are used for system configuration: +CONFIG0 for system parameters, and CONFIG1 for system +and diagnostic parameters. +• The RUN register contains motor drive settings used to control +the motor movement and phase current. +• The fourth writable register, TBLLD, is used for diagnostic +configuration and to program the phase current table. +Reading from Diagnostic Registers +In addition to the writable registers there are two diagnostic +registers. The first eight (most significant) bits of both diagnostic +registers contain the same flags, only the last eight (least signifi­ +cant) bits differ, as follows: +• FAULT0 contains the short-circuit fault flags +• FAULT1 contains the present Step Angle Number +Each time a configuration and control register is written, one +of the diagnostic registers can be read, MSB first, on the serial +output pin, SDO (see timing in Figure 1). FAULT1 is made the +active register for serial transfer and output on SDO only while +CONFIG1 is being written, that is, only when the first bit of the +input word is 0 and the second bit is 1. FAULT0 is the active +register for serial transfer and output on SDO during writes to any +other configuration or control register. +When STRn goes low to start a serial write, SDO comes out of its +high impedance state and outputs the serial register Fault Register +flag. This allows the main controller to poll the A3981 through +the serial interface to determine if a fault has been detected. If no +faults have been detected then the serial transfer may be termi­ +nated without generating a serial read fault by ensuring that SCK +remains high while STRn is low. When STRn goes high the trans­ +fer will be terminated and SDO will go into its high impedance +state. Configuration and Run Registers +These registers are used for system configuration and motor con­ +trol. Access is described in the section Writing to Configuration +and Control Registers, above. +CONFIG0 sets certain system parameters, and CONFIG1 sets +system and diagnostic output selection parameters. The RUN +register contains motor drive settings used to control the motor +movement and phase current. +Phase Table Load Register +This is one of the configuration and control registers, accessed +when both address bits are 1, and can be used to write a sequence +of values to the phase current table in the A3981. This allows the +current at each Step Angle Number to be tailored to suit the mic­ +rostep current profile requirements of a specific motor. In most +cases this feature will not be required and the default sinusoidal +profile will suffice. However for some motor / load combinations, +altering the current profile can improve torque ripple, resulting in +lower mechanical vibration and noise. +Although the phase current table contains 64 entries for each of +two phases, only 16 distinct values are required. These 16 values +correspond to one quadrant of the table for a single phase, and +they are repeated for the other three quadrants and again for the +four quadrants of the other phase. So each of the 16 values writ­ +ten to the Phase Table Load register are written to 8 locations in +the phase current table. +The 16 values must be entered by sequential writes to the Phase +Table Load register. The first write to the register after writing to +any other register, or after a reset (RESETn pulse low or power- +on), puts that value, PT[5..0], into the first phase table address, +a 6-bit field defined as PT(0). Subsequent writes put values into +successive addresses: PT(1), PT(2), and so forth up to PT(15). +After the sixteenth value has been written, no more values are +accepted and any writes to the Phase Table Load register are +ignored. As each value is received, it is effectively distributed to +all eight required locations in the phase current table. +An optional simple odd parity scheme is included to provide +some measure of error checking, if required. Each 6-bit value +can be supplemented with an additional parity bit, PTP, to ensure +an odd number of 1s in the transmission. This is checked by the +A3981 and if a the number of 1s in the value plus parity bit is not +odd, the FF bit will be set and the SDO pin will go high the next +time STRn is taken low, indicating a parity error. That data will + +![Image 1 from page 18](pdf-image://page_18_img_1) + +## Page 19 + +Automotive Programmable Stepper Driver +A3981 +19 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +still be written to the next phase table value address; it is incum­ +bent upon the external controller to take action, if required. +If the write sequence is broken (by a reset, by writing to another +register, or by a data transfer error) before the sequence has been +completed, then the phase table value address will be reset to +PT(0). If it is required to load the table, then the entire 16-value +sequence must be sent. +After loading, although the phase current table is volatile, a reset +using a low pulse on the RESETn pin does not corrupt the table. +The table is only reset to default values on a power-on reset. +The Phase Table Load register also contains the diagnostic +parameter used to select the stall detection scheme, STS[1..0]. +When writing to the Phase Table Load register to set the +STS[1..0] bits, the remaining bits in the serial transfer, PT[5..0], +must match the phase table value for the first phase table +address, PT(0). Before re-writing the STS[1..0] bits, a write to +another register is required to ensure that the phase table value +address is reset to PT(0). +Diagnostic Registers +The diagnostic registers comprise two read-only fault data regis­ +ters. Access is described in the section Reading from Diagnostic +Registers, above. +The diagnostic registers contain fault flags for each fault condi­ +tion and are reset to all 0s on the completion of each serial access. +They are also reset to all 0s each time the RESETn input is low +for longer than the Reset Pulse Width, tRST . FAULT0 is set to +all 1s at power-up or after a power-on reset. This indicates to the +external controller that a power-on reset has taken place and all +registers have been reset. Note that a power-on reset occurs when +power is first applied or the logic supply, VDD , drops below the +VDD Power-On Reset Threshold, VDDPOR . +Power-on reset function is not affected by the state of the motor +supply or VREG . +The first bit in both registers is the Fault Register flag, FF. This +is high if any bits in FAULT0 are set, or if a serial write error or +parity error has occurred. + +![Image 1 from page 19](pdf-image://page_19_img_1) + +## Page 20 + +Automotive Programmable Stepper Driver +A3981 +20 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +CONFIG 0 +0 +0 +SYR +MS1 +MS0 +MXI1 +MXI0 +PFD2 +PFD1 +PFD0 +TBK1 +TBK0 +TOF2 +FRQ2 +TOF1 +FRQ1 +TOF0 +FRQ0 +PWM +1 +0 +0 +1 +1 +1 +0 +0 +0 +1 +1 +1 +0 +0 +Configuration Register 0 +PWM +PWM configuration +PWM +MODE +Default +0 +Fixed off-time +D +1 +Fixed frequency +TOF[2..0] +Off time (only valid when PWM bit = 0) Re­ +places FRQ bits +Assumes 4-MHz clock +TOF2 +TOF1 +TOF0 +Off Time +Default +0 +0 +0 +20 µs +0 +0 +1 +24 µs +0 +1 +0 +28 µs +0 +1 +1 +32 µs +1 +0 +0 +36 µs +1 +0 +1 +40 µs +1 +1 +0 +44 µs +D +1 +1 +1 +48 µs +FRQ[2..0] +Frequency (only valid when PWM bit = 1) +Replace TOF bits +Assumes 4-MHz clock +FRQ2 +FRQ1 +FRQ0 +Period / Frequency +Default +0 +0 +0 +24 µs / 41.7 kHz +0 +0 +1 +32 µs / 31.3 kHz +0 +1 +0 +40 µs / 25.0 kHz +0 +1 +1 +46 µs / 21.7 kHz +1 +0 +0 +52 µs / 19.2 kHz +1 +0 +1 +56 µs / 17.9 kHz +1 +1 +0 +60 µs / 16.7 kHz +D +1 +1 +1 +64 µs / 15.6 kHz +PFD[2..0] +Fast decay time for mixed decay +Assumes 4-MHz clock +PFD2 +PFD1 +PFD0 +Fast Decay Time +Default +0 +0 +0 +2 µs +0 +0 +1 +3 µs +0 +1 +0 +4 µs +0 +1 +1 +6 µs +1 +0 +0 +8 µs +D +1 +0 +1 +10 µs +1 +1 +0 +14 µs +1 +1 +1 +20 µs +MXI[1..0] +Max phase current as a percentage of ISMAX +MXI1 +MXI0 +Maximum Current +Default +0 +0 +25% +0 +1 +50% +1 +0 +75% +1 +1 +100% +D +MS[1..0] +Microstep mode for external STEP input control +MS1 +MS0 +Microstep Mode +Default +0 +0 +Full Step +D +0 +1 +Half Step +1 +0 +Quarter Step +1 +1 +Sixteenth Step +TBK[1..0] +Blank Time +Assumes 4-MHz clock +TBK1 +TBK0 +Blank Time +Default +0 +0 +1 µs +0 +1 +1.5 µs +D +1 +0 +2.5 µs +1 +1 +3.5 µs +SYR +Synchronous rectification +SYR +Synchronous Rectification +Default +0 +Diode recirculation +1 +Synchronous +D + +![Image 1 from page 20](pdf-image://page_20_img_1) + +## Page 21 + +Automotive Programmable Stepper Driver +A3981 +21 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +CONFIG 1 +0 +1 +OSC +TSC1 +TSC0 +CD7 +CD6 +CD5 +CD4 +CD3 +CD2 +CD1 +CD0 +DIAG1 DIAG0 +0 +1 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +0 +RUN +1 +0 +EN +OL1 +OL0 +HLR +SLEW +BRK +DCY1 +DCY0 +SC5 +SC4 +SC3 +SC2 +SC1 +SC0 +0 +0 +1 +0 +1 +0 +0 +1 +0 +0 +0 +0 +0 +0 +Configuration Register 1 +Run Register +SC[5..0] +Step change number +2’s complement format +Positive value increases Step Angle Number +Negative value decreases Step Angle Number +DCY[1..0] Decay mode selection +DCY1 +DCY0 +Decay Mode +Default +0 +0 +Slow +0 +1 +Mixed—PFD fixed +D +1 +0 +Mixed—PFD auto +1 +1 +Fast +DIAG[1..0] Selects signal routed to DIAG output +DIAG1 DIAG0 +Signal on DIAG Pin +Default +0 +0 +Fault–low true +D +0 +1 +ST–low true +1 +0 +PWM-on, Phase A +1 +1 +Temperature +TSC[1..0] +Overcurrent fault delay +Assumes 4-MHz clock +TSC1 +TSC0 +Detect Delay Time +Default +0 +0 +0.5 µs +0 +1 +1 µs +1 +0 +2 µs +D +1 +1 +3 µs +OL[1..0] +Open load current threshold as a percentage of +maximum current defined by ISMAX and MXI[1..0] +OL1 +OL0 +Open Load Current +Default +0 +0 +20% +0 +1 +30% +D +1 +0 +40% +1 +1 +50% +CD[7..0] +PWM count difference for ST detection +Default to 8 +OSC +Selects clock source +OSC +Clock Source +Default +0 +Internal +D +1 +External +BRK +Brake enable +BRK +Brake +Default +0 +Normal operation +D +1 +Brake active +SLEW +Slew rate control +SLEW +Slew Rate Control +Default +0 +Disable +1 +Enable +D +HLR +Selects slow decay and brake recirculation path +HLR +Recirculation Path +Default +0 +High side +D +1 +Low side +EN +Phase current enable +OR with ENABLE pin +EN +Phase Current Enable +Default +0 +Output bridges disabled if ENABLE +pin = 0 +D +1 +Output bridges enabled + +![Image 1 from page 21](pdf-image://page_21_img_1) + +## Page 22 + +Automotive Programmable Stepper Driver +A3981 +22 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +FF +Fault register flag +TW1 +Temperature diagnostic +TW0 +Temperature diagnostic +OV +Overvoltage on VBB detected +UV +Undervoltage on VREG +ST +Stall detected +OLB +Open load detected on phase B +OLA +Open load detected on phase A +BML +Overcurrent detected on BM output low side +BMH +Overcurrent detected on BM output high side +BPL +Overcurrent detected on BP output low side +BPH +Overcurrent detected on BP output high side +AML +Overcurrent detected on AM output low side +AMH +Overcurrent detected on AM output high side +APL +Overcurrent detected on AP output low side +APH +Overcurrent detected on AP output high side +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +TBLLD +1 +1 +STS1 +STS0 +PTP +PT5 +PT4 +PT3 +PT2 +PT1 +PT0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +1 +0 +1 +Fault 0 +FF +TW1 +TW0 +OV +UV +ST +OLB +OLA +BML +BMH +BPL +BPH +AML +AMH +APL +APH +Fault 1 +FF +TW1 +TW0 +OV +UV +ST +OLB +OLA +0 +0 +SA5 +SA4 +SA3 +SA2 +SA1 +SA0 +Table Load Register +Fault Register 0 +Fault Register 1 +Table Load Register Mapping +Step Angle Number +Phase A +Phase B +0% +0 +32 +16 +48 +PT(0) +1 +31 +33 +63 +15 +17 +47 +49 +PT(1) +2 +30 +34 +62 +14 +18 +46 +50 +PT(2) +3 +29 +35 +61 +13 +19 +45 +51 +PT(3) +4 +28 +36 +60 +12 +20 +44 +52 +PT(4) +5 +27 +37 +59 +11 +21 +43 +53 +PT(5) +6 +26 +38 +58 +10 +22 +42 +54 +PT(6) +7 +25 +39 +57 +9 +23 +41 +55 +PT(7) +8 +24 +40 +56 +8 +24 +40 +56 +PT(8) +9 +23 +41 +55 +7 +25 +39 +57 +PT(9) +10 +22 +42 +54 +6 +26 +38 +58 +PT(10) +11 +21 +43 +53 +5 +27 +37 +59 +PT(11) +12 +20 +44 +52 +4 +28 +36 +60 +PT(12) +13 +19 +45 +51 +3 +29 +35 +61 +PT(13) +14 +18 +46 +50 +2 +30 +34 +62 +PT(14) +15 +17 +47 +49 +1 +31 +33 +63 +PT(15) +16 +48 +0 +32 +FF +Fault register flag +TW1 +Temperature diagnostic +TW0 +Temperature diagnostic +OV +Overvoltage on VBB detected +UV +Undervoltage on VREG +ST +Stall detected +OLB +Open load detected on phase B +OLA +Open load detected on phase A +SA[5..0] +Step Angle Number read back +TW[1..0] +Temperature diagnostic +TW1 +TW0 +Thermal Indicator +0 +0 +No Fault +0 +1 +Cold Warning +1 +0 +Hot Warning +1 +1 +Overtemperature Shutdown +PTP +Parity bit (odd parity) +PT(0..15)[5..0] Phase Table Value +STS[1..0] +Selects stall detection scheme +STS1 +STS0 +Stall Detection Scheme +Default +0 +0 +Compare opposite phases +D +0 +1 +Compare each phase +1 +0 +Reserved +1 +1 +Disable stall detection + +![Image 1 from page 22](pdf-image://page_22_img_1) + +## Page 23 + +Automotive Programmable Stepper Driver +A3981 +23 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Motor Movement Control +The A3981 provides two independent methods to control the +movement of a stepper motor. The simpler is the Step and Direc­ +tion method, which only requires two control signals to control +the stepper motor in either direction. The other method is through +the serial interface, which provides more flexible control capa­ +bility. Both methods can be used together (although it is not +common), provided the timing restrictions of the STEP input in +relation to the STRn input are preserved. +PHASE TABLE AND PHASE DIAGRAM +The key to understanding both of the available control methods +lies in understanding the Phase Current table (Table 7). This table +contains the relative phase current magnitude and direction for +each of the two motor phases at each microstep position. The +maximum resolution of the A3981 is one-sixteenth microstep. +That is 16 microsteps per full step. There are 4 full steps per elec­ +trical cycle, so the phase current table has 64 microstep entries. +The entries are numbered from 0 to 63. This number represents +the phase angle within the full 360° electrical cycle and is called +the Step Angle Number. This is illustrated in Figure 6. +Figure 6 shows the contents of the phase current table as a phase +diagram. The phase B current, IB, from the phase current table, is +plotted on horizontal axis and the phase A current, IA, is plotted +on the vertical axis. The resultant motor current at each microstep +is shown as numbered radial arrows. The number shown corre­ +sponds to the one-sixteenth microstep Step Angle Number in the +phase current table. +Figure 7 shows an example of calculating the resultant motor +current magnitude and angle for step number 28. The target is to +have the magnitude of the resultant motor current be 100% at all +microstep positions. The relative phase currents from the phase +current table are: +IA = 37.50% +IB = –92.19% +Assuming a full scale (100%) current of 1A means that the two +phase currents are: +IA = 0.3750 A +IB = -0.9219 A +The magnitude of the resultant will be the square root of the sum +of the squares of these two currents: +9953 (A) +.0 +8499 +.0 +1406 +.0 +| +| +2 +2 +28 += ++ += ++ += +B +A +I +I +I +APPLICATION INFORMATION +IA +IB +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +13 +14 +15 +16 +17 +18 +19 +20 +21 +23 +22 +24 +25 +26 +27 +28 +29 +30 +31 +32 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 46 47 +48 49 +50 51 52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63 +Figure 6: A3981 Phase Current Table as a Phase +Diagram +Values shown are referred to as the Step Angle Number. +Figure 7: Calculation of Resultant Motor Current +IA +24 +28 +32 +IB +IA28 +IB28= –92.19% +α28= +157.9° +=37.5% +31 +30 +29 +27 +26 +25 + +![Image 1 from page 23](pdf-image://page_23_img_1) + +## Page 24 + +Automotive Programmable Stepper Driver +A3981 +24 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +So the resultant current magnitude is 99.53% of full scale. This +is within 0.5% of the target (100%) and is well within the ±5% +accuracy of the A3981. +The reference angle, zero degrees (0°), within the full electrical +cycle (360°), is defined as the angle where IB is at +100% and IA +is zero. Each full step is represented by 90° in the electrical cycle +so each one-sixteenth microstep is: 90°/16 steps = 5.625°. The +target angle of each microstep position with the electrical cycle +is determined by the product of the Step Angle Number and the +angle for a single microstep. So for the example of figure 7: +° += +° +× += +5. +157 +625 +.5 +28 +) +( +28 TARGET +α +The actual angle is calculated using basic trigonometry as: + + + + + + ++ += +− +28 +28 +1 +) +( +28 +tan +180 +B +A +ACTUAL +I +I +α +( +) +° += +− ++ += +9. +157 +1. +22 +180 +So the angle error is only 0.4°. Equivalent to about 0.1% error in +360° and well within the current accuracy of the A3981. +Note that each phase current in the A3981 is defined by a 6-bit +DAC. This means that the smallest resolution of the DAC is +100 / 64 = 1.56% of the full scale, so the A3981 cannot produce +a resultant motor current of exactly 100% at each microstep. Nor +can it produce an exact microstep angle. However, as can be seen +from the calculations above, the results for both are well within +the specified accuracy of the A3981 current control. The resultant +motor current angle and magnitude are also more than precise +enough for all but the highest precision stepper motors. +With the phase current table, control of a stepper motor is simply +a matter of increasing or decreasing the Step Angle Number +to move around the phase diagram of Figure 7. This can be in +predefined multiples using the STEP input, or it can be variable +using the serial interface. +USING STEP AND DIRECTION CONTROL +The STEP input moves the motor at the microstep resolution +defined by the two microstep select variables, MS0 and MS1, +logic levels. The DIR input defines the motor direction. These +inputs define the output of a translator which determines the +required Step Angle Number in the phase current table. The MS0 +and MS1 can be set to select full step, half step, quarter step, or +sixteenth step microstepping as follows: +MS1 +MS0 +Microstep Mode +0 +0 +Full step +0 +1 +Half step +1 +0 +Quarter step +1 +1 +Sixteenth step +MS0 and MS1 can be accessed through the serial interface or +directly on pins 13 and 12 respectively. The values of MS0 and +MS1 are defined as the logical OR of the logic level on the input +pins and the value in Configuration Register 0. The bits in the +register default to 0 so if the serial interface is not used then MS0 +and MS1 are defined by the input pins alone. If only the serial +interface is used to set the microstep resolution, then the MS0 and +MS1 logic input pins should be tied low to ensure that the register +retains full control over all resolutions. Note that the microstep +select variables, MS0 and MS1, are only used with the STEP +input; they can be ignored if the motor is fully controlled through +the serial interface. +In sixteenth step mode the translator simply increases or +decreases the Step Angle Number on each rising edge of the +STEP input, depending on the logic state of the DIR input. In the +other three microstep resolution modes the translator outputs spe­ +cific Step Angle Numbers as defined in the phase current table. +Full step uses four of the entries in the phase current table. These +are 8, 24, 40, and 56 as shown in Figure 8. Note that the four +positions selected for full step are not the points at which only +one current is active, as would be the case in a simple on-off full +step driver. There are two advantages in using these positions +rather than the single full current positions. With both phases +active, the power dissipation is shared between two drivers. This +slightly improves the ability to dissipate the heat generated and +reduces the stress on each driver. +The second reason is that the holding torque is slightly improved +because the forces holding the motor are mainly rotational rather +than mainly radial. +Half step uses eight of the entries in the phase current table. +These are 0, 8, 16, 24, 32, 40, 48, and 56 as shown in Figure 9. +Quarter step uses sixteen of the entries in the phase current table. +These are 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, +and 60 as shown in Figure 10. +In half step and in quarter step, the single phase active positions +are used to preserve symmetry. However, if the motor is required + +![Image 1 from page 24](pdf-image://page_24_img_1) + +## Page 25 + +Automotive Programmable Stepper Driver +A3981 +25 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +to stop with a significant holding torque for any length of time +it is recommended that the 45° positions be used; those are Step +Angle Numbers 8, 24, 40, and 56, as used with full-step resolu­ +tion. +The following table summarizes the Step Angle Numbers used +for the four resolutions available when using the STEP input to +control the output of the A3981: +Mode +Step Angle Numbers used +Full +8, 24, 40, 56 +Half +0, 8, 16, 24, 32, 40, 48, 56 +Quarter +0, 4, 8, 12, 16, 20, 24, 28, 32, +36, 40, 44, 48, 52, 56, 60 +Sixteenth +All +The microstep select inputs can be changed between each rising +edge of the STEP input. The only restriction is that the MSO and +MS1 logic inputs must comply with the set-up and hold timing +constraints. When the microstep resolution changes, the A3981 +moves to the next available Step Angle Number on the next rising +edge of the STEP input. For example, if the microstep mode is +sixteenth and the present Step Angle Number is 59, then with the +direction forwards (increasing Step Angle Number), changing +to quarter step mode will cause the phase number to go to 60 on +the next rising edge of the STEP input. If instead the microstep +mode is changed to half step then the phase number will go to 0 +on the next rising edge of the STEP input. If the microstep mode +is changed to full step then the phase number will go to 8 on the +next rising edge of the STEP input. +CONTROL THROUGH THE SERIAL INTERFACE +The A3981 provides the ability to directly control the motor +movement using only the serial interface. In fact, all features +of the A3981, except sleep mode, can be controlled through the +serial interface thus removing the requirement for individual +control inputs. This can reduce the interface requirement from +multiple I/O signals to a single four wire interface. +Motor movement is controlled using the serial interface by +increasing or decreasing the Step Angle Number. Note that the +maximum value of the Step Angle Number is 63 and the mini­ +mum number is 0.Therefore, any increase or decrease in the +microstep number is performed using modulo 64 arithmetic. This +means that increasing a Step Angle Number of 63 by 1 will pro­ +duce a Step Angle Number of 0. Increasing by two from 63 will +produce 1 and so on. Similarly in the reverse direction, decreasing +a Step Angle Number of 0 by 1 will produce a Step Angle Num­ +ber of 63. Decreasing by two from 0 will produce 62 and so on. +The least significant six bits of the Run register, bits 0 to 5, are +the step change number, SC[5..0]. This number is a two’s comple­ +ment number that is added to the Step Angle Number causing it +to increase or decrease. Two’s complement is the natural integer +number system for most microcontrollers. This allows standard +arithmetic operators to be used, within the microcontroller, to +determine the size of the next step increment. Table 6 shows the +IA +0 +4 +8 +12 +16 +20 +24 +28 +IB +32 +36 +40 +44 +48 +52 +56 +60 +0 +8 +16 +24 +32 +40 +48 +56 +IB +IA +8 +24 +40 +56 +IB +IA +Figure 8: Full-step Phase Diagram Using STEP Input +Figure 9: Half-step Phase Diagram Using STEP Input +Figure 10: Quarter-step Phase Diagram Using STEP +Input + +![Image 1 from page 25](pdf-image://page_25_img_1) + +## Page 26 + +Automotive Programmable Stepper Driver +A3981 +26 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +binary equivalent of each decimal number between –16 and +16. +Each increase in the Step Angle Number represents a forwards +movement of one-sixteenth microstep. Each decrease in the Step +Angle Number represents a reverse movement of one-sixteenth +microstep. +To move the motor one full step, the Step Angle Number must be +increased or decreased by 16. To move the motor one half step, +the Step Angle Number must be increased or decreased by 8. For +quarter step the increase or decrease is 4 and for eighth step, 2. +So, for example, to continuously move the motor forwards in +quarter-step increments, the number 4 (000100) is repeatedly +written to SC[5..0] through the serial interface Run register (see +Figure 11). To move the motor backwards in quarter step incre­ +ments, the number -4 (111100) is repeatedly written to SC[5..0] +(see Figure 12). The remaining bits in the Run register should be +set for the required configuration and sent with the step change +number each time. +The step rate is controlled by the timing of the serial interface. +It is the inverse of the step time, tSTEP , shown in Figure 11. The +motor step only takes place when the STRn goes from low to +high when writing to the Run register. The motor step rate is +therefore determined by the timing of the rising edge of the STRn +input. The clock rate of the serial interface, defined by the fre­ +quency of the SCK input, has no effect on the step rate. +Table 6. Binary Equivalents +Decimal +2’s Complement +Decimal +2’s Complement +0 +000000 +1 +000001 +–1 +111111 +2 +000010 +–2 +111110 +3 +000011 +–3 +111101 +4 +000100 +–4 +111100 +5 +000101 +–5 +111011 +6 +000110 +–6 +111010 +7 +000111 +–7 +111001 +8 +001000 +–8 +111000 +9 +001001 +–9 +110111 +10 +001010 +–10 +110110 +11 +001011 +–11 +110101 +12 +001100 +–12 +110100 +13 +001101 +–13 +110011 +14 +001110 +–14 +110010 +15 +001111 +–15 +110001 +16 +010000 +–16 +110000 +SDI +SCK +STRn +1 0 1 0 +1 0 1 0 +1 0 1 1 1 1 0 0 +-4 +SDI +SCK +STRn +1 0 1 0 +1 0 1 0 +1 0 0 0 0 1 0 0 ++4 +tSTEP +Figure 11: Serial Interface Sequence for Quarter Step in Forward Direction +Figure 12: Serial Interface Sequence for Quarter Step in Reverse Direction + +![Image 1 from page 26](pdf-image://page_26_img_1) + +## Page 27 + +Automotive Programmable Stepper Driver +A3981 +27 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Using the Phase Table Load Capability +TORQUE RIPPLE REDUCTION +The performance and audible noise of any motor drive system is +defined, to a large extent, by the torque ripple generated by both +the motor and the load. In most cases, when using a stepper motor +as the mechanical drive, the torque ripple of the load is not related +to the mechanical steps of the motor and must be reduced by +means unrelated to the motor and its drive system. However, for +stepper motors in particular, torque ripple produced by the motor +can be reduced by improvements in the mechanical design of the +motor and by improvements in the phase current control system. +Torque ripple will naturally be high when driving a stepper motor +in full step mode, due to the nature of stepping. However the +torque ripple can be reduced by using microstepping. Increas­ +ing the number of microsteps per mechanical step will result in +reduced torque ripple. This is one of the major reasons for using +microstepping. +In the majority of cases the standard sinusoidal, microstep current +profile will be sufficient to achieve a good performance with +a good quality motor. In a few cases, further improvements in +torque ripple performance may be achieved by modifying the +microstep current profile to more closely match the motor charac­ +teristics. This is usually only necessary for higher quality, higher +power stepper motors. +When using microstepping, the torque ripple is defined by the +variation in torque at each microstep. In a hybrid stepper motor +this is mostly determined by the mechanical construction of the +motor, particularly the shape of the teeth on the poles of the sta­ +tor. The shape of these teeth determine the variation in the torque +constant, the ratio between current and torque, as the motor +rotates. The variation in the torque constant can be seen by mea­ +suring the back EMF of the motor when being driven as a genera­ +tor, that is when the shaft is driven by external means and the +phase voltage is monitored. The back EMF represents the motor +constant, which is essentially proportional to the torque constant. +If such torque ripple reduction measures are required, the A3981 +provides the ability to modify the microstep current profile by +programming the internal phase current table through the serial +interface. The modified profile is then used, in place of the default +sinusoidal profile, to compensate for any variation in motor torque +constant. The current at each Step Angle Number can be set to suit +the microstep current profile requirements of a specific motor. +Note: This is an advanced feature of the A3981, which will not be +required for most applications. In general the default sinusoidal +profile will suffice and therefore the phase current table does not +have to be loaded. +LOADING PHASE CURRENT TABLE +The full phase current table in the A3981 contains one 6-bit value +for each phase, at each microstep position. With 16 microsteps +per mechanical step, 4 mechanical steps per electrical cycle, and +2 phases this gives a total of 128 values. However, due to symme­ +try, described below, this reduces to 17 independent values, one +of which is always zero. The remaining 16 values can be loaded +sequentially through the serial interface using the Phase Table +Load register. Figure 13 shows the default phase table values +plotted by Step Angle Number. Similar information is provided in +Table 7. +The diagram in Figure 13 is marked with four quadrants, Q1 to +Q4. The set of phase table values is the same in each quadrant in +each phase. Consider phase A (bottom graph), quadrant 1 (Q1). +This contains Step Angle Numbers 0 to 15. The default values +in these 16 positions are selected to produce one quarter of a +sinusoid. +Now consider the next quadrant (Q2) of phase A. The sequence +of values in this quadrant form a mirror image, by Step Angle +Number, of the values in Q1 so the same values are used but +entered in the reverse sequence. +The following table shows the Step Angle Number in the first +row increasing from 0 to 15, from left to right, and the default +values also increasing from left to right in the second row. These +first two rows are the entries for Q1 of phase A. +Step +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 13 14 15 +Q1 +Value +0 +5 +11 +18 23 29 35 40 44 48 52 55 58 60 62 63 +Step +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 +Q2 +Value +5 +11 +18 23 29 35 40 44 48 52 55 58 60 62 63 63 +The second two rows are the entries for Q2 of phase A. The Step +Angle Number in the third row increases from 16 to 31, this time +from right to left, but the same default values still increase from +left to right. A single value is therefore placed in more than one +location in the table. Shown outlined above, steps 4 and 28 both +contain the value 23. +The same principal can be applied to Q3 and Q4 of phase A. In +this case the mirror image is in the horizontal axis, about the zero +reference value. Although the current in Q3 and Q4 for phase A is +effectively negative, the negation is provided by controlling the + +![Image 1 from page 27](pdf-image://page_27_img_1) + +## Page 28 + +Automotive Programmable Stepper Driver +A3981 +28 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +(DAC value) +0 +2 +3 +4 +5 +6 +7 +8 +9 +14 +15 +16 +17 +18 +19 +20 +22 +23 +24 +25 +26 +27 +28 +29 +30 +31 +32 +33 +34 +35 +36 +37 +38 +39 +40 +41 +42 +43 +44 +45 +46 +47 +48 +49 +50 +51 +52 +53 +54 +55 +56 +57 +58 +59 +60 +61 +62 +63 +1 +21 +11 +10 +13 +12 +48 +Q1 +Q2 +Q3 +Q4 +Q1 +Q2 +Q3 +Q4 +IB +(forwards) +63 +62 +58 +52 +44 +35 +23 +11 +11 +23 +35 +44 +52 +58 +62 +63 +5 +18 +29 +40 +48 +55 +60 +5 +18 +29 +40 +48 +55 +60 +63 +62 +58 +52 +44 +35 +23 +11 +11 +23 +35 +44 +52 +58 +62 +63 +5 +18 +29 +40 +48 +55 +60 +5 +18 +29 +40 +48 +55 +60 +IB +(reverse) +IA +(forwards) +IA +(reverse) +Figure 13. Default Phase Table Values +Step Angle Number +(DAC value) +(DAC value) +(DAC value) + +![Image 1 from page 28](pdf-image://page_28_img_1) + +## Page 29 + +Automotive Programmable Stepper Driver +A3981 +29 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Table 7: Phase Current Table (default, power-on content) +Step Angle Number +Phase Cur­ +rent +(% of IPMAX) +Step +Angle +Phase +DAC +Step Angle Number +Phase Current +(% of IPMAX) +Step +Angle +Phase +DAC +Full +1/2 +1/4 +1/8 +1/16 +A +B +A +B +A +B +Full +1/2 +1/4 +1/8 +1/16 +A +B +A +B +A +B +0 +0 +0 +0 +0.00 100.00 +0.0 +0 +0 +0 +63 +4 +8 +16 +32 +0.00 +-100.00 180.0 +0 +1 +0 +63 +1 +9.38 100.00 +5.4 +0 +0 +5 +63 +33 +-9.38 +-100.00 185.4 +1 +1 +5 +63 +1 +2 +18.75 98.44 +10.8 +0 +0 +11 +62 +17 +34 +-18.75 +-98.44 190.8 +1 +1 +11 +62 +3 +29.69 95.31 +17.3 +0 +0 +18 +60 +35 +-29.69 +-95.31 197.3 +1 +1 +18 +60 +1 +2 +4 +37.50 92.19 +22.1 +0 +0 +23 +58 +9 +18 +36 +-37.50 +-92.19 202.1 +1 +1 +23 +58 +5 +46.88 87.50 +28.2 +0 +0 +29 +55 +37 +-46.88 +-87.50 208.2 +1 +1 +29 +55 +3 +6 +56.25 82.81 +34.2 +0 +0 +35 +52 +19 +38 +-56.25 +-82.81 214.2 +1 +1 +35 +52 +7 +64.06 76.56 +39.9 +0 +0 +40 +48 +39 +-64.06 +-76.56 219.9 +1 +1 +40 +48 +0 +1 +2 +4 +8 +70.31 70.31 +45.0 +0 +0 +44 +44 +2 +5 +10 +20 +40 +-70.31 +-70.31 225.0 +1 +1 +44 +44 +9 +76.56 64.06 +50.1 +0 +0 +48 +40 +41 +-76.56 +-64.06 230.1 +1 +1 +48 +40 +5 +10 +82.81 56.25 +55.8 +0 +0 +52 +35 +21 +42 +-82.81 +-56.25 235.8 +1 +1 +52 +35 +11 +87.50 46.88 +61.8 +0 +0 +55 +29 +43 +-87.50 +-46.88 241.8 +1 +1 +55 +29 +3 +6 +12 +92.19 37.50 +67.9 +0 +0 +58 +23 +11 +22 +44 +-92.19 +-37.50 247.9 +1 +1 +58 +23 +13 +95.31 29.69 +72.7 +0 +0 +60 +18 +45 +-95.31 +-29.69 252.7 +1 +1 +60 +18 +7 +14 +98.44 18.75 +79.2 +0 +0 +62 +11 +23 +46 +-98.44 +-18.75 259.2 +1 +1 +62 +11 +15 +100.00 9.38 +84.6 +0 +0 +63 +5 +47 +-100.00 +-9.38 +264.6 +1 +1 +63 +5 +2 +4 +8 +16 +100.00 0.00 +90.0 +0 +0 +63 +0 +6 +12 +24 +48 +-100.00 +0.00 +270.0 +1 +1 +63 +0 +17 +100.00 -9.38 +95.4 +0 +1 +63 +5 +49 +-100.00 +9.38 +275.4 +1 +0 +63 +5 +9 +18 +98.44 -18.75 100.8 +0 +1 +62 +11 +25 +50 +-98.44 +18.75 +280.8 +1 +0 +62 +11 +19 +95.31 -29.69 107.3 +0 +1 +60 +18 +51 +-95.31 +29.69 +287.3 +1 +0 +60 +18 +5 +10 +20 +92.19 -37.50 112.1 +0 +1 +58 +23 +13 +26 +52 +-92.19 +37.50 +292.1 +1 +0 +58 +23 +21 +87.50 -46.88 118.2 +0 +1 +55 +29 +53 +-87.50 +46.88 +298.2 +1 +0 +55 +29 +11 +22 +82.81 -56.25 124.2 +0 +1 +52 +35 +27 +54 +-82.81 +56.25 +304.2 +1 +0 +52 +35 +23 +76.56 -64.06 129.9 +0 +1 +48 +40 +55 +-76.56 +64.06 +309.9 +1 +0 +48 +40 +1 +3 +6 +12 +24 +70.31 -70.31 135.0 +0 +1 +44 +44 +3 +7 +14 +28 +56 +-70.31 +70.31 +315.0 +1 +0 +44 +44 +25 +64.06 -76.56 140.1 +0 +1 +40 +48 +57 +-64.06 +76.56 +320.1 +1 +0 +40 +48 +13 +26 +56.25 -82.81 145.8 +0 +1 +35 +52 +29 +58 +-56.25 +82.81 +325.8 +1 +0 +35 +52 +27 +46.88 -87.50 151.8 +0 +1 +29 +55 +59 +-46.88 +87.50 +331.8 +1 +0 +29 +55 +7 +14 +28 +37.50 -92.19 157.9 +0 +1 +23 +58 +15 +30 +60 +-37.50 +92.19 +337.9 +1 +0 +23 +58 +29 +29.69 -95.31 162.7 +0 +1 +18 +60 +61 +-29.69 +95.31 +342.7 +1 +0 +18 +60 +15 +30 +18.75 -98.44 169.2 +0 +1 +11 +62 +31 +62 +-18.75 +98.44 +349.2 +1 +0 +11 +62 +31 +9.38 -100.00 174.6 +0 +1 +5 +63 +63 +-9.38 +100.00 354.6 +1 +0 +5 +63 +4 +8 +16 +32 +0.00 -100.00 180.0 +0 +1 +0 +63 +0 +0 +0 +0 +0.00 +100.00 +0.0 +0 +0 +0 +63 +direction of the current. The current control scheme still operates +using positive values. +As shown below, the table of values can be extended to include +Q3 and Q4 with the current direction indicated in the last column. +Note that the same value is now applied to four locations in the +full 360-degree electrical cycle. +Step +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 11 12 13 14 15 +Q1 FWD +Value +0 +5 +11 18 23 29 35 40 44 48 52 55 58 60 62 63 +Step +31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 +Q2 FWD +Value +5 +11 18 23 29 35 40 44 48 52 55 58 60 62 63 63 +Step +32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 +Q3 Rev +Value +0 +5 +11 18 23 29 35 40 44 48 52 55 58 60 62 63 +Step +63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 +Q4 Rev +Value +5 +11 18 23 29 35 40 44 48 52 55 58 60 62 63 63 +Shown outlined above, steps 4, 28, 36, and 60 all contain the +value 23. +The other phase, phase B, uses the same values as phase A but +shifted back by 16 Step Angle Numbers. The full distribution of +the value entered in step 4 of phase A is highlighted in Figure 13 +(and shown in Table 7). This single value is used in a total of +eight locations. The same distribution of values applies to all the +values in steps 1 to 15. These values are defined in the A3981 as +PT(0) to PT(14), respectively. +There are two exceptions to this data distribution principal. These +are the zero value and the maximum value: +• The values in phase A steps 0 and 32 and phase B steps 16 and +48 are always set to zero and cannot be programmed. +• The maximum value, PT(15), is distributed to only two Step +Angle Numbers in each phase. These are the points in the +cycle where the peak current is required, namely phase A steps +16 and 48 and phase B steps 0 and 32. + +![Image 1 from page 29](pdf-image://page_29_img_1) + +## Page 30 + +Automotive Programmable Stepper Driver +A3981 +30 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Each of the 16 values written to the phase table is a 6-bit num­ +ber that determines the current trip point for the associated step. +The highest value, 63, represents the maximum phase current, +IPMAX , defined in the section of the specification on phase cur­ +rent control. Other numbers represent a percentage of IPMAX . For +example, the number 23 sets the phase current trip point to 23/63 += 36.51% of IPMAX . +There are two restrictions when using the phase table load capa­ +bility: +• The required current profile must conform to the symmetry +shown in Figure 14. The forward (positive) current part must +be symmetrical about Step Angle Number16 for phase A and +about 0 for phase B. The reverse (negative) current part must +be symmetrical about Step Angle Number 48 for phase A and +about 32 for phase B. The forward and reverse profiles for +each phase must be the same. +• The phase current must be zero at Step Angle Numbers 0 and +32 for phase A and Step Angle Numbers 16 and 48 for phase +B. +PHASE CURRENT TABLE PROGRAMMING EXAMPLE +As an example of programming the phase current table, consider +the current profile shown in Figure 14. This shows a profile +where the torque from each phase is required to be relatively +higher at the detent points, that is, the points where only one +phase is active. (This current profile does not relate to any spe­ +cific motor, it is only shown as an example.) +Figure 14 shows the required current for each phase at each +Step Angle Number as a percentage of the maximum phase +current, IPMAX , defined above. The waveform conforms to the +required symmetry and zero crossing restrictions, so the profile +for phase A for Step Angle Numbers from 0 to 16 (outlined and +shaded) can be used to determine the phase table contents. +The first step is to digitize the profile into microsteps and the +percentage values into 6-bit numbers, as shown in Figure 15. +At each of the one-sixteenth microsteps, identified by Step Angle +Number, the value of the phase current, as a percentage of the +maximum phase current, IPMAX , is digitized to a 6-bit value from +Figure 14: Example Current Profile +Phase Current Table Value +Figure 15: Digitizing the Example Current Profile + +![Image 1 from page 30](pdf-image://page_30_img_1) + +![Image 2 from page 30](pdf-image://page_30_img_2) + +![Image 3 from page 30](pdf-image://page_30_img_3) + +## Page 31 + +Automotive Programmable Stepper Driver +A3981 +31 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +0 to 63. The value 63 represents 100% of IPMAX , 32 represents +32/63=50.8% and so on. The value at each Step Angle Number is +then assigned to its corresponding phase table values as follows: +( +) +n +DI +n +PT += +−1 +where DIn represents the digitized value of the current at Step +Angle Number n. +A selection of the values and the corresponding phase current +table entries is shown in Figure15. The full set of phase current +table values is shown in the table below. +Step +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 13 14 15 16 +Value +10 20 25 28 29 30 31 32 35 40 50 58 60 62 63 63 +PT +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 13 14 15 +These 16 values are then loaded sequentially into the phase +current table through the Phase Table Load register of the serial +interface. Each value is then distributed to the appropriate Step +Angle Numbers as described above and as shown in table 4C in +the Phase Table Load Register section. +A representation of the final result is shown in Figure 16. This +is the digitized version of the required current profile shown in +Figure 14. +Figure 16: Resulting Example Current Profile + +![Image 1 from page 31](pdf-image://page_31_img_1) + +![Image 2 from page 31](pdf-image://page_31_img_2) + +## Page 32 + +Automotive Programmable Stepper Driver +A3981 +32 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Power Dissipation +The A3981 is a power circuit, therefore careful consideration +must be given to power dissipation and the effects of high cur­ +rents on interconnect and supply wiring. +A first order approximation of the power dissipation in the A3981 +can be determined by examining the power dissipation in each of +the two bridges during each of the operation modes. When syn­ +chronous rectification is used current will flow most of the time +through the DMOS transistors that are switched on. When syn­ +chronous rectification is not used the current will flow through +the body diode of the DMOS transistors during the decay phase. +The use of fast or slow decay will also affect the dissipation. All +the above combinations can be calculated from five basic DMOS +output states as shown in Figure 17. +Figure 17. Basic Output States +• +Diagonally opposite DMOS +output transistors are on +• +Current flows from ground +through load to positive supply +• +Dissipation is I2R losses in the +DMOS transistors: +PD(SF) = I2 × (RDS(on)H+RDS(on)L ) +• +Both low-side DMOS output +transistors are on +• +Current circulates through both +transistors and the load +• +Dissipation is I2R losses in the +DMOS transistors: +PD(SS) = I2 × (2 × RDS(on)L ) +• +Diagonally opposite body diodes +conducting +• +Current flows from ground +through load to positive supply +• +Dissipation is IV losses in the +diodes: +PD(NF) = I × ( VFH + VFL ) +• +One low-side DMOS output +transistor and one body diode +conducting +• +Current circulates through the +diode, the transistor and the load +• +Dissipation is I2R losses in the +DMOS transistors plus IV loss in +the diode: +PD(NS) = (I2 × RDS(on)L ) ⁄ ( I × VF ) +• +(Used in all combinations) +• +Diagonally opposite DMOS +output transistors are on +• +Current flows from positive +supply through load to +ground +• +Dissipation is I2R losses in +the DMOS transistors: +PD = I2 × (RDS(on)H + RDS(on)L ) +Synchronous Fast Decay +Non-Synchronous Fast Decay +Synchronous Slow Decay +Non-Synchronous Slow Decay +Drive Current Ramp-up + +![Image 1 from page 32](pdf-image://page_32_img_1) + +## Page 33 + +Automotive Programmable Stepper Driver +A3981 +33 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +The total power dissipation for each of the four decay modes, +PD(TOT) XX, is the average power for the drive current ramp por­ +tion, PD , and the drive current decay portion, PD(XX) of the PWM +cycle. For slow decay the current will be rising for approximately +20% of the cycle and decaying for approximately 80%. For fast +decay the ratio will be approximately 50%. Note that these are +approximate figures and will vary slightly depending on the +motor characteristics and the use of synchronous rectification. +The following formulas may be used to estimate total power dis­ +sipation: +• Synchronous slow decay mode +PD(TOT)SS = 0.2 × PD + 0.8 × PD(SS) +PD(TOT)SS = 0.2 (I 2 [RDS(on)H + RDS(on)L ]) + 0.8 (I 2 × 2 × RDS(on)L) +• Non-synchronous slow decay mode +PD(TOT)NS = 0.2 × PD + 0.8 × PD(NS) +PD(TOT)NS = 0.2 ( I 2 [RDS(on)H + RDS(on)L ]) + 0.8 (I 2 × RDS(on)L + I × VF) +• Synchronous fast decay mode +PD(TOT)SF = 0.5 × PD + 0.5 × PD(SF) +PD(TOT)SF = I 2 (RDS(on)H + RDS(on)L ) +• Non-synchronous fast decay mode +PD(TOT)NF = 0.5 × PD + 0.5 × PD(NF) +PD(TOT)NF = 0.5( I 2 [RDS(on)H + RDS(on)L ] ) + 0.5( I × [VFH + VFL ] ) +An approximation of the total dissipation can be calculated by +summing the total power dissipated in both bridges and adding +the control circuit power due to VBB × IBB and VDD × IDD . +The total power at the required ambient temperature can then be +compared to the allowable power dissipation shown in figure 18. +For critical applications, where the first order power estimate is +close to the allowable dissipation, the power calculation should +take several other parameters into account including: motor +parameters, dead time, and switching losses in the controller. +Ambient Temperature (°C) +Allowable Power Dissipation (W) +150 +125 +100 +75 +50 +25 +5 +4 +3 +2 +1 +0 +RθJA = 28 °C/W +(on 4-layer PCB) +RθJA = 32 °C/W +(on 2-layer PCB) +Figure 18: Allowable Power Dissipation, on Typical PCBs + +![Image 1 from page 33](pdf-image://page_33_img_1) + +## Page 34 + +Automotive Programmable Stepper Driver +A3981 +34 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Layout +TRACES +PCB The printed circuit board (PCB, or printed wiring board) +should use a higher weight copper thickness than a standard small +signal or digital circuit board. This helps to reduce the impedance +of the printed traces when conducting high currents. PCB traces +carrying switching currents should be as wide and short as pos­ +sible to reduce the inductance of the trace. This will help reduce +any voltage transients caused by current switching during PWM +current control. +For optimum thermal performance, the exposed thermal pad on +the underside of the A3981 should be soldered directly onto the +board. A solid ground plane should be added to the opposite side +of the board, and multiple vias through the board to the ground +plane should be placed in the area under the thermal pad. +DECOUPLING +All supplies should be decoupled with an electrolytic capacitor in +parallel with a ceramic capacitor. The ceramic capacitor should +have a value of 100 nF and should be placed as close as pos­ +sible to the associated supply and ground pins of the A3981. The +electrolytic capacitor connected to VBB should be rated at least +1.5 times the maximum circuit voltage, and selected to support +the maximum ripple current provided to the motor. The value of +the capacitor is unimportant but should be the lowest value with +the necessary ripple current capability. +The pump capacitor between CP1 and CP2, the pump storage +capacitor between VCP and VBB, and the compensation capaci­ +tor between VREG and ground should be connected as close as +possible to the respective pins of the A3981. +GROUNDING +A star ground system, with the common star point located close to +the A3981, is recommended. The reference ground, AGND (pin +7), and the power ground, PGND (pin 21), must be connected +together externally. The copper ground plane located under the +exposed thermal pad is typically used as the star ground point. +CURRENT SENSE REGISTER +In sensing the output current level, to minimize inaccuracies +caused by ground-trace IR drops, the current sense resistor (RS) +should have an independent ground return to the star ground +point. This path should be as short as possible. For low-value +sense resistors, the IR drop in the PCB trace to the sense resis­ +tor can be significant and should be taken into account. Surface +mount chip resistors are recommended to minimize contact +resistance and parasitic inductance. The value, RS , of the sense +resistor is given by: +SMAX +REF +S +I +V +R +× += 16 +There is no restriction on the value of RS or VREF , other than the +range of VREF over which the output current precision is guaran­ +teed. However, it is recommended that the value of VREF be kept +as high as possible to improve the current accuracy. The table +below provides increasing values of ISMAX for suggested values +of VREF and standard E96 values of RS . +Suggested Values +ISMAX +(mA) +RS +(mΩ) +VREF +(V) +100 +499 +0.8 +200 +499 +1.6 +300 +417 +2.0 +405 +309 +2.0 +501 +249 +2.0 +610 +205 +2.0 +702 +178 +2.0 +812 +154 +2.0 +912 +137 +2.0 +1008 +124 +2.0 + +![Image 1 from page 34](pdf-image://page_34_img_1) + +## Page 35 + +Automotive Programmable Stepper Driver +A3981 +35 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +INPUT/OUTPUT STRUCTURES +DIR +STEP +MS1 +MS0 +2 kΩ +8 V +6 V +VDD +47 kΩ +1 pF +OSC +8 V +6 V +VDD +6 V +EN +8 V +6 V +VDD +1 pF +STRN +SCK +SDI +8 V +6 V +VDD +SDO +8 V +VDD +OAP +OAM +OBP +OBM +VBB +VCP +VBB +18 V +18 V +14 V +VDD +8 V +CP1 +CP2 +VREG +8 V +7.5 V +AGND +PGND +REF +5 kΩ +8 V +6 V +6 V +RESETn +8 V +6 V +VDD +1 pF +50 kΩ +6 V +DIAG +8 V +VDD +6 V +SENSA +SENSB +22 V +VREG +2 kΩ +25 Ω +25 Ω +2 kΩ +51 kΩ +51 kΩ +500 Ω +120 Ω +Figure 19a: Supplies and Reference +Figure 19b: Sense Inputs +Figure 19e: STRN, SCK, SDI Inputs +Figure 19h: SDO Output +Figure 19c: DIR, STEP, MS1, MS0 Inputs +Figure 19f: OSC Input +Figure 19i: Phase Outputs +Figure 19d: EN Input +Figure 19g: RESETn Input +Figure 19j: DIAG Output + +![Image 1 from page 35](pdf-image://page_35_img_1) + +## Page 36 + +Automotive Programmable Stepper Driver +A3981 +36 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Figure 20: Package LP, 28-Pin TSSOP with Exposed Thermal Pad +For Reference Only – Not for Tooling Use +(Reference Allegro DWG-0000379, Rev. 3 and JEDEC MO-153AET) +Dimensions in millimeters – NOT TO SCALE +Dimensions exclusive of mold flash, gate burrs, and dambar protrusions +Exact case and lead configuration at supplier discretion within limits shown +A +1.20 MAX +0.15 +0.025 +0.30 +0.19 +0.20 +0.09 +8º +0º +0.60 ±0.15 1.00 REF +C +SEATING +PLANE +C +0.10 +28X +0.65 BSC +0.25 BSC +2 +1 +28 +9.70 ±0.10 +4.40±0.10 +6.40±0.20 +GAUGE PLANE +SEATING PLANE +B +Branded Face +6.10 +0.65 +0.45 +1.65 +3.00 +5.00 +28 +2 +1 +C +5.08 NOM +3 NOM +PCB Layout Reference View +A +B +C +Exposed thermal pad (bottom surface) +Terminal \#1 mark area +Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM); +All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary +to meet application process requirements and PCB layout tolerances; when +mounting on a multilayer PCB, thermal vias at the exposed thermal pad land +can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) +Branding scale and appearance at supplier discretion. +D +Standard Branding Reference View +Lines 1, 2, 3 = 10 characters +Line 1: Part Number +Line 2: Logo A, 4-digit Date Code +Line 3: Characters 5, 6, 7, 8 of +Assembly Lot Number +E +XXXXXXX +Date Code +Lot Number +CUSTOMER PACKAGE DRAWING + +![Image 1 from page 36](pdf-image://page_36_img_1) + +## Page 37 + +Automotive Programmable Stepper Driver +A3981 +37 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +APPENDIX A: DRIVING A STEPPER MOTOR +A stepper motor is a particular form of brushless DC motor. As +for any electric motor, motion is created by magnetic interaction +between the stationary part of the motor, known as the stator, and +the moving part of the motor, known as the rotor. The information +presented here concentrates on a specific type of motor known as +a hybrid stepper motor. This is the most common type of small +stepper motor. It uses permanent magnets in the rotor to produce +one set of constant magnetic fields and electromagnets in the +stator to produce another set of varying magnetic fields. The term +hybrid relates to the use of both electromagnets and permanent +magnets. +Comparing Bipolar and Unipolar Motors +There are two options in small hybrid stepper motor construction. +In the first, known as a unipolar stepper motor, there are indepen­ +dent electromagnets to generate each magnetic polarity, so two +electromagnets are required per phase. Each of these is energized +with current in only one direction, producing a single magnetic +field direction (unipolar). Because the current in each electromag­ +net only flows in a single fixed direction, the control circuit can +be very simple. The drawback is that only one electromagnet per +phase can be energized at any time so, at most, only half of the +motor volume is ever used to create torque on the rotor. +A bipolar motor, in contrast, uses each electromagnet to pro­ +duce two opposing fields (bipolar) at different times, by allow­ +ing the current to flow in both directions. This means that the +motor volume required for a bipolar motor is half of the volume +required for a unipolar motor for the same torque output. The +minor drawback is that a bipolar motor requires a more complex +drive circuit in order to reverse the forcing voltage across the coil +of the electromagnet. However, if the drive circuit is integrated +into a single IC then the drive becomes cost effective. This, along +with the improvement in torque output makes the bipolar motor +a better solution for applications where the volume available is +restricted. For this reason the following information will relate +only to bipolar motors. +In order to create continuous motion in one direction it is neces­ +sary to have two or more sets of electromagnets, that is, two or +more phases. The simplest and most cost effective configuration +for a stepper motor is to have two phases. For some applications +that require an extremely low torque ripple, 3 phase, 5 phase, and +even 9 phase stepper motors are sometimes used. However, the +remainder of the information presented here relates specifically to +2-phase bipolar motors. +Moving a 2-Phase Bipolar Stepper Motor +Figure A1 shows the four possible current combinations in two +phase windings, A and B, and the effect on a simplified repre­ +sentation of part of a stepper motor. In each case the stator with +the electromagnets is shown at the top of the diagram and the +rotor with the permanent magnets is shown at the bottom of the +diagram. +In Figure A1 the stator consists of alternate phase A and phase +B electromagnets. The winding direction of the electromagnet +changes for each sequential electromagnet in each phase as indi­ +cated by the overbar above the phase letter and identified below +as A-bar and B-bar. The result is that the magnetic poles will +alternate for each sequential electromagnet of each phase. That +means, for example, when the A electromagnet produces a north +(N) magnetic pole at the end nearest to the rotor, then the A-bar +electromagnet will produce a south (S) magnetic pole at the end +nearest to the rotor. +The windings for all the A and A-bar electromagnets are con­ +nected in series and driven by a single full bridge. Similarly the +windings for all the B and B-bar electromagnets are connected +in series and driven by another single full bridge. So a 2-phase +bipolar stepper motor requires two full bridges for full control. +The rotor is much simpler than the stator, and consists of a solid +base holding permanent magnets with alternating pole directions. +There are no windings on the rotor, so there is no requirement to +conduct current to the moving part of the motor. In addition the +lack of current and windings means that there is no heat generated +in the rotor, making cooling of the moving parts much simpler. +The diagrams in Figure A1 provide a representation of a small +section of the mechanics of the motor. In practice the motor struc­ +ture is a little different from this, but the principle of operation is +the same. +Starting at the top, panel (a) in Figure A1, the current is flowing +down through the phase A winding from top to bottom and there +is no current in phase B. The result is an N magnetic pole on the +A electromagnets and an S pole on the A-bar electromagnets. The +rotor position is such that that the poles of the permanent magnets +align with the poles of the electromagnets, N to S. +In the next panel, panel (b), the current is flowing down through +the phase B winding from top to bottom and there is no current +in phase A. The result is an N pole on the B electromagnets and +an S pole on the B-bar electromagnets. These magnetic poles will +attract and repel the permanent magnets on the rotor producing a + +![Image 1 from page 37](pdf-image://page_37_img_1) + +## Page 38 + +Automotive Programmable Stepper Driver +A3981 +38 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +A +S +\_ +A +N +B +\_ +B +A +S +\_ +A +N +B +\_ +B +Stator +S +N +N +S +S +N +N +S +N +S +Rotor +B +A +A +\_ +A +B +N +\_ +B +S +A +\_ +A +B +N +\_ +B +S +Stator +S +N +N +S +S +N +N +S +N +S +Rotor +A +B +N +S +A +N +\_ +A +S +B +\_ +B +A +N +\_ +A +S +B +\_ +B +Stator +N +S +S +N +N +S +S +N +Rotor +B +A +A +\_ +A +B +S +\_ +B +N +A +\_ +A +B +S +\_ +B +N +N +S +S +N +N +S +S +N +S +N +Stator +Rotor +A +B +Figure A1. Basic Principle of Bipolar Stepper Motor Operation +(a) +• Phase A energized in positive direction +• Phase B not energized +Permanent magnet poles on the rotor aligned with +electromagnet poles on the stator +(b) +• Phase A not energized +• Phase B energized in positive direction +Rotor moves to the right to realign permanent +magnet poles on the rotor to the electromag­ +net poles on the stator. +(c) +• Phase A energized in negative direction. +• Phase B not energized +Rotor moves to the right to realign permanent +magnet poles on the rotor to the electromag­ +net poles on the stator. +(d) +• Phase A not energized. +• Phase B energized in negative direction +Rotor moves to the right to realign permanent +magnet poles on the rotor to the electromagnet +poles on the stator. + +![Image 1 from page 38](pdf-image://page_38_img_1) + +## Page 39 + +Automotive Programmable Stepper Driver +A3981 +39 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +Figure A2: Half Step Operation +force that moves the rotor from left to right in the diagram until +the poles of the permanent magnets again align with the poles of +the electromagnets. +In panel (c), the current is flowing up through the phase A wind­ +ing from bottom to top and there is no current in phase B. This +reverses the pole orientation from the top panel, such that there +is an S pole on the A electromagnets and an N pole on the A-bar +electromagnets. As before, these magnetic poles will attract and +repel the permanent magnets on the rotor producing a force that +moves the rotor from left to right in the diagram, until poles of +the permanent magnets again align with the poles of the electro­ +magnets. +The bottom panel, panel (d), shows the final combination with +current flowing up through the phase B winding from bottom to +top and there is no current in phase A. This produces an N pole +on the B electromagnets and a S pole on the B-bar electromag­ +nets. As before, these magnetic poles will attract and repel the +permanent magnets on the rotor producing a force that moves the +rotor from left to right until poles of the permanent magnets again +align with the poles of the electromagnets. +Each of the four steps in Figure A1 represents a single full +mechanical step of the stepper motor. The four steps together +represent a single electrical cycle. +The step resolution depends entirely on the mechanical construc­ +tion of the motor and typically there will be 200 or more full +steps per mechanical revolution of the motor. A 200-step motor +will provide a resolution of 360 / 200 = 1.8° of rotation per step. +Stepping in the opposite direction to that described above is sim­ +ply a case of changing the step sequence or inverting one of the +phase current directions. +Microstepping +In many applications it is necessary to improve the resolution of +the stepper motor, for more precise positioning control, or simply +to increase the number of steps per revolution to reduce the +torque ripple and therefore the vibration and noise of the motor. +Fortunately this can be achieved by driving both phases at the +same time in order to move the rotor to a position between two +electromagnets. This is known generically as microstepping. +Figure A2 shows the basic principle of microstepping. Panels (a) +and (c) of Figure A2 correspond to panels (a) and (b) of figure +A1. Panel (b) shows each phase energized such that there are now +two adjacent N poles and two adjacent S poles. In this example +the currents in both phases is the same, and so the S and N poles +of the rotor now move to half way between the positions in +diagrams (a) and (c). Figure A2 only shows a single mechanical +step in total, which is one quarter of a full electrical cycle. This +sequence is the lowest resolution form of microstepping, known +as half step, and is the simplest method of driving a stepper motor +in half-step mode. +The currents are switched-on in the correct direction in sequence +and no current control is required. The current is simply defined, +in the first instance, by the resistance of the winding and the +applied voltage. +A +\_ +A +B +N +\_ +B +S +A +Stator +S +N +N +S +N +A +B +Rotor +A +N +\_ +A +S +B +N +\_ +B +S +A +N +Stator +S +N +N +S +S +N +A +B +Rotor +A +N +\_ +A +S +B +\_ +B +A +N +Stator +N +S +S +N +S +N +B +A +Rotor +(a) Same as +figure A1(a) +(b) Half-step +position +(c) Same as +figure A1(b) + +![Image 1 from page 39](pdf-image://page_39_img_1) + +## Page 40 + +Automotive Programmable Stepper Driver +A3981 +40 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +From Figure A2(b) it is also apparent that varying the rela­ +tive current in each phase will make it possible to move the +rotor to any intermediate position between the four positions of +Figure A1, which occur when only a single phase is energized. +When there is one intermediate position this is known as half +step. When there are three intermediate positions this is known +as quarter step and so on. Higher resolution microstepping is +described in more detail below. +PHASE CURRENT-SEQUENCE DIAGRAMS +Figure A3 shows the full sequence of the two phase currents illus­ +trated in Figure A2. This shows two electrical cycles, equivalent +to 4 full mechanical steps (8 half steps). The full-step positions are +marked F and the half-step positions are marked H. Each half step +in the electrical cycle is numbered, from 0 to 7, for reference later. +This figure shows that, when discussing stepper motor control, it +is necessary to know the relative magnitude and direction of the +current in each phase. So, rather than use physical representations +of the motor, such as in Figures A1 and A2, or simple time-based +current waveforms, such as Figure A3, it is simpler to use a phase +diagram. For a 2-pole bipolar motor this diagram is created by +plotting the current in the two phases as orthogonal vectors, that +is, as vectors at 90° to each other as shown in Figure A4. +PHASE CURRENT-PHASE DIAGRAMS +Figure A4 shows the currents of Figure A3 plotted on a phase +diagram where the phase A current is represented by the vertical +line and the phase B current by the horizontal line. The half-step +numbers correspond to the numbers in Figure A3. For example, +at step 1 in Figure A3, the phase A current and the phase B cur­ +rent are both positive and with the same magnitude. These two +currents are shown in figure A4 as the two solid arrows. Adding +these two current vectors together gives the resultant motor cur­ +rent vector indicated. The resultant is the hypotenuse of a right- +angled triangle with the two other sides equal. If the other two +sides are assumed to be 1 then the magnitude of the hypotenuse +will be: +41.1 +2 +1 +1 +2 +2 += += ++ +So the resultant current vector will be 141% of the value of the +current in phase A or B, positioned at 45°. +Torque Ripple +Now, the torque output of any electrical motor is directly propor­ +tional to the magnitude of the motor current, and the motor cur­ +rent is the resultant phase current. It is clear from Figure A4 that +the resultant phase current at the half-step position is higher than +the current at the full-step position. This means that the motor +torque will be changing as the motor rotates, resulting in what is +known as torque ripple. Torque ripple in any rotating system will +cause mechanical vibration and will result in increased audible +noise and possible wear on other mechanical components. Torque +ripple can be reduced by ensuring that the resultant current at the +half-step point has the same magnitude as the full current in the +single phase at the full-step positions. +F +H +F +H +F +H +F +H +F +H +F +H +F +H +F +F +H +Phase +B +Current +Phase +A +Current +0 +1 +2 +3 +4 +5 +6 +7 +0 +1 +2 +3 +4 +5 +6 +6 +7 +F +0 +1 +2 +3 +4 +5 +6 +7 +H +F +F +F +H +H +H +Phase B +Current +Phase A +Current +Resultant +Figure A3: Phase Current Sequence for +Uncompensated Half Step +Figure A4: Phase Diagram for Uncompensated Half +Step + +![Image 1 from page 40](pdf-image://page_40_img_1) + +## Page 41 + +Automotive Programmable Stepper Driver +A3981 +41 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +COMPENSATED HALF STEP +Figure A5 shows a circle superimposed on the phase diagram. +This circle represents the required locus of the resultant phase cur­ +rent vectors to maintain 100% current magnitude. At the full-step +positions, 0, 2, 4, and 6, only one phase is active and the magni­ +tude of the phase current is at 100%. At the half-step positions, 1, +3, 5, and 7, both phases are active. To ensure that the magnitude +of the resultant current is 100%, the magnitude of each phase cur­ +rent must be 70.7%. Calculating the value of the resultant current +as before gives a resultant current of 100%. += +0.7072 + 0.7072 +0.5 + 0.5 = +1 = 1 +The current vectors at half-step position 1 are shown specifically +to illustrate that the magnitude of the resultant sits on the 100% +circle. +For a standard stepper motor to operate with minimum torque +ripple, the resultant current must always lie on the constant torque +circle irrespective of the number of microsteps. For higher resolu­ +tion microstepping this then defines the relative phase currents at +each microstep position. +QUARTER STEP +For example consider the next resolution in microstepping; quar­ +ter step. The locus of the required phase currents are shown in +Figure A6. The required current level in each phase can be calcu­ +lated using simple trigonometry. For example, consider microstep +position 7 in Figure A6 as detailed in Figure A7. +There are 4 quarter steps for each full step. A full step on the +phase diagram is represented by 90°. So each quarter step incre­ +ments the phase angle by 90° / 4 = 22.5°. +In Figure A7 the resultant motor current at quarter-step posi­ +tion 8 is one quarter step from the horizontal, so it is at 22.5°. The +magnitude of the current in phase A at quarter-step position 7, +IA7 , is therefore sin 22.5°, which is equal to 0.383 or 38.3% of +the maximum current. +Similarly, the magnitude of the current in phase B at quarter-step +position 7, IB7 , is therefore cos 22.5°, which is equal to 0.924 or +92.4% of the maximum current. +At the 45° positions, 2, 6, 10 and 14, the magnitude of the current +in phase A and phase B will be cos 45° = 0.707 or 70.7%, which +is the same magnitude as in the half-step case shown in figure A5. +Due to symmetry, the phase A current is the same at quarter-step +F +0 +1 +2 +3 +4 +5 +6 +7 +H +F +F +F +H +H +H +Phase B +Current +Phase A +Current +Resultant +IA +0 +1 +2 +3 +4 +5 +6 +7 +IB +8 +9 +10 +11 +12 +13 +14 +15 +IA +6 +7 +8 +IB +IA7 +IB7=-cos22.5° +22.5° +=sin22.5° +Figure A5: Phase Diagram for Compensated Half Step +Figure A6: Phase Diagram for Quarter Step +Figure A7: Calculating Phase Current Magnitudes + +![Image 1 from page 41](pdf-image://page_41_img_1) + +## Page 42 + +Automotive Programmable Stepper Driver +A3981 +42 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +positions 7 and 1. The phase A current at quarter-step positions +9 and 15 also has the same magnitude, but the current is in the +opposite direction. In addition the phase B current at quarter- +step positions 3, 5, 11, and 13 also have the same magnitude as +that of phase A at quarter-step position 7, with a positive current +direction for steps 3 and 13 and a negative direction for steps 5 +and 11. Similar symmetry can be applied to the phase B current at +quarter-step position 7, calculated above. +This means that only five discrete current magnitudes are +required, including 0% and 100%, in order to drive the stepper +motor to all 16 quarter-step positions. Using the same nomencla­ +ture as Figure A7, that is, IPn , where P is the phase, A or B, and +n is the quarter-step number from Figure A6, Table A1 shows +where each of the five magnitude values are used. +Figure A8 shows these values plotted as a current sequence +diagram. This figure is therefore the time-based equivalent of the +phase diagram in Figure A6. +HIGHER MICROSTEP RESOLUTION +The principles described above can easily be extended to higher +microstep resolutions. As the microstep resolution increases, it +becomes more apparent that the phase current sequences approxi­ +mate ever closer to a sin and cosine function. Figure A9 shows +the measured phase current sequence of the A3981 running in +sixteenth-step mode. The phase current sequences for eighth-step +and sixteenth-step resolutions are shown in figures A10 and A11. +Most applications using small motors are limited to sixteenth-step +mode due to the mechanical precision of the motor. Larger, high- +precision stepper motors are sometimes driven at 32, 64, or even +up to 256 microsteps in some extreme cases. +Practical Implementation +A system to drive a stepper motor with microstep capability +requires sequencers, current reference generators, and current +controllers. Developing such a system from discrete components, +or even using a fast microcontroller, is a complex task. The +A3981 is one of several fully integrated stepper drivers that are +available with microstep resolutions, from compensated half step +to sixteenth step and higher, using programmable current tables. +All aspects of the stepper control system are included in these +single chip solutions and many of them can be controlled by a +simple Step and Direction interface. +IB +14 15 0 +1 +2 +3 +4 +5 +6 +7 +8 +9 10 11 12 +12 13 +IA +38% +70% +92% +100% +0 +-38% +-70% +-92% +-100% +38% +70% +92% +100% +0 +-38% +-70% +-92% +-100% +Figure A8: Phase Current Sequence for Quarter Step +Figure A9: Measured Sixteenth-step Phase Current +Sequence +Table A1: Quarter-Step Phase Current Magnitudes +Magnitude +(%) +Phase B +Phase A +0. +IA0 +– +IA8 +– +– +IB4 +– +IB12 +38.3 +IA1 +IA7 +IA9 +IA15 +IB3 +IB5 +IB11 +IB13 +70.7 +IA2 +IA6 +IA10 +IA14 +IB2 +IB6 +IB10 +IB14 +92.4 +IA3 +IA5 +IA11 +IA13 +IB1 +IB7 +IB9 +IB15 +100. +– +IA4 +– +IA12 +IB0 +– +IB8 +– + +![Image 1 from page 42](pdf-image://page_42_img_1) + +![Image 2 from page 42](pdf-image://page_42_img_2) + +## Page 43 + +Automotive Programmable Stepper Driver +A3981 +43 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +PRACTICAL LIMITATIONS +The information presented here assumes ideal stepper motors +being stepped slowly, with accurate, efficient current control +circuits. In practice the stepper motor phase windings are repre­ +sented by two non-ideal inductors and the motor may be driven at +a high stepping rate. +A high stepping rate will produce a back EMF, like any other +motor, that will act against any current control circuits. The +current control circuits must also be able to work with inductive +loads. In general the current control circuit will be a PWM cur­ +rent control scheme to make the driver as efficient as possible and +reduce the dissipation in the driver. +Like any other motor, the back EMF will also limit the maximum +stepping rate of the motor. As the motor speed increases the back +EMF will increase. When it reaches a value close to the supply +voltage the resulting voltage difference will be insufficient to +drive the phase current required to produce the necessary output +torque. When this occurs the motor will stall and slip out of syn­ +chronization with the driving circuit. +The mechanical precision of the motor will also have an effect +on the overall performance of the system. If the effect of the +motor windings on the rotor are non-linear then the relationship +between current and torque may not be linear. The magnitude of +the currents at each microstep may then require a relationship +other than sinusoidal. The A3981 and a few other integrated driv­ +ers are able to accommodate this by allowing the phase current +values for each microstep position to be reprogrammed. In most +systems this effect will be very small and can be ignored but in +some cases some improvement in torque ripple and audible noise +can be achieved. +Figure A10: Phase Current Sequence for Eighth Step +100% +98% +92% +83% +70% +56% +38% +19% +19% +38% +56% +70% +83% +92% +98% +100% +100% +98% +92% +83% +70% +56% +38% +19% +19% +38% +56% +70% +83% +92% +98% +100% +IB +IA +0 1 2 3 4 +5 +6 +7 +8 +9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 +24 25 26 27 28 29 30 31 + +![Image 1 from page 43](pdf-image://page_43_img_1) + +## Page 44 + +Automotive Programmable Stepper Driver +A3981 +44 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +100% +98% +92% +83% +70% +56% +38% +19% +19% +38% +56% +70% +83% +92% +98% +100% +IB +10% +29% +47% +63% +77% +88% +96% +99% +10% +29% +47% +63% +77% +88% +96% +99% +100% +98% +92% +83% +70% +56% +38% +19% +19% +38% +56% +70% +83% +92% +98% +100% +10% +29% +47% +63% +77% +88% +96% +99% +10% +29% +47% +63% +77% +88% +96% +99% +IA +Figure A11: Phase Current Sequence for Sixteenth Step + +![Image 1 from page 44](pdf-image://page_44_img_1) + +## Page 45 + +Automotive Programmable Stepper Driver +A3981 +45 +Allegro MicroSystems +955 Perimeter Road +Manchester, NH 03103-3353 U.S.A. +www.allegromicro.com +For the latest version of this document, visit our website: +www.allegromicro.com +Revision History +Number +Date +Description +4 +June 21, 2012 +Update Electrical Characteristics table. +5 +January 23, 2015 +Update stall detection, VDD power-on reset, pin-out, and miscellaneous changes. +6 +January 29, 2016 +Corrected Figure 19j. +7 +November 22, 2019 +Minor editorial updates +8 +February 3, 2022 +Updated package drawing (page 36) +9 +July 11, 2024 +Removed tube packing option from selection guide (page 2) +Copyright 2024, Allegro MicroSystems. +Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit +improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the +information being relied upon is current. +Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of +Allegro’s product can reasonably be expected to cause bodily harm. +The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor +for any infringement of patents or other rights of third parties which may result from its use. +Copies of this document are considered uncontrolled documents. + +![Image 1 from page 45](pdf-image://page_45_img_1) + diff --git a/docs/A3981-datasheet.pdf b/docs/A3981-datasheet.pdf new file mode 100644 index 0000000..3bc8eef --- /dev/null +++ b/docs/A3981-datasheet.pdf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:fd9cedc2cbfc6a71e96465f11d9db50e255a5e9d304132917bbb2a8abd738424 +size 3015781 diff --git a/docs/A3981-ecad.3dshapes/TSSOP-28_L9.7-W4.4-P0.65-LS6.4-BL-EP-1.step b/docs/A3981-ecad.3dshapes/TSSOP-28_L9.7-W4.4-P0.65-LS6.4-BL-EP-1.step new file mode 100644 index 0000000..571a29d --- /dev/null +++ b/docs/A3981-ecad.3dshapes/TSSOP-28_L9.7-W4.4-P0.65-LS6.4-BL-EP-1.step @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid 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+**Producer:** Antenna House PDF Output Library 2.6.0 (Linux64); modified using iText® 5.5.4 ©2000-2014 iText Group NV (AGPL-version) +**Creation Date:** D:20130620162538-06'00' +**Mod Date:** D:20150219181659-06'00' +**Trapped:** False + +--- + +## Page 1 + +K60P144M100SF2V2 +K60 Sub-Family +Supports the following: +MK60DN256VLQ10, +MK60DX256VLQ10, +MK60DN512VLQ10, +MK60DN256VMD10, +MK60DX256VMD10, +MK60DN512VMD10 +Features +• Operating Characteristics +– Voltage range: 1.71 to 3.6 V +– Flash write voltage range: 1.71 to 3.6 V +– Temperature range (ambient): -40 to 105°C +• Performance +– Up to 100 MHz ARM Cortex-M4 core with DSP +instructions delivering 1.25 Dhrystone MIPS per +MHz +• Memories and memory interfaces +– Up to 512 KB program flash memory on non- +FlexMemory devices +– Up to 256 KB program flash memory on +FlexMemory devices +– Up to 256 KB FlexNVM on FlexMemory devices +– 4 KB FlexRAM on FlexMemory devices +– Up to 128 KB RAM +– Serial programming interface (EzPort) +– FlexBus external bus interface +• Clocks +– 3 to 32 MHz crystal oscillator +– 32 kHz crystal oscillator +– Multi-purpose clock generator +• System peripherals +– Multiple low-power modes to provide power +optimization based on application requirements +– Memory protection unit with multi-master +protection +– 16-channel DMA controller, supporting up to 63 +request sources +– External watchdog monitor +– Software watchdog +– Low-leakage wakeup unit +• Security and integrity modules +– Hardware CRC module to support fast cyclic +redundancy checks +– Hardware random-number generator +– Hardware encryption supporting DES, 3DES, AES, +MD5, SHA-1, and SHA-256 algorithms +– 128-bit unique identification (ID) number per chip +• Human-machine interface +– Low-power hardware touch sensor interface (TSI) +– General-purpose input/output +• Analog modules +– Two 16-bit SAR ADCs +– Programmable gain amplifier (PGA) (up to x64) +integrated into each ADC +– Two 12-bit DACs +– Two transimpedance amplifiers +– Three analog comparators (CMP) containing a 6-bit +DAC and programmable reference input +– Voltage reference +• Timers +– Programmable delay block +– Eight-channel motor control/general purpose/PWM +timer +– Two 2-channel quadrature decoder/general purpose +timers +– IEEE 1588 timers +– Periodic interrupt timers +– 16-bit low-power timer +– Carrier modulator transmitter +– Real-time clock +Freescale Semiconductor +Document Number: K60P144M100SF2V2 +Data Sheet: Technical Data +Rev. 3, 6/2013 +Freescale reserves the right to change the detail specifications as may be +required to permit improvements in the design of its products. +© 2012–2013 Freescale Semiconductor, Inc. + +![Image 1 from page 1](pdf-image://page_1_img_1) + +## Page 2 + +• Communication interfaces +– Ethernet controller with MII and RMII interface to external PHY and hardware IEEE 1588 capability +– USB full-/low-speed On-the-Go controller with on-chip transceiver +– Two Controller Area Network (CAN) modules +– Three SPI modules +– Two I2C modules +– Six UART modules +– Secure Digital host controller (SDHC) +– I2S module +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +2 +Freescale Semiconductor, Inc. + +![Image 1 from page 2](pdf-image://page_2_img_1) + +## Page 3 + +Table of Contents +1 Ordering parts...........................................................................5 +1.1 Determining valid orderable parts......................................5 +2 Part identification......................................................................5 +2.1 Description.........................................................................5 +2.2 Format...............................................................................5 +2.3 Fields.................................................................................5 +2.4 Example............................................................................6 +3 Terminology and guidelines......................................................6 +3.1 Definition: Operating requirement......................................6 +3.2 Definition: Operating behavior...........................................7 +3.3 Definition: Attribute............................................................7 +3.4 Definition: Rating...............................................................8 +3.5 Result of exceeding a rating..............................................8 +3.6 Relationship between ratings and operating +requirements......................................................................8 +3.7 Guidelines for ratings and operating requirements............9 +3.8 Definition: Typical value.....................................................9 +3.9 Typical value conditions....................................................10 +4 Ratings......................................................................................11 +4.1 Thermal handling ratings...................................................11 +4.2 Moisture handling ratings..................................................11 +4.3 ESD handling ratings.........................................................11 +4.4 Voltage and current operating ratings...............................11 +5 General.....................................................................................12 +5.1 AC electrical characteristics..............................................12 +5.2 Nonswitching electrical specifications...............................12 +5.2.1 +Voltage and current operating requirements......13 +5.2.2 +LVD and POR operating requirements...............14 +5.2.3 +Voltage and current operating behaviors............14 +5.2.4 +Power mode transition operating behaviors.......16 +5.2.5 +Power consumption operating behaviors............17 +5.2.6 +EMC radiated emissions operating behaviors....20 +5.2.7 +Designing with radiated emissions in mind.........21 +5.2.8 +Capacitance attributes........................................21 +5.3 Switching specifications.....................................................21 +5.3.1 +Device clock specifications.................................21 +5.3.2 +General switching specifications.........................22 +5.4 Thermal specifications.......................................................23 +5.4.1 +Thermal operating requirements.........................23 +5.4.2 +Thermal attributes...............................................23 +6 Peripheral operating requirements and behaviors....................24 +6.1 Core modules....................................................................24 +6.1.1 +Debug trace timing specifications.......................24 +6.1.2 +JTAG electricals..................................................25 +6.2 System modules................................................................28 +6.3 Clock modules...................................................................28 +6.3.1 +MCG specifications.............................................28 +6.3.2 +Oscillator electrical specifications.......................30 +6.3.3 +32 kHz oscillator electrical characteristics..........33 +6.4 Memories and memory interfaces.....................................33 +6.4.1 +Flash electrical specifications.............................33 +6.4.2 +EzPort switching specifications...........................38 +6.4.3 +Flexbus switching specifications.........................39 +6.5 Security and integrity modules..........................................42 +6.6 Analog...............................................................................42 +6.6.1 +ADC electrical specifications..............................42 +6.6.2 +CMP and 6-bit DAC electrical specifications......50 +6.6.3 +12-bit DAC electrical characteristics...................53 +6.6.4 +Voltage reference electrical specifications..........56 +6.7 Timers................................................................................57 +6.8 Communication interfaces.................................................57 +6.8.1 +Ethernet switching specifications........................57 +6.8.2 +USB electrical specifications...............................59 +6.8.3 +USB DCD electrical specifications......................59 +6.8.4 +USB VREG electrical specifications...................60 +6.8.5 +CAN switching specifications..............................60 +6.8.6 +DSPI switching specifications (limited voltage +range).................................................................61 +6.8.7 +DSPI switching specifications (full voltage +range).................................................................62 +6.8.8 +Inter-Integrated Circuit Interface (I2C) timing.....64 +6.8.9 +UART switching specifications............................65 +6.8.10 +SDHC specifications...........................................65 +6.8.11 +I2S/SAI switching specifications.........................66 +6.9 Human-machine interfaces (HMI)......................................72 +6.9.1 +TSI electrical specifications................................72 +7 Dimensions...............................................................................73 +7.1 Obtaining package dimensions.........................................73 +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +3 + +![Image 1 from page 3](pdf-image://page_3_img_1) + +## Page 4 + +8 Pinout........................................................................................73 +8.1 K60 signal multiplexing and pin assignments....................73 +8.2 K60 pinouts.......................................................................79 +9 Revision history.........................................................................81 +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +4 +Freescale Semiconductor, Inc. + +![Image 1 from page 4](pdf-image://page_4_img_1) + +## Page 5 + +1 +Ordering parts +1.1 +Determining valid orderable parts +Valid orderable part numbers are provided on the web. To determine the orderable part +numbers for this device, go to freescale.com and perform a part number search for the +following device numbers: PK60 and MK60. +2 +Part identification +2.1 +Description +Part numbers for the chip have fields that identify the specific part. You can use the +values of these fields to determine the specific part you have received. +2.2 +Format +Part numbers for this device have the following format: +Q K## A M FFF R T PP CC N +2.3 +Fields +This table lists the possible values for each field in the part number (not all combinations +are valid): +Field +Description +Values +Q +Qualification status +• M = Fully qualified, general market flow +• P = Prequalification +K\#\# +Kinetis family +• K60 +A +Key attribute +• D = Cortex-M4 w/ DSP +• F = Cortex-M4 w/ DSP and FPU +M +Flash memory type +• N = Program flash only +• X = Program flash and FlexMemory +Table continues on the next page... +Ordering parts +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +5 + +![Image 1 from page 5](pdf-image://page_5_img_1) + +## Page 6 + +Field +Description +Values +FFF +Program flash memory size +• 32 = 32 KB +• 64 = 64 KB +• 128 = 128 KB +• 256 = 256 KB +• 512 = 512 KB +• 1M0 = 1 MB +• 2M0 = 2 MB +R +Silicon revision +• Z = Initial +• (Blank) = Main +• A = Revision after main +T +Temperature range (°C) +• V = –40 to 105 +• C = –40 to 85 +PP +Package identifier +• FM = 32 QFN (5 mm x 5 mm) +• FT = 48 QFN (7 mm x 7 mm) +• LF = 48 LQFP (7 mm x 7 mm) +• LH = 64 LQFP (10 mm x 10 mm) +• MP = 64 MAPBGA (5 mm x 5 mm) +• LK = 80 LQFP (12 mm x 12 mm) +• LL = 100 LQFP (14 mm x 14 mm) +• MC = 121 MAPBGA (8 mm x 8 mm) +• LQ = 144 LQFP (20 mm x 20 mm) +• MD = 144 MAPBGA (13 mm x 13 mm) +• MJ = 256 MAPBGA (17 mm x 17 mm) +CC +Maximum CPU frequency (MHz) +• 5 = 50 MHz +• 7 = 72 MHz +• 10 = 100 MHz +• 12 = 120 MHz +• 15 = 150 MHz +N +Packaging type +• R = Tape and reel +• (Blank) = Trays +2.4 +Example +This is an example part number: +MK60DN512ZVMD10 +3 +Terminology and guidelines +3.1 +Definition: Operating requirement +An operating requirement is a specified value or range of values for a technical +characteristic that you must guarantee during operation to avoid incorrect operation and +possibly decreasing the useful life of the chip. +Terminology and guidelines +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +6 +Freescale Semiconductor, Inc. + +![Image 1 from page 6](pdf-image://page_6_img_1) + +## Page 7 + +3.1.1 +Example +This is an example of an operating requirement: +Symbol +Description +Min. +Max. +Unit +VDD +1.0 V core supply +voltage +0.9 +1.1 +V +3.2 +Definition: Operating behavior +An operating behavior is a specified value or range of values for a technical +characteristic that are guaranteed during operation if you meet the operating requirements +and any other specified conditions. +3.2.1 +Example +This is an example of an operating behavior: +Symbol +Description +Min. +Max. +Unit +IWP +Digital I/O weak pullup/ +pulldown current +10 +130 +µA +3.3 +Definition: Attribute +An attribute is a specified value or range of values for a technical characteristic that are +guaranteed, regardless of whether you meet the operating requirements. +3.3.1 +Example +This is an example of an attribute: +Symbol +Description +Min. +Max. +Unit +CIN\_D +Input capacitance: +digital pins +— +7 +pF +Terminology and guidelines +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +7 + +![Image 1 from page 7](pdf-image://page_7_img_1) + +## Page 8 + +3.4 +Definition: Rating +A rating is a minimum or maximum value of a technical characteristic that, if exceeded, +may cause permanent chip failure: +• Operating ratings apply during operation of the chip. +• Handling ratings apply when the chip is not powered. +3.4.1 +Example +This is an example of an operating rating: +Symbol +Description +Min. +Max. +Unit +VDD +1.0 V core supply +voltage +–0.3 +1.2 +V +3.5 +Result of exceeding a rating +40 +30 +20 +10 +0 +Measured characteristic +Operating rating +Failures in time (ppm) +The likelihood of permanent chip failure increases rapidly as +soon as a characteristic begins to exceed one of its operating ratings. +Terminology and guidelines +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +8 +Freescale Semiconductor, Inc. + +![Image 1 from page 8](pdf-image://page_8_img_1) + +## Page 9 + +3.6 +Relationship between ratings and operating requirements +–∞ +- No permanent failure +- Correct operation +Normal operating range +Fatal range +Expected permanent failure +Fatal range +Expected permanent failure +∞ +Operating rating (max.) +Operating requirement (max.) +Operating requirement (min.) +Operating rating (min.) +Operating (power on) +Degraded operating range +Degraded operating range +–∞ +No permanent failure +Handling range +Fatal range +Expected permanent failure +Fatal range +Expected permanent failure +∞ +Handling rating (max.) +Handling rating (min.) +Handling (power off) +- No permanent failure +- Possible decreased life +- Possible incorrect operation +- No permanent failure +- Possible decreased life +- Possible incorrect operation +3.7 +Guidelines for ratings and operating requirements +Follow these guidelines for ratings and operating requirements: +• Never exceed any of the chip’s ratings. +• During normal operation, don’t exceed any of the chip’s operating requirements. +• If you must exceed an operating requirement at times other than during normal +operation (for example, during power sequencing), limit the duration as much as +possible. +3.8 +Definition: Typical value +A typical value is a specified value for a technical characteristic that: +• Lies within the range of values specified by the operating behavior +• Given the typical manufacturing process, is representative of that characteristic +during operation when you meet the typical-value conditions or other specified +conditions +Typical values are provided as design guidelines and are neither tested nor guaranteed. +Terminology and guidelines +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +9 + +![Image 1 from page 9](pdf-image://page_9_img_1) + +## Page 10 + +3.8.1 +Example 1 +This is an example of an operating behavior that includes a typical value: +Symbol +Description +Min. +Typ. +Max. +Unit +IWP +Digital I/O weak +pullup/pulldown +current +10 +70 +130 +µA +3.8.2 +Example 2 +This is an example of a chart that shows typical values for various voltage and +temperature conditions: +0.90 +0.95 +1.00 +1.05 +1.10 +0 +500 +1000 +1500 +2000 +2500 +3000 +3500 +4000 +4500 +5000 +150 °C +105 °C +25 °C +–40 °C +VDD (V) +I +(μA) +DD\_STOP +TJ +3.9 +Typical value conditions +Typical values assume you meet the following conditions (or other conditions as +specified): +Symbol +Description +Value +Unit +TA +Ambient temperature +25 +°C +VDD +3.3 V supply voltage +3.3 +V +Terminology and guidelines +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +10 +Freescale Semiconductor, Inc. + +![Image 1 from page 10](pdf-image://page_10_img_1) + +## Page 11 + +4 +Ratings +4.1 +Thermal handling ratings +Symbol +Description +Min. +Max. +Unit +Notes +TSTG +Storage temperature +–55 +150 +°C +1 +TSDR +Solder temperature, lead-free +— +260 +°C +2 +1. +Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life. +2. +Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic +Solid State Surface Mount Devices. +4.2 +Moisture handling ratings +Symbol +Description +Min. +Max. +Unit +Notes +MSL +Moisture sensitivity level +— +3 +— +1 +1. +Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic +Solid State Surface Mount Devices. +4.3 +ESD handling ratings +Symbol +Description +Min. +Max. +Unit +Notes +VHBM +Electrostatic discharge voltage, human body model +-2000 ++2000 +V +1 +VCDM +Electrostatic discharge voltage, charged-device model +-500 ++500 +V +2 +ILAT +Latch-up current at ambient temperature of 105°C +-100 ++100 +mA +3 +1. +Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body +Model (HBM). +2. +Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for +Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. +3. +Determined according to JEDEC Standard JESD78, IC Latch-Up Test. +4.4 +Voltage and current operating ratings +Ratings +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +11 + +![Image 1 from page 11](pdf-image://page_11_img_1) + +## Page 12 + +Symbol +Description +Min. +Max. +Unit +VDD +Digital supply voltage +–0.3 +3.8 +V +IDD +Digital supply current +— +185 +mA +VDIO +Digital input voltage (except RESET, EXTAL, and XTAL) +–0.3 +5.5 +V +VAIO +Analog1, RESET, EXTAL, and XTAL input voltage +–0.3 +VDD + 0.3 +V +ID +Maximum current single pin limit (applies to all digital pins) +–25 +25 +mA +VDDA +Analog supply voltage +VDD – 0.3 +VDD + 0.3 +V +VUSB\_DP +USB\_DP input voltage +–0.3 +3.63 +V +VUSB\_DM +USB\_DM input voltage +–0.3 +3.63 +V +VREGIN +USB regulator input +–0.3 +6.0 +V +VBAT +RTC battery supply voltage +–0.3 +3.8 +V +1. +Analog pins are defined as pins that do not have an associated general purpose I/O port function. +5 +General +5.1 +AC electrical characteristics +Unless otherwise specified, propagation delays are measured from the 50% to the 50% +point, and rise and fall times are measured at the 20% and 80% points, as shown in the +following figure. +Figure 1. Input signal measurement reference +All digital I/O switching characteristics assume: +1. output pins +• have CL=30pF loads, +• are configured for fast slew rate (PORTx\_PCRn[SRE]=0), and +• are configured for high drive strength (PORTx\_PCRn[DSE]=1) +2. input pins +• have their passive filter disabled (PORTx\_PCRn[PFE]=0) +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +12 +Freescale Semiconductor, Inc. + +![Image 1 from page 12](pdf-image://page_12_img_1) + +![Image 2 from page 12](pdf-image://page_12_img_2) + +## Page 13 + +5.2 +Nonswitching electrical specifications +5.2.1 +Voltage and current operating requirements +Table 1. Voltage and current operating requirements +Symbol +Description +Min. +Max. +Unit +Notes +VDD +Supply voltage +1.71 +3.6 +V +VDDA +Analog supply voltage +1.71 +3.6 +V +VDD – VDDA +VDD-to-VDDA differential voltage +–0.1 +0.1 +V +VSS – VSSA +VSS-to-VSSA differential voltage +–0.1 +0.1 +V +VBAT +RTC battery supply voltage +1.71 +3.6 +V +VIH +Input high voltage +• 2.7 V ≤ VDD ≤ 3.6 V +• 1.7 V ≤ VDD ≤ 2.7 V +0.7 × VDD +0.75 × VDD +— +— +V +V +VIL +Input low voltage +• 2.7 V ≤ VDD ≤ 3.6 V +• 1.7 V ≤ VDD ≤ 2.7 V +— +— +0.35 × VDD +0.3 × VDD +V +V +VHYS +Input hysteresis +0.06 × VDD +— +V +IICDIO +Digital pin negative DC injection current — single pin +• VIN < VSS-0.3V +-5 +— +mA +1 +IICAIO +Analog2, EXTAL, and XTAL pin DC injection current — +single pin +• VIN < VSS-0.3V (Negative current injection) +• VIN > VDD+0.3V (Positive current injection) +-5 +— +— ++5 +mA +3 +IICcont +Contiguous pin DC injection current —regional limit, +includes sum of negative injection currents or sum of +positive injection currents of 16 contiguous pins +• Negative current injection +• Positive current injection +-25 +— +— ++25 +mA +VODPU +Open drain pullup voltage level +VDD +VDD +V +4 +VRAM +VDD voltage required to retain RAM +1.2 +— +V +VRFVBAT +VBAT voltage required to retain the VBAT register file +VPOR\_VBAT +— +V +1. +All 5 V tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode +connection to VDD. If VIN is less than VDIO\_MIN, a current limiting resistor is required. The negative DC injection current +limiting resistor is calculated as R=(VDIO\_MIN-VIN)/|IICDIO|. +2. +Analog pins are defined as pins that do not have an associated general purpose I/O port function. Additionally, EXTAL and +XTAL are analog pins. +3. +All analog pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VAIO\_MIN or greater +than VAIO\_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as +R=(VAIO\_MIN-VIN)/|IICAIO|. The positive injection current limiting resistor is calculated as R=(VIN-VAIO\_MAX)/|IICAIO|. Select the +larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. +4. +Open drain outputs must be pulled to VDD. +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +13 + +![Image 1 from page 13](pdf-image://page_13_img_1) + +## Page 14 + +5.2.2 +LVD and POR operating requirements +Table 2. VDD supply LVD and POR operating requirements +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +VPOR +Falling VDD POR detect voltage +0.8 +1.1 +1.5 +V +VLVDH +Falling low-voltage detect threshold — high +range (LVDV=01) +2.48 +2.56 +2.64 +V +VLVW1H +VLVW2H +VLVW3H +VLVW4H +Low-voltage warning thresholds — high range +• Level 1 falling (LVWV=00) +• Level 2 falling (LVWV=01) +• Level 3 falling (LVWV=10) +• Level 4 falling (LVWV=11) +2.62 +2.72 +2.82 +2.92 +2.70 +2.80 +2.90 +3.00 +2.78 +2.88 +2.98 +3.08 +V +V +V +V +1 +VHYSH +Low-voltage inhibit reset/recover hysteresis — +high range +— +±80 +— +mV +VLVDL +Falling low-voltage detect threshold — low range +(LVDV=00) +1.54 +1.60 +1.66 +V +VLVW1L +VLVW2L +VLVW3L +VLVW4L +Low-voltage warning thresholds — low range +• Level 1 falling (LVWV=00) +• Level 2 falling (LVWV=01) +• Level 3 falling (LVWV=10) +• Level 4 falling (LVWV=11) +1.74 +1.84 +1.94 +2.04 +1.80 +1.90 +2.00 +2.10 +1.86 +1.96 +2.06 +2.16 +V +V +V +V +1 +VHYSL +Low-voltage inhibit reset/recover hysteresis — +low range +— +±60 +— +mV +VBG +Bandgap voltage reference +0.97 +1.00 +1.03 +V +tLPO +Internal low power oscillator period — factory +trimmed +900 +1000 +1100 +μs +1. +Rising thresholds are falling threshold + hysteresis voltage +Table 3. VBAT power operating requirements +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +VPOR\_VBAT Falling VBAT supply POR detect voltage +0.8 +1.1 +1.5 +V +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +14 +Freescale Semiconductor, Inc. + +![Image 1 from page 14](pdf-image://page_14_img_1) + +## Page 15 + +5.2.3 +Voltage and current operating behaviors +Table 4. Voltage and current operating behaviors +Symbol +Description +Min. +Typ.1 +Max. +Unit +Notes +VOH +Output high voltage — high drive strength +• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -9mA +• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -3mA +VDD – 0.5 +VDD – 0.5 +— +— +— +— +V +V +Output high voltage — low drive strength +• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -2mA +• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -0.6mA +VDD – 0.5 +VDD – 0.5 +— +— +— +— +V +V +IOHT +Output high current total for all ports +— +— +100 +mA +VOL +Output low voltage — high drive strength +• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10mA +• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5mA +— +— +— +— +0.5 +0.5 +V +V +2 +Output low voltage — low drive strength +• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 2mA +• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1mA +— +— +— +— +0.5 +0.5 +V +V +IOLT +Output low current total for all ports +— +— +100 +mA +IINA +Input leakage current, analog pins and digital +pins configured as analog inputs +• VSS ≤ VIN ≤ VDD +• All pins except EXTAL32, XTAL32, +EXTAL, XTAL +• EXTAL (PTA18) and XTAL (PTA19) +• EXTAL32, XTAL32 +— +— +— +0.002 +0.004 +0.075 +0.5 +1.5 +10 +μA +μA +μA +3, 4 +IIND +Input leakage current, digital pins +• VSS ≤ VIN ≤ VIL +• All digital pins +• VIN = VDD +• All digital pins except PTD7 +• PTD7 +— +— +— +0.002 +0.002 +0.004 +0.5 +0.5 +1 +μA +μA +μA +4, 5 +IIND +Input leakage current, digital pins +• VIL < VIN < VDD +• VDD = 3.6 V +• VDD = 3.0 V +• VDD = 2.5 V +• VDD = 1.7 V +— +— +— +— +18 +12 +8 +3 +26 +49 +13 +6 +μA +μA +μA +μA +4, 5, 6 +Table continues on the next page... +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +15 + +![Image 1 from page 15](pdf-image://page_15_img_1) + +## Page 16 + +Table 4. Voltage and current operating behaviors (continued) +Symbol +Description +Min. +Typ.1 +Max. +Unit +Notes +IIND +Input leakage current, digital pins +• VDD < VIN < 5.5 V +— +1 +50 +μA +4, 5 +ZIND +Input impedance examples, digital pins +• VDD = 3.6 V +• VDD = 3.0 V +• VDD = 2.5 V +• VDD = 1.7 V +— +— +— +— +— +— +— +— +48 +55 +57 +85 +kΩ +kΩ +kΩ +kΩ +4, 7 +RPU +Internal pullup resistors +20 +35 +50 +kΩ +8 +RPD +Internal pulldown resistors +20 +35 +50 +kΩ +9 +1. +Typical values characterized at 25°C and VDD = 3.6 V unless otherwise noted. +2. +Open drain outputs must be pulled to VDD. +3. +Analog pins are defined as pins that do not have an associated general purpose I/O port function. +4. +Digital pins have an associated GPIO port function and have 5V tolerant inputs, except EXTAL and XTAL. +5. +Internal pull-up/pull-down resistors disabled. +6. +Characterized, not tested in production. +7. +Examples calculated using VIL relation, VDD, and max IIND: ZIND=VIL/IIND. This is the impedance needed to pull a high +signal to a level below VIL due to leakage when VIL < VIN < VDD. These examples assume signal source low = 0 V. +8. +Measured at VDD supply voltage = VDD min and Vinput = VSS +9. +Measured at VDD supply voltage = VDD min and Vinput = VDD ++ +– +Digital input +Source +Z IND +I IND +5.2.4 +Power mode transition operating behaviors +All specifications except tPOR, and VLLSx→RUN recovery times in the following table +assume this clock configuration: +• CPU and system clocks = 100 MHz +• Bus clock = 50 MHz +• FlexBus clock = 50 MHz +• Flash clock = 25 MHz +• MCG mode: FEI +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +16 +Freescale Semiconductor, Inc. + +![Image 1 from page 16](pdf-image://page_16_img_1) + +## Page 17 + +Table 5. Power mode transition operating behaviors +Symbol +Description +Min. +Max. +Unit +Notes +tPOR +After a POR event, amount of time from the point VDD +reaches 1.71 V to execution of the first instruction +across the operating temperature range of the chip. +• VDD slew rate ≥ 5.7 kV/s +• VDD slew rate < 5.7 kV/s +— +— +300 +1.7 V / (VDD +slew rate) +μs +1 +• VLLS1 → RUN +— +130 +μs +• VLLS2 → RUN +— +92 +μs +• VLLS3 → RUN +— +92 +μs +• LLS → RUN +— +5.9 +μs +• VLPS → RUN +— +5.0 +μs +• STOP → RUN +— +5.0 +μs +1. +Normal boot (FTFL\_OPT[LPBOOT]=1) +5.2.5 +Power consumption operating behaviors +Table 6. Power consumption operating behaviors +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +IDDA +Analog supply current +— +— +See note +mA +1 +IDD\_RUN +Run mode current — all peripheral clocks +disabled, code executing from flash +• @ 1.8V +• @ 3.0V +— +— +37 +38 +63 +64 +mA +mA +2 +IDD\_RUN +Run mode current — all peripheral clocks +enabled, code executing from flash +• @ 1.8V +• @ 3.0V +• @ 25°C +• @ 125°C +— +— +— +46 +47 +58 +77 +63 +79 +mA +mA +mA +3, 4 +IDD\_WAIT +Wait mode high frequency current at 3.0 V — all +peripheral clocks disabled +— +20 +— +mA +2 +IDD\_WAIT +Wait mode reduced frequency current at 3.0 V — +all peripheral clocks disabled +— +9 +— +mA +5 +IDD\_VLPR +Very-low-power run mode current at 3.0 V — all +peripheral clocks disabled +— +1.12 +— +mA +6 +Table continues on the next page... +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +17 + +![Image 1 from page 17](pdf-image://page_17_img_1) + +## Page 18 + +Table 6. Power consumption operating behaviors (continued) +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +IDD\_VLPR +Very-low-power run mode current at 3.0 V — all +peripheral clocks enabled +— +1.71 +— +mA +7 +IDD\_VLPW +Very-low-power wait mode current at 3.0 V — all +peripheral clocks disabled +— +0.77 +— +mA +8 +IDD\_STOP +Stop mode current at 3.0 V +• @ –40 to 25°C +• @ 70°C +• @ 105°C +— +— +— +0.74 +2.45 +6.61 +1.41 +11.5 +30 +mA +mA +mA +IDD\_VLPS +Very-low-power stop mode current at 3.0 V +• @ –40 to 25°C +• @ 70°C +• @ 105°C +— +— +— +83 +425 +1280 +435 +2000 +4000 +μA +μA +μA +IDD\_LLS +Low leakage stop mode current at 3.0 V +• @ –40 to 25°C +• @ 70°C +• @ 105°C +— +— +— +4.58 +30.6 +137 +19.9 +105 +500 +μA +μA +μA +9 +IDD\_VLLS3 +Very low-leakage stop mode 3 current at 3.0 V +• @ –40 to 25°C +• @ 70°C +• @ 105°C +— +— +— +3.0 +18.6 +84.9 +23 +43 +230 +μA +μA +μA +9 +IDD\_VLLS2 +Very low-leakage stop mode 2 current at 3.0 V +• @ –40 to 25°C +• @ 70°C +• @ 105°C +— +— +— +2.2 +9.3 +41.4 +5.4 +35 +128 +μA +μA +μA +IDD\_VLLS1 +Very low-leakage stop mode 1 current at 3.0 V +• @ –40 to 25°C +• @ 70°C +• @ 105°C +— +— +— +2.1 +7.6 +33.5 +9 +28 +95.5 +μA +μA +μA +IDD\_VBAT +Average current with RTC and 32kHz disabled at +3.0 V +• @ –40 to 25°C +• @ 70°C +• @ 105°C +— +— +— +0.19 +0.49 +2.2 +0.22 +0.64 +3.2 +μA +μA +μA +Table continues on the next page... +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +18 +Freescale Semiconductor, Inc. + +![Image 1 from page 18](pdf-image://page_18_img_1) + +## Page 19 + +Table 6. Power consumption operating behaviors (continued) +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +IDD\_VBAT +Average current when CPU is not accessing RTC +registers +• @ 1.8V +• @ –40 to 25°C +• @ 70°C +• @ 105°C +• @ 3.0V +• @ –40 to 25°C +• @ 70°C +• @ 105°C +— +— +— +— +— +— +0.57 +0.90 +2.4 +0.67 +1.0 +2.7 +0.67 +1.2 +3.5 +0.94 +1.4 +3.9 +μA +μA +μA +μA +μA +μA +10 +1. +The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See +each module's specification for its supply current. +2. +100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock . MCG configured for FEI mode. +All peripheral clocks disabled. +3. +100MHz core and system clock, 50MHz bus and FlexBus clock, and 25MHz flash clock. MCG configured for FEI mode. All +peripheral clocks enabled. +4. +Max values are measured with CPU executing DSP instructions. +5. +25MHz core and system clock, 25MHz bus clock, and 12.5MHz FlexBus and flash clock. MCG configured for FEI mode. +6. +4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks +disabled. Code executing from flash. +7. +4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks +enabled but peripherals are not in active operation. Code executing from flash. +8. +4 MHz core, system, FlexBus, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks +disabled. +9. +Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA. +10. Includes 32kHz oscillator current and RTC operation. +5.2.5.1 +Diagram: Typical IDD\_RUN operating behavior +The following data was measured under these conditions: +• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at greater +than 50 MHz frequencies. +• USB regulator disabled +• No GPIOs toggled +• Code execution from flash with cache enabled +• For the ALLOFF curve, all peripheral clocks are disabled except FTFL +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +19 + +![Image 1 from page 19](pdf-image://page_19_img_1) + +## Page 20 + +Figure 2. Run mode supply current vs. core frequency +5.2.6 +EMC radiated emissions operating behaviors +Table 7. EMC radiated emissions operating behaviors for 144LQFP and +144MAPBGA +Symbol +Description +Frequency +band (MHz) +144LQFP +144MAPBGA +Unit +Notes +VRE1 +Radiated emissions voltage, band 1 +0.15–50 +23 +12 +dBμV +1, 2 +VRE2 +Radiated emissions voltage, band 2 +50–150 +27 +24 +dBμV +VRE3 +Radiated emissions voltage, band 3 +150–500 +28 +27 +dBμV +VRE4 +Radiated emissions voltage, band 4 +500–1000 +14 +11 +dBμV +VRE\_IEC +IEC level +0.15–1000 +K +K +— +2, 3 +1. +Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150 +kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of +Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband +TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported +emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the +measured orientations in each frequency range. +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +20 +Freescale Semiconductor, Inc. + +![Image 1 from page 20](pdf-image://page_20_img_1) + +![Image 2 from page 20](pdf-image://page_20_img_2) + +## Page 21 + +2. +VDD = 3.3 V, TA = 25 °C, fOSC = 12 MHz (crystal), fSYS = 96 MHz, fBUS = 48 MHz +3. +Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband +TEM Cell Method +5.2.7 +Designing with radiated emissions in mind +To find application notes that provide guidance on designing your system to minimize +interference from radiated emissions: +1. Go to www.freescale.com. +2. Perform a keyword search for “EMC design.” +5.2.8 +Capacitance attributes +Table 8. Capacitance attributes +Symbol +Description +Min. +Max. +Unit +CIN\_A +Input capacitance: analog pins +— +7 +pF +CIN\_D +Input capacitance: digital pins +— +7 +pF +5.3 +Switching specifications +5.3.1 +Device clock specifications +Table 9. Device clock specifications +Symbol +Description +Min. +Max. +Unit +Notes +Normal run mode +fSYS +System and core clock +— +100 +MHz +fSYS\_USB +System and core clock when Full Speed USB in +operation +20 +— +MHz +fENET +System and core clock when ethernet in operation +• 10 Mbps +• 100 Mbps +5 +50 +— +— +MHz +fBUS +Bus clock +— +50 +MHz +FB\_CLK +FlexBus clock +— +50 +MHz +fFLASH +Flash clock +— +25 +MHz +fLPTMR +LPTMR clock +— +25 +MHz +VLPR mode1 +fSYS +System and core clock +— +4 +MHz +Table continues on the next page... +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +21 + +![Image 1 from page 21](pdf-image://page_21_img_1) + +## Page 22 + +Table 9. Device clock specifications (continued) +Symbol +Description +Min. +Max. +Unit +Notes +fBUS +Bus clock +— +4 +MHz +FB\_CLK +FlexBus clock +— +4 +MHz +fFLASH +Flash clock +— +1 +MHz +fERCLK +External reference clock +— +16 +MHz +fLPTMR\_pin +LPTMR clock +— +25 +MHz +fLPTMR\_ERCLK +LPTMR external reference clock +— +16 +MHz +fFlexCAN\_ERCLK +FlexCAN external reference clock +— +8 +MHz +fI2S\_MCLK +I2S master clock +— +12.5 +MHz +fI2S\_BCLK +I2S bit clock +— +4 +MHz +1. +The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any +other module. +5.3.2 +General switching specifications +These general purpose specifications apply to all signals configured for GPIO, UART, +CAN, CMT, IEEE 1588 timer, and I2C signals. +Table 10. General switching specifications +Symbol +Description +Min. +Max. +Unit +Notes +GPIO pin interrupt pulse width (digital glitch filter +disabled) — Synchronous path +1.5 +— +Bus clock +cycles +1, 2 +GPIO pin interrupt pulse width (digital glitch filter +disabled, analog filter enabled) — Asynchronous path +100 +— +ns +3 +GPIO pin interrupt pulse width (digital glitch filter +disabled, analog filter disabled) — Asynchronous path +16 +— +ns +3 +External reset pulse width (digital glitch filter disabled) +100 +— +ns +3 +Mode select (EZP\_CS) hold time after reset +deassertion +2 +— +Bus clock +cycles +Port rise and fall time (high drive strength) +• Slew disabled +• 1.71 ≤ VDD ≤ 2.7V +• 2.7 ≤ VDD ≤ 3.6V +• Slew enabled +• 1.71 ≤ VDD ≤ 2.7V +• 2.7 ≤ VDD ≤ 3.6V +— +— +— +— +12 +6 +36 +24 +ns +ns +ns +ns +4 +Table continues on the next page... +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +22 +Freescale Semiconductor, Inc. + +![Image 1 from page 22](pdf-image://page_22_img_1) + +## Page 23 + +Table 10. General switching specifications (continued) +Symbol +Description +Min. +Max. +Unit +Notes +Port rise and fall time (low drive strength) +• Slew disabled +• 1.71 ≤ VDD ≤ 2.7V +• 2.7 ≤ VDD ≤ 3.6V +• Slew enabled +• 1.71 ≤ VDD ≤ 2.7V +• 2.7 ≤ VDD ≤ 3.6V +— +— +— +— +12 +6 +36 +24 +ns +ns +ns +ns +5 +1. +This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or +may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be +recognized in that case. +2. +The greater synchronous and asynchronous timing must be met. +3. +This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and +VLLSx modes. +4. +75 pF load +5. +15 pF load +5.4 +Thermal specifications +5.4.1 +Thermal operating requirements +Table 11. Thermal operating requirements +Symbol +Description +Min. +Max. +Unit +TJ +Die junction temperature +–40 +125 +°C +TA +Ambient temperature +–40 +105 +°C +5.4.2 +Thermal attributes +Board type +Symbol +Description +144 LQFP +144 +MAPBGA +Unit +Notes +Single-layer +(1s) +RθJA +Thermal +resistance, +junction to +ambient (natural +convection) +45 +48 +°C/W +1 +Table continues on the next page... +General +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +23 + +![Image 1 from page 23](pdf-image://page_23_img_1) + +## Page 24 + +Board type +Symbol +Description +144 LQFP +144 +MAPBGA +Unit +Notes +Four-layer +(2s2p) +RθJA +Thermal +resistance, +junction to +ambient (natural +convection) +36 +29 +°C/W +1 +Single-layer +(1s) +RθJMA +Thermal +resistance, +junction to +ambient (200 ft./ +min. air speed) +36 +38 +°C/W +1 +Four-layer +(2s2p) +RθJMA +Thermal +resistance, +junction to +ambient (200 ft./ +min. air speed) +30 +25 +°C/W +1 +— +RθJB +Thermal +resistance, +junction to +board +24 +16 +°C/W +2 +— +RθJC +Thermal +resistance, +junction to case +9 +9 +°C/W +3 +— +ΨJT +Thermal +characterization +parameter, +junction to +package top +outside center +(natural +convection) +2 +2 +°C/W +4 +1. +Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental +Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method +Environmental Conditions—Forced Convection (Moving Air). +2. +Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental +Conditions—Junction-to-Board. +3. +Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate +temperature used for the case temperature. The value includes the thermal resistance of the interface material +between the top of the package and the cold plate. +4. +Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental +Conditions—Natural Convection (Still Air). +6 +Peripheral operating requirements and behaviors +6.1 +Core modules +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +24 +Freescale Semiconductor, Inc. + +![Image 1 from page 24](pdf-image://page_24_img_1) + +## Page 25 + +6.1.1 +Debug trace timing specifications +Table 12. Debug trace operating behaviors +Symbol +Description +Min. +Max. +Unit +Tcyc +Clock period +Frequency dependent +MHz +Twl +Low pulse width +2 +— +ns +Twh +High pulse width +2 +— +ns +Tr +Clock and data rise time +— +3 +ns +Tf +Clock and data fall time +— +3 +ns +Ts +Data setup +3 +— +ns +Th +Data hold +2 +— +ns +Figure 3. TRACE\_CLKOUT specifications +Th +Ts +Ts +Th +TRACE\_CLKOUT +TRACE\_D[3:0] +Figure 4. Trace data specifications +6.1.2 +JTAG electricals +Table 13. JTAG limited voltage range electricals +Symbol +Description +Min. +Max. +Unit +Operating voltage +2.7 +3.6 +V +J1 +TCLK frequency of operation +• Boundary Scan +• JTAG and CJTAG +• Serial Wire Debug +0 +0 +0 +10 +25 +50 +MHz +J2 +TCLK cycle period +1/J1 +— +ns +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +25 + +![Image 1 from page 25](pdf-image://page_25_img_1) + +![Image 2 from page 25](pdf-image://page_25_img_2) + +## Page 26 + +Table 13. JTAG limited voltage range electricals (continued) +Symbol +Description +Min. +Max. +Unit +J3 +TCLK clock pulse width +• Boundary Scan +• JTAG and CJTAG +• Serial Wire Debug +50 +20 +10 +— +— +— +ns +ns +ns +J4 +TCLK rise and fall times +— +3 +ns +J5 +Boundary scan input data setup time to TCLK rise +20 +— +ns +J6 +Boundary scan input data hold time after TCLK rise +0 +— +ns +J7 +TCLK low to boundary scan output data valid +— +25 +ns +J8 +TCLK low to boundary scan output high-Z +— +25 +ns +J9 +TMS, TDI input data setup time to TCLK rise +8 +— +ns +J10 +TMS, TDI input data hold time after TCLK rise +1 +— +ns +J11 +TCLK low to TDO data valid +— +17 +ns +J12 +TCLK low to TDO high-Z +— +17 +ns +J13 +TRST assert time +100 +— +ns +J14 +TRST setup time (negation) to TCLK high +8 +— +ns +Table 14. JTAG full voltage range electricals +Symbol +Description +Min. +Max. +Unit +Operating voltage +1.71 +3.6 +V +J1 +TCLK frequency of operation +• Boundary Scan +• JTAG and CJTAG +• Serial Wire Debug +0 +0 +0 +10 +20 +40 +MHz +J2 +TCLK cycle period +1/J1 +— +ns +J3 +TCLK clock pulse width +• Boundary Scan +• JTAG and CJTAG +• Serial Wire Debug +50 +25 +12.5 +— +— +— +ns +ns +ns +J4 +TCLK rise and fall times +— +3 +ns +J5 +Boundary scan input data setup time to TCLK rise +20 +— +ns +J6 +Boundary scan input data hold time after TCLK rise +0 +— +ns +J7 +TCLK low to boundary scan output data valid +— +25 +ns +J8 +TCLK low to boundary scan output high-Z +— +25 +ns +J9 +TMS, TDI input data setup time to TCLK rise +8 +— +ns +J10 +TMS, TDI input data hold time after TCLK rise +1.4 +— +ns +J11 +TCLK low to TDO data valid +— +22.1 +ns +J12 +TCLK low to TDO high-Z +— +22.1 +ns +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +26 +Freescale Semiconductor, Inc. + +![Image 1 from page 26](pdf-image://page_26_img_1) + +## Page 27 + +Table 14. JTAG full voltage range electricals (continued) +Symbol +Description +Min. +Max. +Unit +J13 +TRST assert time +100 +— +ns +J14 +TRST setup time (negation) to TCLK high +8 +— +ns +J2 +J3 +J3 +J4 +J4 +TCLK (input) +Figure 5. Test clock input timing +J7 +J8 +J7 +J5 +J6 +Input data valid +Output data valid +Output data valid +TCLK +Data inputs +Data outputs +Data outputs +Data outputs +Figure 6. Boundary scan (JTAG) timing +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +27 + +![Image 1 from page 27](pdf-image://page_27_img_1) + +## Page 28 + +J11 +J12 +J11 +J9 +J10 +Input data valid +Output data valid +Output data valid +TCLK +TDI/TMS +TDO +TDO +TDO +Figure 7. Test Access Port timing +J14 +J13 +TCLK +TRST +Figure 8. TRST timing +6.2 +System modules +There are no specifications necessary for the device's system modules. +6.3 +Clock modules +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +28 +Freescale Semiconductor, Inc. + +![Image 1 from page 28](pdf-image://page_28_img_1) + +## Page 29 + +6.3.1 +MCG specifications +Table 15. MCG specifications +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +fints\_ft +Internal reference frequency (slow clock) — +factory trimmed at nominal VDD and 25 °C +— +32.768 +— +kHz +fints\_t +Internal reference frequency (slow clock) — user +trimmed +31.25 +— +39.0625 +kHz +Δfdco\_res\_t +Resolution of trimmed average DCO output +frequency at fixed voltage and temperature — +using SCTRIM and SCFTRIM +— +± 0.3 +± 0.6 +%fdco +1 +Δfdco\_res\_t +Resolution of trimmed average DCO output +frequency at fixed voltage and temperature — +using SCTRIM only +— +± 0.2 +± 0.5 +%fdco +1 +Δfdco\_t +Total deviation of trimmed average DCO output +frequency over voltage and temperature +— ++0.5/-0.7 +± 3 +%fdco +1, +Δfdco\_t +Total deviation of trimmed average DCO output +frequency over fixed voltage and temperature +range of 0–70°C +— +± 0.3 +± 3 +%fdco +1 +fintf\_ft +Internal reference frequency (fast clock) — +factory trimmed at nominal VDD and 25°C +— +4 +— +MHz +fintf\_t +Internal reference frequency (fast clock) — user +trimmed at nominal VDD and 25 °C +3 +— +5 +MHz +floc\_low +Loss of external clock minimum frequency — +RANGE = 00 +(3/5) x +fints\_t +— +— +kHz +floc\_high +Loss of external clock minimum frequency — +RANGE = 01, 10, or 11 +(16/5) x +fints\_t +— +— +kHz +FLL +ffll\_ref +FLL reference frequency range +31.25 +— +39.0625 +kHz +fdco +DCO output +frequency range +Low range (DRS=00) +640 × ffll\_ref +20 +20.97 +25 +MHz +2, 3 +Mid range (DRS=01) +1280 × ffll\_ref +40 +41.94 +50 +MHz +Mid-high range (DRS=10) +1920 × ffll\_ref +60 +62.91 +75 +MHz +High range (DRS=11) +2560 × ffll\_ref +80 +83.89 +100 +MHz +fdco\_t\_DMX32 DCO output +frequency +Low range (DRS=00) +732 × ffll\_ref +— +23.99 +— +MHz +4, 5 +Mid range (DRS=01) +1464 × ffll\_ref +— +47.97 +— +MHz +Mid-high range (DRS=10) +2197 × ffll\_ref +— +71.99 +— +MHz +High range (DRS=11) +2929 × ffll\_ref +— +95.98 +— +MHz +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +29 + +![Image 1 from page 29](pdf-image://page_29_img_1) + +## Page 30 + +Table 15. MCG specifications (continued) +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +Jcyc\_fll +FLL period jitter +• fDCO = 48 MHz +• fDCO = 98 MHz +— +— +180 +150 +— +— +ps +tfll\_acquire +FLL target frequency acquisition time +— +— +1 +ms +6 +PLL +fvco +VCO operating frequency +48.0 +— +100 +MHz +Ipll +PLL operating current +• PLL @ 96 MHz (fosc\_hi\_1 = 8 MHz, fpll\_ref = +2 MHz, VDIV multiplier = 48) +— +1060 +— +µA +7 +Ipll +PLL operating current +• PLL @ 48 MHz (fosc\_hi\_1 = 8 MHz, fpll\_ref = +2 MHz, VDIV multiplier = 24) +— +600 +— +µA +7 +fpll\_ref +PLL reference frequency range +2.0 +— +4.0 +MHz +Jcyc\_pll +PLL period jitter (RMS) +• fvco = 48 MHz +• fvco = 100 MHz +— +— +120 +50 +— +— +ps +ps +8 +Jacc\_pll +PLL accumulated jitter over 1µs (RMS) +• fvco = 48 MHz +• fvco = 100 MHz +— +— +1350 +600 +— +— +ps +ps +8 +Dlock +Lock entry frequency tolerance +± 1.49 +— +± 2.98 +% +Dunl +Lock exit frequency tolerance +± 4.47 +— +± 5.97 +% +tpll\_lock +Lock detector detection time +— +— +150 × 10-6 ++ 1075(1/ +fpll\_ref) +s +9 +1. +This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock +mode). +2. +These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0. +3. +The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation +(Δfdco\_t) over voltage and temperature should be considered. +4. +These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1. +5. +The resulting clock frequency must not exceed the maximum specified clock frequency of the device. +6. +This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, +DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, +FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. +7. +Excludes any oscillator currents that are also consuming power while PLL is in operation. +8. +This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of +each PCB and results will vary. +9. +This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled +(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes +it is already running. +6.3.2 +Oscillator electrical specifications +This section provides the electrical characteristics of the module. +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +30 +Freescale Semiconductor, Inc. + +![Image 1 from page 30](pdf-image://page_30_img_1) + +## Page 31 + +6.3.2.1 +Oscillator DC electrical specifications +Table 16. Oscillator DC electrical specifications +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +VDD +Supply voltage +1.71 +— +3.6 +V +IDDOSC +Supply current — low-power mode (HGO=0) +• 32 kHz +• 4 MHz +• 8 MHz (RANGE=01) +• 16 MHz +• 24 MHz +• 32 MHz +— +— +— +— +— +— +500 +200 +300 +950 +1.2 +1.5 +— +— +— +— +— +— +nA +μA +μA +μA +mA +mA +1 +IDDOSC +Supply current — high gain mode (HGO=1) +• 32 kHz +• 4 MHz +• 8 MHz (RANGE=01) +• 16 MHz +• 24 MHz +• 32 MHz +— +— +— +— +— +— +25 +400 +500 +2.5 +3 +4 +— +— +— +— +— +— +μA +μA +μA +mA +mA +mA +1 +Cx +EXTAL load capacitance +— +— +— +2, 3 +Cy +XTAL load capacitance +— +— +— +2, 3 +RF +Feedback resistor — low-frequency, low-power +mode (HGO=0) +— +— +— +MΩ +2, 4 +Feedback resistor — low-frequency, high-gain +mode (HGO=1) +— +10 +— +MΩ +Feedback resistor — high-frequency, low-power +mode (HGO=0) +— +— +— +MΩ +Feedback resistor — high-frequency, high-gain +mode (HGO=1) +— +1 +— +MΩ +RS +Series resistor — low-frequency, low-power +mode (HGO=0) +— +— +— +kΩ +Series resistor — low-frequency, high-gain mode +(HGO=1) +— +200 +— +kΩ +Series resistor — high-frequency, low-power +mode (HGO=0) +— +— +— +kΩ +Series resistor — high-frequency, high-gain +mode (HGO=1) +— +0 +— +kΩ +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +31 + +![Image 1 from page 31](pdf-image://page_31_img_1) + +## Page 32 + +Table 16. Oscillator DC electrical specifications (continued) +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +Vpp5 +Peak-to-peak amplitude of oscillation (oscillator +mode) — low-frequency, low-power mode +(HGO=0) +— +0.6 +— +V +Peak-to-peak amplitude of oscillation (oscillator +mode) — low-frequency, high-gain mode +(HGO=1) +— +VDD +— +V +Peak-to-peak amplitude of oscillation (oscillator +mode) — high-frequency, low-power mode +(HGO=0) +— +0.6 +— +V +Peak-to-peak amplitude of oscillation (oscillator +mode) — high-frequency, high-gain mode +(HGO=1) +— +VDD +— +V +1. +VDD=3.3 V, Temperature =25 °C +2. +See crystal or resonator manufacturer's recommendation +3. +Cx,Cy can be provided by using either the integrated capacitors or by using external components. +4. +When low power mode is selected, RF is integrated and must not be attached externally. +5. +The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any +other devices. +6.3.2.2 +Oscillator frequency specifications +Table 17. Oscillator frequency specifications +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +fosc\_lo +Oscillator crystal or resonator frequency — low +frequency mode (MCG\_C2[RANGE]=00) +32 +— +40 +kHz +fosc\_hi\_1 +Oscillator crystal or resonator frequency — high +frequency mode (low range) +(MCG\_C2[RANGE]=01) +3 +— +8 +MHz +fosc\_hi\_2 +Oscillator crystal or resonator frequency — high +frequency mode (high range) +(MCG\_C2[RANGE]=1x) +8 +— +32 +MHz +fec\_extal +Input clock frequency (external clock mode) +— +— +50 +MHz +1, 2 +tdc\_extal +Input clock duty cycle (external clock mode) +40 +50 +60 +% +tcst +Crystal startup time — 32 kHz low-frequency, +low-power mode (HGO=0) +— +750 +— +ms +3, 4 +Crystal startup time — 32 kHz low-frequency, +high-gain mode (HGO=1) +— +250 +— +ms +Crystal startup time — 8 MHz high-frequency +(MCG\_C2[RANGE]=01), low-power mode +(HGO=0) +— +0.6 +— +ms +Crystal startup time — 8 MHz high-frequency +(MCG\_C2[RANGE]=01), high-gain mode +(HGO=1) +— +1 +— +ms +1. +Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL. +2. +When transitioning from FBE to FEI mode, restrict the frequency of the input clock so that, when it is divided by FRDIV, it +remains within the limits of the DCO input clock frequency. +3. +Proper PC board layout procedures must be followed to achieve specifications. +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +32 +Freescale Semiconductor, Inc. + +![Image 1 from page 32](pdf-image://page_32_img_1) + +## Page 33 + +4. +Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG\_S register +being set. +NOTE +The 32 kHz oscillator works in low power mode by default and +cannot be moved into high power/gain mode. +6.3.3 +32 kHz oscillator electrical characteristics +This section describes the module electrical characteristics. +6.3.3.1 +32 kHz oscillator DC electrical specifications +Table 18. 32kHz oscillator DC electrical specifications +Symbol +Description +Min. +Typ. +Max. +Unit +VBAT +Supply voltage +1.71 +— +3.6 +V +RF +Internal feedback resistor +— +100 +— +MΩ +Cpara +Parasitical capacitance of EXTAL32 and XTAL32 +— +5 +7 +pF +Vpp1 +Peak-to-peak amplitude of oscillation +— +0.6 +— +V +1. +When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to +required oscillator components and must not be connected to any other devices. +6.3.3.2 +32 kHz oscillator frequency specifications +Table 19. 32 kHz oscillator frequency specifications +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +fosc\_lo +Oscillator crystal +— +32.768 +— +kHz +tstart +Crystal start-up time +— +1000 +— +ms +1 +fec\_extal32 +Externally provided input clock frequency +— +32.768 +— +kHz +2 +vec\_extal32 +Externally provided input clock amplitude +700 +— +VBAT +mV +2, 3 +1. +Proper PC board layout procedures must be followed to achieve specifications. +2. +This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The +oscillator remains enabled and XTAL32 must be left unconnected. +3. +The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied +clock must be within the range of VSS to VBAT. +6.4 +Memories and memory interfaces +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +33 + +![Image 1 from page 33](pdf-image://page_33_img_1) + +## Page 34 + +6.4.1 +Flash electrical specifications +This section describes the electrical characteristics of the flash memory module. +6.4.1.1 +Flash timing specifications — program and erase +The following specifications represent the amount of time the internal charge pumps are +active and do not include command overhead. +Table 20. NVM program/erase timing specifications +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +thvpgm4 +Longword Program high-voltage time +— +7.5 +18 +μs +thversscr +Sector Erase high-voltage time +— +13 +113 +ms +1 +thversblk256k Erase Block high-voltage time for 256 KB +— +104 +904 +ms +1 +1. +Maximum time based on expectations at cycling end-of-life. +6.4.1.2 +Flash timing specifications — commands +Table 21. Flash command timing specifications +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +trd1blk256k +Read 1s Block execution time +• 256 KB program/data flash +— +— +1.7 +ms +trd1sec2k +Read 1s Section execution time (flash sector) +— +— +60 +μs +1 +tpgmchk +Program Check execution time +— +— +45 +μs +1 +trdrsrc +Read Resource execution time +— +— +30 +μs +1 +tpgm4 +Program Longword execution time +— +65 +145 +μs +tersblk256k +Erase Flash Block execution time +• 256 KB program/data flash +— +122 +985 +ms +2 +tersscr +Erase Flash Sector execution time +— +14 +114 +ms +2 +tpgmsec512 +tpgmsec1k +tpgmsec2k +Program Section execution time +• 512 bytes flash +• 1 KB flash +• 2 KB flash +— +— +— +2.4 +4.7 +9.3 +— +— +— +ms +ms +ms +trd1all +Read 1s All Blocks execution time +— +— +1.8 +ms +trdonce +Read Once execution time +— +— +25 +μs +1 +tpgmonce +Program Once execution time +— +65 +— +μs +tersall +Erase All Blocks execution time +— +250 +2000 +ms +2 +tvfykey +Verify Backdoor Access Key execution time +— +— +30 +μs +1 +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +34 +Freescale Semiconductor, Inc. + +![Image 1 from page 34](pdf-image://page_34_img_1) + +## Page 35 + +Table 21. Flash command timing specifications (continued) +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +tswapx01 +tswapx02 +tswapx04 +tswapx08 +Swap Control execution time +• control code 0x01 +• control code 0x02 +• control code 0x04 +• control code 0x08 +— +— +— +— +200 +70 +70 +— +— +150 +150 +30 +μs +μs +μs +μs +tpgmpart64k +tpgmpart256k +Program Partition for EEPROM execution time +• 64 KB FlexNVM +• 256 KB FlexNVM +— +— +138 +145 +— +— +ms +ms +tsetramff +tsetram32k +tsetram64k +tsetram256k +Set FlexRAM Function execution time: +• Control Code 0xFF +• 32 KB EEPROM backup +• 64 KB EEPROM backup +• 256 KB EEPROM backup +— +— +— +— +70 +0.8 +1.3 +4.5 +— +1.2 +1.9 +5.5 +μs +ms +ms +ms +Byte-write to FlexRAM for EEPROM operation +teewr8bers +Byte-write to erased FlexRAM location execution +time +— +175 +260 +μs +3 +teewr8b32k +teewr8b64k +teewr8b128k +teewr8b256k +Byte-write to FlexRAM execution time: +• 32 KB EEPROM backup +• 64 KB EEPROM backup +• 128 KB EEPROM backup +• 256 KB EEPROM backup +— +— +— +— +385 +475 +650 +1000 +1800 +2000 +2400 +3200 +μs +μs +μs +μs +Word-write to FlexRAM for EEPROM operation +teewr16bers +Word-write to erased FlexRAM location +execution time +— +175 +260 +μs +teewr16b32k +teewr16b64k +teewr16b128k +teewr16b256k +Word-write to FlexRAM execution time: +• 32 KB EEPROM backup +• 64 KB EEPROM backup +• 128 KB EEPROM backup +• 256 KB EEPROM backup +— +— +— +— +385 +475 +650 +1000 +1800 +2000 +2400 +3200 +μs +μs +μs +μs +Longword-write to FlexRAM for EEPROM operation +teewr32bers +Longword-write to erased FlexRAM location +execution time +— +360 +540 +μs +teewr32b32k +teewr32b64k +teewr32b128k +teewr32b256k +Longword-write to FlexRAM execution time: +• 32 KB EEPROM backup +• 64 KB EEPROM backup +• 128 KB EEPROM backup +• 256 KB EEPROM backup +— +— +— +— +630 +810 +1200 +1900 +2050 +2250 +2675 +3500 +μs +μs +μs +μs +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +35 + +![Image 1 from page 35](pdf-image://page_35_img_1) + +## Page 36 + +1. +Assumes 25 MHz flash clock frequency. +2. +Maximum times for erase parameters based on expectations at cycling end-of-life. +3. +For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased. +6.4.1.3 +Flash high voltage current behaviors +Table 22. Flash high voltage current behaviors +Symbol +Description +Min. +Typ. +Max. +Unit +IDD\_PGM +Average current adder during high voltage +flash programming operation +— +2.5 +6.0 +mA +IDD\_ERS +Average current adder during high voltage +flash erase operation +— +1.5 +4.0 +mA +6.4.1.4 +Reliability specifications +Table 23. NVM reliability specifications +Symbol +Description +Min. +Typ.1 +Max. +Unit +Notes +Program Flash +tnvmretp10k +Data retention after up to 10 K cycles +5 +50 +— +years +tnvmretp1k +Data retention after up to 1 K cycles +20 +100 +— +years +nnvmcycp +Cycling endurance +10 K +50 K +— +cycles +2 +Data Flash +tnvmretd10k +Data retention after up to 10 K cycles +5 +50 +— +years +tnvmretd1k +Data retention after up to 1 K cycles +20 +100 +— +years +nnvmcycd +Cycling endurance +10 K +50 K +— +cycles +2 +FlexRAM as EEPROM +tnvmretee100 Data retention up to 100% of write endurance +5 +50 +— +years +tnvmretee10 +Data retention up to 10% of write endurance +20 +100 +— +years +nnvmwree16 +nnvmwree128 +nnvmwree512 +nnvmwree4k +nnvmwree32k +Write endurance +• EEPROM backup to FlexRAM ratio = 16 +• EEPROM backup to FlexRAM ratio = 128 +• EEPROM backup to FlexRAM ratio = 512 +• EEPROM backup to FlexRAM ratio = 4096 +• EEPROM backup to FlexRAM ratio = +32,768 +35 K +315 K +1.27 M +10 M +80 M +175 K +1.6 M +6.4 M +50 M +400 M +— +— +— +— +— +writes +writes +writes +writes +writes +3 +1. +Typical data retention values are based on measured response accelerated at high temperature and derated to a constant +25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering +Bulletin EB619. +2. +Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C. +3. +Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the cycling +endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and +typical values assume all byte-writes to FlexRAM. +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +36 +Freescale Semiconductor, Inc. + +![Image 1 from page 36](pdf-image://page_36_img_1) + +## Page 37 + +6.4.1.5 +Write endurance to FlexRAM for EEPROM +When the FlexNVM partition code is not set to full data flash, the EEPROM data set size +can be set to any of several non-zero values. +The bytes not assigned to data flash via the FlexNVM partition code are used by the flash +memory module to obtain an effective endurance increase for the EEPROM data. The +built-in EEPROM record management system raises the number of program/erase cycles +that can be attained prior to device wear-out by cycling the EEPROM data through a +larger EEPROM NVM storage space. +While different partitions of the FlexNVM are available, the intention is that a single +choice for the FlexNVM partition code and EEPROM data set size is used throughout the +entire lifetime of a given application. The EEPROM endurance equation and graph +shown below assume that only one configuration is ever used. +Writes\_subsystem = +× Write\_efficiency × n +EEPROM – 2 × EEESPLIT × EEESIZE +EEESPLIT × EEESIZE +nvmcycd +where +• Writes\_subsystem — minimum number of writes to each FlexRAM location for +subsystem (each subsystem can have different endurance) +• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; +entered with the Program Partition command +• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program +Partition command +• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program +Partition command +• Write\_efficiency — +• 0.25 for 8-bit writes to FlexRAM +• 0.50 for 16-bit or 32-bit writes to FlexRAM +• nnvmcycd — data flash cycling endurance (the following graph assumes 10,000 +cycles) +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +37 + +![Image 1 from page 37](pdf-image://page_37_img_1) + +## Page 38 + +Figure 9. EEPROM backup writes to FlexRAM +6.4.2 +EzPort switching specifications +Table 24. EzPort switching specifications +Num +Description +Min. +Max. +Unit +Operating voltage +1.71 +3.6 +V +EP1 +EZP\_CK frequency of operation (all commands except +READ) +— +fSYS/2 +MHz +EP1a +EZP\_CK frequency of operation (READ command) +— +fSYS/8 +MHz +EP2 +EZP\_CS negation to next EZP\_CS assertion +2 x tEZP\_CK +— +ns +EP3 +EZP\_CS input valid to EZP\_CK high (setup) +5 +— +ns +EP4 +EZP\_CK high to EZP\_CS input invalid (hold) +5 +— +ns +EP5 +EZP\_D input valid to EZP\_CK high (setup) +2 +— +ns +EP6 +EZP\_CK high to EZP\_D input invalid (hold) +5 +— +ns +EP7 +EZP\_CK low to EZP\_Q output valid +— +16 +ns +EP8 +EZP\_CK low to EZP\_Q output invalid (hold) +0 +— +ns +EP9 +EZP\_CS negation to EZP\_Q tri-state +— +12 +ns +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +38 +Freescale Semiconductor, Inc. + +![Image 1 from page 38](pdf-image://page_38_img_1) + +![Image 2 from page 38](pdf-image://page_38_img_2) + +## Page 39 + +EP2 +EP3 +EP4 +EP5 +EP6 +EP7 +EP8 +EP9 +EZP\_CK +EZP\_CS +EZP\_Q (output) +EZP\_D (input) +Figure 10. EzPort Timing Diagram +6.4.3 +Flexbus switching specifications +All processor bus timings are synchronous; input setup/hold and output delay are given in +respect to the rising edge of a reference clock, FB\_CLK. The FB\_CLK frequency may be +the same as the internal system bus frequency or an integer divider of that frequency. +The following timing numbers indicate when data is latched or driven onto the external +bus, relative to the Flexbus output clock (FB\_CLK). All other timing relationships can be +derived from these values. +Table 25. Flexbus limited voltage range switching specifications +Num +Description +Min. +Max. +Unit +Notes +Operating voltage +2.7 +3.6 +V +Frequency of operation +— +FB\_CLK +MHz +FB1 +Clock period +20 +— +ns +FB2 +Address, data, and control output valid +— +11.5 +ns +1 +FB3 +Address, data, and control output hold +0.5 +— +ns +1 +FB4 +Data and FB\_TA input setup +8.5 +— +ns +2 +FB5 +Data and FB\_TA input hold +0.5 +— +ns +2 +1. +Specification is valid for all FB\_AD[31:0], FB\_BE/BWEn, FB\_CSn, FB\_OE, FB\_R/W,FB\_TBST, FB\_TSIZ[1:0], FB\_ALE, +and FB\_TS. +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +39 + +![Image 1 from page 39](pdf-image://page_39_img_1) + +## Page 40 + +2. +Specification is valid for all FB\_AD[31:0] and FB\_TA. +Table 26. Flexbus full voltage range switching specifications +Num +Description +Min. +Max. +Unit +Notes +Operating voltage +1.71 +3.6 +V +Frequency of operation +— +FB\_CLK +MHz +FB1 +Clock period +1/FB\_CLK +— +ns +FB2 +Address, data, and control output valid +— +13.5 +ns +1 +FB3 +Address, data, and control output hold +0 +— +ns +1 +FB4 +Data and FB\_TA input setup +13.7 +— +ns +2 +FB5 +Data and FB\_TA input hold +0.5 +— +ns +2 +1. +Specification is valid for all FB\_AD[31:0], FB\_BE/BWEn, FB\_CSn, FB\_OE, FB\_R/W,FB\_TBST, FB\_TSIZ[1:0], FB\_ALE, +and FB\_TS. +2. +Specification is valid for all FB\_AD[31:0] and FB\_TA. +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +40 +Freescale Semiconductor, Inc. + +![Image 1 from page 40](pdf-image://page_40_img_1) + +## Page 41 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB1 +FB3 +FB5 +FB4 +FB4 +FB5 +FB2 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BEn +FB\_TA +FB\_TSIZ[1:0] +Figure 11. FlexBus read timing diagram +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +41 + +![Image 1 from page 41](pdf-image://page_41_img_1) + +## Page 42 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB1 +FB3 +FB4 +FB5 +FB2 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BEn +FB\_TA +FB\_TSIZ[1:0] +Figure 12. FlexBus write timing diagram +6.5 +Security and integrity modules +There are no specifications necessary for the device's security and integrity modules. +6.6 +Analog +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +42 +Freescale Semiconductor, Inc. + +![Image 1 from page 42](pdf-image://page_42_img_1) + +## Page 43 + +6.6.1 +ADC electrical specifications +The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the +differential pins ADCx\_DP0, ADCx\_DM0, ADCx\_DP1, ADCx\_DM1, ADCx\_DP3, and +ADCx\_DM3. +The ADCx\_DP2 and ADCx\_DM2 ADC inputs are connected to the PGA outputs and are +not direct device pins. Accuracy specifications for these pins are defined in Table 29 and +Table 30. +All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy +specifications. +6.6.1.1 +16-bit ADC operating conditions +Table 27. 16-bit ADC operating conditions +Symbol +Description +Conditions +Min. +Typ.1 +Max. +Unit +Notes +VDDA +Supply voltage +Absolute +1.71 +— +3.6 +V +ΔVDDA +Supply voltage +Delta to VDD (VDD – VDDA) +-100 +0 ++100 +mV +2 +ΔVSSA +Ground voltage +Delta to VSS (VSS – VSSA) +-100 +0 ++100 +mV +2 +VREFH +ADC reference +voltage high +1.13 +VDDA +VDDA +V +VREFL +ADC reference +voltage low +VSSA +VSSA +VSSA +V +VADIN +Input voltage +• 16-bit differential mode +• All other modes +VREFL +VREFL +— +— +31/32 \* +VREFH +VREFH +V +CADIN +Input capacitance +• 16-bit mode +• 8-bit / 10-bit / 12-bit +modes +— +— +8 +4 +10 +5 +pF +RADIN +Input resistance +— +2 +5 +kΩ +RAS +Analog source +resistance +13-bit / 12-bit modes +fADCK < 4 MHz +— +— +5 +kΩ +3 +fADCK +ADC conversion +clock frequency +≤ 13-bit mode +1.0 +— +18.0 +MHz +4 +fADCK +ADC conversion +clock frequency +16-bit mode +2.0 +— +12.0 +MHz +4 +Crate +ADC conversion +rate +≤ 13-bit modes +No ADC hardware averaging +Continuous conversions +enabled, subsequent +conversion time +20.000 +— +818.330 +Ksps +5 +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +43 + +![Image 1 from page 43](pdf-image://page_43_img_1) + +## Page 44 + +Table 27. 16-bit ADC operating conditions (continued) +Symbol +Description +Conditions +Min. +Typ.1 +Max. +Unit +Notes +Crate +ADC conversion +rate +16-bit mode +No ADC hardware averaging +Continuous conversions +enabled, subsequent +conversion time +37.037 +— +461.467 +Ksps +5 +1. +Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for +reference only, and are not tested in production. +2. +DC potential difference. +3. +This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as +possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The RAS/CAS +time constant should be kept to < 1 ns. +4. +To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear. +5. +For guidelines and examples of conversion rate calculation, download the ADC calculator tool. +RAS +VAS +CAS +ZAS +VADIN +ZADIN +RADIN +RADIN +RADIN +RADIN +CADIN +Pad +leakage +due to +input +protection +INPUT PIN +INPUT PIN +INPUT PIN +INPUT PIN +SIMPLIFIED +INPUT PIN EQUIVALENT +CIRCUIT +SIMPLIFIED +CHANNEL SELECT +CIRCUIT +ADC SAR +ENGINE +Figure 13. ADC input impedance equivalency diagram +6.6.1.2 +16-bit ADC electrical characteristics +Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) +Symbol +Description +Conditions1. +Min. +Typ.2 +Max. +Unit +Notes +IDDA\_ADC +Supply current +0.215 +— +1.7 +mA +3 +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +44 +Freescale Semiconductor, Inc. + +![Image 1 from page 44](pdf-image://page_44_img_1) + +## Page 45 + +Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) +Symbol +Description +Conditions1. +Min. +Typ.2 +Max. +Unit +Notes +fADACK +ADC +asynchronous +clock source +• ADLPC = 1, ADHSC = 0 +• ADLPC = 1, ADHSC = 1 +• ADLPC = 0, ADHSC = 0 +• ADLPC = 0, ADHSC = 1 +1.2 +2.4 +3.0 +4.4 +2.4 +4.0 +5.2 +6.2 +3.9 +6.1 +7.3 +9.5 +MHz +MHz +MHz +MHz +tADACK = 1/ +fADACK +Sample Time +See Reference Manual chapter for sample times +TUE +Total unadjusted +error +• 12-bit modes +• <12-bit modes +— +— +±4 +±1.4 +±6.8 +±2.1 +LSB4 +5 +DNL +Differential non- +linearity +• 12-bit modes +• <12-bit modes +— +— +±0.7 +±0.2 +-1.1 to +1.9 +-0.3 to 0.5 +LSB4 +5 +INL +Integral non- +linearity +• 12-bit modes +• <12-bit modes +— +— +±1.0 +±0.5 +-2.7 to +1.9 +-0.7 to +0.5 +LSB4 +5 +EFS +Full-scale error +• 12-bit modes +• <12-bit modes +— +— +-4 +-1.4 +-5.4 +-1.8 +LSB4 +VADIN = +VDDA +5 +EQ +Quantization +error +• 16-bit modes +• ≤13-bit modes +— +— +-1 to 0 +— +— +±0.5 +LSB4 +ENOB +Effective number +of bits +16-bit differential mode +• Avg = 32 +• Avg = 4 +16-bit single-ended mode +• Avg = 32 +• Avg = 4 +12.8 +11.9 +12.2 +11.4 +14.5 +13.8 +13.9 +13.1 +— +— +— +— +bits +bits +bits +bits +6 +SINAD +Signal-to-noise +plus distortion +See ENOB +6.02 × ENOB + 1.76 +dB +THD +Total harmonic +distortion +16-bit differential mode +• Avg = 32 +16-bit single-ended mode +• Avg = 32 +— +— +–94 +-85 +— +— +dB +dB +7 +SFDR +Spurious free +dynamic range +16-bit differential mode +• Avg = 32 +16-bit single-ended mode +• Avg = 32 +82 +78 +95 +90 +— +— +dB +dB +7 +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +45 + +![Image 1 from page 45](pdf-image://page_45_img_1) + +## Page 46 + +Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued) +Symbol +Description +Conditions1. +Min. +Typ.2 +Max. +Unit +Notes +EIL +Input leakage +error +IIn × RAS +mV +IIn = +leakage +current +(refer to +the MCU's +voltage +and current +operating +ratings) +Temp sensor +slope +Across the full temperature +range of the device +1.55 +1.62 +1.69 +mV/°C +VTEMP25 +Temp sensor +voltage +25 °C +706 +716 +726 +mV +1. +All accuracy numbers assume the ADC is calibrated with VREFH = VDDA +2. +Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for +reference only and are not tested in production. +3. +The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC\_CFG1[ADLPC] (low +power). For lowest power operation, ADC\_CFG1[ADLPC] must be set, the ADC\_CFG2[ADHSC] bit must be clear with 1 +MHz ADC conversion clock speed. +4. +1 LSB = (VREFH - VREFL)/2N +5. +ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11) +6. +Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz. +7. +Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz. +Figure 14. Typical ENOB vs. ADC\_CLK for 16-bit differential mode +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +46 +Freescale Semiconductor, Inc. + +![Image 1 from page 46](pdf-image://page_46_img_1) + +![Image 2 from page 46](pdf-image://page_46_img_2) + +## Page 47 + +Figure 15. Typical ENOB vs. ADC\_CLK for 16-bit single-ended mode +6.6.1.3 +16-bit ADC with PGA operating conditions +Table 29. 16-bit ADC with PGA operating conditions +Symbol +Description +Conditions +Min. +Typ.1 +Max. +Unit +Notes +VDDA +Supply voltage +Absolute +1.71 +— +3.6 +V +VREFPGA +PGA ref voltage +VREF\_OU +T +VREF\_OU +T +VREF\_OU +T +V +2, 3 +VADIN +Input voltage +VSSA +— +VDDA +V +VCM +Input Common +Mode range +VSSA +— +VDDA +V +RPGAD +Differential input +impedance +Gain = 1, 2, 4, 8 +Gain = 16, 32 +Gain = 64 +— +— +— +128 +64 +32 +— +— +— +kΩ +IN+ to IN-4 +RAS +Analog source +resistance +— +100 +— +Ω +5 +TS +ADC sampling +time +1.25 +— +— +µs +6 +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +47 + +![Image 1 from page 47](pdf-image://page_47_img_1) + +![Image 2 from page 47](pdf-image://page_47_img_2) + +## Page 48 + +Table 29. 16-bit ADC with PGA operating conditions (continued) +Symbol +Description +Conditions +Min. +Typ.1 +Max. +Unit +Notes +Crate +ADC conversion +rate +≤ 13 bit modes +No ADC hardware +averaging +Continuous conversions +enabled +Peripheral clock = 50 +MHz +18.484 +— +450 +Ksps +7 +16 bit modes +No ADC hardware +averaging +Continuous conversions +enabled +Peripheral clock = 50 +MHz +37.037 +— +250 +Ksps +8 +1. +Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 6 MHz unless otherwise stated. Typical values are for +reference only and are not tested in production. +2. +ADC must be configured to use the internal voltage reference (VREF\_OUT) +3. +PGA reference is internally connected to the VREF\_OUT pin. If the user wishes to drive VREF\_OUT with a voltage other +than the output of the VREF module, the VREF module must be disabled. +4. +For single ended configurations the input impedance of the driven input is RPGAD/2 +5. +The analog source resistance (RAS), external to MCU, should be kept as minimum as possible. Increased RAS causes drop +in PGA gain without affecting other performances. This is not dependent on ADC clock frequency. +6. +The minimum sampling time is dependent on input signal frequency and ADC mode of operation. A minimum of 1.25µs +time should be allowed for Fin=4 kHz at 16-bit differential mode. Recommended ADC setting is: ADLSMP=1, ADLSTS=2 at +8 MHz ADC clock. +7. +ADC clock = 18 MHz, ADLSMP = 1, ADLST = 00, ADHSC = 1 +8. +ADC clock = 12 MHz, ADLSMP = 1, ADLST = 01, ADHSC = 1 +6.6.1.4 +16-bit ADC with PGA characteristics with Chop enabled +(ADC\_PGA[PGACHPb] =0) +Table 30. 16-bit ADC with PGA characteristics +Symbol +Description +Conditions +Min. +Typ.1 +Max. +Unit +Notes +IDDA\_PGA +Supply current +Low power +(ADC\_PGA[PGALPb]=0) +— +420 +644 +μA +2 +IDC\_PGA +Input DC current +A +3 +Gain =1, VREFPGA=1.2V, +VCM=0.5V +— +1.54 +— +μA +Gain =64, VREFPGA=1.2V, +VCM=0.1V +— +0.57 +— +μA +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +48 +Freescale Semiconductor, Inc. + +![Image 1 from page 48](pdf-image://page_48_img_1) + +## Page 49 + +Table 30. 16-bit ADC with PGA characteristics (continued) +Symbol +Description +Conditions +Min. +Typ.1 +Max. +Unit +Notes +G +Gain4 +• PGAG=0 +• PGAG=1 +• PGAG=2 +• PGAG=3 +• PGAG=4 +• PGAG=5 +• PGAG=6 +0.95 +1.9 +3.8 +7.6 +15.2 +30.0 +58.8 +1 +2 +4 +8 +16 +31.6 +63.3 +1.05 +2.1 +4.2 +8.4 +16.6 +33.2 +67.8 +RAS < 100Ω +BW +Input signal +bandwidth +• 16-bit modes +• < 16-bit modes +— +— +— +— +4 +40 +kHz +kHz +PSRR +Power supply +rejection ratio +Gain=1 +— +-84 +— +dB +VDDA= 3V +±100mV, +fVDDA= 50Hz, +60Hz +CMRR +Common mode +rejection ratio +• Gain=1 +• Gain=64 +— +— +-84 +-85 +— +— +dB +dB +VCM= +500mVpp, +fVCM= 50Hz, +100Hz +VOFS +Input offset +voltage +— +0.2 +— +mV +Output offset = +VOFS\*(Gain+1) +TGSW +Gain switching +settling time +— +— +10 +µs +5 +dG/dT +Gain drift over full +temperature range +• Gain=1 +• Gain=64 +— +— +6 +31 +10 +42 +ppm/°C +ppm/°C +dG/dVDDA +Gain drift over +supply voltage +• Gain=1 +• Gain=64 +— +— +0.07 +0.14 +0.21 +0.31 +%/V +%/V +VDDA from 1.71 +to 3.6V +EIL +Input leakage +error +All modes +IIn × RAS +mV +IIn = leakage +current +(refer to the +MCU's voltage +and current +operating +ratings) +VPP,DIFF +Maximum +differential input +signal swing +where VX = VREFPGA × 0.583 +V +6 +SNR +Signal-to-noise +ratio +• Gain=1 +• Gain=64 +80 +52 +90 +66 +— +— +dB +dB +16-bit +differential +mode, +Average=32 +THD +Total harmonic +distortion +• Gain=1 +• Gain=64 +85 +49 +100 +95 +— +— +dB +dB +16-bit +differential +mode, +Average=32, +fin=100Hz +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +49 + +![Image 1 from page 49](pdf-image://page_49_img_1) + +## Page 50 + +Table 30. 16-bit ADC with PGA characteristics (continued) +Symbol +Description +Conditions +Min. +Typ.1 +Max. +Unit +Notes +SFDR +Spurious free +dynamic range +• Gain=1 +• Gain=64 +85 +53 +105 +88 +— +— +dB +dB +16-bit +differential +mode, +Average=32, +fin=100Hz +ENOB +Effective number +of bits +• Gain=1, Average=4 +• Gain=1, Average=8 +• Gain=64, Average=4 +• Gain=64, Average=8 +• Gain=1, Average=32 +• Gain=2, Average=32 +• Gain=4, Average=32 +• Gain=8, Average=32 +• Gain=16, Average=32 +• Gain=32, Average=32 +• Gain=64, Average=32 +11.6 +8.0 +7.2 +6.3 +12.8 +11.0 +7.9 +7.3 +6.8 +6.8 +7.5 +13.4 +13.6 +9.6 +9.6 +14.5 +14.3 +13.8 +13.1 +12.5 +11.5 +10.6 +— +— +— +— +— +— +— +— +— +— +— +bits +bits +bits +bits +bits +bits +bits +bits +bits +bits +bits +16-bit +differential +mode,fin=100Hz +SINAD +Signal-to-noise +plus distortion +ratio +See ENOB +6.02 × ENOB + 1.76 +dB +1. +Typical values assume VDDA =3.0V, Temp=25°C, fADCK=6MHz unless otherwise stated. +2. +This current is a PGA module adder, in addition to ADC conversion currents. +3. +Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong +function of input common mode voltage (VCM) and the PGA gain. +4. +Gain = 2PGAG +5. +After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored. +6. +Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the +PGA reference voltage and gain setting. +6.6.2 +CMP and 6-bit DAC electrical specifications +Table 31. Comparator and 6-bit DAC electrical specifications +Symbol +Description +Min. +Typ. +Max. +Unit +VDD +Supply voltage +1.71 +— +3.6 +V +IDDHS +Supply current, High-speed mode (EN=1, PMODE=1) +— +— +200 +μA +IDDLS +Supply current, low-speed mode (EN=1, PMODE=0) +— +— +20 +μA +VAIN +Analog input voltage +VSS – 0.3 +— +VDD +V +VAIO +Analog input offset voltage +— +— +20 +mV +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +50 +Freescale Semiconductor, Inc. + +![Image 1 from page 50](pdf-image://page_50_img_1) + +## Page 51 + +Table 31. Comparator and 6-bit DAC electrical specifications (continued) +Symbol +Description +Min. +Typ. +Max. +Unit +VH +Analog comparator hysteresis1 +• CR0[HYSTCTR] = 00 +• CR0[HYSTCTR] = 01 +• CR0[HYSTCTR] = 10 +• CR0[HYSTCTR] = 11 +— +— +— +— +5 +10 +20 +30 +— +— +— +— +mV +mV +mV +mV +VCMPOh +Output high +VDD – 0.5 +— +— +V +VCMPOl +Output low +— +— +0.5 +V +tDHS +Propagation delay, high-speed mode (EN=1, +PMODE=1) +20 +50 +200 +ns +tDLS +Propagation delay, low-speed mode (EN=1, +PMODE=0) +80 +250 +600 +ns +Analog comparator initialization delay2 +— +— +40 +μs +IDAC6b +6-bit DAC current adder (enabled) +— +7 +— +μA +INL +6-bit DAC integral non-linearity +–0.5 +— +0.5 +LSB3 +DNL +6-bit DAC differential non-linearity +–0.3 +— +0.3 +LSB +1. +Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6 V. +2. +Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, +VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. +3. +1 LSB = Vreference/64 +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +51 + +![Image 1 from page 51](pdf-image://page_51_img_1) + +## Page 52 + +0.04 +0.05 +0.06 +0.07 +0.08 +P Hystereris (V) +00 +01 +10 +HYSTCTR +Setting +0 +0.01 +0.02 +0.03 +0.1 +0.4 +0.7 +1 +1.3 +1.6 +1.9 +2.2 +2.5 +2.8 +3.1 +CM +10 +11 +Vin level (V) +Figure 16. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=0) +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +52 +Freescale Semiconductor, Inc. + +![Image 1 from page 52](pdf-image://page_52_img_1) + +## Page 53 + +0 08 +0.1 +0.12 +0.14 +0.16 +0.18 +P Hystereris (V) +00 +01 +10 +HYSTCTR +Setting +0 +0.02 +0.04 +0.06 +0.08 +0.1 +0.4 +0.7 +1 +1.3 +1.6 +1.9 +2.2 +2.5 +2.8 +3.1 +CMP +10 +11 +Vin level (V) +Figure 17. Typical hysteresis vs. Vin level (VDD=3.3V, PMODE=1) +6.6.3 +12-bit DAC electrical characteristics +6.6.3.1 +12-bit DAC operating requirements +Table 32. 12-bit DAC operating requirements +Symbol +Desciption +Min. +Max. +Unit +Notes +VDDA +Supply voltage +1.71 +3.6 +V +VDACR +Reference voltage +1.13 +3.6 +V +1 +TA +Temperature +Operating temperature +range of the device +°C +CL +Output load capacitance +— +100 +pF +2 +IL +Output load current +— +1 +mA +1. +The DAC reference can be selected to be VDDA or the voltage output of the VREF module (VREF\_OUT) +2. +A small load capacitance (47 pF) can improve the bandwidth performance of the DAC +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +53 + +![Image 1 from page 53](pdf-image://page_53_img_1) + +## Page 54 + +6.6.3.2 +12-bit DAC operating behaviors +Table 33. 12-bit DAC operating behaviors +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +IDDA\_DACL +P +Supply current — low-power mode +— +— +330 +μA +IDDA\_DACH +P +Supply current — high-speed mode +— +— +1200 +μA +tDACLP +Full-scale settling time (0x080 to 0xF7F) — +low-power mode +— +100 +200 +μs +1 +tDACHP +Full-scale settling time (0x080 to 0xF7F) — +high-power mode +— +15 +30 +μs +1 +tCCDACLP +Code-to-code settling time (0xBF8 to 0xC08) +— low-power mode and high-speed mode +— +0.7 +1 +μs +1 +Vdacoutl +DAC output voltage range low — high-speed +mode, no load, DAC set to 0x000 +— +— +100 +mV +Vdacouth +DAC output voltage range high — high- +speed mode, no load, DAC set to 0xFFF +VDACR +−100 +— +VDACR +mV +INL +Integral non-linearity error — high speed +mode +— +— +±8 +LSB +2 +DNL +Differential non-linearity error — VDACR > 2 +V +— +— +±1 +LSB +3 +DNL +Differential non-linearity error — VDACR = +VREF\_OUT +— +— +±1 +LSB +4 +VOFFSET +Offset error +— +±0.4 +±0.8 +%FSR +5 +EG +Gain error +— +±0.1 +±0.6 +%FSR +5 +PSRR +Power supply rejection ratio, VDDA > = 2.4 V +60 +— +90 +dB +TCO +Temperature coefficient offset voltage +— +3.7 +— +μV/C +6 +TGE +Temperature coefficient gain error +— +0.000421 +— +%FSR/C +Rop +Output resistance load = 3 kΩ +— +— +250 +Ω +SR +Slew rate -80h→ F7Fh→ 80h +• High power (SPHP) +• Low power (SPLP) +1.2 +0.05 +1.7 +0.12 +— +— +V/μs +CT +Channel to channel cross talk +— +— +-80 +dB +BW +3dB bandwidth +• High power (SPHP) +• Low power (SPLP) +550 +40 +— +— +— +— +kHz +1. +Settling within ±1 LSB +2. +The INL is measured for 0+100mV to VDACR−100 mV +3. +The DNL is measured for 0+100 mV to VDACR−100 mV +4. +The DNL is measured for 0+100mV to VDACR−100 mV with VDDA > 2.4V +5. +Calculated by a best fit curve from VSS+100 mV to VDACR−100 mV +6. +VDDA = 3.0V, reference select set for VDDA (DACx\_CO:DACRFS = 1), high power mode(DACx\_C0:LPEN = 0), DAC set +to 0x800, Temp range from -40C to 105C +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +54 +Freescale Semiconductor, Inc. + +![Image 1 from page 54](pdf-image://page_54_img_1) + +## Page 55 + +Figure 18. Typical INL error vs. digital code +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +55 + +![Image 1 from page 55](pdf-image://page_55_img_1) + +![Image 2 from page 55](pdf-image://page_55_img_2) + +## Page 56 + +Figure 19. Offset at half scale vs. temperature +6.6.4 +Voltage reference electrical specifications +Table 34. VREF full-range operating requirements +Symbol +Description +Min. +Max. +Unit +Notes +VDDA +Supply voltage +1.71 +3.6 +V +TA +Temperature +Operating temperature +range of the device +°C +CL +Output load capacitance +100 +nF +1, 2 +1. +CL must be connected to VREF\_OUT if the VREF\_OUT functionality is being used for either an internal or external +reference. +2. +The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range of +the device. +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +56 +Freescale Semiconductor, Inc. + +![Image 1 from page 56](pdf-image://page_56_img_1) + +![Image 2 from page 56](pdf-image://page_56_img_2) + +## Page 57 + +Table 35. VREF full-range operating behaviors +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +Vout +Voltage reference output with factory trim at +nominal VDDA and temperature=25C +1.1915 +1.195 +1.1977 +V +Vout +Voltage reference output — factory trim +1.1584 +— +1.2376 +V +Vout +Voltage reference output — user trim +1.193 +— +1.197 +V +Vstep +Voltage reference trim step +— +0.5 +— +mV +Vtdrift +Temperature drift (Vmax -Vmin across the full +temperature range) +— +— +80 +mV +Ibg +Bandgap only current +— +— +80 +µA +1 +Ilp +Low-power buffer current +— +— +360 +uA +1 +Ihp +High-power buffer current +— +— +1 +mA +1 +ΔVLOAD +Load regulation +• current = ± 1.0 mA +— +200 +— +µV +1, 2 +Tstup +Buffer startup time +— +— +100 +µs +Vvdrift +Voltage drift (Vmax -Vmin across the full voltage +range) +— +2 +— +mV +1 +1. +See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register. +2. +Load regulation voltage is the difference between the VREF\_OUT voltage with no load vs. voltage with defined load +Table 36. VREF limited-range operating requirements +Symbol +Description +Min. +Max. +Unit +Notes +TA +Temperature +0 +50 +°C +Table 37. VREF limited-range operating behaviors +Symbol +Description +Min. +Max. +Unit +Notes +Vout +Voltage reference output with factory trim +1.173 +1.225 +V +6.7 +Timers +See General switching specifications. +6.8 +Communication interfaces +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +57 + +![Image 1 from page 57](pdf-image://page_57_img_1) + +## Page 58 + +6.8.1 +Ethernet switching specifications +The following timing specs are defined at the chip I/O pin and must be translated +appropriately to arrive at timing specs/constraints for the physical interface. +6.8.1.1 +MII signal switching specifications +The following timing specs meet the requirements for MII style interfaces for a range of +transceiver devices. +Table 38. MII signal switching specifications +Symbol +Description +Min. +Max. +Unit +— +RXCLK frequency +— +25 +MHz +MII1 +RXCLK pulse width high +35% +65% +RXCLK +period +MII2 +RXCLK pulse width low +35% +65% +RXCLK +period +MII3 +RXD[3:0], RXDV, RXER to RXCLK setup +5 +— +ns +MII4 +RXCLK to RXD[3:0], RXDV, RXER hold +5 +— +ns +— +TXCLK frequency +— +25 +MHz +MII5 +TXCLK pulse width high +35% +65% +TXCLK +period +MII6 +TXCLK pulse width low +35% +65% +TXCLK +period +MII7 +TXCLK to TXD[3:0], TXEN, TXER invalid +2 +— +ns +MII8 +TXCLK to TXD[3:0], TXEN, TXER valid +— +25 +ns +MII7 +MII8 +Valid data +Valid data +Valid data +MII6 +MII5 +TXCLK (input) +TXD[n:0] +TXEN +TXER +Figure 20. MII transmit signal timing diagram +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +58 +Freescale Semiconductor, Inc. + +![Image 1 from page 58](pdf-image://page_58_img_1) + +## Page 59 + +MII2 +MII1 +MII4 +MII3 +Valid data +Valid data +Valid data +RXCLK (input) +RXD[n:0] +RXDV +RXER +Figure 21. MII receive signal timing diagram +6.8.1.2 +RMII signal switching specifications +The following timing specs meet the requirements for RMII style interfaces for a range of +transceiver devices. +Table 39. RMII signal switching specifications +Num +Description +Min. +Max. +Unit +— +EXTAL frequency (RMII input clock RMII\_CLK) +— +50 +MHz +RMII1 +RMII\_CLK pulse width high +35% +65% +RMII\_CLK +period +RMII2 +RMII\_CLK pulse width low +35% +65% +RMII\_CLK +period +RMII3 +RXD[1:0], CRS\_DV, RXER to RMII\_CLK setup +4 +— +ns +RMII4 +RMII\_CLK to RXD[1:0], CRS\_DV, RXER hold +2 +— +ns +RMII7 +RMII\_CLK to TXD[1:0], TXEN invalid +4 +— +ns +RMII8 +RMII\_CLK to TXD[1:0], TXEN valid +— +15 +ns +6.8.2 +USB electrical specifications +The USB electricals for the USB On-the-Go module conform to the standards +documented by the Universal Serial Bus Implementers Forum. For the most up-to-date +standards, visit usb.org. +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +59 + +![Image 1 from page 59](pdf-image://page_59_img_1) + +## Page 60 + +6.8.3 +USB DCD electrical specifications +Table 40. USB DCD electrical specifications +Symbol +Description +Min. +Typ. +Max. +Unit +VDP\_SRC +USB\_DP source voltage (up to 250 μA) +0.5 +— +0.7 +V +VLGC +Threshold voltage for logic high +0.8 +— +2.0 +V +IDP\_SRC +USB\_DP source current +7 +10 +13 +μA +IDM\_SINK +USB\_DM sink current +50 +100 +150 +μA +RDM\_DWN +D- pulldown resistance for data pin contact detect +14.25 +— +24.8 +kΩ +VDAT\_REF +Data detect voltage +0.25 +0.33 +0.4 +V +6.8.4 +USB VREG electrical specifications +Table 41. USB VREG electrical specifications +Symbol +Description +Min. +Typ.1 +Max. +Unit +Notes +VREGIN +Input supply voltage +2.7 +— +5.5 +V +IDDon +Quiescent current — Run mode, load current +equal zero, input supply (VREGIN) > 3.6 V +— +120 +186 +μA +IDDstby +Quiescent current — Standby mode, load current +equal zero +— +1.1 +10 +μA +IDDoff +Quiescent current — Shutdown mode +• VREGIN = 5.0 V and temperature=25 °C +• Across operating voltage and temperature +— +— +650 +— +— +4 +nA +μA +ILOADrun +Maximum load current — Run mode +— +— +120 +mA +ILOADstby +Maximum load current — Standby mode +— +— +1 +mA +VReg33out +Regulator output voltage — Input supply +(VREGIN) > 3.6 V +• Run mode +• Standby mode +3 +2.1 +3.3 +2.8 +3.6 +3.6 +V +V +VReg33out +Regulator output voltage — Input supply +(VREGIN) < 3.6 V, pass-through mode +2.1 +— +3.6 +V +2 +COUT +External output capacitor +1.76 +2.2 +8.16 +μF +ESR +External output capacitor equivalent series +resistance +1 +— +100 +mΩ +ILIM +Short circuit current +— +290 +— +mA +1. +Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated. +2. +Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad. +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +60 +Freescale Semiconductor, Inc. + +![Image 1 from page 60](pdf-image://page_60_img_1) + +## Page 61 + +6.8.5 +CAN switching specifications +See General switching specifications. +6.8.6 +DSPI switching specifications (limited voltage range) +The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with +master and slave operations. Many of the transfer attributes are programmable. The tables +below provide DSPI timing characteristics for classic SPI timing modes. Refer to the +DSPI chapter of the Reference Manual for information on the modified transfer formats +used for communicating with slower peripheral devices. +Table 42. Master mode DSPI timing (limited voltage range) +Num +Description +Min. +Max. +Unit +Notes +Operating voltage +2.7 +3.6 +V +Frequency of operation +— +25 +MHz +DS1 +DSPI\_SCK output cycle time +2 x tBUS +— +ns +DS2 +DSPI\_SCK output high/low time +(tSCK/2) − 2 +(tSCK/2) + 2 +ns +DS3 +DSPI\_PCSn valid to DSPI\_SCK delay +(tBUS x 2) − +2 +— +ns +1 +DS4 +DSPI\_SCK to DSPI\_PCSn invalid delay +(tBUS x 2) − +2 +— +ns +2 +DS5 +DSPI\_SCK to DSPI\_SOUT valid +— +8 +ns +DS6 +DSPI\_SCK to DSPI\_SOUT invalid +0 +— +ns +DS7 +DSPI\_SIN to DSPI\_SCK input setup +14 +— +ns +DS8 +DSPI\_SCK to DSPI\_SIN input hold +0 +— +ns +1. +The delay is programmable in SPIx\_CTARn[PSSCK] and SPIx\_CTARn[CSSCK]. +2. +The delay is programmable in SPIx\_CTARn[PASC] and SPIx\_CTARn[ASC]. +DS3 +DS4 +DS1 +DS2 +DS7 +DS8 +First data +Last data +DS5 +First data +Data +Last data +DS6 +Data +DSPI\_PCSn +DSPI\_SCK +(CPOL=0) +DSPI\_SIN +DSPI\_SOUT +Figure 22. DSPI classic SPI timing — master mode +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +61 + +![Image 1 from page 61](pdf-image://page_61_img_1) + +## Page 62 + +Table 43. Slave mode DSPI timing (limited voltage range) +Num +Description +Min. +Max. +Unit +Operating voltage +2.7 +3.6 +V +Frequency of operation +12.5 +MHz +DS9 +DSPI\_SCK input cycle time +4 x tBUS +— +ns +DS10 +DSPI\_SCK input high/low time +(tSCK/2) − 2 +(tSCK/2) + 2 +ns +DS11 +DSPI\_SCK to DSPI\_SOUT valid +— +20 +ns +DS12 +DSPI\_SCK to DSPI\_SOUT invalid +0 +— +ns +DS13 +DSPI\_SIN to DSPI\_SCK input setup +2 +— +ns +DS14 +DSPI\_SCK to DSPI\_SIN input hold +7 +— +ns +DS15 +DSPI\_SS active to DSPI\_SOUT driven +— +14 +ns +DS16 +DSPI\_SS inactive to DSPI\_SOUT not driven +— +14 +ns +First data +Last data +First data +Data +Last data +Data +DS15 +DS10 +DS9 +DS16 +DS11 +DS12 +DS14 +DS13 +DSPI\_SS +DSPI\_SCK +(CPOL=0) +DSPI\_SOUT +DSPI\_SIN +Figure 23. DSPI classic SPI timing — slave mode +6.8.7 +DSPI switching specifications (full voltage range) +The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with +master and slave operations. Many of the transfer attributes are programmable. The tables +below provides DSPI timing characteristics for classic SPI timing modes. Refer to the +DSPI chapter of the Reference Manual for information on the modified transfer formats +used for communicating with slower peripheral devices. +Table 44. Master mode DSPI timing (full voltage range) +Num +Description +Min. +Max. +Unit +Notes +Operating voltage +1.71 +3.6 +V +1 +Frequency of operation +— +12.5 +MHz +DS1 +DSPI\_SCK output cycle time +4 x tBUS +— +ns +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +62 +Freescale Semiconductor, Inc. + +![Image 1 from page 62](pdf-image://page_62_img_1) + +## Page 63 + +Table 44. Master mode DSPI timing (full voltage range) (continued) +Num +Description +Min. +Max. +Unit +Notes +DS2 +DSPI\_SCK output high/low time +(tSCK/2) - 4 +(tSCK/2) + 4 +ns +DS3 +DSPI\_PCSn valid to DSPI\_SCK delay +(tBUS x 2) − +4 +— +ns +2 +DS4 +DSPI\_SCK to DSPI\_PCSn invalid delay +(tBUS x 2) − +4 +— +ns +3 +DS5 +DSPI\_SCK to DSPI\_SOUT valid +— +8.5 +ns +DS6 +DSPI\_SCK to DSPI\_SOUT invalid +-1.2 +— +ns +DS7 +DSPI\_SIN to DSPI\_SCK input setup +19.1 +— +ns +DS8 +DSPI\_SCK to DSPI\_SIN input hold +0 +— +ns +1. +The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage +range the maximum frequency of operation is reduced. +2. +The delay is programmable in SPIx\_CTARn[PSSCK] and SPIx\_CTARn[CSSCK]. +3. +The delay is programmable in SPIx\_CTARn[PASC] and SPIx\_CTARn[ASC]. +DS3 +DS4 +DS1 +DS2 +DS7 +DS8 +First data +Last data +DS5 +First data +Data +Last data +DS6 +Data +DSPI\_PCSn +DSPI\_SCK +(CPOL=0) +DSPI\_SIN +DSPI\_SOUT +Figure 24. DSPI classic SPI timing — master mode +Table 45. Slave mode DSPI timing (full voltage range) +Num +Description +Min. +Max. +Unit +Operating voltage +1.71 +3.6 +V +Frequency of operation +— +6.25 +MHz +DS9 +DSPI\_SCK input cycle time +8 x tBUS +— +ns +DS10 +DSPI\_SCK input high/low time +(tSCK/2) - 4 +(tSCK/2) + 4 +ns +DS11 +DSPI\_SCK to DSPI\_SOUT valid +— +24 +ns +DS12 +DSPI\_SCK to DSPI\_SOUT invalid +0 +— +ns +DS13 +DSPI\_SIN to DSPI\_SCK input setup +3.2 +— +ns +DS14 +DSPI\_SCK to DSPI\_SIN input hold +7 +— +ns +DS15 +DSPI\_SS active to DSPI\_SOUT driven +— +19 +ns +DS16 +DSPI\_SS inactive to DSPI\_SOUT not driven +— +19 +ns +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +63 + +![Image 1 from page 63](pdf-image://page_63_img_1) + +## Page 64 + +First data +Last data +First data +Data +Last data +Data +DS15 +DS10 +DS9 +DS16 +DS11 +DS12 +DS14 +DS13 +DSPI\_SS +DSPI\_SCK +(CPOL=0) +DSPI\_SOUT +DSPI\_SIN +Figure 25. DSPI classic SPI timing — slave mode +6.8.8 +Inter-Integrated Circuit Interface (I2C) timing +Table 46. I 2C timing +Characteristic +Symbol +Standard Mode +Fast Mode +Unit +Minimum +Maximum +Minimum +Maximum +SCL Clock Frequency +fSCL +0 +100 +0 +400 +kHz +Hold time (repeated) START condition. +After this period, the first clock pulse is +generated. +tHD; STA +4 +— +0.6 +— +µs +LOW period of the SCL clock +tLOW +4.7 +— +1.3 +— +µs +HIGH period of the SCL clock +tHIGH +4 +— +0.6 +— +µs +Set-up time for a repeated START +condition +tSU; STA +4.7 +— +0.6 +— +µs +Data hold time for I2C bus devices +tHD; DAT +01 +3.452 +03 +0.91 +µs +Data set-up time +tSU; DAT +2504 +— +1002, 5 +— +ns +Rise time of SDA and SCL signals +tr +— +1000 +20 +0.1Cb6 +300 +ns +Fall time of SDA and SCL signals +tf +— +300 +20 +0.1Cb5 +300 +ns +Set-up time for STOP condition +tSU; STO +4 +— +0.6 +— +µs +Bus free time between STOP and +START condition +tBUF +4.7 +— +1.3 +— +µs +Pulse width of spikes that must be +suppressed by the input filter +tSP +N/A +N/A +0 +50 +ns +1. +The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves +acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL +lines. +2. +The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal. +3. +Input signal Slew = 10 ns and Output Load = 50 pF +4. +Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty. +5. +A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns must +then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a +device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU; DAT += 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released. +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +64 +Freescale Semiconductor, Inc. + +![Image 1 from page 64](pdf-image://page_64_img_1) + +## Page 65 + +6. +Cb = total capacitance of the one bus line in pF. +SDA +SCL +tHD; STA +tHD; DAT +tLOW +tSU; DAT +tHIGH +tSU; STA +SR +P +S +S +tHD; STA +tSP +tSU; STO +tBUF +tf +tr +tf +tr +Figure 26. Timing definition for fast and standard mode devices on the I2C bus +6.8.9 +UART switching specifications +See General switching specifications. +6.8.10 +SDHC specifications +The following timing specs are defined at the chip I/O pin and must be translated +appropriately to arrive at timing specs/constraints for the physical interface. +Table 47. SDHC switching specifications +Num +Symbol +Description +Min. +Max. +Unit +Operating voltage +1.71 +3.6 +V +Card input clock +SD1 +fpp +Clock frequency (low speed) +0 +400 +kHz +fpp +Clock frequency (SD\SDIO full speed\high speed) +0 +25\50 +MHz +fpp +Clock frequency (MMC full speed\high speed) +0 +20\50 +MHz +fOD +Clock frequency (identification mode) +0 +400 +kHz +SD2 +tWL +Clock low time +7 +— +ns +SD3 +tWH +Clock high time +7 +— +ns +SD4 +tTLH +Clock rise time +— +3 +ns +SD5 +tTHL +Clock fall time +— +3 +ns +SDHC output / card inputs SDHC\_CMD, SDHC\_DAT (reference to SDHC\_CLK) +SD6 +tOD +SDHC output delay (output valid) +-5 +8.3 +ns +SDHC input / card inputs SDHC\_CMD, SDHC\_DAT (reference to SDHC\_CLK) +SD7 +tISU +SDHC input setup time +5 +— +ns +SD8 +tIH +SDHC input hold time +0 +— +ns +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +65 + +![Image 1 from page 65](pdf-image://page_65_img_1) + +## Page 66 + +SD2 +SD3 +SD1 +SD6 +SD8 +SD7 +SDHC\_CLK +Output SDHC\_CMD +Output SDHC\_DAT[3:0] +Input SDHC\_CMD +Input SDHC\_DAT[3:0] +Figure 27. SDHC timing +6.8.11 +I2S/SAI switching specifications +This section provides the AC timing for the I2S/SAI module in master mode (clocks are +driven) and slave mode (clocks are input). All timing is given for noninverted serial clock +polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync (TCR4[FSP] +is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync have been +inverted, all the timing remains valid by inverting the bit clock signal (BCLK) and/or the +frame sync (FS) signal shown in the following figures. +6.8.11.1 +Normal Run, Wait and Stop mode performance over a limited +operating voltage range +This section provides the operating performance over a limited operating voltage for the +device in Normal Run, Wait and Stop modes. +Table 48. I2S/SAI master mode timing in Normal Run, Wait and Stop modes +(limited voltage range) +Num. +Characteristic +Min. +Max. +Unit +Operating voltage +2.7 +3.6 +V +S1 +I2S\_MCLK cycle time +40 +— +ns +S2 +I2S\_MCLK pulse width high/low +45% +55% +MCLK period +S3 +I2S\_TX\_BCLK/I2S\_RX\_BCLK cycle time (output) +80 +— +ns +S4 +I2S\_TX\_BCLK/I2S\_RX\_BCLK pulse width high/low +45% +55% +BCLK period +S5 +I2S\_TX\_BCLK/I2S\_RX\_BCLK to I2S\_TX\_FS/ +I2S\_RX\_FS output valid +— +15 +ns +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +66 +Freescale Semiconductor, Inc. + +![Image 1 from page 66](pdf-image://page_66_img_1) + +## Page 67 + +Table 48. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage +range) (continued) +Num. +Characteristic +Min. +Max. +Unit +S6 +I2S\_TX\_BCLK/I2S\_RX\_BCLK to I2S\_TX\_FS/ +I2S\_RX\_FS output invalid +0 +— +ns +S7 +I2S\_TX\_BCLK to I2S\_TXD valid +— +15 +ns +S8 +I2S\_TX\_BCLK to I2S\_TXD invalid +0 +— +ns +S9 +I2S\_RXD/I2S\_RX\_FS input setup before +I2S\_RX\_BCLK +15 +— +ns +S10 +I2S\_RXD/I2S\_RX\_FS input hold after I2S\_RX\_BCLK +0 +— +ns +S1 +S2 +S2 +S3 +S4 +S4 +S5 +S9 +S7 +S9 +S10 +S7 +S8 +S6 +S10 +S8 +I2S\_MCLK (output) +I2S\_TX\_BCLK/ +I2S\_RX\_BCLK (output) +I2S\_TX\_FS/ +I2S\_RX\_FS (output) +I2S\_TX\_FS/ +I2S\_RX\_FS (input) +I2S\_TXD +I2S\_RXD +Figure 28. I2S/SAI timing — master modes +Table 49. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes +(limited voltage range) +Num. +Characteristic +Min. +Max. +Unit +Operating voltage +2.7 +3.6 +V +S11 +I2S\_TX\_BCLK/I2S\_RX\_BCLK cycle time (input) +80 +— +ns +S12 +I2S\_TX\_BCLK/I2S\_RX\_BCLK pulse width high/low +(input) +45% +55% +MCLK period +S13 +I2S\_TX\_FS/I2S\_RX\_FS input setup before +I2S\_TX\_BCLK/I2S\_RX\_BCLK +4.5 +— +ns +S14 +I2S\_TX\_FS/I2S\_RX\_FS input hold after +I2S\_TX\_BCLK/I2S\_RX\_BCLK +2 +— +ns +S15 +I2S\_TX\_BCLK to I2S\_TXD/I2S\_TX\_FS output valid +• Multiple SAI Synchronous mode +• All other modes +— +— +21 +15 +ns +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +67 + +![Image 1 from page 67](pdf-image://page_67_img_1) + +## Page 68 + +Table 49. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage +range) (continued) +Num. +Characteristic +Min. +Max. +Unit +S16 +I2S\_TX\_BCLK to I2S\_TXD/I2S\_TX\_FS output invalid +0 +— +ns +S17 +I2S\_RXD setup before I2S\_RX\_BCLK +4.5 +— +ns +S18 +I2S\_RXD hold after I2S\_RX\_BCLK +2 +— +ns +S19 +I2S\_TX\_FS input assertion to I2S\_TXD output valid1 +— +25 +ns +1. +Applies to first bit in each frame and only if the TCR4[FSE] bit is clear +S15 +S13 +S15 +S17 +S18 +S15 +S16 +S16 +S14 +S16 +S11 +S12 +S12 +I2S\_TX\_BCLK/ +I2S\_RX\_BCLK (input) +I2S\_TX\_FS/ +I2S\_RX\_FS (output) +I2S\_TXD +I2S\_RXD +I2S\_TX\_FS/ +I2S\_RX\_FS (input) +S19 +Figure 29. I2S/SAI timing — slave modes +6.8.11.2 +Normal Run, Wait and Stop mode performance over the full +operating voltage range +This section provides the operating performance over the full operating voltage for the +device in Normal Run, Wait and Stop modes. +Table 50. I2S/SAI master mode timing in Normal Run, Wait and Stop modes +(full voltage range) +Num. +Characteristic +Min. +Max. +Unit +Operating voltage +1.71 +3.6 +V +S1 +I2S\_MCLK cycle time +40 +— +ns +S2 +I2S\_MCLK pulse width high/low +45% +55% +MCLK period +S3 +I2S\_TX\_BCLK/I2S\_RX\_BCLK cycle time (output) +80 +— +ns +S4 +I2S\_TX\_BCLK/I2S\_RX\_BCLK pulse width high/low +45% +55% +BCLK period +S5 +I2S\_TX\_BCLK/I2S\_RX\_BCLK to I2S\_TX\_FS/ +I2S\_RX\_FS output valid +— +15 +ns +S6 +I2S\_TX\_BCLK/I2S\_RX\_BCLK to I2S\_TX\_FS/ +I2S\_RX\_FS output invalid +-1.0 +— +ns +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +68 +Freescale Semiconductor, Inc. + +![Image 1 from page 68](pdf-image://page_68_img_1) + +## Page 69 + +Table 50. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage +range) (continued) +Num. +Characteristic +Min. +Max. +Unit +S7 +I2S\_TX\_BCLK to I2S\_TXD valid +— +15 +ns +S8 +I2S\_TX\_BCLK to I2S\_TXD invalid +0 +— +ns +S9 +I2S\_RXD/I2S\_RX\_FS input setup before +I2S\_RX\_BCLK +20.5 +— +ns +S10 +I2S\_RXD/I2S\_RX\_FS input hold after I2S\_RX\_BCLK +0 +— +ns +S1 +S2 +S2 +S3 +S4 +S4 +S5 +S9 +S7 +S9 +S10 +S7 +S8 +S6 +S10 +S8 +I2S\_MCLK (output) +I2S\_TX\_BCLK/ +I2S\_RX\_BCLK (output) +I2S\_TX\_FS/ +I2S\_RX\_FS (output) +I2S\_TX\_FS/ +I2S\_RX\_FS (input) +I2S\_TXD +I2S\_RXD +Figure 30. I2S/SAI timing — master modes +Table 51. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes +(full voltage range) +Num. +Characteristic +Min. +Max. +Unit +Operating voltage +1.71 +3.6 +V +S11 +I2S\_TX\_BCLK/I2S\_RX\_BCLK cycle time (input) +80 +— +ns +S12 +I2S\_TX\_BCLK/I2S\_RX\_BCLK pulse width high/low +(input) +45% +55% +MCLK period +S13 +I2S\_TX\_FS/I2S\_RX\_FS input setup before +I2S\_TX\_BCLK/I2S\_RX\_BCLK +5.8 +— +ns +S14 +I2S\_TX\_FS/I2S\_RX\_FS input hold after +I2S\_TX\_BCLK/I2S\_RX\_BCLK +2 +— +ns +S15 +I2S\_TX\_BCLK to I2S\_TXD/I2S\_TX\_FS output valid +• Multiple SAI Synchronous mode +• All other modes +— +— +24 +20.6 +ns +S16 +I2S\_TX\_BCLK to I2S\_TXD/I2S\_TX\_FS output invalid +0 +— +ns +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +69 + +![Image 1 from page 69](pdf-image://page_69_img_1) + +## Page 70 + +Table 51. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage +range) (continued) +Num. +Characteristic +Min. +Max. +Unit +S17 +I2S\_RXD setup before I2S\_RX\_BCLK +5.8 +— +ns +S18 +I2S\_RXD hold after I2S\_RX\_BCLK +2 +— +ns +S19 +I2S\_TX\_FS input assertion to I2S\_TXD output valid1 +— +25 +ns +1. +Applies to first bit in each frame and only if the TCR4[FSE] bit is clear +S15 +S13 +S15 +S17 +S18 +S15 +S16 +S16 +S14 +S16 +S11 +S12 +S12 +I2S\_TX\_BCLK/ +I2S\_RX\_BCLK (input) +I2S\_TX\_FS/ +I2S\_RX\_FS (output) +I2S\_TXD +I2S\_RXD +I2S\_TX\_FS/ +I2S\_RX\_FS (input) +S19 +Figure 31. I2S/SAI timing — slave modes +6.8.11.3 +VLPR, VLPW, and VLPS mode performance over the full +operating voltage range +This section provides the operating performance over the full operating voltage for the +device in VLPR, VLPW, and VLPS modes. +Table 52. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes +(full voltage range) +Num. +Characteristic +Min. +Max. +Unit +Operating voltage +1.71 +3.6 +V +S1 +I2S\_MCLK cycle time +62.5 +— +ns +S2 +I2S\_MCLK pulse width high/low +45% +55% +MCLK period +S3 +I2S\_TX\_BCLK/I2S\_RX\_BCLK cycle time (output) +250 +— +ns +S4 +I2S\_TX\_BCLK/I2S\_RX\_BCLK pulse width high/low +45% +55% +BCLK period +S5 +I2S\_TX\_BCLK/I2S\_RX\_BCLK to I2S\_TX\_FS/ +I2S\_RX\_FS output valid +— +45 +ns +S6 +I2S\_TX\_BCLK/I2S\_RX\_BCLK to I2S\_TX\_FS/ +I2S\_RX\_FS output invalid +0 +— +ns +S7 +I2S\_TX\_BCLK to I2S\_TXD valid +— +45 +ns +Table continues on the next page... +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +70 +Freescale Semiconductor, Inc. + +![Image 1 from page 70](pdf-image://page_70_img_1) + +## Page 71 + +Table 52. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range) +(continued) +Num. +Characteristic +Min. +Max. +Unit +S8 +I2S\_TX\_BCLK to I2S\_TXD invalid +0 +— +ns +S9 +I2S\_RXD/I2S\_RX\_FS input setup before +I2S\_RX\_BCLK +45 +— +ns +S10 +I2S\_RXD/I2S\_RX\_FS input hold after I2S\_RX\_BCLK +0 +— +ns +S1 +S2 +S2 +S3 +S4 +S4 +S5 +S9 +S7 +S9 +S10 +S7 +S8 +S6 +S10 +S8 +I2S\_MCLK (output) +I2S\_TX\_BCLK/ +I2S\_RX\_BCLK (output) +I2S\_TX\_FS/ +I2S\_RX\_FS (output) +I2S\_TX\_FS/ +I2S\_RX\_FS (input) +I2S\_TXD +I2S\_RXD +Figure 32. I2S/SAI timing — master modes +Table 53. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full +voltage range) +Num. +Characteristic +Min. +Max. +Unit +Operating voltage +1.71 +3.6 +V +S11 +I2S\_TX\_BCLK/I2S\_RX\_BCLK cycle time (input) +250 +— +ns +S12 +I2S\_TX\_BCLK/I2S\_RX\_BCLK pulse width high/low +(input) +45% +55% +MCLK period +S13 +I2S\_TX\_FS/I2S\_RX\_FS input setup before +I2S\_TX\_BCLK/I2S\_RX\_BCLK +30 +— +ns +S14 +I2S\_TX\_FS/I2S\_RX\_FS input hold after +I2S\_TX\_BCLK/I2S\_RX\_BCLK +3 +— +ns +S15 +I2S\_TX\_BCLK to I2S\_TXD/I2S\_TX\_FS output valid +— +63 +ns +S16 +I2S\_TX\_BCLK to I2S\_TXD/I2S\_TX\_FS output invalid +0 +— +ns +S17 +I2S\_RXD setup before I2S\_RX\_BCLK +30 +— +ns +S18 +I2S\_RXD hold after I2S\_RX\_BCLK +2 +— +ns +S19 +I2S\_TX\_FS input assertion to I2S\_TXD output valid1 +— +72 +ns +1. +Applies to first bit in each frame and only if the TCR4[FSE] bit is clear +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +71 + +![Image 1 from page 71](pdf-image://page_71_img_1) + +## Page 72 + +S15 +S13 +S15 +S17 +S18 +S15 +S16 +S16 +S14 +S16 +S11 +S12 +S12 +I2S\_TX\_BCLK/ +I2S\_RX\_BCLK (input) +I2S\_TX\_FS/ +I2S\_RX\_FS (output) +I2S\_TXD +I2S\_RXD +I2S\_TX\_FS/ +I2S\_RX\_FS (input) +S19 +Figure 33. I2S/SAI timing — slave modes +6.9 +Human-machine interfaces (HMI) +6.9.1 +TSI electrical specifications +Table 54. TSI electrical specifications +Symbol +Description +Min. +Typ. +Max. +Unit +Notes +VDDTSI +Operating voltage +1.71 +— +3.6 +V +CELE +Target electrode capacitance range +1 +20 +500 +pF +1 +fREFmax +Reference oscillator frequency +— +8 +15 +MHz +2, 3 +fELEmax +Electrode oscillator frequency +— +1 +1.8 +MHz +2, 4 +CREF +Internal reference capacitor +— +1 +— +pF +VDELTA +Oscillator delta voltage +— +500 +— +mV +2, 5 +IREF +Reference oscillator current source base current +• 2 μA setting (REFCHRG = 0) +• 32 μA setting (REFCHRG = 15) +— +— +2 +36 +3 +50 +μA +2, 6 +IELE +Electrode oscillator current source base current +• 2 μA setting (EXTCHRG = 0) +• 32 μA setting (EXTCHRG = 15) +— +— +2 +36 +3 +50 +μA +2, 7 +Pres5 +Electrode capacitance measurement precision +— +8.3333 +38400 +fF/count +8 +Pres20 +Electrode capacitance measurement precision +— +8.3333 +38400 +fF/count +9 +Pres100 +Electrode capacitance measurement precision +— +8.3333 +38400 +fF/count +10 +MaxSens +Maximum sensitivity +0.008 +1.46 +— +fF/count +11 +Res +Resolution +— +— +16 +bits +TCon20 +Response time @ 20 pF +8 +15 +25 +μs +12 +ITSI\_RUN +Current added in run mode +— +55 +— +μA +ITSI\_LP +Low power mode current adder +— +1.3 +2.5 +μA +13 +Peripheral operating requirements and behaviors +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +72 +Freescale Semiconductor, Inc. + +![Image 1 from page 72](pdf-image://page_72_img_1) + +## Page 73 + +1. +The TSI module is functional with capacitance values outside this range. However, optimal performance is not guaranteed. +2. +Fixed external capacitance of 20 pF. +3. +REFCHRG = 2, EXTCHRG=0. +4. +REFCHRG = 0, EXTCHRG = 10. +5. +VDD = 3.0 V. +6. +The programmable current source value is generated by multiplying the SCANC[REFCHRG] value and the base current. +7. +The programmable current source value is generated by multiplying the SCANC[EXTCHRG] value and the base current. +8. +Measured with a 5 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 8; Iext = 16. +9. +Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 128, NSCN = 2; Iext = 16. +10. Measured with a 20 pF electrode, reference oscillator frequency of 10 MHz, PS = 16, NSCN = 3; Iext = 16. +11. Sensitivity defines the minimum capacitance change when a single count from the TSI module changes. Sensitivity +depends on the configuration used. The documented values are provided as examples calculated for a specific +configuration of operating conditions using the following equation: (Cref * Iext)/( Iref * PS * NSCN) +The typical value is calculated with the following configuration: +Iext = 6 μA (EXTCHRG = 2), PS = 128, NSCN = 2, Iref = 16 μA (REFCHRG = 7), Cref = 1.0 pF +The minimum value is calculated with the following configuration: +Iext = 2 μA (EXTCHRG = 0), PS = 128, NSCN = 32, Iref = 32 μA (REFCHRG = 15), Cref = 0.5 pF +The highest possible sensitivity is the minimum value because it represents the smallest possible capacitance that can be +measured by a single count. +12. Time to do one complete measurement of the electrode. Sensitivity resolution of 0.0133 pF, PS = 0, NSCN = 0, 1 +electrode, EXTCHRG = 7. +13. REFCHRG=0, EXTCHRG=4, PS=7, NSCN=0F, LPSCNITV=F, LPO is selected (1 kHz), and fixed external capacitance of +20 pF. Data is captured with an average of 7 periods window. +7 +Dimensions +7.1 +Obtaining package dimensions +Package dimensions are provided in package drawings. +To find a package drawing, go to freescale.com and perform a keyword search for the +drawing’s document number: +If you want the drawing for this package +Then use this document number +144-pin LQFP +98ASS23177W +144-pin MAPBGA +98ASA00222D +8 +Pinout +Dimensions +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +73 + +![Image 1 from page 73](pdf-image://page_73_img_1) + +## Page 74 + +8.1 +K60 signal multiplexing and pin assignments +The following table shows the signals available on each pin and the locations of these +pins on the devices supported by this document. The Port Control Module is responsible +for selecting which ALT functionality is available on each pin. +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +— +L5 +RTC\_ +WAKEUP\_B +RTC\_ +WAKEUP\_B +RTC\_ +WAKEUP\_B +— +M5 +NC +NC +NC +— +A10 +NC +NC +NC +— +B10 +NC +NC +NC +— +C10 +NC +NC +NC +1 +D3 +PTE0 +ADC1\_SE4a +ADC1\_SE4a +PTE0 +SPI1\_PCS1 +UART1\_TX +SDHC0\_D1 +I2C1\_SDA +RTC\_CLKOUT +2 +D2 +PTE1/ +LLWU\_P0 +ADC1\_SE5a +ADC1\_SE5a +PTE1/ +LLWU\_P0 +SPI1\_SOUT +UART1\_RX +SDHC0\_D0 +I2C1\_SCL +SPI1\_SIN +3 +D1 +PTE2/ +LLWU\_P1 +ADC1\_SE6a +ADC1\_SE6a +PTE2/ +LLWU\_P1 +SPI1\_SCK +UART1\_CTS\_ +b +SDHC0\_DCLK +4 +E4 +PTE3 +ADC1\_SE7a +ADC1\_SE7a +PTE3 +SPI1\_SIN +UART1\_RTS\_ +b +SDHC0\_CMD +SPI1\_SOUT +5 +E5 +VDD +VDD +VDD +6 +F6 +VSS +VSS +VSS +7 +E3 +PTE4/ +LLWU\_P2 +DISABLED +PTE4/ +LLWU\_P2 +SPI1\_PCS0 +UART3\_TX +SDHC0\_D3 +8 +E2 +PTE5 +DISABLED +PTE5 +SPI1\_PCS2 +UART3\_RX +SDHC0\_D2 +9 +E1 +PTE6 +DISABLED +PTE6 +SPI1\_PCS3 +UART3\_CTS\_ +b +I2S0\_MCLK +USB\_SOF\_ +OUT +10 +F4 +PTE7 +DISABLED +PTE7 +UART3\_RTS\_ +b +I2S0\_RXD0 +11 +F3 +PTE8 +DISABLED +PTE8 +I2S0\_RXD1 +UART5\_TX +I2S0\_RX\_FS +12 +F2 +PTE9 +DISABLED +PTE9 +I2S0\_TXD1 +UART5\_RX +I2S0\_RX\_ +BCLK +13 +F1 +PTE10 +DISABLED +PTE10 +UART5\_CTS\_ +b +I2S0\_TXD0 +14 +G4 +PTE11 +DISABLED +PTE11 +UART5\_RTS\_ +b +I2S0\_TX\_FS +15 +G3 +PTE12 +DISABLED +PTE12 +I2S0\_TX\_ +BCLK +16 +E6 +VDD +VDD +VDD +17 +F7 +VSS +VSS +VSS +18 +H3 +VSS +VSS +VSS +19 +H1 +USB0\_DP +USB0\_DP +USB0\_DP +20 +H2 +USB0\_DM +USB0\_DM +USB0\_DM +21 +G1 +VOUT33 +VOUT33 +VOUT33 +22 +G2 +VREGIN +VREGIN +VREGIN +Pinout +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +74 +Freescale Semiconductor, Inc. + +![Image 1 from page 74](pdf-image://page_74_img_1) + +## Page 75 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +23 +J1 +ADC0\_DP1 +ADC0\_DP1 +ADC0\_DP1 +24 +J2 +ADC0\_DM1 +ADC0\_DM1 +ADC0\_DM1 +25 +K1 +ADC1\_DP1 +ADC1\_DP1 +ADC1\_DP1 +26 +K2 +ADC1\_DM1 +ADC1\_DM1 +ADC1\_DM1 +27 +L1 +PGA0\_DP/ +ADC0\_DP0/ +ADC1\_DP3 +PGA0\_DP/ +ADC0\_DP0/ +ADC1\_DP3 +PGA0\_DP/ +ADC0\_DP0/ +ADC1\_DP3 +28 +L2 +PGA0\_DM/ +ADC0\_DM0/ +ADC1\_DM3 +PGA0\_DM/ +ADC0\_DM0/ +ADC1\_DM3 +PGA0\_DM/ +ADC0\_DM0/ +ADC1\_DM3 +29 +M1 +PGA1\_DP/ +ADC1\_DP0/ +ADC0\_DP3 +PGA1\_DP/ +ADC1\_DP0/ +ADC0\_DP3 +PGA1\_DP/ +ADC1\_DP0/ +ADC0\_DP3 +30 +M2 +PGA1\_DM/ +ADC1\_DM0/ +ADC0\_DM3 +PGA1\_DM/ +ADC1\_DM0/ +ADC0\_DM3 +PGA1\_DM/ +ADC1\_DM0/ +ADC0\_DM3 +31 +H5 +VDDA +VDDA +VDDA +32 +G5 +VREFH +VREFH +VREFH +33 +G6 +VREFL +VREFL +VREFL +34 +H6 +VSSA +VSSA +VSSA +35 +K3 +ADC1\_SE16/ +CMP2\_IN2/ +ADC0\_SE22 +ADC1\_SE16/ +CMP2\_IN2/ +ADC0\_SE22 +ADC1\_SE16/ +CMP2\_IN2/ +ADC0\_SE22 +36 +J3 +ADC0\_SE16/ +CMP1\_IN2/ +ADC0\_SE21 +ADC0\_SE16/ +CMP1\_IN2/ +ADC0\_SE21 +ADC0\_SE16/ +CMP1\_IN2/ +ADC0\_SE21 +37 +M3 +VREF\_OUT/ +CMP1\_IN5/ +CMP0\_IN5/ +ADC1\_SE18 +VREF\_OUT/ +CMP1\_IN5/ +CMP0\_IN5/ +ADC1\_SE18 +VREF\_OUT/ +CMP1\_IN5/ +CMP0\_IN5/ +ADC1\_SE18 +38 +L3 +DAC0\_OUT/ +CMP1\_IN3/ +ADC0\_SE23 +DAC0\_OUT/ +CMP1\_IN3/ +ADC0\_SE23 +DAC0\_OUT/ +CMP1\_IN3/ +ADC0\_SE23 +39 +L4 +DAC1\_OUT/ +CMP0\_IN4/ +CMP2\_IN3/ +ADC1\_SE23 +DAC1\_OUT/ +CMP0\_IN4/ +CMP2\_IN3/ +ADC1\_SE23 +DAC1\_OUT/ +CMP0\_IN4/ +CMP2\_IN3/ +ADC1\_SE23 +40 +M7 +XTAL32 +XTAL32 +XTAL32 +41 +M6 +EXTAL32 +EXTAL32 +EXTAL32 +42 +L6 +VBAT +VBAT +VBAT +43 +— +VDD +VDD +VDD +44 +— +VSS +VSS +VSS +45 +M4 +PTE24 +ADC0\_SE17 +ADC0\_SE17 +PTE24 +CAN1\_TX +UART4\_TX +EWM\_OUT\_b +46 +K5 +PTE25 +ADC0\_SE18 +ADC0\_SE18 +PTE25 +CAN1\_RX +UART4\_RX +EWM\_IN +47 +K4 +PTE26 +DISABLED +PTE26 +ENET\_1588\_ +CLKIN +UART4\_CTS\_ +b +RTC\_CLKOUT +USB\_CLKIN +Pinout +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +75 + +![Image 1 from page 75](pdf-image://page_75_img_1) + +## Page 76 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +48 +J4 +PTE27 +DISABLED +PTE27 +UART4\_RTS\_ +b +49 +H4 +PTE28 +DISABLED +PTE28 +50 +J5 +PTA0 +JTAG\_TCLK/ +SWD\_CLK/ +EZP\_CLK +TSI0\_CH1 +PTA0 +UART0\_CTS\_ +b/ +UART0\_COL\_ +b +FTM0\_CH5 +JTAG\_TCLK/ +SWD\_CLK +EZP\_CLK +51 +J6 +PTA1 +JTAG\_TDI/ +EZP\_DI +TSI0\_CH2 +PTA1 +UART0\_RX +FTM0\_CH6 +JTAG\_TDI +EZP\_DI +52 +K6 +PTA2 +JTAG\_TDO/ +TRACE\_SWO/ +EZP\_DO +TSI0\_CH3 +PTA2 +UART0\_TX +FTM0\_CH7 +JTAG\_TDO/ +TRACE\_SWO +EZP\_DO +53 +K7 +PTA3 +JTAG\_TMS/ +SWD\_DIO +TSI0\_CH4 +PTA3 +UART0\_RTS\_ +b +FTM0\_CH0 +JTAG\_TMS/ +SWD\_DIO +54 +L7 +PTA4/ +LLWU\_P3 +NMI\_b/ +EZP\_CS\_b +TSI0\_CH5 +PTA4/ +LLWU\_P3 +FTM0\_CH1 +NMI\_b +EZP\_CS\_b +55 +M8 +PTA5 +DISABLED +PTA5 +USB\_CLKIN +FTM0\_CH2 +RMII0\_RXER/ +MII0\_RXER +CMP2\_OUT +I2S0\_TX\_ +BCLK +JTAG\_TRST\_ +b +56 +E7 +VDD +VDD +VDD +57 +G7 +VSS +VSS +VSS +58 +J7 +PTA6 +DISABLED +PTA6 +FTM0\_CH3 +TRACE\_ +CLKOUT +59 +J8 +PTA7 +ADC0\_SE10 +ADC0\_SE10 +PTA7 +FTM0\_CH4 +TRACE\_D3 +60 +K8 +PTA8 +ADC0\_SE11 +ADC0\_SE11 +PTA8 +FTM1\_CH0 +FTM1\_QD\_ +PHA +TRACE\_D2 +61 +L8 +PTA9 +DISABLED +PTA9 +FTM1\_CH1 +MII0\_RXD3 +FTM1\_QD\_ +PHB +TRACE\_D1 +62 +M9 +PTA10 +DISABLED +PTA10 +FTM2\_CH0 +MII0\_RXD2 +FTM2\_QD\_ +PHA +TRACE\_D0 +63 +L9 +PTA11 +DISABLED +PTA11 +FTM2\_CH1 +MII0\_RXCLK +FTM2\_QD\_ +PHB +64 +K9 +PTA12 +CMP2\_IN0 +CMP2\_IN0 +PTA12 +CAN0\_TX +FTM1\_CH0 +RMII0\_RXD1/ +MII0\_RXD1 +I2S0\_TXD0 +FTM1\_QD\_ +PHA +65 +J9 +PTA13/ +LLWU\_P4 +CMP2\_IN1 +CMP2\_IN1 +PTA13/ +LLWU\_P4 +CAN0\_RX +FTM1\_CH1 +RMII0\_RXD0/ +MII0\_RXD0 +I2S0\_TX\_FS +FTM1\_QD\_ +PHB +66 +L10 +PTA14 +DISABLED +PTA14 +SPI0\_PCS0 +UART0\_TX +RMII0\_CRS\_ +DV/ +MII0\_RXDV +I2S0\_RX\_ +BCLK +I2S0\_TXD1 +67 +L11 +PTA15 +DISABLED +PTA15 +SPI0\_SCK +UART0\_RX +RMII0\_TXEN/ +MII0\_TXEN +I2S0\_RXD0 +68 +K10 +PTA16 +DISABLED +PTA16 +SPI0\_SOUT +UART0\_CTS\_ +b/ +UART0\_COL\_ +b +RMII0\_TXD0/ +MII0\_TXD0 +I2S0\_RX\_FS +I2S0\_RXD1 +69 +K11 +PTA17 +ADC1\_SE17 +ADC1\_SE17 +PTA17 +SPI0\_SIN +UART0\_RTS\_ +b +RMII0\_TXD1/ +MII0\_TXD1 +I2S0\_MCLK +70 +E8 +VDD +VDD +VDD +Pinout +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +76 +Freescale Semiconductor, Inc. + +![Image 1 from page 76](pdf-image://page_76_img_1) + +## Page 77 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +71 +G8 +VSS +VSS +VSS +72 +M12 +PTA18 +EXTAL0 +EXTAL0 +PTA18 +FTM0\_FLT2 +FTM\_CLKIN0 +73 +M11 +PTA19 +XTAL0 +XTAL0 +PTA19 +FTM1\_FLT0 +FTM\_CLKIN1 +LPTMR0\_ +ALT1 +74 +L12 +RESET\_b +RESET\_b +RESET\_b +75 +K12 +PTA24 +DISABLED +PTA24 +MII0\_TXD2 +FB\_A29 +76 +J12 +PTA25 +DISABLED +PTA25 +MII0\_TXCLK +FB\_A28 +77 +J11 +PTA26 +DISABLED +PTA26 +MII0\_TXD3 +FB\_A27 +78 +J10 +PTA27 +DISABLED +PTA27 +MII0\_CRS +FB\_A26 +79 +H12 +PTA28 +DISABLED +PTA28 +MII0\_TXER +FB\_A25 +80 +H11 +PTA29 +DISABLED +PTA29 +MII0\_COL +FB\_A24 +81 +H10 +PTB0/ +LLWU\_P5 +ADC0\_SE8/ +ADC1\_SE8/ +TSI0\_CH0 +ADC0\_SE8/ +ADC1\_SE8/ +TSI0\_CH0 +PTB0/ +LLWU\_P5 +I2C0\_SCL +FTM1\_CH0 +RMII0\_MDIO/ +MII0\_MDIO +FTM1\_QD\_ +PHA +82 +H9 +PTB1 +ADC0\_SE9/ +ADC1\_SE9/ +TSI0\_CH6 +ADC0\_SE9/ +ADC1\_SE9/ +TSI0\_CH6 +PTB1 +I2C0\_SDA +FTM1\_CH1 +RMII0\_MDC/ +MII0\_MDC +FTM1\_QD\_ +PHB +83 +G12 +PTB2 +ADC0\_SE12/ +TSI0\_CH7 +ADC0\_SE12/ +TSI0\_CH7 +PTB2 +I2C0\_SCL +UART0\_RTS\_ +b +ENET0\_1588\_ +TMR0 +FTM0\_FLT3 +84 +G11 +PTB3 +ADC0\_SE13/ +TSI0\_CH8 +ADC0\_SE13/ +TSI0\_CH8 +PTB3 +I2C0\_SDA +UART0\_CTS\_ +b/ +UART0\_COL\_ +b +ENET0\_1588\_ +TMR1 +FTM0\_FLT0 +85 +G10 +PTB4 +ADC1\_SE10 +ADC1\_SE10 +PTB4 +ENET0\_1588\_ +TMR2 +FTM1\_FLT0 +86 +G9 +PTB5 +ADC1\_SE11 +ADC1\_SE11 +PTB5 +ENET0\_1588\_ +TMR3 +FTM2\_FLT0 +87 +F12 +PTB6 +ADC1\_SE12 +ADC1\_SE12 +PTB6 +FB\_AD23 +88 +F11 +PTB7 +ADC1\_SE13 +ADC1\_SE13 +PTB7 +FB\_AD22 +89 +F10 +PTB8 +DISABLED +PTB8 +UART3\_RTS\_ +b +FB\_AD21 +90 +F9 +PTB9 +DISABLED +PTB9 +SPI1\_PCS1 +UART3\_CTS\_ +b +FB\_AD20 +91 +E12 +PTB10 +ADC1\_SE14 +ADC1\_SE14 +PTB10 +SPI1\_PCS0 +UART3\_RX +FB\_AD19 +FTM0\_FLT1 +92 +E11 +PTB11 +ADC1\_SE15 +ADC1\_SE15 +PTB11 +SPI1\_SCK +UART3\_TX +FB\_AD18 +FTM0\_FLT2 +93 +H7 +VSS +VSS +VSS +94 +F5 +VDD +VDD +VDD +95 +E10 +PTB16 +TSI0\_CH9 +TSI0\_CH9 +PTB16 +SPI1\_SOUT +UART0\_RX +FB\_AD17 +EWM\_IN +96 +E9 +PTB17 +TSI0\_CH10 +TSI0\_CH10 +PTB17 +SPI1\_SIN +UART0\_TX +FB\_AD16 +EWM\_OUT\_b +97 +D12 +PTB18 +TSI0\_CH11 +TSI0\_CH11 +PTB18 +CAN0\_TX +FTM2\_CH0 +I2S0\_TX\_ +BCLK +FB\_AD15 +FTM2\_QD\_ +PHA +98 +D11 +PTB19 +TSI0\_CH12 +TSI0\_CH12 +PTB19 +CAN0\_RX +FTM2\_CH1 +I2S0\_TX\_FS +FB\_OE\_b +FTM2\_QD\_ +PHB +99 +D10 +PTB20 +DISABLED +PTB20 +SPI2\_PCS0 +FB\_AD31 +CMP0\_OUT +100 +D9 +PTB21 +DISABLED +PTB21 +SPI2\_SCK +FB\_AD30 +CMP1\_OUT +Pinout +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +77 + +![Image 1 from page 77](pdf-image://page_77_img_1) + +## Page 78 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +101 +C12 +PTB22 +DISABLED +PTB22 +SPI2\_SOUT +FB\_AD29 +CMP2\_OUT +102 +C11 +PTB23 +DISABLED +PTB23 +SPI2\_SIN +SPI0\_PCS5 +FB\_AD28 +103 +B12 +PTC0 +ADC0\_SE14/ +TSI0\_CH13 +ADC0\_SE14/ +TSI0\_CH13 +PTC0 +SPI0\_PCS4 +PDB0\_EXTRG +FB\_AD14 +I2S0\_TXD1 +104 +B11 +PTC1/ +LLWU\_P6 +ADC0\_SE15/ +TSI0\_CH14 +ADC0\_SE15/ +TSI0\_CH14 +PTC1/ +LLWU\_P6 +SPI0\_PCS3 +UART1\_RTS\_ +b +FTM0\_CH0 +FB\_AD13 +I2S0\_TXD0 +105 +A12 +PTC2 +ADC0\_SE4b/ +CMP1\_IN0/ +TSI0\_CH15 +ADC0\_SE4b/ +CMP1\_IN0/ +TSI0\_CH15 +PTC2 +SPI0\_PCS2 +UART1\_CTS\_ +b +FTM0\_CH1 +FB\_AD12 +I2S0\_TX\_FS +106 +A11 +PTC3/ +LLWU\_P7 +CMP1\_IN1 +CMP1\_IN1 +PTC3/ +LLWU\_P7 +SPI0\_PCS1 +UART1\_RX +FTM0\_CH2 +CLKOUT +I2S0\_TX\_ +BCLK +107 +H8 +VSS +VSS +VSS +108 +— +VDD +VDD +VDD +109 +A9 +PTC4/ +LLWU\_P8 +DISABLED +PTC4/ +LLWU\_P8 +SPI0\_PCS0 +UART1\_TX +FTM0\_CH3 +FB\_AD11 +CMP1\_OUT +110 +D8 +PTC5/ +LLWU\_P9 +DISABLED +PTC5/ +LLWU\_P9 +SPI0\_SCK +LPTMR0\_ +ALT2 +I2S0\_RXD0 +FB\_AD10 +CMP0\_OUT +111 +C8 +PTC6/ +LLWU\_P10 +CMP0\_IN0 +CMP0\_IN0 +PTC6/ +LLWU\_P10 +SPI0\_SOUT +PDB0\_EXTRG +I2S0\_RX\_ +BCLK +FB\_AD9 +I2S0\_MCLK +112 +B8 +PTC7 +CMP0\_IN1 +CMP0\_IN1 +PTC7 +SPI0\_SIN +USB\_SOF\_ +OUT +I2S0\_RX\_FS +FB\_AD8 +113 +A8 +PTC8 +ADC1\_SE4b/ +CMP0\_IN2 +ADC1\_SE4b/ +CMP0\_IN2 +PTC8 +I2S0\_MCLK +FB\_AD7 +114 +D7 +PTC9 +ADC1\_SE5b/ +CMP0\_IN3 +ADC1\_SE5b/ +CMP0\_IN3 +PTC9 +I2S0\_RX\_ +BCLK +FB\_AD6 +FTM2\_FLT0 +115 +C7 +PTC10 +ADC1\_SE6b +ADC1\_SE6b +PTC10 +I2C1\_SCL +I2S0\_RX\_FS +FB\_AD5 +116 +B7 +PTC11/ +LLWU\_P11 +ADC1\_SE7b +ADC1\_SE7b +PTC11/ +LLWU\_P11 +I2C1\_SDA +I2S0\_RXD1 +FB\_RW\_b +117 +A7 +PTC12 +DISABLED +PTC12 +UART4\_RTS\_ +b +FB\_AD27 +118 +D6 +PTC13 +DISABLED +PTC13 +UART4\_CTS\_ +b +FB\_AD26 +119 +C6 +PTC14 +DISABLED +PTC14 +UART4\_RX +FB\_AD25 +120 +B6 +PTC15 +DISABLED +PTC15 +UART4\_TX +FB\_AD24 +121 +— +VSS +VSS +VSS +122 +— +VDD +VDD +VDD +123 +A6 +PTC16 +DISABLED +PTC16 +CAN1\_RX +UART3\_RX +ENET0\_1588\_ +TMR0 +FB\_CS5\_b/ +FB\_TSIZ1/ +FB\_BE23\_16\_ +b +124 +D5 +PTC17 +DISABLED +PTC17 +CAN1\_TX +UART3\_TX +ENET0\_1588\_ +TMR1 +FB\_CS4\_b/ +FB\_TSIZ0/ +FB\_BE31\_24\_ +b +125 +C5 +PTC18 +DISABLED +PTC18 +UART3\_RTS\_ +b +ENET0\_1588\_ +TMR2 +FB\_TBST\_b/ +FB\_CS2\_b/ +FB\_BE15\_8\_b +Pinout +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +78 +Freescale Semiconductor, Inc. + +![Image 1 from page 78](pdf-image://page_78_img_1) + +## Page 79 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +126 +B5 +PTC19 +DISABLED +PTC19 +UART3\_CTS\_ +b +ENET0\_1588\_ +TMR3 +FB\_CS3\_b/ +FB\_BE7\_0\_b +FB\_TA\_b +127 +A5 +PTD0/ +LLWU\_P12 +DISABLED +PTD0/ +LLWU\_P12 +SPI0\_PCS0 +UART2\_RTS\_ +b +FB\_ALE/ +FB\_CS1\_b/ +FB\_TS\_b +128 +D4 +PTD1 +ADC0\_SE5b +ADC0\_SE5b +PTD1 +SPI0\_SCK +UART2\_CTS\_ +b +FB\_CS0\_b +129 +C4 +PTD2/ +LLWU\_P13 +DISABLED +PTD2/ +LLWU\_P13 +SPI0\_SOUT +UART2\_RX +FB\_AD4 +130 +B4 +PTD3 +DISABLED +PTD3 +SPI0\_SIN +UART2\_TX +FB\_AD3 +131 +A4 +PTD4/ +LLWU\_P14 +DISABLED +PTD4/ +LLWU\_P14 +SPI0\_PCS1 +UART0\_RTS\_ +b +FTM0\_CH4 +FB\_AD2 +EWM\_IN +132 +A3 +PTD5 +ADC0\_SE6b +ADC0\_SE6b +PTD5 +SPI0\_PCS2 +UART0\_CTS\_ +b/ +UART0\_COL\_ +b +FTM0\_CH5 +FB\_AD1 +EWM\_OUT\_b +133 +A2 +PTD6/ +LLWU\_P15 +ADC0\_SE7b +ADC0\_SE7b +PTD6/ +LLWU\_P15 +SPI0\_PCS3 +UART0\_RX +FTM0\_CH6 +FB\_AD0 +FTM0\_FLT0 +134 +M10 +VSS +VSS +VSS +135 +F8 +VDD +VDD +VDD +136 +A1 +PTD7 +DISABLED +PTD7 +CMT\_IRO +UART0\_TX +FTM0\_CH7 +FTM0\_FLT1 +137 +C9 +PTD8 +DISABLED +PTD8 +I2C0\_SCL +UART5\_RX +FB\_A16 +138 +B9 +PTD9 +DISABLED +PTD9 +I2C0\_SDA +UART5\_TX +FB\_A17 +139 +B3 +PTD10 +DISABLED +PTD10 +UART5\_RTS\_ +b +FB\_A18 +140 +B2 +PTD11 +DISABLED +PTD11 +SPI2\_PCS0 +UART5\_CTS\_ +b +SDHC0\_ +CLKIN +FB\_A19 +141 +B1 +PTD12 +DISABLED +PTD12 +SPI2\_SCK +SDHC0\_D4 +FB\_A20 +142 +C3 +PTD13 +DISABLED +PTD13 +SPI2\_SOUT +SDHC0\_D5 +FB\_A21 +143 +C2 +PTD14 +DISABLED +PTD14 +SPI2\_SIN +SDHC0\_D6 +FB\_A22 +144 +C1 +PTD15 +DISABLED +PTD15 +SPI2\_PCS1 +SDHC0\_D7 +FB\_A23 +8.2 +K60 pinouts +The figure below shows the pinout diagram for the devices supported by this document. +Many signals may be multiplexed onto a single pin. To determine what signals can be +used on which pin, see the previous section. +Pinout +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +79 + +![Image 1 from page 79](pdf-image://page_79_img_1) + +## Page 80 + +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +75 +74 +73 +60 +59 +58 +57 +56 +55 +54 +53 +52 +51 +72 +71 +70 +69 +68 +67 +66 +65 +64 +63 +62 +61 +25 +24 +23 +22 +21 +40 +39 +38 +37 +50 +49 +48 +47 +46 +45 +44 +43 +42 +41 +36 +35 +34 +33 +32 +31 +30 +29 +28 +27 +26 +99 +79 +78 +77 +76 +98 +97 +96 +95 +94 +93 +92 +91 +90 +89 +88 +80 +81 +82 +83 +84 +85 +86 +87 +100 +108 +VDD +107 +106 +105 +104 +103 +102 +101 +VSS +PTC3/LLWU\_P7 +PTC2 +PTC1/LLWU\_P6 +PTC0 +PTB23 +PTB22 +116 +PTC11/LLWU\_P11 +115 +114 +113 +112 +111 +110 +109 +PTC10 +PTC9 +PTC8 +PTC7 +PTC6/LLWU\_P10 +PTC5/LLWU\_P9 +PTC4/LLWU\_P8 +124 +PTC17 +123 +122 +121 +120 +119 +118 +117 +PTC16 +VDD +VSS +PTC15 +PTC14 +PTC13 +PTC12 +132 +PTD5 +131 +130 +129 +128 +127 +126 +125 +PTD4/LLWU\_P14 +PTD3 +PTD2/LLWU\_P13 +PTD1 +PTD0/LLWU\_P12 +PTC19 +PTC18 +140 +PTD11 +139 +138 +137 +136 +135 +134 +133 +PTD10 +PTD9 +PTD8 +PTD7 +VDD +VSS +PTD6/LLWU\_P15 +144 +143 +142 +141 +PTD15 +PTD14 +PTD13 +PTD12 +PTB20 +PTA28 +PTA27 +PTA26 +PTA25 +PTB19 +PTB18 +PTB17 +PTB16 +VDD +VSS +PTB11 +PTB10 +PTB9 +PTB8 +PTB7 +PTA29 +PTB0/LLWU\_P5 +PTB1 +PTB2 +PTB3 +PTB4 +PTB5 +PTB6 +PTB21 +PTA24 +RESET\_b +PTA19 +PTA18 +VSS +VDD +PTA17 +PTA16 +PTA15 +PTA14 +PTA13/LLWU\_P4 +PTA12 +PTA11 +PTA10 +PTA9 +PTA8 +PTA7 +PTA6 +VSS +VDD +PTA5 +PTA4/LLWU\_P3 +PTA3 +PTA2 +PTA1 +PTA0 +PTE28 +PTE27 +PTE26 +PTE25 +PTE24 +VSS +VDD +VBAT +EXTAL32 +XTAL32 +DAC1\_OUT/CMP0\_IN4/CMP2\_IN3/ADC1\_SE23 +DAC0\_OUT/CMP1\_IN3/ADC0\_SE23 +VREF\_OUT/CMP1\_IN5/CMP0\_IN5/ADC1\_SE18 +USB0\_DM +USB0\_DP +VSS +VSS +VDD +PTE12 +PTE11 +PTE10 +PTE9 +PTE8 +PTE7 +PTE6 +PTE5 +PTE4/LLWU\_P2 +VSS +VDD +PTE3 +PTE2/LLWU\_P1 +PTE1/LLWU\_P0 +PTE0 +ADC1\_DP1 +ADC0\_DM1 +ADC0\_DP1 +VREGIN +VOUT33 +ADC0\_SE16/CMP1\_IN2/ADC0\_SE21 +ADC1\_SE16/CMP2\_IN2/ADC0\_SE22 +VSSA +VREFL +VREFH +VDDA +PGA1\_DM/ADC1\_DM0/ADC0\_DM3 +PGA1\_DP/ADC1\_DP0/ADC0\_DP3 +PGA0\_DM/ADC0\_DM0/ADC1\_DM3 +PGA0\_DP/ADC0\_DP0/ADC1\_DP3 +ADC1\_DM1 +Figure 34. K60 144 LQFP Pinout Diagram +Pinout +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +80 +Freescale Semiconductor, Inc. + +![Image 1 from page 80](pdf-image://page_80_img_1) + +## Page 81 + +1 +2 +3 +4 +5 +6 +7 +8 +9 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F +G +H +J +A +B +C +D +E +F +G +H +J +10 +K +K +10 +11 +11 +L +L +12 +12 +M +M +PTA18 +PTC8 +PTC4/ +NC +PTC3/ +PTC2 +PTA1 +PTA6 +PTA0 +PTE27 +ADC0\_SE16/ +ADC1\_SE16/ +PTE26 +PTE25 +PTA2 +PTA3 +PTA8 +PTA7 +VSS +VSS +VSSA +VDDA +PTE28 +VSS +USB0\_DM +ADC0\_DM1 +ADC1\_DM1 +PGA0\_DM/ +DAC0\_OUT/ +DAC1\_OUT/ +RTC +VBAT +PTA4/ +PTA9 +PTA11 +PTA12 +PTA13/ +PTB1 +PTA27 +PTB0/ +PTB4 +PTB5 +VSS +VSS +VREFL +VREFH +PTE11 +PTE12 +VREGIN +VOUT33 +USB0\_DP +ADC0\_DP1 +ADC1\_DP1 +PGA0\_DP/ +PGA1\_DP/ +PGA1\_DM/ +VREF\_OUT/ +PTE24 +NC +EXTAL32 +XTAL32 +PTA5 +PTA10 +VSS +PTA16 +PTA14 +PTB3 +PTA29 +PTA26 +PTA17 +PTA15 +PTA19 +RESET\_b +PTA24 +PTA25 +PTA28 +PTB2 +PTB6 +PTB7 +PTB8 +PTB9 +VDD +VDD +PTB17 +PTB16 +PTB10 +PTB11 +PTB19 +PTB18 +PTB22 +PTB23 +NC +PTB20 +PTB21 +PTC5/ +PTD8 +PTC6/ +PTC7 +PTD9 +NC +PTC1/ +PTC0 +VSS +VSS +VDD +VDD +PTC13 +PTC9 +PTC11/ +PTC10 +PTC19 +PTC15 +PTC14 +PTC18 +PTD2/ +PTD3 +PTD10 +PTD13 +PTE0 +PTD1 +PTC17 +VDD +VDD +PTE7 +PTE3 +PTE4/ +PTE8 +PTE9 +PTE10 +PTE6 +PTE5 +PTE1/ +PTE2/ +PTD15 +PTD14 +PTD11 +PTD12 +PTC12 +PTC16 +PTD0/ +PTD4/ +PTD5 +PTD6/ +PTD7 +LLWU\_P15 +LLWU\_P14 +LLWU\_P12 +LLWU\_P8 +LLWU\_P7 +LLWU\_P11 +LLWU\_P6 +LLWU\_P13 +LLWU\_P10 +LLWU\_P1 +LLWU\_P0 +LLWU\_P9 +LLWU\_P2 +LLWU\_P5 +CMP1\_IN2/ +ADC0\_SE21 +LLWU\_P4 +CMP2\_IN2/ +ADC0\_SE22 +ADC0\_DP0/ +ADC1\_DP3 +ADC0\_DM0/ +ADC1\_DM3 +CMP1\_IN3/ +ADC0\_SE23 +CMP0\_IN4/ +CMP2\_IN3/ +ADC1\_SE23 +\_WAKEUP\_B +LLWU\_P3 +CMP1\_IN5/ +CMP0\_IN5/ +ADC1\_SE18 +ADC1\_DP0/ +ADC0\_DP3 +ADC1\_DM0/ +ADC0\_DM3 +Figure 35. K60 144 MAPBGA Pinout Diagram +9 +Revision history +The following table provides a revision history for this document. +Table 55. Revision history +Rev. No. +Date +Substantial Changes +1 +6/2012 +Initial public revision +Table continues on the next page... +Revision history +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +Freescale Semiconductor, Inc. +81 + +![Image 1 from page 81](pdf-image://page_81_img_1) + +## Page 82 + +Table 55. Revision history (continued) +Rev. No. +Date +Substantial Changes +2 +12/2012 +Replaced TBDs throughout. +3 +6/2013 +• In ESD handling ratings, added a note for ILAT. +• Updated "Voltage and current operating requirements" Table 1. +• Updated IOL data for VOL row in "Voltage and current operating behaviors" Table 4. +• Updated wakeup times and tPOR value in "Power mode transition operating behaviors" +Table 5. +• In "EMC radiated emissions operating behaviors . . ." Table 7, added a column for +144MAPBGA. +• In "16-bit ADC operating conditions" Table 27, updated the max spec of VADIN. +• In "16-bit ADC electrical characteristics" Table 28, updated the temp sensor slope and +voltage specs. +• Updated Inter-Integrated Circuit Interface (I2C) timing. +• In SDHC specifications, added operating voltage row. +Revision history +K60 Sub-Family Data Sheet, Rev. 3, 6/2013. +82 +Freescale Semiconductor, Inc. + +![Image 1 from page 82](pdf-image://page_82_img_1) + +## Page 83 + +Information in this document is provided solely to enable system and software +implementers to use Freescale products. There are no express or implied copyright +licenses granted hereunder to design or fabricate any integrated circuits based on the +information in this document. +Freescale reserves the right to make changes without further notice to any products +herein. Freescale makes no warranty, representation, or guarantee regarding the +suitability of its products for any particular purpose, nor does Freescale assume any +liability arising out of the application or use of any product or circuit, and specifically +disclaims any and all liability, including without limitation consequential or incidental +damages. “Typical” parameters that may be provided in Freescale data sheets and/or +specifications can and do vary in different applications, and actual performance may +vary over time. All operating parameters, including “typicals,” must be validated for each +customer application by customer’s technical experts. Freescale does not convey any +license under its patent rights nor the rights of others. Freescale sells products pursuant +to standard terms and conditions of sale, which can be found at the following address: +freescale.com/SalesTermsandConditions. +How to Reach Us: +Home Page: +freescale.com +Web Support: +freescale.com/support +Freescale, the Freescale logo and Kinetis are trademarks of Freescale Semiconductor, +Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property +of their respective owners. ARM is the registered trademark of ARM Limited. Cortex-M4 +is the trademark of ARM Limited. +are the registered trademarks of ARM Limited. +© 2012–2013Freescale Semiconductor, Inc. +Document Number: K60P144M100SF2V2 +Rev. 3 +06/2013 + +![Image 1 from page 83](pdf-image://page_83_img_1) + +![Image 2 from page 83](pdf-image://page_83_img_2) + +![Image 3 from page 83](pdf-image://page_83_img_3) + diff --git a/docs/K60-datasheet.pdf b/docs/K60-datasheet.pdf new file mode 100644 index 0000000..1a38ef0 --- /dev/null +++ b/docs/K60-datasheet.pdf @@ -0,0 +1,3 @@ +version https://git-lfs.github.com/spec/v1 +oid sha256:2d623b55b2910d10b1e3a9e164368edca8736cd546c7f3de0d56d37e24525963 +size 1670228 diff --git a/docs/K60-reference-manual.md b/docs/K60-reference-manual.md new file mode 100644 index 0000000..d108649 --- /dev/null +++ b/docs/K60-reference-manual.md @@ -0,0 +1,61249 @@ +# Document Metadata +**Format:** PDF 1.4 +**Title:** Kinetis K60: 100MHz Cortex-M4 256/512KB Flash (144 pin) +**Author:** Freescale Semiconductor Inc. +**Subject:** Kinetis K60 Reference Manual: 100MHz high-performance ARM Cortex-M4 microcontroller(MCU), Ethernet, mixed-signal, up to 512KB Flash/128KB SRAM (144pin) +**Keywords:** K60P144M100SF2V2RM, MK60DN512VMD10,MK60DN256VMD10,MK60DX256VMD10,MK60DN256VLQ10,MK60DX256VLQ10,MK60DN512VLQ10, reference manual, Kinetis, microcontroller, MCU, Cortex-M, ARM, specification, architecture, features, registers, high-performance, Cortex-M4, Kinetis K, K-series, K7x, Ethernet, K60, mixed-signal integration +**Creator:** AH Formatter V5.2 MR1 (5,2,2010,1221) for Linux64 +**Producer:** Antenna House PDF Output Library 2.6.0 (Linux64); modified using iText® 5.5.4 ©2000-2014 iText Group NV (AGPL-version) +**Creation Date:** D:20120602111254-05'00' +**Mod Date:** D:20150220201302-06'00' +**Trapped:** False + +--- + +## Page 1 + +K60 Sub-Family Reference Manual +Supports: MK60DN256VLQ10, MK60DX256VLQ10, +MK60DN512VLQ10, MK60DN256VMD10, MK60DX256VMD10, +MK60DN512VMD10 +Document Number: K60P144M100SF2V2RM +Rev. 2 Jun 2012 +Preliminary +General Business Information + +![Image 1 from page 1](pdf-image://page_1_img_1) + +![Image 2 from page 1](pdf-image://page_1_img_2) + +![Image 3 from page 1](pdf-image://page_1_img_3) + +## Page 2 + +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +2 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 2](pdf-image://page_2_img_1) + +## Page 3 + +Contents +Section number +Title +Page +Chapter 1 +About This Document +1.1 +Overview.......................................................................................................................................................................59 +1.1.1 +Purpose.........................................................................................................................................................59 +1.1.2 +Audience......................................................................................................................................................59 +1.2 +Conventions..................................................................................................................................................................59 +1.2.1 +Numbering systems......................................................................................................................................59 +1.2.2 +Typographic notation...................................................................................................................................60 +1.2.3 +Special terms................................................................................................................................................60 +Chapter 2 +Introduction +2.1 +Overview.......................................................................................................................................................................61 +2.2 +Module Functional Categories......................................................................................................................................61 +2.2.1 +ARM Cortex-M4 Core Modules..................................................................................................................62 +2.2.2 +System Modules...........................................................................................................................................63 +2.2.3 +Memories and Memory Interfaces...............................................................................................................64 +2.2.4 +Clocks...........................................................................................................................................................65 +2.2.5 +Security and Integrity modules....................................................................................................................65 +2.2.6 +Analog modules...........................................................................................................................................66 +2.2.7 +Timer modules.............................................................................................................................................66 +2.2.8 +Communication interfaces...........................................................................................................................67 +2.2.9 +Human-machine interfaces..........................................................................................................................68 +2.3 +Orderable part numbers.................................................................................................................................................68 +Chapter 3 +Chip Configuration +3.1 +Introduction...................................................................................................................................................................71 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +3 +General Business Information + +![Image 1 from page 3](pdf-image://page_3_img_1) + +## Page 4 + +Section number +Title +Page +3.2 +Core modules................................................................................................................................................................71 +3.2.1 +ARM Cortex-M4 Core Configuration..........................................................................................................71 +3.2.2 +Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................73 +3.2.3 +Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................79 +3.2.4 +JTAG Controller Configuration...................................................................................................................81 +3.3 +System modules............................................................................................................................................................81 +3.3.1 +SIM Configuration.......................................................................................................................................81 +3.3.2 +System Mode Controller (SMC) Configuration...........................................................................................82 +3.3.3 +PMC Configuration......................................................................................................................................83 +3.3.4 +Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................84 +3.3.5 +MCM Configuration....................................................................................................................................86 +3.3.6 +Crossbar Switch Configuration....................................................................................................................87 +3.3.7 +Memory Protection Unit (MPU) Configuration...........................................................................................89 +3.3.8 +Peripheral Bridge Configuration..................................................................................................................92 +3.3.9 +DMA request multiplexer configuration......................................................................................................93 +3.3.10 +DMA Controller Configuration...................................................................................................................96 +3.3.11 +External Watchdog Monitor (EWM) Configuration....................................................................................97 +3.3.12 +Watchdog Configuration..............................................................................................................................99 +3.4 +Clock modules..............................................................................................................................................................100 +3.4.1 +MCG Configuration.....................................................................................................................................100 +3.4.2 +OSC Configuration......................................................................................................................................101 +3.4.3 +RTC OSC configuration...............................................................................................................................102 +3.5 +Memories and memory interfaces.................................................................................................................................102 +3.5.1 +Flash Memory Configuration.......................................................................................................................102 +3.5.2 +Flash Memory Controller Configuration.....................................................................................................106 +3.5.3 +SRAM Configuration...................................................................................................................................107 +3.5.4 +SRAM Controller Configuration.................................................................................................................111 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +4 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 4](pdf-image://page_4_img_1) + +## Page 5 + +Section number +Title +Page +3.5.5 +System Register File Configuration.............................................................................................................111 +3.5.6 +VBAT Register File Configuration..............................................................................................................112 +3.5.7 +EzPort Configuration...................................................................................................................................113 +3.5.8 +FlexBus Configuration.................................................................................................................................114 +3.6 +Security.........................................................................................................................................................................117 +3.6.1 +CRC Configuration......................................................................................................................................117 +3.6.2 +MMCAU Configuration...............................................................................................................................118 +3.6.3 +RNG Configuration......................................................................................................................................119 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +5 +General Business Information + +![Image 1 from page 5](pdf-image://page_5_img_1) + +## Page 6 + +Section number +Title +Page +3.7 +Analog...........................................................................................................................................................................119 +3.7.1 +16-bit SAR ADC with PGA Configuration.................................................................................................119 +3.7.2 +CMP Configuration......................................................................................................................................127 +3.7.3 +12-bit DAC Configuration...........................................................................................................................129 +3.7.4 +VREF Configuration....................................................................................................................................130 +3.8 +Timers...........................................................................................................................................................................131 +3.8.1 +PDB Configuration......................................................................................................................................131 +3.8.2 +FlexTimer Configuration.............................................................................................................................134 +3.8.3 +PIT Configuration........................................................................................................................................138 +3.8.4 +Low-power timer configuration...................................................................................................................139 +3.8.5 +CMT Configuration......................................................................................................................................141 +3.8.6 +RTC configuration.......................................................................................................................................142 +3.9 +Communication interfaces............................................................................................................................................143 +3.9.1 +Ethernet Configuration.................................................................................................................................143 +3.9.2 +Universal Serial Bus (USB) FS Subsystem.................................................................................................146 +3.9.3 +CAN Configuration......................................................................................................................................151 +3.9.4 +SPI configuration.........................................................................................................................................153 +3.9.5 +I2C Configuration........................................................................................................................................156 +3.9.6 +UART Configuration...................................................................................................................................157 +3.9.7 +SDHC Configuration....................................................................................................................................160 +3.9.8 +I2S configuration..........................................................................................................................................162 +3.10 +Human-machine interfaces...........................................................................................................................................164 +3.10.1 +GPIO configuration......................................................................................................................................164 +3.10.2 +TSI Configuration........................................................................................................................................165 +Chapter 4 +Memory Map +4.1 +Introduction...................................................................................................................................................................169 +4.2 +System memory map.....................................................................................................................................................169 +4.2.1 +Aliased bit-band regions..............................................................................................................................170 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +6 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 6](pdf-image://page_6_img_1) + +## Page 7 + +Section number +Title +Page +4.3 +Flash Memory Map.......................................................................................................................................................171 +4.3.1 +Alternate Non-Volatile IRC User Trim Description....................................................................................172 +4.4 +SRAM memory map.....................................................................................................................................................173 +4.5 +Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................173 +4.5.1 +Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................173 +4.5.2 +Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................177 +4.6 +Private Peripheral Bus (PPB) memory map..................................................................................................................181 +Chapter 5 +Clock Distribution +5.1 +Introduction...................................................................................................................................................................183 +5.2 +Programming model......................................................................................................................................................183 +5.3 +High-Level device clocking diagram............................................................................................................................183 +5.4 +Clock definitions...........................................................................................................................................................184 +5.4.1 +Device clock summary.................................................................................................................................185 +5.5 +Internal clocking requirements.....................................................................................................................................187 +5.5.1 +Clock divider values after reset....................................................................................................................188 +5.5.2 +VLPR mode clocking...................................................................................................................................188 +5.6 +Clock Gating.................................................................................................................................................................189 +5.7 +Module clocks...............................................................................................................................................................189 +5.7.1 +PMC 1-kHz LPO clock................................................................................................................................191 +5.7.2 +WDOG clocking..........................................................................................................................................191 +5.7.3 +Debug trace clock.........................................................................................................................................191 +5.7.4 +PORT digital filter clocking.........................................................................................................................192 +5.7.5 +LPTMR clocking..........................................................................................................................................192 +5.7.6 +Ethernet Clocking........................................................................................................................................193 +5.7.7 +USB FS OTG Controller clocking...............................................................................................................194 +5.7.8 +FlexCAN clocking.......................................................................................................................................195 +5.7.9 +UART clocking............................................................................................................................................195 +5.7.10 +SDHC clocking............................................................................................................................................195 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +7 +General Business Information + +![Image 1 from page 7](pdf-image://page_7_img_1) + +## Page 8 + +Section number +Title +Page +5.7.11 +I2S/SAI clocking..........................................................................................................................................196 +5.7.12 +TSI clocking.................................................................................................................................................196 +Chapter 6 +Reset and Boot +6.1 +Introduction...................................................................................................................................................................199 +6.2 +Reset..............................................................................................................................................................................200 +6.2.1 +Power-on reset (POR)..................................................................................................................................200 +6.2.2 +System reset sources....................................................................................................................................200 +6.2.3 +MCU Resets.................................................................................................................................................204 +6.2.4 +Reset Pin .....................................................................................................................................................206 +6.2.5 +Debug resets.................................................................................................................................................206 +6.3 +Boot...............................................................................................................................................................................207 +6.3.1 +Boot sources.................................................................................................................................................207 +6.3.2 +Boot options.................................................................................................................................................208 +6.3.3 +FOPT boot options.......................................................................................................................................208 +6.3.4 +Boot sequence..............................................................................................................................................209 +Chapter 7 +Power Management +7.1 +Introduction...................................................................................................................................................................211 +7.2 +Power modes.................................................................................................................................................................211 +7.3 +Entering and exiting power modes...............................................................................................................................213 +7.4 +Power mode transitions.................................................................................................................................................214 +7.5 +Power modes shutdown sequencing.............................................................................................................................215 +7.6 +Module Operation in Low Power Modes......................................................................................................................215 +7.7 +Clock Gating.................................................................................................................................................................218 +Chapter 8 +Security +8.1 +Introduction...................................................................................................................................................................219 +8.2 +Flash Security...............................................................................................................................................................219 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +8 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 8](pdf-image://page_8_img_1) + +## Page 9 + +Section number +Title +Page +8.3 +Security Interactions with other Modules.....................................................................................................................220 +8.3.1 +Security interactions with FlexBus..............................................................................................................220 +8.3.2 +Security Interactions with EzPort................................................................................................................220 +8.3.3 +Security Interactions with Debug.................................................................................................................220 +Chapter 9 +Debug +9.1 +Introduction...................................................................................................................................................................223 +9.1.1 +References....................................................................................................................................................225 +9.2 +The Debug Port.............................................................................................................................................................225 +9.2.1 +JTAG-to-SWD change sequence.................................................................................................................226 +9.2.2 +JTAG-to-cJTAG change sequence...............................................................................................................226 +9.3 +Debug Port Pin Descriptions.........................................................................................................................................227 +9.4 +System TAP connection................................................................................................................................................227 +9.4.1 +IR Codes.......................................................................................................................................................227 +9.5 +JTAG status and control registers.................................................................................................................................228 +9.5.1 +MDM-AP Control Register..........................................................................................................................229 +9.5.2 +MDM-AP Status Register............................................................................................................................231 +9.6 +Debug Resets................................................................................................................................................................232 +9.7 +AHB-AP........................................................................................................................................................................233 +9.8 +ITM...............................................................................................................................................................................234 +9.9 +Core Trace Connectivity...............................................................................................................................................234 +9.10 +Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................235 +9.11 +Coresight Embedded Trace Buffer (ETB)....................................................................................................................236 +9.11.1 +Performance Profiling with the ETB...........................................................................................................236 +9.11.2 +ETB Counter Control...................................................................................................................................237 +9.12 +TPIU..............................................................................................................................................................................237 +9.13 +DWT.............................................................................................................................................................................237 +9.14 +Debug in Low Power Modes........................................................................................................................................238 +9.14.1 +Debug Module State in Low Power Modes.................................................................................................239 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +9 +General Business Information + +![Image 1 from page 9](pdf-image://page_9_img_1) + +## Page 10 + +Section number +Title +Page +9.15 +Debug & Security.........................................................................................................................................................239 +Chapter 10 +Signal Multiplexing and Signal Descriptions +10.1 +Introduction...................................................................................................................................................................241 +10.2 +Signal Multiplexing Integration....................................................................................................................................241 +10.2.1 +Port control and interrupt module features..................................................................................................242 +10.2.2 +PCRn reset values for port A.......................................................................................................................242 +10.2.3 +Clock gating.................................................................................................................................................242 +10.2.4 +Signal multiplexing constraints....................................................................................................................242 +10.3 +Pinout............................................................................................................................................................................243 +10.3.1 +K60 Signal Multiplexing and Pin Assignments...........................................................................................243 +10.3.2 +K60 Pinouts..................................................................................................................................................249 +10.4 +Module Signal Description Tables................................................................................................................................251 +10.4.1 +Core Modules...............................................................................................................................................251 +10.4.2 +System Modules...........................................................................................................................................252 +10.4.3 +Clock Modules.............................................................................................................................................253 +10.4.4 +Memories and Memory Interfaces...............................................................................................................253 +10.4.5 +Analog..........................................................................................................................................................256 +10.4.6 +Timer Modules.............................................................................................................................................258 +10.4.7 +Communication Interfaces...........................................................................................................................261 +10.4.8 +Human-Machine Interfaces (HMI)..............................................................................................................267 +Chapter 11 +Port control and interrupts (PORT) +11.1 +Introduction...................................................................................................................................................................269 +11.2 +Overview.......................................................................................................................................................................269 +11.2.1 +Features........................................................................................................................................................269 +11.2.2 +Modes of operation......................................................................................................................................270 +11.3 +External signal description............................................................................................................................................271 +11.4 +Detailed signal description............................................................................................................................................271 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +10 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 10](pdf-image://page_10_img_1) + +## Page 11 + +Section number +Title +Page +11.5 +Memory map and register definition.............................................................................................................................271 +11.5.1 +Pin Control Register n (PORTx\_PCRn).......................................................................................................277 +11.5.2 +Global Pin Control Low Register (PORTx\_GPCLR)..................................................................................280 +11.5.3 +Global Pin Control High Register (PORTx\_GPCHR).................................................................................280 +11.5.4 +Interrupt Status Flag Register (PORTx\_ISFR)............................................................................................281 +11.6 +Functional description...................................................................................................................................................281 +11.6.1 +Pin control....................................................................................................................................................281 +11.6.2 +Global pin control........................................................................................................................................282 +11.6.3 +External interrupts........................................................................................................................................282 +Chapter 12 +System Integration Module (SIM) +12.1 +Introduction...................................................................................................................................................................285 +12.1.1 +Features........................................................................................................................................................285 +12.2 +Memory map and register definition.............................................................................................................................286 +12.2.1 +System Options Register 1 (SIM\_SOPT1)..................................................................................................287 +12.2.2 +SOPT1 Configuration Register (SIM\_SOPT1CFG)....................................................................................289 +12.2.3 +System Options Register 2 (SIM\_SOPT2)..................................................................................................290 +12.2.4 +System Options Register 4 (SIM\_SOPT4)..................................................................................................293 +12.2.5 +System Options Register 5 (SIM\_SOPT5)..................................................................................................295 +12.2.6 +System Options Register 7 (SIM\_SOPT7)..................................................................................................297 +12.2.7 +System Device Identification Register (SIM\_SDID)...................................................................................299 +12.2.8 +System Clock Gating Control Register 1 (SIM\_SCGC1)............................................................................300 +12.2.9 +System Clock Gating Control Register 2 (SIM\_SCGC2)............................................................................301 +12.2.10 +System Clock Gating Control Register 3 (SIM\_SCGC3)............................................................................302 +12.2.11 +System Clock Gating Control Register 4 (SIM\_SCGC4)............................................................................304 +12.2.12 +System Clock Gating Control Register 5 (SIM\_SCGC5)............................................................................306 +12.2.13 +System Clock Gating Control Register 6 (SIM\_SCGC6)............................................................................308 +12.2.14 +System Clock Gating Control Register 7 (SIM\_SCGC7)............................................................................310 +12.2.15 +System Clock Divider Register 1 (SIM\_CLKDIV1)...................................................................................311 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +11 +General Business Information + +![Image 1 from page 11](pdf-image://page_11_img_1) + +## Page 12 + +Section number +Title +Page +12.2.16 +System Clock Divider Register 2 (SIM\_CLKDIV2)...................................................................................314 +12.2.17 +Flash Configuration Register 1 (SIM\_FCFG1)...........................................................................................314 +12.2.18 +Flash Configuration Register 2 (SIM\_FCFG2)...........................................................................................317 +12.2.19 +Unique Identification Register High (SIM\_UIDH).....................................................................................318 +12.2.20 +Unique Identification Register Mid-High (SIM\_UIDMH)..........................................................................319 +12.2.21 +Unique Identification Register Mid Low (SIM\_UIDML)...........................................................................319 +12.2.22 +Unique Identification Register Low (SIM\_UIDL)......................................................................................320 +12.3 +Functional description...................................................................................................................................................320 +Chapter 13 +Reset Control Module (RCM) +13.1 +Introduction...................................................................................................................................................................321 +13.2 +Reset memory map and register descriptions...............................................................................................................321 +13.2.1 +System Reset Status Register 0 (RCM\_SRS0)............................................................................................321 +13.2.2 +System Reset Status Register 1 (RCM\_SRS1)............................................................................................323 +13.2.3 +Reset Pin Filter Control register (RCM\_RPFC)..........................................................................................324 +13.2.4 +Reset Pin Filter Width register (RCM\_RPFW)...........................................................................................325 +13.2.5 +Mode Register (RCM\_MR).........................................................................................................................327 +Chapter 14 +System Mode Controller +14.1 +Introduction...................................................................................................................................................................329 +14.2 +Modes of operation.......................................................................................................................................................329 +14.3 +Memory map and register descriptions.........................................................................................................................331 +14.3.1 +Power Mode Protection register (SMC\_PMPROT).....................................................................................332 +14.3.2 +Power Mode Control register (SMC\_PMCTRL).........................................................................................333 +14.3.3 +VLLS Control register (SMC\_VLLSCTRL)...............................................................................................334 +14.3.4 +Power Mode Status register (SMC\_PMSTAT)...........................................................................................335 +14.4 +Functional description...................................................................................................................................................336 +14.4.1 +Power mode transitions................................................................................................................................336 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +12 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 12](pdf-image://page_12_img_1) + +## Page 13 + +Section number +Title +Page +14.4.2 +Power mode entry/exit sequencing..............................................................................................................339 +14.4.3 +Run modes....................................................................................................................................................341 +14.4.4 +Wait modes..................................................................................................................................................343 +14.4.5 +Stop modes...................................................................................................................................................344 +14.4.6 +Debug in low power modes.........................................................................................................................347 +Chapter 15 +Power Management Controller +15.1 +Introduction...................................................................................................................................................................349 +15.2 +Features.........................................................................................................................................................................349 +15.3 +Low-voltage detect (LVD) system................................................................................................................................349 +15.3.1 +LVD reset operation.....................................................................................................................................350 +15.3.2 +LVD interrupt operation...............................................................................................................................350 +15.3.3 +Low-voltage warning (LVW) interrupt operation.......................................................................................350 +15.4 +I/O retention..................................................................................................................................................................351 +15.5 +Memory map and register descriptions.........................................................................................................................351 +15.5.1 +Low Voltage Detect Status And Control 1 register (PMC\_LVDSC1)........................................................352 +15.5.2 +Low Voltage Detect Status And Control 2 register (PMC\_LVDSC2)........................................................353 +15.5.3 +Regulator Status And Control register (PMC\_REGSC)..............................................................................354 +Chapter 16 +Low-Leakage Wakeup Unit (LLWU) +16.1 +Introduction...................................................................................................................................................................357 +16.1.1 +Features........................................................................................................................................................357 +16.1.2 +Modes of operation......................................................................................................................................358 +16.1.3 +Block diagram..............................................................................................................................................359 +16.2 +LLWU signal descriptions............................................................................................................................................360 +16.3 +Memory map/register definition...................................................................................................................................361 +16.3.1 +LLWU Pin Enable 1 register (LLWU\_PE1)................................................................................................362 +16.3.2 +LLWU Pin Enable 2 register (LLWU\_PE2)................................................................................................363 +16.3.3 +LLWU Pin Enable 3 register (LLWU\_PE3)................................................................................................364 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +13 +General Business Information + +![Image 1 from page 13](pdf-image://page_13_img_1) + +## Page 14 + +Section number +Title +Page +16.3.4 +LLWU Pin Enable 4 register (LLWU\_PE4)................................................................................................365 +16.3.5 +LLWU Module Enable register (LLWU\_ME)............................................................................................366 +16.3.6 +LLWU Flag 1 register (LLWU\_F1).............................................................................................................368 +16.3.7 +LLWU Flag 2 register (LLWU\_F2).............................................................................................................369 +16.3.8 +LLWU Flag 3 register (LLWU\_F3).............................................................................................................371 +16.3.9 +LLWU Pin Filter 1 register (LLWU\_FILT1)..............................................................................................373 +16.3.10 +LLWU Pin Filter 2 register (LLWU\_FILT2)..............................................................................................374 +16.3.11 +LLWU Reset Enable register (LLWU\_RST)...............................................................................................375 +16.4 +Functional description...................................................................................................................................................376 +16.4.1 +LLS mode.....................................................................................................................................................376 +16.4.2 +VLLS modes................................................................................................................................................376 +16.4.3 +Initialization.................................................................................................................................................377 +Chapter 17 +Miscellaneous Control Module (MCM) +17.1 +Introduction...................................................................................................................................................................379 +17.1.1 +Features........................................................................................................................................................379 +17.2 +Memory map/register descriptions...............................................................................................................................379 +17.2.1 +Crossbar Switch (AXBS) Slave Configuration (MCM\_PLASC)................................................................380 +17.2.2 +Crossbar Switch (AXBS) Master Configuration (MCM\_PLAMC)............................................................381 +17.2.3 +Control Register (MCM\_CR)......................................................................................................................381 +17.2.4 +Interrupt Status Register (MCM\_ISR).........................................................................................................383 +17.2.5 +ETB Counter Control register (MCM\_ETBCC)..........................................................................................384 +17.2.6 +ETB Reload register (MCM\_ETBRL).........................................................................................................385 +17.2.7 +ETB Counter Value register (MCM\_ETBCNT)..........................................................................................385 +17.2.8 +Process ID register (MCM\_PID).................................................................................................................386 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +14 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 14](pdf-image://page_14_img_1) + +## Page 15 + +Section number +Title +Page +17.3 +Functional description...................................................................................................................................................386 +17.3.1 +Interrupts......................................................................................................................................................386 +Chapter 18 +Crossbar Switch (AXBS) +18.1 +Introduction...................................................................................................................................................................389 +18.1.1 +Features........................................................................................................................................................389 +18.2 +Memory Map / Register Definition...............................................................................................................................390 +18.2.1 +Priority Registers Slave (AXBS\_PRSn)......................................................................................................391 +18.2.2 +Control Register (AXBS\_CRSn).................................................................................................................394 +18.2.3 +Master General Purpose Control Register (AXBS\_MGPCRn)...................................................................396 +18.3 +Functional Description..................................................................................................................................................396 +18.3.1 +General operation.........................................................................................................................................396 +18.3.2 +Register coherency.......................................................................................................................................398 +18.3.3 +Arbitration....................................................................................................................................................398 +18.4 +Initialization/application information...........................................................................................................................401 +Chapter 19 +Memory Protection Unit (MPU) +19.1 +Introduction...................................................................................................................................................................403 +19.2 +Overview.......................................................................................................................................................................403 +19.2.1 +Block diagram..............................................................................................................................................403 +19.2.2 +Features........................................................................................................................................................404 +19.3 +Memory map/register definition...................................................................................................................................405 +19.3.1 +Control/Error Status Register (MPU\_CESR)..............................................................................................409 +19.3.2 +Error Address Register, slave port n (MPU\_EARn)....................................................................................410 +19.3.3 +Error Detail Register, slave port n (MPU\_EDRn).......................................................................................411 +19.3.4 +Region Descriptor n, Word 0 (MPU\_RGDn\_WORD0)..............................................................................412 +19.3.5 +Region Descriptor n, Word 1 (MPU\_RGDn\_WORD1)..............................................................................412 +19.3.6 +Region Descriptor n, Word 2 (MPU\_RGDn\_WORD2)..............................................................................413 +19.3.7 +Region Descriptor n, Word 3 (MPU\_RGDn\_WORD3)..............................................................................416 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +15 +General Business Information + +![Image 1 from page 15](pdf-image://page_15_img_1) + +## Page 16 + +Section number +Title +Page +19.3.8 +Region Descriptor Alternate Access Control n (MPU\_RGDAACn)...........................................................417 +19.4 +Functional description...................................................................................................................................................419 +19.4.1 +Access evaluation macro..............................................................................................................................419 +19.4.2 +Putting it all together and error terminations...............................................................................................420 +19.4.3 +Power management......................................................................................................................................421 +19.5 +Initialization information..............................................................................................................................................421 +19.6 +Application information................................................................................................................................................421 +Chapter 20 +Peripheral Bridge (AIPS-Lite) +20.1 +Introduction...................................................................................................................................................................425 +20.1.1 +Features........................................................................................................................................................425 +20.1.2 +General operation.........................................................................................................................................426 +20.2 +Memory map/register definition...................................................................................................................................426 +20.2.1 +Master Privilege Register A (AIPSx\_MPRA).............................................................................................428 +20.2.2 +Peripheral Access Control Register (AIPSx\_PACRn).................................................................................431 +20.2.3 +Peripheral Access Control Register (AIPSx\_PACRn).................................................................................436 +20.3 +Functional description...................................................................................................................................................441 +20.3.1 +Access support.............................................................................................................................................441 +Chapter 21 +Direct Memory Access Multiplexer (DMAMUX) +21.1 +Introduction...................................................................................................................................................................443 +21.1.1 +Overview......................................................................................................................................................443 +21.1.2 +Features........................................................................................................................................................444 +21.1.3 +Modes of operation......................................................................................................................................444 +21.2 +External signal description............................................................................................................................................445 +21.3 +Memory map/register definition...................................................................................................................................445 +21.3.1 +Channel Configuration register (DMAMUX\_CHCFGn)............................................................................446 +21.4 +Functional description...................................................................................................................................................447 +21.4.1 +DMA channels with periodic triggering capability......................................................................................447 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +16 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 16](pdf-image://page_16_img_1) + +## Page 17 + +Section number +Title +Page +21.4.2 +DMA channels with no triggering capability...............................................................................................449 +21.4.3 +"Always enabled" DMA sources.................................................................................................................449 +21.5 +Initialization/application information...........................................................................................................................450 +21.5.1 +Reset.............................................................................................................................................................451 +21.5.2 +Enabling and configuring sources................................................................................................................451 +Chapter 22 +Direct Memory Access Controller (eDMA) +22.1 +Introduction...................................................................................................................................................................455 +22.1.1 +Block diagram..............................................................................................................................................455 +22.1.2 +Block parts...................................................................................................................................................456 +22.1.3 +Features........................................................................................................................................................457 +22.2 +Modes of operation.......................................................................................................................................................459 +22.3 +Memory map/register definition...................................................................................................................................459 +22.3.1 +Control Register (DMA\_CR).......................................................................................................................470 +22.3.2 +Error Status Register (DMA\_ES)................................................................................................................472 +22.3.3 +Enable Request Register (DMA\_ ERQ ).....................................................................................................474 +22.3.4 +Enable Error Interrupt Register (DMA\_ EEI ).............................................................................................476 +22.3.5 +Clear Enable Error Interrupt Register (DMA\_CEEI)..................................................................................479 +22.3.6 +Set Enable Error Interrupt Register (DMA\_SEEI)......................................................................................480 +22.3.7 +Clear Enable Request Register (DMA\_CERQ)...........................................................................................481 +22.3.8 +Set Enable Request Register (DMA\_SERQ)...............................................................................................482 +22.3.9 +Clear DONE Status Bit Register (DMA\_CDNE)........................................................................................483 +22.3.10 +Set START Bit Register (DMA\_SSRT)......................................................................................................484 +22.3.11 +Clear Error Register (DMA\_CERR)............................................................................................................485 +22.3.12 +Clear Interrupt Request Register (DMA\_CINT).........................................................................................486 +22.3.13 +Interrupt Request Register (DMA\_ INT )....................................................................................................487 +22.3.14 +Error Register (DMA\_ ERR )......................................................................................................................489 +22.3.15 +Hardware Request Status Register (DMA\_ HRS )......................................................................................492 +22.3.16 +Channel n Priority Register (DMA\_DCHPRIn)..........................................................................................494 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +17 +General Business Information + +![Image 1 from page 17](pdf-image://page_17_img_1) + +## Page 18 + +Section number +Title +Page +22.3.17 +TCD Source Address (DMA\_TCDn\_SADDR)...........................................................................................495 +22.3.18 +TCD Signed Source Address Offset (DMA\_TCDn\_SOFF)........................................................................495 +22.3.19 +TCD Transfer Attributes (DMA\_TCDn\_ATTR).........................................................................................496 +22.3.20 +TCD Minor Byte Count (Minor Loop Disabled) (DMA\_TCDn\_NBYTES\_MLNO).................................497 +22.3.21 +TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) +(DMA\_TCDn\_NBYTES\_MLOFFNO).......................................................................................................497 +22.3.22 +TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) +(DMA\_TCDn\_NBYTES\_MLOFFYES).....................................................................................................498 +22.3.23 +TCD Last Source Address Adjustment (DMA\_TCDn\_SLAST).................................................................500 +22.3.24 +TCD Destination Address (DMA\_TCDn\_DADDR)...................................................................................500 +22.3.25 +TCD Signed Destination Address Offset (DMA\_TCDn\_DOFF)................................................................501 +22.3.26 +TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) +(DMA\_TCDn\_CITER\_ELINKYES)...........................................................................................................501 +22.3.27 +TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) +(DMA\_TCDn\_CITER\_ELINKNO)............................................................................................................502 +22.3.28 +TCD Last Destination Address Adjustment/Scatter Gather Address (DMA\_TCDn\_DLASTSGA)..........503 +22.3.29 +TCD Control and Status (DMA\_TCDn\_CSR)............................................................................................504 +22.3.30 +TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) +(DMA\_TCDn\_BITER\_ELINKYES)...........................................................................................................506 +22.3.31 +TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) +(DMA\_TCDn\_BITER\_ELINKNO)............................................................................................................507 +22.4 +Functional description...................................................................................................................................................508 +22.4.1 +eDMA basic data flow.................................................................................................................................508 +22.4.2 +Error reporting and handling........................................................................................................................511 +22.4.3 +Channel preemption.....................................................................................................................................513 +22.4.4 +Performance.................................................................................................................................................513 +22.5 +Initialization/application information...........................................................................................................................518 +22.5.1 +eDMA initialization.....................................................................................................................................518 +22.5.2 +Programming errors.....................................................................................................................................520 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +18 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 18](pdf-image://page_18_img_1) + +## Page 19 + +Section number +Title +Page +22.5.3 +Arbitration mode considerations..................................................................................................................520 +22.5.4 +Performing DMA transfers (examples)........................................................................................................521 +22.5.5 +Monitoring transfer descriptor status...........................................................................................................525 +22.5.6 +Channel Linking...........................................................................................................................................526 +22.5.7 +Dynamic programming................................................................................................................................528 +Chapter 23 +External Watchdog Monitor (EWM) +23.1 +Introduction...................................................................................................................................................................533 +23.1.1 +Features........................................................................................................................................................533 +23.1.2 +Modes of Operation.....................................................................................................................................534 +23.1.3 +Block Diagram.............................................................................................................................................535 +23.2 +EWM Signal Descriptions............................................................................................................................................536 +23.3 +Memory Map/Register Definition.................................................................................................................................536 +23.3.1 +Control Register (EWM\_CTRL).................................................................................................................536 +23.3.2 +Service Register (EWM\_SERV)..................................................................................................................537 +23.3.3 +Compare Low Register (EWM\_CMPL)......................................................................................................537 +23.3.4 +Compare High Register (EWM\_CMPH).....................................................................................................538 +23.3.5 +Clock Prescaler Register (EWM\_CLKPRESCALER)................................................................................539 +23.4 +Functional Description..................................................................................................................................................539 +23.4.1 +The EWM\_out Signal..................................................................................................................................539 +23.4.2 +The EWM\_in Signal....................................................................................................................................540 +23.4.3 +EWM Counter..............................................................................................................................................541 +23.4.4 +EWM Compare Registers............................................................................................................................541 +23.4.5 +EWM Refresh Mechanism...........................................................................................................................541 +23.4.6 +EWM Interrupt.............................................................................................................................................542 +23.4.7 +Counter clock prescaler................................................................................................................................542 +Chapter 24 +Watchdog Timer (WDOG) +24.1 +Introduction...................................................................................................................................................................543 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +19 +General Business Information + +![Image 1 from page 19](pdf-image://page_19_img_1) + +## Page 20 + +Section number +Title +Page +24.2 +Features.........................................................................................................................................................................543 +24.3 +Functional overview......................................................................................................................................................545 +24.3.1 +Unlocking and updating the watchdog.........................................................................................................546 +24.3.2 +Watchdog configuration time (WCT)..........................................................................................................547 +24.3.3 +Refreshing the watchdog..............................................................................................................................548 +24.3.4 +Windowed mode of operation......................................................................................................................548 +24.3.5 +Watchdog disabled mode of operation.........................................................................................................548 +24.3.6 +Low-power modes of operation...................................................................................................................549 +24.3.7 +Debug modes of operation...........................................................................................................................549 +24.4 +Testing the watchdog....................................................................................................................................................550 +24.4.1 +Quick test.....................................................................................................................................................550 +24.4.2 +Byte test........................................................................................................................................................551 +24.5 +Backup reset generator..................................................................................................................................................552 +24.6 +Generated resets and interrupts.....................................................................................................................................552 +24.7 +Memory map and register definition.............................................................................................................................553 +24.7.1 +Watchdog Status and Control Register High (WDOG\_STCTRLH)...........................................................554 +24.7.2 +Watchdog Status and Control Register Low (WDOG\_STCTRLL)............................................................555 +24.7.3 +Watchdog Time-out Value Register High (WDOG\_TOVALH).................................................................556 +24.7.4 +Watchdog Time-out Value Register Low (WDOG\_TOVALL)..................................................................556 +24.7.5 +Watchdog Window Register High (WDOG\_WINH)..................................................................................557 +24.7.6 +Watchdog Window Register Low (WDOG\_WINL)...................................................................................557 +24.7.7 +Watchdog Refresh register (WDOG\_REFRESH).......................................................................................558 +24.7.8 +Watchdog Unlock register (WDOG\_UNLOCK).........................................................................................558 +24.7.9 +Watchdog Timer Output Register High (WDOG\_TMROUTH).................................................................558 +24.7.10 +Watchdog Timer Output Register Low (WDOG\_TMROUTL)..................................................................559 +24.7.11 +Watchdog Reset Count register (WDOG\_RSTCNT)..................................................................................559 +24.7.12 +Watchdog Prescaler register (WDOG\_PRESC)..........................................................................................560 +24.8 +Watchdog operation with 8-bit access..........................................................................................................................560 +24.8.1 +General guideline.........................................................................................................................................560 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +20 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 20](pdf-image://page_20_img_1) + +## Page 21 + +Section number +Title +Page +24.8.2 +Refresh and unlock operations with 8-bit access.........................................................................................560 +24.9 +Restrictions on watchdog operation..............................................................................................................................561 +Chapter 25 +Multipurpose Clock Generator (MCG) +25.1 +Introduction...................................................................................................................................................................565 +25.1.1 +Features........................................................................................................................................................565 +25.1.2 +Modes of Operation.....................................................................................................................................568 +25.2 +External Signal Description..........................................................................................................................................569 +25.3 +Memory Map/Register Definition.................................................................................................................................569 +25.3.1 +MCG Control 1 Register (MCG\_C1)...........................................................................................................570 +25.3.2 +MCG Control 2 Register (MCG\_C2)...........................................................................................................571 +25.3.3 +MCG Control 3 Register (MCG\_C3)...........................................................................................................572 +25.3.4 +MCG Control 4 Register (MCG\_C4)...........................................................................................................573 +25.3.5 +MCG Control 5 Register (MCG\_C5)...........................................................................................................574 +25.3.6 +MCG Control 6 Register (MCG\_C6)...........................................................................................................575 +25.3.7 +MCG Status Register (MCG\_S)..................................................................................................................577 +25.3.8 +MCG Status and Control Register (MCG\_SC)............................................................................................578 +25.3.9 +MCG Auto Trim Compare Value High Register (MCG\_ATCVH)............................................................580 +25.3.10 +MCG Auto Trim Compare Value Low Register (MCG\_ATCVL)..............................................................580 +25.3.11 +MCG Control 7 Register (MCG\_C7)...........................................................................................................580 +25.3.12 +MCG Control 8 Register (MCG\_C8)...........................................................................................................581 +25.3.13 +MCG Control 9 Register (MCG\_C9)...........................................................................................................582 +25.3.14 +MCG Control 10 Register (MCG\_C10).......................................................................................................582 +25.4 +Functional Description..................................................................................................................................................583 +25.4.1 +MCG mode state diagram............................................................................................................................583 +25.4.2 +Low Power Bit Usage..................................................................................................................................587 +25.4.3 +MCG Internal Reference Clocks..................................................................................................................587 +25.4.4 +External Reference Clock............................................................................................................................588 +25.4.5 +MCG Fixed frequency clock .......................................................................................................................588 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +21 +General Business Information + +![Image 1 from page 21](pdf-image://page_21_img_1) + +## Page 22 + +Section number +Title +Page +25.4.6 +MCG PLL clock ..........................................................................................................................................589 +25.4.7 +MCG Auto TRIM (ATM)............................................................................................................................589 +25.5 +Initialization / Application information........................................................................................................................590 +25.5.1 +MCG module initialization sequence...........................................................................................................590 +25.5.2 +Using a 32.768 kHz reference......................................................................................................................593 +25.5.3 +MCG mode switching..................................................................................................................................593 +Chapter 26 +Oscillator (OSC) +26.1 +Introduction...................................................................................................................................................................603 +26.2 +Features and Modes......................................................................................................................................................603 +26.3 +Block Diagram..............................................................................................................................................................604 +26.4 +OSC Signal Descriptions..............................................................................................................................................604 +26.5 +External Crystal / Resonator Connections....................................................................................................................605 +26.6 +External Clock Connections.........................................................................................................................................606 +26.7 +Memory Map/Register Definitions...............................................................................................................................607 +26.7.1 +OSC Memory Map/Register Definition.......................................................................................................607 +26.8 +Functional Description..................................................................................................................................................608 +26.8.1 +OSC Module States......................................................................................................................................608 +26.8.2 +OSC Module Modes.....................................................................................................................................610 +26.8.3 +Counter.........................................................................................................................................................612 +26.8.4 +Reference Clock Pin Requirements.............................................................................................................612 +26.9 +Reset..............................................................................................................................................................................612 +26.10 Low Power Modes Operation.......................................................................................................................................613 +26.11 Interrupts.......................................................................................................................................................................613 +Chapter 27 +RTC Oscillator +27.1 +Introduction...................................................................................................................................................................615 +27.1.1 +Features and Modes.....................................................................................................................................615 +27.1.2 +Block Diagram.............................................................................................................................................615 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +22 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 22](pdf-image://page_22_img_1) + +## Page 23 + +Section number +Title +Page +27.2 +RTC Signal Descriptions..............................................................................................................................................616 +27.2.1 +EXTAL32 — Oscillator Input.....................................................................................................................616 +27.2.2 +XTAL32 — Oscillator Output.....................................................................................................................616 +27.3 +External Crystal Connections.......................................................................................................................................617 +27.4 +Memory Map/Register Descriptions.............................................................................................................................617 +27.5 +Functional Description..................................................................................................................................................617 +27.6 +Reset Overview.............................................................................................................................................................618 +27.7 +Interrupts.......................................................................................................................................................................618 +Chapter 28 +Flash Memory Controller (FMC) +28.1 +Introduction...................................................................................................................................................................619 +28.1.1 +Overview......................................................................................................................................................619 +28.1.2 +Features........................................................................................................................................................620 +28.2 +Modes of operation.......................................................................................................................................................620 +28.3 +External signal description............................................................................................................................................621 +28.4 +Memory map and register descriptions.........................................................................................................................621 +28.4.1 +Flash Access Protection Register (FMC\_PFAPR).......................................................................................627 +28.4.2 +Flash Bank 0 Control Register (FMC\_PFB0CR)........................................................................................630 +28.4.3 +Flash Bank 1 Control Register (FMC\_PFB1CR)........................................................................................633 +28.4.4 +Cache Tag Storage (FMC\_TAGVDW0Sn).................................................................................................635 +28.4.5 +Cache Tag Storage (FMC\_TAGVDW1Sn).................................................................................................636 +28.4.6 +Cache Tag Storage (FMC\_TAGVDW2Sn).................................................................................................637 +28.4.7 +Cache Tag Storage (FMC\_TAGVDW3Sn).................................................................................................638 +28.4.8 +Cache Data Storage (upper word) (FMC\_DATAW0SnU)..........................................................................638 +28.4.9 +Cache Data Storage (lower word) (FMC\_DATAW0SnL)..........................................................................639 +28.4.10 +Cache Data Storage (upper word) (FMC\_DATAW1SnU)..........................................................................639 +28.4.11 +Cache Data Storage (lower word) (FMC\_DATAW1SnL)..........................................................................640 +28.4.12 +Cache Data Storage (upper word) (FMC\_DATAW2SnU)..........................................................................640 +28.4.13 +Cache Data Storage (lower word) (FMC\_DATAW2SnL)..........................................................................641 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +23 +General Business Information + +![Image 1 from page 23](pdf-image://page_23_img_1) + +## Page 24 + +Section number +Title +Page +28.4.14 +Cache Data Storage (upper word) (FMC\_DATAW3SnU)..........................................................................641 +28.4.15 +Cache Data Storage (lower word) (FMC\_DATAW3SnL)..........................................................................642 +28.5 +Functional description...................................................................................................................................................642 +28.5.1 +Default configuration...................................................................................................................................642 +28.5.2 +Configuration options..................................................................................................................................643 +28.5.3 +Wait states....................................................................................................................................................643 +28.5.4 +Speculative reads..........................................................................................................................................644 +28.6 +Initialization and application information.....................................................................................................................645 +Chapter 29 +Flash Memory Module (FTFL) +29.1 +Introduction...................................................................................................................................................................647 +29.1.1 +Features........................................................................................................................................................648 +29.1.2 +Block Diagram.............................................................................................................................................650 +29.1.3 +Glossary.......................................................................................................................................................651 +29.2 +External Signal Description..........................................................................................................................................653 +29.3 +Memory Map and Registers..........................................................................................................................................653 +29.3.1 +Flash Configuration Field Description.........................................................................................................654 +29.3.2 +Program Flash IFR Map...............................................................................................................................654 +29.3.3 +Data Flash IFR Map.....................................................................................................................................655 +29.3.4 +Register Descriptions...................................................................................................................................657 +29.4 +Functional Description..................................................................................................................................................670 +29.4.1 +Program Flash Memory Swap......................................................................................................................670 +29.4.2 +Flash Protection............................................................................................................................................670 +29.4.3 +FlexNVM Description..................................................................................................................................672 +29.4.4 +Interrupts......................................................................................................................................................677 +29.4.5 +Flash Operation in Low-Power Modes........................................................................................................678 +29.4.6 +Functional Modes of Operation...................................................................................................................678 +29.4.7 +Flash Reads and Ignored Writes..................................................................................................................678 +29.4.8 +Read While Write (RWW)...........................................................................................................................679 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +24 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 24](pdf-image://page_24_img_1) + +## Page 25 + +Section number +Title +Page +29.4.9 +Flash Program and Erase..............................................................................................................................679 +29.4.10 +Flash Command Operations.........................................................................................................................679 +29.4.11 +Margin Read Commands.............................................................................................................................688 +29.4.12 +Flash Command Description........................................................................................................................689 +29.4.13 +Security........................................................................................................................................................717 +29.4.14 +Reset Sequence............................................................................................................................................719 +Chapter 30 +External Bus Interface (FlexBus) +30.1 +Introduction...................................................................................................................................................................721 +30.1.1 +Definition.....................................................................................................................................................721 +30.1.2 +Features........................................................................................................................................................722 +30.2 +Signal descriptions........................................................................................................................................................722 +30.3 +Memory Map/Register Definition.................................................................................................................................725 +30.3.1 +Chip Select Address Register (FB\_CSARn)................................................................................................727 +30.3.2 +Chip Select Mask Register (FB\_CSMRn)...................................................................................................727 +30.3.3 +Chip Select Control Register (FB\_CSCRn).................................................................................................728 +30.3.4 +Chip Select port Multiplexing Control Register (FB\_CSPMCR)................................................................731 +30.4 +Functional description...................................................................................................................................................732 +30.4.1 +Modes of operation......................................................................................................................................733 +30.4.2 +Address comparison.....................................................................................................................................733 +30.4.3 +Address driven on address bus.....................................................................................................................733 +30.4.4 +Connecting address/data lines......................................................................................................................733 +30.4.5 +Bit ordering..................................................................................................................................................734 +30.4.6 +Data transfer signals.....................................................................................................................................734 +30.4.7 +Signal transitions..........................................................................................................................................734 +30.4.8 +Data-byte alignment and physical connections............................................................................................734 +30.4.9 +Address/data bus multiplexing.....................................................................................................................735 +30.4.10 +Data transfer states.......................................................................................................................................736 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +25 +General Business Information + +![Image 1 from page 25](pdf-image://page_25_img_1) + +## Page 26 + +Section number +Title +Page +30.4.11 +FlexBus Timing Examples...........................................................................................................................737 +30.4.12 +Burst cycles..................................................................................................................................................756 +30.4.13 +Extended Transfer Start/Address Latch Enable...........................................................................................764 +30.4.14 +Bus errors.....................................................................................................................................................765 +30.5 +Initialization/Application Information..........................................................................................................................766 +30.5.1 +Initializing a chip-select...............................................................................................................................766 +30.5.2 +Reconfiguring a chip-select.........................................................................................................................766 +Chapter 31 +EzPort +31.1 +Overview.......................................................................................................................................................................767 +31.1.1 +Introduction..................................................................................................................................................767 +31.1.2 +Features........................................................................................................................................................768 +31.1.3 +Modes of operation......................................................................................................................................768 +31.2 +External signal description............................................................................................................................................769 +31.2.1 +EzPort Clock (EZP\_CK)..............................................................................................................................769 +31.2.2 +EzPort Chip Select (EZP\_CS)......................................................................................................................769 +31.2.3 +EzPort Serial Data In (EZP\_D)....................................................................................................................770 +31.2.4 +EzPort Serial Data Out (EZP\_Q).................................................................................................................770 +31.3 +Command definition.....................................................................................................................................................770 +31.3.1 +Command descriptions.................................................................................................................................771 +31.4 +Flash memory map for EzPort access...........................................................................................................................777 +Chapter 32 +Cyclic Redundancy Check (CRC) +32.1 +Introduction...................................................................................................................................................................779 +32.1.1 +Features........................................................................................................................................................779 +32.1.2 +Block diagram..............................................................................................................................................780 +32.1.3 +Modes of operation......................................................................................................................................780 +32.2 +Memory map and register descriptions.........................................................................................................................780 +32.2.1 +CRC Data register (CRC\_CRC)..................................................................................................................781 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +26 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 26](pdf-image://page_26_img_1) + +## Page 27 + +Section number +Title +Page +32.2.2 +CRC Polynomial register (CRC\_GPOLY)..................................................................................................782 +32.2.3 +CRC Control register (CRC\_CTRL)............................................................................................................783 +32.3 +Functional description...................................................................................................................................................784 +32.3.1 +CRC initialization/reinitialization................................................................................................................784 +32.3.2 +CRC calculations..........................................................................................................................................784 +32.3.3 +Transpose feature.........................................................................................................................................785 +32.3.4 +CRC result complement...............................................................................................................................787 +Chapter 33 +Memory-Mapped Cryptographic Acceleration Unit (MMCAU) +33.1 +Introduction...................................................................................................................................................................789 +33.2 +MMCAU Block Diagram.............................................................................................................................................789 +33.3 +Overview.......................................................................................................................................................................791 +33.4 +Features.........................................................................................................................................................................792 +33.5 +Memory map/register definition...................................................................................................................................792 +33.5.1 +Status Register (CAU\_CASR).....................................................................................................................794 +33.5.2 +Accumulator (CAU\_CAA)..........................................................................................................................795 +33.5.3 +General Purpose Register (CAU\_CAn).......................................................................................................795 +33.6 +Functional description...................................................................................................................................................796 +33.6.1 +MMCAU programming model....................................................................................................................796 +33.6.2 +MMCAU integrity checks............................................................................................................................798 +33.6.3 +CAU commands...........................................................................................................................................800 +33.7 +Application/initialization information..........................................................................................................................807 +33.7.1 +Code example...............................................................................................................................................807 +33.7.2 +Assembler equate values..............................................................................................................................807 +Chapter 34 +Random Number Generator Accelerator (RNGA) +34.1 +Introduction...................................................................................................................................................................809 +34.1.1 +Overview......................................................................................................................................................809 +34.2 +Modes of operation.......................................................................................................................................................810 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +27 +General Business Information + +![Image 1 from page 27](pdf-image://page_27_img_1) + +## Page 28 + +Section number +Title +Page +34.3 +Memory map and register definition.............................................................................................................................810 +34.3.1 +RNGA Control Register (RNG\_CR)...........................................................................................................811 +34.3.2 +RNGA Status Register (RNG\_SR)..............................................................................................................813 +34.3.3 +RNGA Entropy Register (RNG\_ER)...........................................................................................................815 +34.3.4 +RNGA Output Register (RNG\_OR)............................................................................................................816 +34.4 +Functional description...................................................................................................................................................816 +34.4.1 +RNGA Output Register................................................................................................................................817 +34.4.2 +RNGA Core/Control Logic Block...............................................................................................................817 +34.5 +Initialization/application information...........................................................................................................................818 +Chapter 35 +Analog-to-Digital Converter (ADC) +35.1 +Introduction...................................................................................................................................................................819 +35.1.1 +Features........................................................................................................................................................819 +35.1.2 +Block diagram..............................................................................................................................................820 +35.2 +ADC Signal Descriptions..............................................................................................................................................821 +35.2.1 +Analog Power (VDDA)...............................................................................................................................822 +35.2.2 +Analog Ground (VSSA)...............................................................................................................................822 +35.2.3 +Voltage Reference Select.............................................................................................................................822 +35.2.4 +Analog Channel Inputs (ADx).....................................................................................................................823 +35.2.5 +Differential Analog Channel Inputs (DADx)...............................................................................................823 +35.3 +Register definition.........................................................................................................................................................823 +35.3.1 +ADC Status and Control Registers 1 (ADCx\_SC1n)...................................................................................826 +35.3.2 +ADC Configuration Register 1 (ADCx\_CFG1)...........................................................................................829 +35.3.3 +ADC Configuration Register 2 (ADCx\_CFG2)...........................................................................................831 +35.3.4 +ADC Data Result Register (ADCx\_Rn).......................................................................................................832 +35.3.5 +Compare Value Registers (ADCx\_CVn).....................................................................................................833 +35.3.6 +Status and Control Register 2 (ADCx\_SC2)................................................................................................834 +35.3.7 +Status and Control Register 3 (ADCx\_SC3)................................................................................................836 +35.3.8 +ADC Offset Correction Register (ADCx\_OFS)...........................................................................................838 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +28 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 28](pdf-image://page_28_img_1) + +## Page 29 + +Section number +Title +Page +35.3.9 +ADC Plus-Side Gain Register (ADCx\_PG).................................................................................................838 +35.3.10 +ADC Minus-Side Gain Register (ADCx\_MG)............................................................................................839 +35.3.11 +ADC Plus-Side General Calibration Value Register (ADCx\_CLPD).........................................................839 +35.3.12 +ADC Plus-Side General Calibration Value Register (ADCx\_CLPS)..........................................................840 +35.3.13 +ADC Plus-Side General Calibration Value Register (ADCx\_CLP4)..........................................................840 +35.3.14 +ADC Plus-Side General Calibration Value Register (ADCx\_CLP3)..........................................................841 +35.3.15 +ADC Plus-Side General Calibration Value Register (ADCx\_CLP2)..........................................................841 +35.3.16 +ADC Plus-Side General Calibration Value Register (ADCx\_CLP1)..........................................................842 +35.3.17 +ADC Plus-Side General Calibration Value Register (ADCx\_CLP0)..........................................................842 +35.3.18 +ADC PGA Register (ADCx\_PGA)..............................................................................................................843 +35.3.19 +ADC Minus-Side General Calibration Value Register (ADCx\_CLMD).....................................................844 +35.3.20 +ADC Minus-Side General Calibration Value Register (ADCx\_CLMS).....................................................845 +35.3.21 +ADC Minus-Side General Calibration Value Register (ADCx\_CLM4).....................................................845 +35.3.22 +ADC Minus-Side General Calibration Value Register (ADCx\_CLM3).....................................................846 +35.3.23 +ADC Minus-Side General Calibration Value Register (ADCx\_CLM2).....................................................846 +35.3.24 +ADC Minus-Side General Calibration Value Register (ADCx\_CLM1).....................................................847 +35.3.25 +ADC Minus-Side General Calibration Value Register (ADCx\_CLM0).....................................................847 +35.4 +Functional description...................................................................................................................................................847 +35.4.1 +PGA functional description..........................................................................................................................848 +35.4.2 +Clock select and divide control....................................................................................................................849 +35.4.3 +Voltage reference selection..........................................................................................................................849 +35.4.4 +Hardware trigger and channel selects..........................................................................................................850 +35.4.5 +Conversion control.......................................................................................................................................851 +35.4.6 +Automatic compare function........................................................................................................................858 +35.4.7 +Calibration function.....................................................................................................................................859 +35.4.8 +User-defined offset function........................................................................................................................861 +35.4.9 +Temperature sensor......................................................................................................................................862 +35.4.10 +MCU wait mode operation...........................................................................................................................863 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +29 +General Business Information + +![Image 1 from page 29](pdf-image://page_29_img_1) + +## Page 30 + +Section number +Title +Page +35.4.11 +MCU Normal Stop mode operation.............................................................................................................863 +35.4.12 +MCU Low-Power Stop mode operation......................................................................................................864 +35.5 +Initialization information..............................................................................................................................................865 +35.5.1 +ADC module initialization example............................................................................................................865 +35.6 +Application information................................................................................................................................................867 +35.6.1 +External pins and routing.............................................................................................................................867 +35.6.2 +Sources of error............................................................................................................................................869 +Chapter 36 +Comparator (CMP) +36.1 +Introduction...................................................................................................................................................................875 +36.2 +CMP features................................................................................................................................................................875 +36.3 +6-bit DAC key features.................................................................................................................................................876 +36.4 +ANMUX key features...................................................................................................................................................877 +36.5 +CMP, DAC and ANMUX diagram...............................................................................................................................877 +36.6 +CMP block diagram......................................................................................................................................................878 +36.7 +Memory map/register definitions..................................................................................................................................880 +36.7.1 +CMP Control Register 0 (CMPx\_CR0).......................................................................................................880 +36.7.2 +CMP Control Register 1 (CMPx\_CR1).......................................................................................................881 +36.7.3 +CMP Filter Period Register (CMPx\_FPR)...................................................................................................883 +36.7.4 +CMP Status and Control Register (CMPx\_SCR).........................................................................................883 +36.7.5 +DAC Control Register (CMPx\_DACCR)....................................................................................................884 +36.7.6 +MUX Control Register (CMPx\_MUXCR)..................................................................................................885 +36.8 +CMP functional description..........................................................................................................................................886 +36.8.1 +CMP functional modes.................................................................................................................................886 +36.8.2 +Power modes................................................................................................................................................895 +36.8.3 +Startup and operation...................................................................................................................................896 +36.8.4 +Low-pass filter.............................................................................................................................................897 +36.9 +CMP interrupts..............................................................................................................................................................899 +36.10 CMP DMA support.......................................................................................................................................................899 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +30 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 30](pdf-image://page_30_img_1) + +## Page 31 + +Section number +Title +Page +36.11 Digital-to-analog converter block diagram...................................................................................................................900 +36.12 DAC functional description..........................................................................................................................................900 +36.12.1 +Voltage reference source select....................................................................................................................900 +36.13 DAC resets....................................................................................................................................................................901 +36.14 DAC clocks...................................................................................................................................................................901 +36.15 DAC interrupts..............................................................................................................................................................901 +Chapter 37 +12-bit Digital-to-Analog Converter (DAC) +37.1 +Introduction...................................................................................................................................................................903 +37.2 +Features.........................................................................................................................................................................903 +37.3 +Block diagram...............................................................................................................................................................904 +37.4 +Memory map/register definition...................................................................................................................................905 +37.4.1 +DAC Data Low Register (DACx\_DATnL).................................................................................................906 +37.4.2 +DAC Data High Register (DACx\_DATnH)................................................................................................906 +37.4.3 +DAC Status Register (DACx\_SR)...............................................................................................................907 +37.4.4 +DAC Control Register (DACx\_C0).............................................................................................................908 +37.4.5 +DAC Control Register 1 (DACx\_C1)..........................................................................................................909 +37.4.6 +DAC Control Register 2 (DACx\_C2)..........................................................................................................910 +37.5 +Functional description...................................................................................................................................................910 +37.5.1 +DAC data buffer operation...........................................................................................................................910 +37.5.2 +DMA operation............................................................................................................................................911 +37.5.3 +Resets...........................................................................................................................................................911 +37.5.4 +Low-Power mode operation.........................................................................................................................912 +Chapter 38 +Voltage Reference (VREFV1) +38.1 +Introduction...................................................................................................................................................................913 +38.1.1 +Overview......................................................................................................................................................914 +38.1.2 +Features........................................................................................................................................................914 +38.1.3 +Modes of Operation.....................................................................................................................................915 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +31 +General Business Information + +![Image 1 from page 31](pdf-image://page_31_img_1) + +## Page 32 + +Section number +Title +Page +38.1.4 +VREF Signal Descriptions...........................................................................................................................915 +38.2 +Memory Map and Register Definition..........................................................................................................................916 +38.2.1 +VREF Trim Register (VREF\_TRM)............................................................................................................916 +38.2.2 +VREF Status and Control Register (VREF\_SC)..........................................................................................917 +38.3 +Functional Description..................................................................................................................................................918 +38.3.1 +Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................918 +38.3.2 +Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................919 +38.4 +Initialization/Application Information..........................................................................................................................920 +Chapter 39 +Programmable Delay Block (PDB) +39.1 +Introduction...................................................................................................................................................................921 +39.1.1 +Features........................................................................................................................................................921 +39.1.2 +Implementation............................................................................................................................................922 +39.1.3 +Back-to-back acknowledgment connections................................................................................................923 +39.1.4 +DAC External Trigger Input Connections...................................................................................................923 +39.1.5 +Block diagram..............................................................................................................................................923 +39.1.6 +Modes of operation......................................................................................................................................925 +39.2 +PDB signal descriptions................................................................................................................................................925 +39.3 +Memory map and register definition.............................................................................................................................925 +39.3.1 +Status and Control Register (PDBx\_SC).....................................................................................................927 +39.3.2 +Modulus Register (PDBx\_MOD).................................................................................................................929 +39.3.3 +Counter Register (PDBx\_CNT)...................................................................................................................930 +39.3.4 +Interrupt Delay Register (PDBx\_IDLY)......................................................................................................930 +39.3.5 +Channel n Control Register 1 (PDBx\_CHnC1)...........................................................................................931 +39.3.6 +Channel n Status Register (PDBx\_CHnS)...................................................................................................932 +39.3.7 +Channel n Delay 0 Register (PDBx\_CHnDLY0)........................................................................................932 +39.3.8 +Channel n Delay 1 Register (PDBx\_CHnDLY1)........................................................................................933 +39.3.9 +DAC Interval Trigger n Control Register (PDBx\_DACINTCn).................................................................933 +39.3.10 +DAC Interval n Register (PDBx\_DACINTn)..............................................................................................934 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +32 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 32](pdf-image://page_32_img_1) + +## Page 33 + +Section number +Title +Page +39.3.11 +Pulse-Out n Enable Register (PDBx\_POEN)...............................................................................................934 +39.3.12 +Pulse-Out n Delay Register (PDBx\_POnDLY)...........................................................................................935 +39.4 +Functional description...................................................................................................................................................935 +39.4.1 +PDB pre-trigger and trigger outputs.............................................................................................................935 +39.4.2 +PDB trigger input source selection..............................................................................................................937 +39.4.3 +DAC interval trigger outputs........................................................................................................................937 +39.4.4 +Pulse-Out's...................................................................................................................................................938 +39.4.5 +Updating the delay registers.........................................................................................................................938 +39.4.6 +Interrupts......................................................................................................................................................940 +39.4.7 +DMA............................................................................................................................................................940 +39.5 +Application information................................................................................................................................................940 +39.5.1 +Impact of using the prescaler and multiplication factor on timing resolution.............................................940 +Chapter 40 +FlexTimer Module (FTM) +40.1 +Introduction...................................................................................................................................................................943 +40.1.1 +FlexTimer philosophy..................................................................................................................................943 +40.1.2 +Features........................................................................................................................................................944 +40.1.3 +Modes of operation......................................................................................................................................945 +40.1.4 +Block diagram..............................................................................................................................................946 +40.2 +FTM signal descriptions...............................................................................................................................................948 +40.3 +Memory map and register definition.............................................................................................................................948 +40.3.1 +Memory map................................................................................................................................................948 +40.3.2 +Register descriptions....................................................................................................................................949 +40.3.3 +Status And Control (FTMx\_SC)..................................................................................................................955 +40.3.4 +Counter (FTMx\_CNT).................................................................................................................................956 +40.3.5 +Modulo (FTMx\_MOD)................................................................................................................................957 +40.3.6 +Channel (n) Status And Control (FTMx\_CnSC)..........................................................................................958 +40.3.7 +Channel (n) Value (FTMx\_CnV).................................................................................................................960 +40.3.8 +Counter Initial Value (FTMx\_CNTIN)........................................................................................................961 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +33 +General Business Information + +![Image 1 from page 33](pdf-image://page_33_img_1) + +## Page 34 + +Section number +Title +Page +40.3.9 +Capture And Compare Status (FTMx\_STATUS)........................................................................................961 +40.3.10 +Features Mode Selection (FTMx\_MODE)..................................................................................................963 +40.3.11 +Synchronization (FTMx\_SYNC).................................................................................................................965 +40.3.12 +Initial State For Channels Output (FTMx\_OUTINIT).................................................................................968 +40.3.13 +Output Mask (FTMx\_OUTMASK).............................................................................................................969 +40.3.14 +Function For Linked Channels (FTMx\_COMBINE)...................................................................................971 +40.3.15 +Deadtime Insertion Control (FTMx\_DEADTIME).....................................................................................976 +40.3.16 +FTM External Trigger (FTMx\_EXTTRIG).................................................................................................977 +40.3.17 +Channels Polarity (FTMx\_POL)..................................................................................................................978 +40.3.18 +Fault Mode Status (FTMx\_FMS).................................................................................................................981 +40.3.19 +Input Capture Filter Control (FTMx\_FILTER)...........................................................................................983 +40.3.20 +Fault Control (FTMx\_FLTCTRL)...............................................................................................................984 +40.3.21 +Quadrature Decoder Control And Status (FTMx\_QDCTRL)......................................................................986 +40.3.22 +Configuration (FTMx\_CONF).....................................................................................................................988 +40.3.23 +FTM Fault Input Polarity (FTMx\_FLTPOL)...............................................................................................989 +40.3.24 +Synchronization Configuration (FTMx\_SYNCONF)..................................................................................991 +40.3.25 +FTM Inverting Control (FTMx\_INVCTRL)................................................................................................993 +40.3.26 +FTM Software Output Control (FTMx\_SWOCTRL)..................................................................................994 +40.3.27 +FTM PWM Load (FTMx\_PWMLOAD).....................................................................................................996 +40.4 +Functional description...................................................................................................................................................997 +40.4.1 +Clock source.................................................................................................................................................998 +40.4.2 +Prescaler.......................................................................................................................................................999 +40.4.3 +Counter.........................................................................................................................................................999 +40.4.4 +Input Capture mode......................................................................................................................................1004 +40.4.5 +Output Compare mode.................................................................................................................................1007 +40.4.6 +Edge-Aligned PWM (EPWM) mode...........................................................................................................1008 +40.4.7 +Center-Aligned PWM (CPWM) mode........................................................................................................1010 +40.4.8 +Combine mode.............................................................................................................................................1012 +40.4.9 +Complementary mode..................................................................................................................................1020 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +34 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 34](pdf-image://page_34_img_1) + +## Page 35 + +Section number +Title +Page +40.4.10 +Registers updated from write buffers...........................................................................................................1021 +40.4.11 +PWM synchronization..................................................................................................................................1023 +40.4.12 +Inverting.......................................................................................................................................................1039 +40.4.13 +Software output control................................................................................................................................1040 +40.4.14 +Deadtime insertion.......................................................................................................................................1042 +40.4.15 +Output mask.................................................................................................................................................1045 +40.4.16 +Fault control.................................................................................................................................................1046 +40.4.17 +Polarity control.............................................................................................................................................1049 +40.4.18 +Initialization.................................................................................................................................................1050 +40.4.19 +Features priority...........................................................................................................................................1050 +40.4.20 +Channel trigger output.................................................................................................................................1051 +40.4.21 +Initialization trigger......................................................................................................................................1052 +40.4.22 +Capture Test mode.......................................................................................................................................1054 +40.4.23 +DMA............................................................................................................................................................1055 +40.4.24 +Dual Edge Capture mode.............................................................................................................................1056 +40.4.25 +Quadrature Decoder mode...........................................................................................................................1063 +40.4.26 +BDM mode...................................................................................................................................................1068 +40.4.27 +Intermediate load..........................................................................................................................................1069 +40.4.28 +Global time base (GTB)...............................................................................................................................1071 +40.5 +Reset overview..............................................................................................................................................................1072 +40.6 +FTM Interrupts..............................................................................................................................................................1074 +40.6.1 +Timer Overflow Interrupt.............................................................................................................................1074 +40.6.2 +Channel (n) Interrupt....................................................................................................................................1074 +40.6.3 +Fault Interrupt..............................................................................................................................................1074 +Chapter 41 +Periodic Interrupt Timer (PIT) +41.1 +Introduction...................................................................................................................................................................1075 +41.1.1 +Block diagram..............................................................................................................................................1075 +41.1.2 +Features........................................................................................................................................................1076 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +35 +General Business Information + +![Image 1 from page 35](pdf-image://page_35_img_1) + +## Page 36 + +Section number +Title +Page +41.2 +Signal description..........................................................................................................................................................1076 +41.3 +Memory map/register description.................................................................................................................................1077 +41.3.1 +PIT Module Control Register (PIT\_MCR)..................................................................................................1078 +41.3.2 +Timer Load Value Register (PIT\_LDVALn)...............................................................................................1078 +41.3.3 +Current Timer Value Register (PIT\_CVALn).............................................................................................1079 +41.3.4 +Timer Control Register (PIT\_TCTRLn)......................................................................................................1079 +41.3.5 +Timer Flag Register (PIT\_TFLGn)..............................................................................................................1080 +41.4 +Functional description...................................................................................................................................................1081 +41.4.1 +General operation.........................................................................................................................................1081 +41.4.2 +Interrupts......................................................................................................................................................1082 +41.4.3 +Chained timers.............................................................................................................................................1083 +41.5 +Initialization and application information.....................................................................................................................1083 +41.6 +Example configuration for chained timers....................................................................................................................1084 +Chapter 42 +Low-Power Timer (LPTMR) +42.1 +Introduction...................................................................................................................................................................1087 +42.1.1 +Features........................................................................................................................................................1087 +42.1.2 +Modes of operation......................................................................................................................................1087 +42.2 +LPTMR signal descriptions..........................................................................................................................................1088 +42.2.1 +Detailed signal descriptions.........................................................................................................................1088 +42.3 +Memory map and register definition.............................................................................................................................1089 +42.3.1 +Low Power Timer Control Status Register (LPTMRx\_CSR)......................................................................1089 +42.3.2 +Low Power Timer Prescale Register (LPTMRx\_PSR)................................................................................1091 +42.3.3 +Low Power Timer Compare Register (LPTMRx\_CMR).............................................................................1092 +42.3.4 +Low Power Timer Counter Register (LPTMRx\_CNR)...............................................................................1093 +42.4 +Functional description...................................................................................................................................................1093 +42.4.1 +LPTMR power and reset..............................................................................................................................1093 +42.4.2 +LPTMR clocking..........................................................................................................................................1093 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +36 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 36](pdf-image://page_36_img_1) + +## Page 37 + +Section number +Title +Page +42.4.3 +LPTMR prescaler/glitch filter......................................................................................................................1094 +42.4.4 +LPTMR compare..........................................................................................................................................1095 +42.4.5 +LPTMR counter...........................................................................................................................................1095 +42.4.6 +LPTMR hardware trigger.............................................................................................................................1096 +42.4.7 +LPTMR interrupt..........................................................................................................................................1096 +Chapter 43 +Carrier Modulator Transmitter (CMT) +43.1 +Introduction...................................................................................................................................................................1099 +43.2 +Features.........................................................................................................................................................................1099 +43.3 +Block diagram...............................................................................................................................................................1100 +43.4 +Modes of operation.......................................................................................................................................................1101 +43.4.1 +Wait mode operation....................................................................................................................................1102 +43.4.2 +Stop mode operation....................................................................................................................................1103 +43.5 +CMT external signal descriptions.................................................................................................................................1103 +43.5.1 +CMT\_IRO — Infrared Output.....................................................................................................................1103 +43.6 +Memory map/register definition...................................................................................................................................1104 +43.6.1 +CMT Carrier Generator High Data Register 1 (CMT\_CGH1)....................................................................1105 +43.6.2 +CMT Carrier Generator Low Data Register 1 (CMT\_CGL1).....................................................................1106 +43.6.3 +CMT Carrier Generator High Data Register 2 (CMT\_CGH2)....................................................................1106 +43.6.4 +CMT Carrier Generator Low Data Register 2 (CMT\_CGL2).....................................................................1107 +43.6.5 +CMT Output Control Register (CMT\_OC).................................................................................................1107 +43.6.6 +CMT Modulator Status and Control Register (CMT\_MSC).......................................................................1108 +43.6.7 +CMT Modulator Data Register Mark High (CMT\_CMD1)........................................................................1110 +43.6.8 +CMT Modulator Data Register Mark Low (CMT\_CMD2).........................................................................1111 +43.6.9 +CMT Modulator Data Register Space High (CMT\_CMD3).......................................................................1111 +43.6.10 +CMT Modulator Data Register Space Low (CMT\_CMD4)........................................................................1112 +43.6.11 +CMT Primary Prescaler Register (CMT\_PPS)............................................................................................1112 +43.6.12 +CMT Direct Memory Access Register (CMT\_DMA).................................................................................1113 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +37 +General Business Information + +![Image 1 from page 37](pdf-image://page_37_img_1) + +## Page 38 + +Section number +Title +Page +43.7 +Functional description...................................................................................................................................................1114 +43.7.1 +Clock divider................................................................................................................................................1114 +43.7.2 +Carrier generator..........................................................................................................................................1114 +43.7.3 +Modulator.....................................................................................................................................................1117 +43.7.4 +Extended space operation.............................................................................................................................1121 +43.8 +CMT interrupts and DMA............................................................................................................................................1123 +Chapter 44 +Real Time Clock (RTC) +44.1 +Introduction...................................................................................................................................................................1125 +44.1.1 +Features........................................................................................................................................................1125 +44.1.2 +Modes of operation......................................................................................................................................1125 +44.1.3 +RTC Signal Descriptions.............................................................................................................................1126 +44.2 +Register definition.........................................................................................................................................................1127 +44.2.1 +RTC Time Seconds Register (RTC\_TSR)...................................................................................................1128 +44.2.2 +RTC Time Prescaler Register (RTC\_TPR)..................................................................................................1128 +44.2.3 +RTC Time Alarm Register (RTC\_TAR).....................................................................................................1129 +44.2.4 +RTC Time Compensation Register (RTC\_TCR).........................................................................................1129 +44.2.5 +RTC Control Register (RTC\_CR)................................................................................................................1130 +44.2.6 +RTC Status Register (RTC\_SR)..................................................................................................................1132 +44.2.7 +RTC Lock Register (RTC\_LR)....................................................................................................................1133 +44.2.8 +RTC Interrupt Enable Register (RTC\_IER).................................................................................................1134 +44.2.9 +RTC Write Access Register (RTC\_WAR)..................................................................................................1135 +44.2.10 +RTC Read Access Register (RTC\_RAR)....................................................................................................1137 +44.3 +Functional description...................................................................................................................................................1138 +44.3.1 +Power, clocking, and reset...........................................................................................................................1138 +44.3.2 +Time counter................................................................................................................................................1139 +44.3.3 +Compensation...............................................................................................................................................1140 +44.3.4 +Time alarm...................................................................................................................................................1140 +44.3.5 +Update mode................................................................................................................................................1141 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +38 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 38](pdf-image://page_38_img_1) + +## Page 39 + +Section number +Title +Page +44.3.6 +Register lock................................................................................................................................................1141 +44.3.7 +Access control..............................................................................................................................................1141 +44.3.8 +Interrupt........................................................................................................................................................1141 +Chapter 45 +10/100-Mbps Ethernet MAC (ENET) +45.1 +Introduction...................................................................................................................................................................1143 +45.1.1 +Overview......................................................................................................................................................1143 +45.1.2 +Features........................................................................................................................................................1144 +45.1.3 +Block diagram..............................................................................................................................................1146 +45.2 +External signal description............................................................................................................................................1147 +45.3 +Memory map/register definition...................................................................................................................................1149 +45.3.1 +Interrupt Event Register (ENET\_EIR).........................................................................................................1152 +45.3.2 +Interrupt Mask Register (ENET\_EIMR)......................................................................................................1154 +45.3.3 +Receive Descriptor Active Register (ENET\_RDAR)..................................................................................1157 +45.3.4 +Transmit Descriptor Active Register (ENET\_TDAR).................................................................................1158 +45.3.5 +Ethernet Control Register (ENET\_ECR).....................................................................................................1159 +45.3.6 +MII Management Frame Register (ENET\_MMFR)....................................................................................1161 +45.3.7 +MII Speed Control Register (ENET\_MSCR)..............................................................................................1162 +45.3.8 +MIB Control Register (ENET\_MIBC)........................................................................................................1164 +45.3.9 +Receive Control Register (ENET\_RCR).....................................................................................................1165 +45.3.10 +Transmit Control Register (ENET\_TCR)....................................................................................................1168 +45.3.11 +Physical Address Lower Register (ENET\_PALR)......................................................................................1170 +45.3.12 +Physical Address Upper Register (ENET\_PAUR)......................................................................................1170 +45.3.13 +Opcode/Pause Duration Register (ENET\_OPD).........................................................................................1171 +45.3.14 +Descriptor Individual Upper Address Register (ENET\_IAUR)..................................................................1171 +45.3.15 +Descriptor Individual Lower Address Register (ENET\_IALR)..................................................................1172 +45.3.16 +Descriptor Group Upper Address Register (ENET\_GAUR).......................................................................1172 +45.3.17 +Descriptor Group Lower Address Register (ENET\_GALR).......................................................................1173 +45.3.18 +Transmit FIFO Watermark Register (ENET\_TFWR).................................................................................1173 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +39 +General Business Information + +![Image 1 from page 39](pdf-image://page_39_img_1) + +## Page 40 + +Section number +Title +Page +45.3.19 +Receive Descriptor Ring Start Register (ENET\_RDSR).............................................................................1174 +45.3.20 +Transmit Buffer Descriptor Ring Start Register (ENET\_TDSR)................................................................1175 +45.3.21 +Maximum Receive Buffer Size Register (ENET\_MRBR)..........................................................................1175 +45.3.22 +Receive FIFO Section Full Threshold (ENET\_RSFL)................................................................................1176 +45.3.23 +Receive FIFO Section Empty Threshold (ENET\_RSEM)..........................................................................1176 +45.3.24 +Receive FIFO Almost Empty Threshold (ENET\_RAEM)..........................................................................1177 +45.3.25 +Receive FIFO Almost Full Threshold (ENET\_RAFL)................................................................................1177 +45.3.26 +Transmit FIFO Section Empty Threshold (ENET\_TSEM).........................................................................1178 +45.3.27 +Transmit FIFO Almost Empty Threshold (ENET\_TAEM).........................................................................1178 +45.3.28 +Transmit FIFO Almost Full Threshold (ENET\_TAFL)..............................................................................1178 +45.3.29 +Transmit Inter-Packet Gap (ENET\_TIPG)..................................................................................................1179 +45.3.30 +Frame Truncation Length (ENET\_FTRL)...................................................................................................1179 +45.3.31 +Transmit Accelerator Function Configuration (ENET\_TACC)..................................................................1180 +45.3.32 +Receive Accelerator Function Configuration (ENET\_RACC)....................................................................1181 +45.3.33 +Timer Control Register (ENET\_ATCR)......................................................................................................1182 +45.3.34 +Timer Value Register (ENET\_ATVR)........................................................................................................1184 +45.3.35 +Timer Offset Register (ENET\_ATOFF)......................................................................................................1184 +45.3.36 +Timer Period Register (ENET\_ATPER)......................................................................................................1185 +45.3.37 +Timer Correction Register (ENET\_ATCOR)..............................................................................................1185 +45.3.38 +Time-Stamping Clock Period Register (ENET\_ATINC)............................................................................1186 +45.3.39 +Timestamp of Last Transmitted Frame (ENET\_ATSTMP)........................................................................1186 +45.3.40 +Timer Global Status Register (ENET\_TGSR).............................................................................................1187 +45.3.41 +Timer Control Status Register (ENET\_TCSRn)..........................................................................................1188 +45.3.42 +Timer Compare Capture Register (ENET\_TCCRn)....................................................................................1189 +45.3.43 +Statistic event counters.................................................................................................................................1189 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +40 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 40](pdf-image://page_40_img_1) + +## Page 41 + +Section number +Title +Page +45.4 +Functional description...................................................................................................................................................1192 +45.4.1 +Ethernet MAC frame formats......................................................................................................................1192 +45.4.2 +IP and higher layers frame format................................................................................................................1195 +45.4.3 +IEEE 1588 message formats........................................................................................................................1199 +45.4.4 +MAC receive................................................................................................................................................1203 +45.4.5 +MAC transmit..............................................................................................................................................1208 +45.4.6 +Full-duplex flow control operation..............................................................................................................1212 +45.4.7 +Magic packet detection................................................................................................................................1214 +45.4.8 +IP accelerator functions................................................................................................................................1215 +45.4.9 +Resets and stop controls...............................................................................................................................1220 +45.4.10 +IEEE 1588 functions....................................................................................................................................1223 +45.4.11 +FIFO thresholds............................................................................................................................................1226 +45.4.12 +Loopback options.........................................................................................................................................1229 +45.4.13 +Legacy buffer descriptors.............................................................................................................................1230 +45.4.14 +Enhanced buffer descriptors.........................................................................................................................1231 +45.4.15 +Client FIFO application interface................................................................................................................1237 +45.4.16 +FIFO protection............................................................................................................................................1240 +45.4.17 +PHY management interface.........................................................................................................................1243 +45.4.18 +Ethernet interfaces........................................................................................................................................1244 +Chapter 46 +Universal Serial Bus OTG Controller (USBOTG) +46.1 +Introduction...................................................................................................................................................................1249 +46.1.1 +USB..............................................................................................................................................................1249 +46.1.2 +USB On-The-Go..........................................................................................................................................1250 +46.1.3 +USB-FS Features..........................................................................................................................................1251 +46.2 +Functional description...................................................................................................................................................1252 +46.2.1 +Data Structures.............................................................................................................................................1252 +46.3 +Programmers interface..................................................................................................................................................1252 +46.3.1 +Buffer Descriptor Table...............................................................................................................................1252 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +41 +General Business Information + +![Image 1 from page 41](pdf-image://page_41_img_1) + +## Page 42 + +Section number +Title +Page +46.3.2 +RX vs. TX as a USB target device or USB host..........................................................................................1253 +46.3.3 +Addressing BDT entries...............................................................................................................................1254 +46.3.4 +Buffer Descriptors (BDs).............................................................................................................................1254 +46.3.5 +USB transaction...........................................................................................................................................1257 +46.4 +Memory map/Register definitions................................................................................................................................1259 +46.4.1 +Peripheral ID register (USBx\_PERID)........................................................................................................1261 +46.4.2 +Peripheral ID Complement register (USBx\_IDCOMP)...............................................................................1262 +46.4.3 +Peripheral Revision register (USBx\_REV)..................................................................................................1262 +46.4.4 +Peripheral Additional Info register (USBx\_ADDINFO).............................................................................1263 +46.4.5 +OTG Interrupt Status register (USBx\_OTGISTAT)....................................................................................1263 +46.4.6 +OTG Interrupt Control Register (USBx\_OTGICR).....................................................................................1264 +46.4.7 +OTG Status register (USBx\_OTGSTAT)....................................................................................................1265 +46.4.8 +OTG Control register (USBx\_OTGCTL)....................................................................................................1266 +46.4.9 +Interrupt Status register (USBx\_ISTAT).....................................................................................................1267 +46.4.10 +Interrupt Enable register (USBx\_INTEN)...................................................................................................1268 +46.4.11 +Error Interrupt Status register (USBx\_ERRSTAT).....................................................................................1269 +46.4.12 +Error Interrupt Enable register (USBx\_ERREN).........................................................................................1270 +46.4.13 +Status register (USBx\_STAT)......................................................................................................................1271 +46.4.14 +Control register (USBx\_CTL)......................................................................................................................1272 +46.4.15 +Address register (USBx\_ADDR).................................................................................................................1273 +46.4.16 +BDT Page Register 1 (USBx\_BDTPAGE1)................................................................................................1274 +46.4.17 +Frame Number Register Low (USBx\_FRMNUML)...................................................................................1274 +46.4.18 +Frame Number Register High (USBx\_FRMNUMH)..................................................................................1275 +46.4.19 +Token register (USBx\_TOKEN)..................................................................................................................1275 +46.4.20 +SOF Threshold Register (USBx\_SOFTHLD)..............................................................................................1276 +46.4.21 +BDT Page Register 2 (USBx\_BDTPAGE2)................................................................................................1277 +46.4.22 +BDT Page Register 3 (USBx\_BDTPAGE3)................................................................................................1277 +46.4.23 +Endpoint Control register (USBx\_ENDPTn)...............................................................................................1277 +46.4.24 +USB Control register (USBx\_USBCTRL)..................................................................................................1278 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +42 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 42](pdf-image://page_42_img_1) + +## Page 43 + +Section number +Title +Page +46.4.25 +USB OTG Observe register (USBx\_OBSERVE)........................................................................................1279 +46.4.26 +USB OTG Control register (USBx\_CONTROL)........................................................................................1280 +46.4.27 +USB Transceiver Control Register 0 (USBx\_USBTRC0)...........................................................................1280 +46.4.28 +Frame Adjust Register (USBx\_USBFRMADJUST)...................................................................................1281 +46.5 +OTG and Host mode operation.....................................................................................................................................1282 +46.6 +Host Mode Operation Examples...................................................................................................................................1282 +46.7 +On-The-Go operation....................................................................................................................................................1285 +46.7.1 +OTG dual role A device operation...............................................................................................................1286 +46.7.2 +OTG dual role B device operation...............................................................................................................1287 +Chapter 47 +USB Device Charger Detection Module (USBDCD) +47.1 +Preface...........................................................................................................................................................................1289 +47.1.1 +References....................................................................................................................................................1289 +47.1.2 +Acronyms and abbreviations........................................................................................................................1289 +47.1.3 +Glossary.......................................................................................................................................................1290 +47.2 +Introduction...................................................................................................................................................................1290 +47.2.1 +Block diagram..............................................................................................................................................1290 +47.2.2 +Features........................................................................................................................................................1291 +47.2.3 +Modes of operation......................................................................................................................................1291 +47.3 +Module signal descriptions...........................................................................................................................................1292 +47.4 +Memory map/Register definition..................................................................................................................................1293 +47.4.1 +Control register (USBDCD\_CONTROL)....................................................................................................1294 +47.4.2 +Clock register (USBDCD\_CLOCK)............................................................................................................1295 +47.4.3 +Status register (USBDCD\_STATUS)..........................................................................................................1297 +47.4.4 +TIMER0 register (USBDCD\_TIMER0)......................................................................................................1298 +47.4.5 +TIMER1 register (USBDCD\_TIMER1)......................................................................................................1299 +47.4.6 +TIMER2 register (USBDCD\_TIMER2)......................................................................................................1300 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +43 +General Business Information + +![Image 1 from page 43](pdf-image://page_43_img_1) + +## Page 44 + +Section number +Title +Page +47.5 +Functional description...................................................................................................................................................1301 +47.5.1 +The charger detection sequence...................................................................................................................1302 +47.5.2 +Interrupts and events....................................................................................................................................1311 +47.5.3 +Resets...........................................................................................................................................................1313 +47.6 +Initialization information..............................................................................................................................................1314 +47.7 +Application information................................................................................................................................................1314 +47.7.1 +External pullups...........................................................................................................................................1314 +47.7.2 +Dead or weak battery...................................................................................................................................1314 +47.7.3 +Handling unplug events...............................................................................................................................1315 +Chapter 48 +USB Voltage Regulator +48.1 +Introduction...................................................................................................................................................................1317 +48.1.1 +Overview......................................................................................................................................................1318 +48.1.2 +Features........................................................................................................................................................1319 +48.1.3 +Modes of Operation.....................................................................................................................................1319 +48.2 +USB Voltage Regulator Module Signal Descriptions..................................................................................................1320 +Chapter 49 +CAN (FlexCAN) +49.1 +Introduction...................................................................................................................................................................1321 +49.1.1 +Overview......................................................................................................................................................1322 +49.1.2 +FlexCAN module features...........................................................................................................................1323 +49.1.3 +Modes of operation......................................................................................................................................1324 +49.2 +FlexCAN signal descriptions........................................................................................................................................1326 +49.2.1 +CAN Rx .......................................................................................................................................................1326 +49.2.2 +CAN Tx .......................................................................................................................................................1326 +49.3 +Memory map/register definition...................................................................................................................................1326 +49.3.1 +FlexCAN memory mapping.........................................................................................................................1326 +49.3.2 +Module Configuration Register (CANx\_MCR)...........................................................................................1331 +49.3.3 +Control 1 register (CANx\_CTRL1).............................................................................................................1336 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +44 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 44](pdf-image://page_44_img_1) + +## Page 45 + +Section number +Title +Page +49.3.4 +Free Running Timer (CANx\_TIMER).........................................................................................................1339 +49.3.5 +Rx Mailboxes Global Mask Register (CANx\_RXMGMASK)....................................................................1340 +49.3.6 +Rx 14 Mask register (CANx\_RX14MASK)................................................................................................1341 +49.3.7 +Rx 15 Mask register (CANx\_RX15MASK)................................................................................................1342 +49.3.8 +Error Counter (CANx\_ECR)........................................................................................................................1342 +49.3.9 +Error and Status 1 register (CANx\_ESR1)..................................................................................................1344 +49.3.10 +Interrupt Masks 1 register (CANx\_IMASK1).............................................................................................1348 +49.3.11 +Interrupt Flags 1 register (CANx\_IFLAG1)................................................................................................1349 +49.3.12 +Control 2 register (CANx\_CTRL2).............................................................................................................1351 +49.3.13 +Error and Status 2 register (CANx\_ESR2)..................................................................................................1354 +49.3.14 +CRC Register (CANx\_CRCR).....................................................................................................................1355 +49.3.15 +Rx FIFO Global Mask register (CANx\_RXFGMASK)..............................................................................1356 +49.3.16 +Rx FIFO Information Register (CANx\_RXFIR).........................................................................................1357 +49.3.17 +Rx Individual Mask Registers (CANx\_RXIMRn).......................................................................................1358 +49.3.50 +Message buffer structure..............................................................................................................................1359 +49.3.51 +Rx FIFO structure........................................................................................................................................1364 +49.4 +Functional description...................................................................................................................................................1366 +49.4.1 +Transmit process..........................................................................................................................................1367 +49.4.2 +Arbitration process.......................................................................................................................................1368 +49.4.3 +Receive process............................................................................................................................................1371 +49.4.4 +Matching process.........................................................................................................................................1373 +49.4.5 +Move process...............................................................................................................................................1378 +49.4.6 +Data coherence.............................................................................................................................................1380 +49.4.7 +Rx FIFO.......................................................................................................................................................1383 +49.4.8 +CAN protocol related features.....................................................................................................................1385 +49.4.9 +Clock domains and restrictions....................................................................................................................1391 +49.4.10 +Modes of operation details...........................................................................................................................1392 +49.4.11 +Interrupts......................................................................................................................................................1395 +49.4.12 +Bus interface................................................................................................................................................1396 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +45 +General Business Information + +![Image 1 from page 45](pdf-image://page_45_img_1) + +## Page 46 + +Section number +Title +Page +49.5 +Initialization/application information...........................................................................................................................1397 +49.5.1 +FlexCAN initialization sequence.................................................................................................................1397 +Chapter 50 +Serial Peripheral Interface (SPI) +50.1 +Introduction...................................................................................................................................................................1401 +50.1.1 +Block Diagram.............................................................................................................................................1401 +50.1.2 +Features........................................................................................................................................................1402 +50.1.3 +SPI Configuration........................................................................................................................................1403 +50.1.4 +Modes of Operation.....................................................................................................................................1404 +50.2 +Module signal descriptions...........................................................................................................................................1406 +50.2.1 +PCS0/SS — Peripheral Chip Select/Slave Select........................................................................................1406 +50.2.2 +PCS1 – PCS3 — Peripheral Chip Selects 1 – 3...........................................................................................1406 +50.2.3 +PCS4 — Peripheral Chip Select 4................................................................................................................1406 +50.2.4 +SIN — Serial Input......................................................................................................................................1407 +50.2.5 +SOUT — Serial Output................................................................................................................................1407 +50.2.6 +SCK — Serial Clock....................................................................................................................................1407 +50.3 +Memory Map/Register Definition.................................................................................................................................1407 +50.3.1 +Module Configuration Register (SPIx\_MCR).............................................................................................1410 +50.3.2 +Transfer Count Register (SPIx\_TCR)..........................................................................................................1413 +50.3.3 +DSPI Clock and Transfer Attributes Register (In Master Mode) (SPIx\_CTARn)......................................1413 +50.3.4 +Clock and Transfer Attributes Register (In Slave Mode) (SPIx\_CTARn\_SLAVE)...................................1418 +50.3.5 +DSPI Status Register (SPIx\_SR)..................................................................................................................1420 +50.3.6 +DMA/Interrupt Request Select and Enable Register (SPIx\_RSER)............................................................1423 +50.3.7 +PUSH TX FIFO Register In Master Mode (SPIx\_PUSHR)........................................................................1425 +50.3.8 +PUSH TX FIFO Register In Slave Mode (SPIx\_PUSHR\_SLAVE)............................................................1427 +50.3.9 +POP RX FIFO Register (SPIx\_POPR).........................................................................................................1427 +50.3.10 +DSPI Transmit FIFO Registers (SPIx\_TXFRn)...........................................................................................1428 +50.3.11 +DSPI Receive FIFO Registers (SPIx\_RXFRn)............................................................................................1428 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +46 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 46](pdf-image://page_46_img_1) + +## Page 47 + +Section number +Title +Page +50.4 +Functional description...................................................................................................................................................1429 +50.4.1 +Start and Stop of module transfers...............................................................................................................1430 +50.4.2 +Serial Peripheral Interface (SPI) configuration............................................................................................1430 +50.4.3 +Module baud rate and clock delay generation.............................................................................................1434 +50.4.4 +Transfer formats...........................................................................................................................................1436 +50.4.5 +Continuous Serial Communications Clock..................................................................................................1441 +50.4.6 +Slave Mode Operation Constraints..............................................................................................................1443 +50.4.7 +Interrupts/DMA requests..............................................................................................................................1443 +50.4.8 +Power saving features..................................................................................................................................1446 +50.5 +Initialization/application information...........................................................................................................................1447 +50.5.1 +How to manage queues................................................................................................................................1447 +50.5.2 +Switching Master and Slave mode...............................................................................................................1448 +50.5.3 +Initializing Module in Master/Slave Modes.................................................................................................1448 +50.5.4 +Baud rate settings.........................................................................................................................................1448 +50.5.5 +Delay settings...............................................................................................................................................1449 +50.5.6 +Calculation of FIFO pointer addresses.........................................................................................................1450 +Chapter 51 +Inter-Integrated Circuit (I2C) +51.1 +Introduction...................................................................................................................................................................1453 +51.1.1 +Features........................................................................................................................................................1453 +51.1.2 +Modes of operation......................................................................................................................................1454 +51.1.3 +Block diagram..............................................................................................................................................1454 +51.2 +I2C signal descriptions..................................................................................................................................................1455 +51.3 +Memory map and register descriptions.........................................................................................................................1455 +51.3.1 +I2C Address Register 1 (I2Cx\_A1)..............................................................................................................1456 +51.3.2 +I2C Frequency Divider register (I2Cx\_F)....................................................................................................1457 +51.3.3 +I2C Control Register 1 (I2Cx\_C1)...............................................................................................................1458 +51.3.4 +I2C Status register (I2Cx\_S)........................................................................................................................1460 +51.3.5 +I2C Data I/O register (I2Cx\_D)...................................................................................................................1461 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +47 +General Business Information + +![Image 1 from page 47](pdf-image://page_47_img_1) + +## Page 48 + +Section number +Title +Page +51.3.6 +I2C Control Register 2 (I2Cx\_C2)...............................................................................................................1462 +51.3.7 +I2C Programmable Input Glitch Filter register (I2Cx\_FLT).......................................................................1463 +51.3.8 +I2C Range Address register (I2Cx\_RA)......................................................................................................1464 +51.3.9 +I2C SMBus Control and Status register (I2Cx\_SMB).................................................................................1464 +51.3.10 +I2C Address Register 2 (I2Cx\_A2)..............................................................................................................1466 +51.3.11 +I2C SCL Low Timeout Register High (I2Cx\_SLTH)..................................................................................1466 +51.3.12 +I2C SCL Low Timeout Register Low (I2Cx\_SLTL)...................................................................................1467 +51.4 +Functional description...................................................................................................................................................1467 +51.4.1 +I2C protocol.................................................................................................................................................1467 +51.4.2 +10-bit address...............................................................................................................................................1472 +51.4.3 +Address matching.........................................................................................................................................1474 +51.4.4 +System management bus specification........................................................................................................1474 +51.4.5 +Resets...........................................................................................................................................................1477 +51.4.6 +Interrupts......................................................................................................................................................1477 +51.4.7 +Programmable input glitch filter..................................................................................................................1479 +51.4.8 +Address matching wakeup...........................................................................................................................1480 +51.4.9 +DMA support...............................................................................................................................................1480 +51.5 +Initialization/application information...........................................................................................................................1481 +Chapter 52 +Universal Asynchronous Receiver/Transmitter (UART) +52.1 +Introduction...................................................................................................................................................................1485 +52.1.1 +Features........................................................................................................................................................1485 +52.1.2 +Modes of operation......................................................................................................................................1487 +52.2 +UART signal descriptions.............................................................................................................................................1488 +52.2.1 +Detailed signal descriptions.........................................................................................................................1489 +52.3 +Memory map and registers............................................................................................................................................1490 +52.3.1 +UART Baud Rate Registers: High (UARTx\_BDH)....................................................................................1504 +52.3.2 +UART Baud Rate Registers: Low (UARTx\_BDL).....................................................................................1505 +52.3.3 +UART Control Register 1 (UARTx\_C1).....................................................................................................1506 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +48 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 48](pdf-image://page_48_img_1) + +## Page 49 + +Section number +Title +Page +52.3.4 +UART Control Register 2 (UARTx\_C2).....................................................................................................1507 +52.3.5 +UART Status Register 1 (UARTx\_S1)........................................................................................................1509 +52.3.6 +UART Status Register 2 (UARTx\_S2)........................................................................................................1512 +52.3.7 +UART Control Register 3 (UARTx\_C3).....................................................................................................1514 +52.3.8 +UART Data Register (UARTx\_D)...............................................................................................................1515 +52.3.9 +UART Match Address Registers 1 (UARTx\_MA1)....................................................................................1517 +52.3.10 +UART Match Address Registers 2 (UARTx\_MA2)....................................................................................1517 +52.3.11 +UART Control Register 4 (UARTx\_C4).....................................................................................................1517 +52.3.12 +UART Control Register 5 (UARTx\_C5).....................................................................................................1518 +52.3.13 +UART Extended Data Register (UARTx\_ED)............................................................................................1519 +52.3.14 +UART Modem Register (UARTx\_MODEM).............................................................................................1520 +52.3.15 +UART Infrared Register (UARTx\_IR)........................................................................................................1521 +52.3.16 +UART FIFO Parameters (UARTx\_PFIFO).................................................................................................1522 +52.3.17 +UART FIFO Control Register (UARTx\_CFIFO)........................................................................................1524 +52.3.18 +UART FIFO Status Register (UARTx\_SFIFO)...........................................................................................1525 +52.3.19 +UART FIFO Transmit Watermark (UARTx\_TWFIFO).............................................................................1526 +52.3.20 +UART FIFO Transmit Count (UARTx\_TCFIFO).......................................................................................1527 +52.3.21 +UART FIFO Receive Watermark (UARTx\_RWFIFO)...............................................................................1527 +52.3.22 +UART FIFO Receive Count (UARTx\_RCFIFO)........................................................................................1528 +52.3.23 +UART 7816 Control Register (UARTx\_C7816).........................................................................................1528 +52.3.24 +UART 7816 Interrupt Enable Register (UARTx\_IE7816)..........................................................................1530 +52.3.25 +UART 7816 Interrupt Status Register (UARTx\_IS7816)............................................................................1531 +52.3.26 +UART 7816 Wait Parameter Register (UARTx\_WP7816T0).....................................................................1532 +52.3.27 +UART 7816 Wait Parameter Register (UARTx\_WP7816T1).....................................................................1533 +52.3.28 +UART 7816 Wait N Register (UARTx\_WN7816)......................................................................................1533 +52.3.29 +UART 7816 Wait FD Register (UARTx\_WF7816)....................................................................................1534 +52.3.30 +UART 7816 Error Threshold Register (UARTx\_ET7816)..........................................................................1534 +52.3.31 +UART 7816 Transmit Length Register (UARTx\_TL7816)........................................................................1535 +52.3.32 +UART CEA709.1-B Control Register 6 (UARTx\_C6)...............................................................................1536 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +49 +General Business Information + +![Image 1 from page 49](pdf-image://page_49_img_1) + +## Page 50 + +Section number +Title +Page +52.3.33 +UART CEA709.1-B Packet Cycle Time Counter High (UARTx\_PCTH)..................................................1536 +52.3.34 +UART CEA709.1-B Packet Cycle Time Counter Low (UARTx\_PCTL)...................................................1537 +52.3.35 +UART CEA709.1-B Interrupt Enable Register 0 (UARTx\_IE0)................................................................1537 +52.3.36 +UART CEA709.1-B Secondary Delay Timer High (UARTx\_SDTH)........................................................1538 +52.3.37 +UART CEA709.1-B Secondary Delay Timer Low (UARTx\_SDTL).........................................................1538 +52.3.38 +UART CEA709.1-B Preamble (UARTx\_PRE)...........................................................................................1539 +52.3.39 +UART CEA709.1-B Transmit Packet Length (UARTx\_TPL)....................................................................1539 +52.3.40 +UART CEA709.1-B Interrupt Enable Register (UARTx\_IE).....................................................................1540 +52.3.41 +UART CEA709.1-B WBASE (UARTx\_WB).............................................................................................1541 +52.3.42 +UART CEA709.1-B Status Register (UARTx\_S3).....................................................................................1541 +52.3.43 +UART CEA709.1-B Status Register (UARTx\_S4).....................................................................................1543 +52.3.44 +UART CEA709.1-B Received Packet Length (UARTx\_RPL)...................................................................1544 +52.3.45 +UART CEA709.1-B Received Preamble Length (UARTx\_RPREL)..........................................................1544 +52.3.46 +UART CEA709.1-B Collision Pulse Width (UARTx\_CPW).....................................................................1544 +52.3.47 +UART CEA709.1-B Receive Indeterminate Time High (UARTx\_RIDTH)...............................................1545 +52.3.48 +UART CEA709.1-B Receive Indeterminate Time Low (UARTx\_RIDTL)................................................1545 +52.3.49 +UART CEA709.1-B Transmit Indeterminate Time High (UARTx\_TIDTH).............................................1546 +52.3.50 +UART CEA709.1-B Transmit Indeterminate Time Low (UARTx\_TIDTL)..............................................1546 +52.3.51 +UART CEA709.1-B Receive Beta1 Timer High (UARTx\_RB1TH)..........................................................1546 +52.3.52 +UART CEA709.1-B Receive Beta1 Timer Low (UARTx\_RB1TL)...........................................................1547 +52.3.53 +UART CEA709.1-B Transmit Beta1 Timer High (UARTx\_TB1TH)........................................................1547 +52.3.54 +UART CEA709.1-B Transmit Beta1 Timer Low (UARTx\_TB1TL)..........................................................1548 +52.3.55 +UART CEA709.1-B Programmable register (UARTx\_PROG\_REG)........................................................1548 +52.3.56 +UART CEA709.1-B State register (UARTx\_STATE\_REG)......................................................................1549 +52.4 +Functional description...................................................................................................................................................1549 +52.4.1 +CEA709.1-B.................................................................................................................................................1549 +52.4.2 +Transmitter...................................................................................................................................................1560 +52.4.3 +Receiver.......................................................................................................................................................1566 +52.4.4 +Baud rate generation....................................................................................................................................1575 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +50 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 50](pdf-image://page_50_img_1) + +## Page 51 + +Section number +Title +Page +52.4.5 +Data format (non ISO-7816)........................................................................................................................1577 +52.4.6 +Single-wire operation...................................................................................................................................1580 +52.4.7 +Loop operation.............................................................................................................................................1581 +52.4.8 +ISO-7816/smartcard support........................................................................................................................1581 +52.4.9 +Infrared interface..........................................................................................................................................1586 +52.5 +Reset..............................................................................................................................................................................1587 +52.6 +System level interrupt sources......................................................................................................................................1587 +52.6.1 +RXEDGIF description..................................................................................................................................1588 +52.7 +DMA operation.............................................................................................................................................................1589 +52.8 +Application information................................................................................................................................................1589 +52.8.1 +Transmit/receive data buffer operation........................................................................................................1589 +52.8.2 +ISO-7816 initialization sequence.................................................................................................................1590 +52.8.3 +Initialization sequence (non ISO-7816).......................................................................................................1592 +52.8.4 +Overrun (OR) flag implications...................................................................................................................1593 +52.8.5 +Overrun NACK considerations....................................................................................................................1594 +52.8.6 +Match address registers................................................................................................................................1595 +52.8.7 +Modem feature.............................................................................................................................................1595 +52.8.8 +IrDA minimum pulse width.........................................................................................................................1596 +52.8.9 +Clearing 7816 wait timer (WT, BWT, CWT) interrupts..............................................................................1596 +52.8.10 +Legacy and reverse compatibility considerations........................................................................................1597 +Chapter 53 +Secured digital host controller (SDHC) +53.1 +Introduction...................................................................................................................................................................1599 +53.2 +Overview.......................................................................................................................................................................1599 +53.2.1 +Supported types of cards..............................................................................................................................1599 +53.2.2 +SDHC block diagram...................................................................................................................................1600 +53.2.3 +Features........................................................................................................................................................1601 +53.2.4 +Modes and operations..................................................................................................................................1602 +53.3 +SDHC signal descriptions.............................................................................................................................................1603 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +51 +General Business Information + +![Image 1 from page 51](pdf-image://page_51_img_1) + +## Page 52 + +Section number +Title +Page +53.4 +Memory map and register definition.............................................................................................................................1604 +53.4.1 +DMA System Address register (SDHC\_DSADDR)....................................................................................1605 +53.4.2 +Block Attributes register (SDHC\_BLKATTR)...........................................................................................1606 +53.4.3 +Command Argument register (SDHC\_CMDARG).....................................................................................1607 +53.4.4 +Transfer Type register (SDHC\_XFERTYP)................................................................................................1608 +53.4.5 +Command Response 0 (SDHC\_CMDRSP0)...............................................................................................1612 +53.4.6 +Command Response 1 (SDHC\_CMDRSP1)...............................................................................................1612 +53.4.7 +Command Response 2 (SDHC\_CMDRSP2)...............................................................................................1613 +53.4.8 +Command Response 3 (SDHC\_CMDRSP3)...............................................................................................1613 +53.4.9 +Buffer Data Port register (SDHC\_DATPORT)...........................................................................................1614 +53.4.10 +Present State register (SDHC\_PRSSTAT)..................................................................................................1615 +53.4.11 +Protocol Control register (SDHC\_PROCTL)..............................................................................................1620 +53.4.12 +System Control register (SDHC\_SYSCTL)................................................................................................1624 +53.4.13 +Interrupt Status register (SDHC\_IRQSTAT)...............................................................................................1627 +53.4.14 +Interrupt Status Enable register (SDHC\_IRQSTATEN).............................................................................1632 +53.4.15 +Interrupt Signal Enable register (SDHC\_IRQSIGEN)................................................................................1635 +53.4.16 +Auto CMD12 Error Status Register (SDHC\_AC12ERR)...........................................................................1637 +53.4.17 +Host Controller Capabilities (SDHC\_HTCAPBLT)....................................................................................1641 +53.4.18 +Watermark Level Register (SDHC\_WML).................................................................................................1643 +53.4.19 +Force Event register (SDHC\_FEVT)...........................................................................................................1644 +53.4.20 +ADMA Error Status register (SDHC\_ADMAES).......................................................................................1646 +53.4.21 +ADMA System Addressregister (SDHC\_ADSADDR)...............................................................................1648 +53.4.22 +Vendor Specific register (SDHC\_VENDOR)..............................................................................................1649 +53.4.23 +MMC Boot register (SDHC\_MMCBOOT).................................................................................................1650 +53.4.24 +Host Controller Version (SDHC\_HOSTVER)............................................................................................1651 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +52 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 52](pdf-image://page_52_img_1) + +## Page 53 + +Section number +Title +Page +53.5 +Functional description...................................................................................................................................................1652 +53.5.1 +Data buffer...................................................................................................................................................1652 +53.5.2 +DMA crossbar switch interface....................................................................................................................1658 +53.5.3 +SD protocol unit...........................................................................................................................................1664 +53.5.4 +Clock and reset manager..............................................................................................................................1666 +53.5.5 +Clock generator............................................................................................................................................1667 +53.5.6 +SDIO card interrupt......................................................................................................................................1667 +53.5.7 +Card insertion and removal detection..........................................................................................................1669 +53.5.8 +Power management and wakeup events.......................................................................................................1670 +53.5.9 +MMC fast boot.............................................................................................................................................1671 +53.6 +Initialization/application of SDHC...............................................................................................................................1673 +53.6.1 +Command send and response receive basic operation.................................................................................1673 +53.6.2 +Card Identification mode.............................................................................................................................1674 +53.6.3 +Card access...................................................................................................................................................1679 +53.6.4 +Switch function............................................................................................................................................1690 +53.6.5 +ADMA operation.........................................................................................................................................1692 +53.6.6 +Fast boot operation.......................................................................................................................................1693 +53.6.7 +Commands for MMC/SD/SDIO/CE-ATA...................................................................................................1697 +53.7 +Software restrictions.....................................................................................................................................................1703 +53.7.1 +Initialization active.......................................................................................................................................1703 +53.7.2 +Software polling procedure..........................................................................................................................1703 +53.7.3 +Suspend operation........................................................................................................................................1704 +53.7.4 +Data length setting.......................................................................................................................................1704 +53.7.5 +(A)DMA address setting..............................................................................................................................1704 +53.7.6 +Data port access...........................................................................................................................................1704 +53.7.7 +Change clock frequency...............................................................................................................................1704 +53.7.8 +Multi-block read...........................................................................................................................................1705 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +53 +General Business Information + +![Image 1 from page 53](pdf-image://page_53_img_1) + +## Page 54 + +Section number +Title +Page +Chapter 54 +Integrated Interchip Sound (I2S) / Synchronous Audio Interface (SAI) +54.1 +Introduction...................................................................................................................................................................1707 +54.1.1 +Features........................................................................................................................................................1707 +54.1.2 +Block diagram..............................................................................................................................................1707 +54.1.3 +Modes of operation......................................................................................................................................1708 +54.2 +External signals.............................................................................................................................................................1709 +54.3 +Memory map and register definition.............................................................................................................................1709 +54.3.1 +SAI Transmit Control Register (I2Sx\_TCSR).............................................................................................1711 +54.3.2 +SAI Transmit Configuration 1 Register (I2Sx\_TCR1)................................................................................1714 +54.3.3 +SAI Transmit Configuration 2 Register (I2Sx\_TCR2)................................................................................1714 +54.3.4 +SAI Transmit Configuration 3 Register (I2Sx\_TCR3)................................................................................1716 +54.3.5 +SAI Transmit Configuration 4 Register (I2Sx\_TCR4)................................................................................1717 +54.3.6 +SAI Transmit Configuration 5 Register (I2Sx\_TCR5)................................................................................1718 +54.3.7 +SAI Transmit Data Register (I2Sx\_TDRn)..................................................................................................1719 +54.3.8 +SAI Transmit FIFO Register (I2Sx\_TFRn).................................................................................................1719 +54.3.9 +SAI Transmit Mask Register (I2Sx\_TMR)..................................................................................................1720 +54.3.10 +SAI Receive Control Register (I2Sx\_RCSR)...............................................................................................1721 +54.3.11 +SAI Receive Configuration 1 Register (I2Sx\_RCR1)..................................................................................1724 +54.3.12 +SAI Receive Configuration 2 Register (I2Sx\_RCR2)..................................................................................1724 +54.3.13 +SAI Receive Configuration 3 Register (I2Sx\_RCR3)..................................................................................1726 +54.3.14 +SAI Receive Configuration 4 Register (I2Sx\_RCR4)..................................................................................1727 +54.3.15 +SAI Receive Configuration 5 Register (I2Sx\_RCR5)..................................................................................1728 +54.3.16 +SAI Receive Data Register (I2Sx\_RDRn)...................................................................................................1729 +54.3.17 +SAI Receive FIFO Register (I2Sx\_RFRn)...................................................................................................1729 +54.3.18 +SAI Receive Mask Register (I2Sx\_RMR)...................................................................................................1730 +54.3.19 +SAI MCLK Control Register (I2Sx\_MCR).................................................................................................1730 +54.3.20 +SAI MCLK Divide Register (I2Sx\_MDR)..................................................................................................1731 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +54 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 54](pdf-image://page_54_img_1) + +## Page 55 + +Section number +Title +Page +54.4 +Functional description...................................................................................................................................................1732 +54.4.1 +SAI clocking................................................................................................................................................1732 +54.4.2 +SAI resets.....................................................................................................................................................1733 +54.4.3 +Synchronous modes.....................................................................................................................................1734 +54.4.4 +Frame sync configuration.............................................................................................................................1735 +54.5 +Data FIFO.....................................................................................................................................................................1735 +54.5.1 +Data alignment.............................................................................................................................................1735 +54.5.2 +FIFO pointers...............................................................................................................................................1736 +54.5.3 +Word mask register......................................................................................................................................1737 +54.5.4 +Interrupts and DMA requests.......................................................................................................................1737 +Chapter 55 +General-Purpose Input/Output (GPIO) +55.1 +Introduction...................................................................................................................................................................1741 +55.1.1 +Features........................................................................................................................................................1741 +55.1.2 +Modes of operation......................................................................................................................................1742 +55.1.3 +GPIO signal descriptions.............................................................................................................................1742 +55.2 +Memory map and register definition.............................................................................................................................1743 +55.2.1 +Port Data Output Register (GPIOx\_PDOR).................................................................................................1745 +55.2.2 +Port Set Output Register (GPIOx\_PSOR)....................................................................................................1746 +55.2.3 +Port Clear Output Register (GPIOx\_PCOR)................................................................................................1746 +55.2.4 +Port Toggle Output Register (GPIOx\_PTOR).............................................................................................1747 +55.2.5 +Port Data Input Register (GPIOx\_PDIR).....................................................................................................1747 +55.2.6 +Port Data Direction Register (GPIOx\_PDDR).............................................................................................1748 +55.3 +Functional description...................................................................................................................................................1748 +55.3.1 +General-purpose input..................................................................................................................................1748 +55.3.2 +General-purpose output................................................................................................................................1748 +Chapter 56 +Touch sense input (TSI) +56.1 +Introduction...................................................................................................................................................................1751 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +55 +General Business Information + +![Image 1 from page 55](pdf-image://page_55_img_1) + +## Page 56 + +Section number +Title +Page +56.2 +Features.........................................................................................................................................................................1751 +56.3 +Overview.......................................................................................................................................................................1752 +56.3.1 +Electrode capacitance measurement unit.....................................................................................................1753 +56.3.2 +Electrode scan unit.......................................................................................................................................1754 +56.3.3 +Touch detection unit.....................................................................................................................................1754 +56.4 +Modes of operation.......................................................................................................................................................1755 +56.4.1 +TSI disabled mode.......................................................................................................................................1756 +56.4.2 +TSI active mode...........................................................................................................................................1756 +56.4.3 +TSI low-power mode...................................................................................................................................1756 +56.4.4 +Block diagram..............................................................................................................................................1756 +56.5 +TSI signal descriptions..................................................................................................................................................1757 +56.5.1 +TSI\_IN[15:0]................................................................................................................................................1757 +56.6 +Memory map and register definition.............................................................................................................................1758 +56.6.1 +General Control and Status register (TSIx\_GENCS)...................................................................................1759 +56.6.2 +SCAN Control register (TSIx\_SCANC)......................................................................................................1762 +56.6.3 +Pin Enable register (TSIx\_PEN)..................................................................................................................1764 +56.6.4 +Wake-Up Channel Counter Register (TSIx\_WUCNTR).............................................................................1766 +56.6.5 +Counter Register (TSIx\_CNTRn)................................................................................................................1767 +56.6.6 +Low-Power Channel Threshold register (TSIx\_THRESHOLD).................................................................1767 +56.7 +Functional description...................................................................................................................................................1767 +56.7.1 +Capacitance measurement............................................................................................................................1768 +56.7.2 +TSI measurement result...............................................................................................................................1771 +56.7.3 +Electrode scan unit.......................................................................................................................................1772 +56.7.4 +Touch detection unit.....................................................................................................................................1775 +56.8 +Application information................................................................................................................................................1776 +56.8.1 +TSI module sensitivity.................................................................................................................................1776 +56.9 +TSI module initialization..............................................................................................................................................1776 +56.9.1 +Initialization sequence..................................................................................................................................1777 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +56 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 56](pdf-image://page_56_img_1) + +## Page 57 + +Section number +Title +Page +Chapter 57 +JTAG Controller (JTAGC) +57.1 +Introduction...................................................................................................................................................................1779 +57.1.1 +Block diagram..............................................................................................................................................1779 +57.1.2 +Features........................................................................................................................................................1780 +57.1.3 +Modes of operation......................................................................................................................................1780 +57.2 +External signal description............................................................................................................................................1782 +57.2.1 +TCK—Test clock input................................................................................................................................1782 +57.2.2 +TDI—Test data input...................................................................................................................................1782 +57.2.3 +TDO—Test data output................................................................................................................................1782 +57.2.4 +TMS—Test mode select...............................................................................................................................1782 +57.3 +Register description......................................................................................................................................................1783 +57.3.1 +Instruction register.......................................................................................................................................1783 +57.3.2 +Bypass register.............................................................................................................................................1783 +57.3.3 +Device identification register.......................................................................................................................1783 +57.3.4 +Boundary scan register.................................................................................................................................1784 +57.4 +Functional description...................................................................................................................................................1785 +57.4.1 +JTAGC reset configuration..........................................................................................................................1785 +57.4.2 +IEEE 1149.1-2001 (JTAG) Test Access Port..............................................................................................1785 +57.4.3 +TAP controller state machine.......................................................................................................................1785 +57.4.4 +JTAGC block instructions............................................................................................................................1787 +57.4.5 +Boundary scan..............................................................................................................................................1790 +57.5 +Initialization/Application information..........................................................................................................................1790 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +57 +General Business Information + +![Image 1 from page 57](pdf-image://page_57_img_1) + +## Page 58 + +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +58 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 58](pdf-image://page_58_img_1) + +## Page 59 + +Chapter 1 +About This Document +1.1 +Overview +1.1.1 +Purpose +This document describes the features, architecture, and programming model of the +Freescale K60 microcontroller. +1.1.2 +Audience +This document is primarily for system architects and software application developers +who are using or considering using the K60 microcontroller in a system. +1.2 +Conventions +1.2.1 +Numbering systems +The following suffixes identify different numbering systems: +This suffix +Identifies a +b +Binary number. For example, the binary equivalent of the +number 5 is written 101b. In some cases, binary numbers are +shown with the prefix 0b. +d +Decimal number. Decimal numbers are followed by this suffix +only when the possibility of confusion exists. In general, +decimal numbers are shown without a suffix. +h +Hexadecimal number. For example, the hexadecimal +equivalent of the number 60 is written 3Ch. In some cases, +hexadecimal numbers are shown with the prefix 0x. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +59 +General Business Information + +![Image 1 from page 59](pdf-image://page_59_img_1) + +## Page 60 + +1.2.2 +Typographic notation +The following typographic notation is used throughout this document: +Example +Description +placeholder, x +Items in italics are placeholders for information that you provide. Italicized text is also used for +the titles of publications and for emphasis. Plain lowercase letters are also used as +placeholders for single letters and numbers. +code +Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction +mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type +is also used for example code. Instruction mnemonics and directives in text and tables are +shown in all caps; for example, BSR. +SR[SCM] +A mnemonic in brackets represents a named field in a register. This example refers to the +Scaling Mode (SCM) field in the Status Register (SR). +REVNO[6:4], XAD[7:0] +Numbers in brackets and separated by a colon represent either: +• A subset of a register's named field +For example, REVNO[6:4] refers to bits 6–4 that are part of the COREREV field that +occupies bits 6–0 of the REVNO register. +• A continuous range of individual signals of a bus +For example, XAD[7:0] refers to signals 7–0 of the XAD bus. +1.2.3 +Special terms +The following terms have special meanings: +Term +Meaning +asserted +Refers to the state of a signal as follows: +• An active-high signal is asserted when high (1). +• An active-low signal is asserted when low (0). +deasserted +Refers to the state of a signal as follows: +• An active-high signal is deasserted when low (0). +• An active-low signal is deasserted when high (1). +In some cases, deasserted signals are described as negated. +reserved +Refers to a memory space, register, or field that is either +reserved for future use or for which, when written to, the +module or chip behavior is unpredictable. +Conventions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +60 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 60](pdf-image://page_60_img_1) + +## Page 61 + +Chapter 2 +Introduction +2.1 +Overview +This chapter provides high-level descriptions of the modules available on the devices +covered by this document. +2.2 +Module Functional Categories +The modules on this device are grouped into functional categories. The following +sections describe the modules assigned to each category in more detail. +Table 2-1. Module functional categories +Module category +Description +ARM Cortex-M4 core +• 32-bit MCU core from ARM’s Cortex-M class adding DSP instructions, 1.25 +DMIPS/MHz, based on ARMv7 architecture +System +• System integration module +• Power management and mode controllers +• Multiple power modes available based on run, wait, stop, and power- +down modes +• Low-leakage wakeup unit +• Miscellaneous control module +• Crossbar switch +• Memory protection unit +• Peripheral bridge +• Direct memory access (DMA) controller with multiplexer to increase available +DMA requests +• External watchdog monitor +• Watchdog +Table continues on the next page... +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +61 +General Business Information + +![Image 1 from page 61](pdf-image://page_61_img_1) + +## Page 62 + +Table 2-1. Module functional categories (continued) +Module category +Description +Memories +• Internal memories include: +• Program flash memory +• On devices with FlexMemory: FlexMemory +• FlexNVM +• FlexRAM +• On devices with program flash only: Programming acceleration RAM +• SRAM +• External memory or peripheral bus interface: FlexBus +• Serial programming interface: EzPort +Clocks +• Multiple clock generation options available from internally- and externally- +generated clocks +• System oscillator to provide clock source for the MCU +• RTC oscillator to provide clock source for the RTC +Security +• Cyclic Redundancy Check module for error detection +• Hardware encryption, along with a random number generator +Analog +• High speed analog-to-digital converter with integrated programmable gain +amplifier +• Comparator +• Digital-to-analog converter +• Internal voltage reference +Timers +• Programmable delay block +• FlexTimers +• Periodic interrupt timer +• Low power timer +• Carrier modulator transmitter +• Independent real time clock +Communications +• Ethernet MAC with IEEE 1588 capability +• USB OTG controller with built-in FS/LS transceiver +• USB device charger detect +• USB voltage regulator +• CAN +• Serial peripheral interface +• Inter-integrated circuit (I2C) +• UART +• Secured Digital host controller +• Integrated interchip sound (I2S) +Human-Machine Interfaces (HMI) +• General purpose input/output controller +• Capacitive touch sense input interface enabled in hardware +2.2.1 +ARM Cortex-M4 Core Modules +The following core modules are available on this device. +Module Functional Categories +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +62 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 62](pdf-image://page_62_img_1) + +## Page 63 + +Table 2-2. Core modules +Module +Description +ARM Cortex-M4 +The ARM Cortex-M4 is the newest member of the Cortex M Series of processors +targeting microcontroller cores focused on very cost sensitive, deterministic, +interrupt driven environments. The Cortex M4 processor is based on the ARMv7 +Architecture and Thumb®-2 ISA and is upward compatible with the Cortex M3, +Cortex M1, and Cortex M0 architectures. Cortex M4 improvements include an +ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile architectures) providing +32-bit instructions with SIMD (single instruction multiple data) DSP style multiply- +accumulates and saturating arithmetic. +NVIC +The ARMv7-M exception model and nested-vectored interrupt controller (NVIC) +implement a relocatable vector table supporting many external interrupts, a single +non-maskable interrupt (NMI), and priority levels. +The NVIC replaces shadow registers with equivalent system and simplified +programmability. The NVIC contains the address of the function to execute for a +particular handler. The address is fetched via the instruction port allowing parallel +register stacking and look-up. The first sixteen entries are allocated to ARM +internal sources with the others mapping to MCU-defined interrupts. +AWIC +The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is +to detect asynchronous wake-up events in stop modes and signal to clock control +logic to resume system clocking. After clock restart, the NVIC observes the +pending interrupt and performs the normal interrupt or event processing. +Debug interfaces +Most of this device's debug is based on the ARM CoreSight™ architecture. Four +debug interfaces are supported: +• IEEE 1149.1 JTAG +• IEEE 1149.7 JTAG (cJTAG) +• Serial Wire Debug (SWD) +• ARM Real-Time Trace Interface +2.2.2 +System Modules +The following system modules are available on this device. +Table 2-3. System modules +Module +Description +System integration module (SIM) +The SIM includes integration logic and several module configuration settings. +System mode controller +The SMC provides control and protection on entry and exit to each power mode, +control for the Power management controller (PMC), and reset entry and exit for +the complete MCU. +Power management controller (PMC) +The PMC provides the user with multiple power options. Ten different modes are +supported that allow the user to optimize power consumption for the level of +functionality needed. Includes power-on-reset (POR) and integrated low voltage +detect (LVD) with reset (brownout) capability and selectable LVD trip points. +Low-leakage wakeup unit (LLWU) +The LLWU module allows the device to wake from low leakage power modes (LLS +and VLLS) through various internal peripheral and external pin sources. +Miscellaneous control module (MCM) +The MCM includes integration logic and embedded trace buffer details. +Table continues on the next page... +Chapter 2 Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +63 +General Business Information + +![Image 1 from page 63](pdf-image://page_63_img_1) + +## Page 64 + +Table 2-3. System modules (continued) +Module +Description +Crossbar switch (XBS) +The XBS connects bus masters and bus slaves, allowing all bus masters to access +different bus slaves simultaneously and providing arbitration among the bus +masters when they access the same slave. +Memory protection unit (MPU) +The MPU provides memory protection and task isolation. It concurrently monitors +all bus master transactions for the slave connections. +Peripheral bridges +The peripheral bridge converts the crossbar switch interface to an interface to +access a majority of peripherals on the device. +DMA multiplexer (DMAMUX) +The DMA multiplexer selects from many DMA requests down to a smaller number +for the DMA controller. +Direct memory access (DMA) controller +The DMA controller provides programmable channels with transfer control +descriptors for data movement via dual-address transfers for 8-, 16-, 32- and 128- +bit data values. +External watchdog monitor (EWM) +The EWM is a redundant mechanism to the software watchdog module that +monitors both internal and external system operation for fail conditions. +Software watchdog (WDOG) +The WDOG monitors internal system operation and forces a reset in case of +failure. It can run from an independent 1 KHz low power oscillator with a +programmable refresh window to detect deviations in program flow or system +frequency. +2.2.3 +Memories and Memory Interfaces +The following memories and memory interfaces are available on this device. +Table 2-4. Memories and memory interfaces +Module +Description +Flash memory +• Program flash memory — non-volatile flash memory that can execute +program code +• FlexMemory — encompasses the following memory types: +• For devices with FlexNVM: FlexNVM — Non-volatile flash memory that +can execute program code, store data, or backup EEPROM data +• For devices with FlexNVM: FlexRAM — RAM memory that can be +used as traditional RAM or as high-endurance EEPROM storage, and +also accelerates flash programming +• For devices with only program flash memory: Programming +acceleration RAM — RAM memory that accelerates flash programming +Flash memory controller +Manages the interface between the device and the on-chip flash memory. +SRAM +Internal system RAM. Partial SRAM kept powered in VLLS2 low leakage mode. +SRAM controller +Manages simultaneous accesses to system RAM by multiple master peripherals +and core. +System register file +32-byte register file that is accessible during all power modes and is powered by +VDD. +VBAT register file +32-byte register file that is accessible during all power modes and is powered by +VBAT. +Table continues on the next page... +Module Functional Categories +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +64 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 64](pdf-image://page_64_img_1) + +## Page 65 + +Table 2-4. Memories and memory interfaces (continued) +Module +Description +Serial programming interface (EzPort) +Same serial interface as, and subset of, the command set used by industry- +standard SPI flash memories. Provides the ability to read, erase, and program +flash memory and reset command to boot the system after flash programming. +FlexBus +External bus interface with multiple independent, user-programmable chip-select +signals that can interface with external SRAM, PROM, EPROM, EEPROM, flash, +and other peripherals via 8-, 16- and 32-bit port sizes. Configurations include +multiplexed or non-multiplexed address and data buses using 8-bit, 16-bit, 32-bit, +and 16-byte line-sized transfers. +2.2.4 +Clocks +The following clock modules are available on this device. +Table 2-5. Clock modules +Module +Description +Multi-clock generator (MCG) +The MCG provides several clock sources for the MCU that include: +• Phase-locked loop (PLL) — Voltage-controlled oscillator (VCO) +• Frequency-locked loop (FLL) — Digitally-controlled oscillator (DCO) +• Internal reference clocks — Can be used as a clock source for other on-chip +peripherals +System oscillator +The system oscillator, in conjunction with an external crystal or resonator, +generates a reference clock for the MCU. +Real-time clock oscillator +The RTC oscillator has an independent power supply and supports a 32 kHz +crystal oscillator to feed the RTC clock. Optionally, the RTC oscillator can replace +the system oscillator as the main oscillator source. +2.2.5 +Security and Integrity modules +The following security and integrity modules are available on this device: +Table 2-6. Security and integrity modules +Module +Description +Cryptographic acceleration unit (CAU) +Supports DES, 3DES, AES, MD5, SHA-1, and SHA-256 algorithms via simple C +calls to optimized security functions provided by Freescale. +Random number generator (RNG) +Supports the key generation algorithm defined in the Digital Signature Standard. +Cyclic Redundancy Check (CRC) +Hardware CRC generator circuit using 16/32-bit shift register. Error detection for all +single, double, odd, and most multi-bit errors, programmable initial seed value, and +optional feature to transpose input data and CRC result via transpose register. +Chapter 2 Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +65 +General Business Information + +![Image 1 from page 65](pdf-image://page_65_img_1) + +## Page 66 + +2.2.6 +Analog modules +The following analog modules are available on this device: +Table 2-7. Analog modules +Module +Description +16-bit analog-to-digital converters (ADC) +and programmable-gain amplifiers +(PGA) +16-bit successive-approximation ADC designed with integrated programmable gain +amplifiers (PGA) +Analog comparators +Compares two analog input voltages across the full range of the supply voltage. +6-bit digital-to-analog converters (DAC) +64-tap resistor ladder network which provides a selectable voltage reference for +applications where voltage reference is needed. +12-bit digital-to-analog converters (DAC) Low-power general-purpose DAC, whose output can be placed on an external pin +or set as one of the inputs to the analog comparator or ADC. +Voltage reference (VREF) +Supplies an accurate voltage output that is trimmable in 0.5 mV steps. The VREF +can be used in medical applications, such as glucose meters, to provide a +reference voltage to biosensors or as a reference to analog peripherals, such as +the ADC, DAC, or CMP. +2.2.7 +Timer modules +The following timer modules are available on this device: +Table 2-8. Timer modules +Module +Description +Programmable delay block (PDB) +• 16-bit resolution +• 3-bit prescaler +• Positive transition of trigger event signal initiates the counter +• Supports two triggered delay output signals, each with an independently- +controlled delay from the trigger event +• Outputs can be OR'd together to schedule two conversions from one input +trigger event and can schedule precise edge placement for a pulsed output. +This feature is used to generate the control signal for the CMP windowing +feature and output to a package pin if needed for applications, such as +critical conductive mode power factor correction. +• Continuous-pulse output or single-shot mode supported, each output is +independently enabled, with possible trigger events +• Supports bypass mode +• Supports DMA +Table continues on the next page... +Module Functional Categories +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +66 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 66](pdf-image://page_66_img_1) + +## Page 67 + +Table 2-8. Timer modules (continued) +Module +Description +Flexible timer modules (FTM) +• Selectable FTM source clock, programmable prescaler +• 16-bit counter supporting free-running or initial/final value, and counting is up +or up-down +• Input capture, output compare, and edge-aligned and center-aligned PWM +modes +• Operation of FTM channels as pairs with equal outputs, pairs with +complimentary outputs, or independent channels with independent outputs +• Deadtime insertion is available for each complementary pair +• Generation of hardware triggers +• Software control of PWM outputs +• Up to 4 fault inputs for global fault control +• Configurable channel polarity +• Programmable interrupt on input capture, reference compare, overflowed +counter, or detected fault condition +• Quadrature decoder with input filters, relative position counting, and interrupt +on position count or capture of position count on external event +• DMA support for FTM events +Periodic interrupt timers (PIT) +• Four general purpose interrupt timers +• Interrupt timers for triggering ADC conversions +• 32-bit counter resolution +• DMA support +Low-power timer (LPTimer) +• Selectable clock for prescaler/glitch filter of 1 kHz (internal LPO), 32.768 kHz +(external crystal), or internal reference clock +• Configurable Glitch Filter or Prescaler with 16-bit counter +• 16-bit time or pulse counter with compare +• Interrupt generated on Timer Compare +• Hardware trigger generated on Timer Compare +Carrier modulator timer (CMT) +• Four CMT modes of operation: +• Time with independent control of high and low times +• Baseband +• Frequency shift key (FSK) +• Direct software control of CMT\_IRO pin +• Extended space operation in time, baseband, and FSK modes +• Selectable input clock divider +• Interrupt on end of cycle with the ability to disable CMT\_IRO pin and use as +timer interrupt +• DMA support +Real-time clock (RTC) +• Independent power supply, POR, and 32 kHz Crystal Oscillator +• 32-bit seconds counter with 32-bit Alarm +• 16-bit Prescaler with compensation that can correct errors between 0.12 ppm +and 3906 ppm +IEEE 1588 timers +• The 10/100 Ethernet module contains timers to provide IEEE 1588 time +stamping +2.2.8 +Communication interfaces +The following communication interfaces are available on this device: +Chapter 2 Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +67 +General Business Information + +![Image 1 from page 67](pdf-image://page_67_img_1) + +## Page 68 + +Table 2-9. Communication modules +Module +Description +Ethernet MAC with IEEE 1588 capability +(ENET) +10/100 MB/s Ethernet MAC (MII and RMII) with hardware support for IEEE 1588 +USB OTG (low-/full-speed) +USB 2.0 compliant module with support for host, device, and On-The-Go modes. +Includes an on-chip transceiver for full and low speeds. +USB Device Charger Detect (USBDCD) +The USBDCD monitors the USB data lines to detect a smart charger meeting the +USB Battery Charging Specification Rev1.1. This information allows the MCU to +better manage the battery charging IC in a portable device. +USB voltage regulator +Up to 5 V regulator input typically provided by USB VBUS power with 3.3 V +regulated output that powers on-chip USB subsystem, capable of sourcing 120 mA +to external board components. +Controller Area Network (CAN) +Supports the full implementation of the CAN Specification Version 2.0, Part B +Serial peripheral interface (SPI) +Synchronous serial bus for communication to an external device +Inter-integrated circuit (I2C) +Allows communication between a number of devices. Also supports the System +Management Bus (SMBus) Specification, version 2. +Universal asynchronous receiver/ +transmitters (UART) +Asynchronous serial bus communication interface with programmable 8- or 9-bit +data format and support of CEA709.1-B (LON), ISO 7816 smart card interface +Secure Digital host controller (SDHC) +Interface between the host system and the SD, SDIO, MMC, or CE-ATA cards. +The SDHC acts as a bridge, passing host bus transactions to the cards by sending +commands and performing data accesses to/from the cards. It handles the SD, +SDIO, MMC, and CE-ATA protocols at the transmission level. +I2S +The I2S is a full-duplex, serial port that allows the chip to communicate with a +variety of serial devices, such as standard codecs, digital signal processors +(DSPs), microprocessors, peripherals, and audio codecs that implement the inter- +IC sound bus (I2S) and the Intel® AC97 standards +2.2.9 +Human-machine interfaces +The following human-machine interfaces (HMI) are available on this device: +Table 2-10. HMI modules +Module +Description +General purpose input/output (GPIO) +All general purpose input or output (GPIO) pins are capable of interrupt and DMA +request generation. All GPIO pins have 5 V tolerance. +Capacitive touch sense input (TSI) +Contains up to 16 channel inputs for capacitive touch sensing applications. +Operation is available in low-power modes via interrupts. +2.3 +Orderable part numbers +The following table summarizes the part numbers of the devices covered by this +document. +Orderable part numbers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +68 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 68](pdf-image://page_68_img_1) + +## Page 69 + +Table 2-11. Orderable part numbers summary +Freescale part number +CPU +frequenc +y +Pin +count +Package +Total +flash +memory +Program +flash +EEPROM +SRAM +GPIO +MK60DN256VLQ10 +100 MHz +144 +LQFP +256 KB +256 KB +— +64 KB +100 +MK60DX256VLQ10 +100 MHz +144 +LQFP +512 KB +256 KB +4 KB +64 KB +100 +MK60DN512VLQ10 +100 MHz +144 +LQFP +512 KB +512 KB +— +128 KB +100 +MK60DN256VMD10 +100 MHz +144 +MAPBGA +256 KB +256 KB +— +64 KB +100 +MK60DX256VMD10 +100 MHz +144 +MAPBGA +512 KB +256 KB +4 KB +64 KB +100 +MK60DN512VMD10 +100 MHz +144 +MAPBGA +512 KB +512 KB +— +128 KB +100 +Chapter 2 Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +69 +General Business Information + +![Image 1 from page 69](pdf-image://page_69_img_1) + +## Page 70 + +Orderable part numbers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +70 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 70](pdf-image://page_70_img_1) + +## Page 71 + +Chapter 3 +Chip Configuration +3.1 +Introduction +This chapter provides details on the individual modules of the microcontroller. It +includes: +• module block diagrams showing immediate connections within the device, +• specific module-to-module interactions not necessarily discussed in the individual +module chapters, and +• links for more information. +3.2 +Core modules +3.2.1 +ARM Cortex-M4 Core Configuration +This section summarizes how the module has been configured in the chip. Full +documentation for this module is provided by ARM and can be found at http:// +www.arm.com. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +71 +General Business Information + +![Image 1 from page 71](pdf-image://page_71_img_1) + +## Page 72 + +PPB Modules +PPB +ARM Cortex-M4 +Core +Debug +Interrupts +Crossbar +switch +SRAM +Upper +SRAM +Lower +Figure 3-1. Core configuration +Table 3-1. Reference links to related information +Topic +Related module +Reference +Full description +ARM Cortex-M4 core, +r0p1 +http://www.arm.com +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +System/instruction/data +bus module +Crossbar switch +Crossbar switch +System/instruction/data +bus module +SRAM +SRAM +Debug +IEEE 1149.1 JTAG +Serial Wire Debug +(SWD) +ARM Real-Time Trace +Interface +Debug +Interrupts +Nested Vectored +Interrupt Controller +(NVIC) +NVIC +Private Peripheral Bus +(PPB) module +Miscellaneous Control +Module (MCM) +MCM +Private Peripheral Bus +(PPB) module +Memory-Mapped +Cryptographic +Acceleration Unit +(MMCAU) +MMCAU +3.2.1.1 +Buses, interconnects, and interfaces +The ARM Cortex-M4 core has four buses as described in the following table. +Core modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +72 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 72](pdf-image://page_72_img_1) + +## Page 73 + +Bus name +Description +Instruction code (ICODE) bus +The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is +connected to the crossbar switch via a single master port. In addition, the CODE bus is also +tightly coupled to the lower half of the system RAM (SRAM\_L). +Data code (DCODE) bus +System bus +The system bus is connected to a separate master port on the crossbar. In addition, the +system bus is tightly coupled to the upper half system RAM (SRAM\_U). +Private peripheral (PPB) bus +The PPB provides access to these modules: +• ARM modules such as the NVIC, ETM, ITM, DWT, FBP, and ROM table +• Freescale Miscellaneous Control Module (MCM) +• Memory-Mapped Cryptographic Acceleration Unit (MMCAU) +3.2.1.2 +System Tick Timer +The System Tick Timer's clock source is always the core clock, FCLK. This results in the +following: +• The CLKSOURCE bit in SysTick Control and Status register is always set to select +the core clock. +• Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the +SysTick Calibration Value Register is always zero. +• The NOREF bit in SysTick Calibration Value Register is always set, implying that +FCLK is the only available source of reference timing. +3.2.1.3 +Debug facilities +This device has extensive debug capabilities including run control and tracing +capabilities. The standard ARM debug port that supports JTAG and SWD interfaces. +Also the cJTAG interface is supported on this device. +3.2.1.4 +Core privilege levels +The ARM documentation uses different terms than this document to distinguish between +privilege levels. +If you see this term... +it also means this term... +Privileged +Supervisor +Unprivileged or user +User +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +73 +General Business Information + +![Image 1 from page 73](pdf-image://page_73_img_1) + +## Page 74 + +3.2.2 +Nested Vectored Interrupt Controller (NVIC) Configuration +This section summarizes how the module has been configured in the chip. Full +documentation for this module is provided by ARM and can be found at http:// +www.arm.com. +Nested Vectored +Interrupt Controller +(NVIC) +ARM Cortex-M4 +core +Interrupts +Module +Module +Module +PPB +Figure 3-2. NVIC configuration +Table 3-2. Reference links to related information +Topic +Related module +Reference +Full description +Nested Vectored +Interrupt Controller +(NVIC) +http://www.arm.com +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Private Peripheral Bus +(PPB) +ARM Cortex-M4 core +ARM Cortex-M4 core +3.2.2.1 +Interrupt priority levels +This device supports 16 priority levels for interrupts. Therefore, in the NVIC each source +in the IPR registers contains 4 bits. For example, IPR0 is shown below: +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +IRQ3 +0 +0 +0 +0 +IRQ2 +0 +0 +0 +0 +IRQ1 +0 +0 +0 +0 +IRQ0 +0 +0 +0 +0 +W +3.2.2.2 +Non-maskable interrupt +The non-maskable interrupt request to the NVIC is controlled by the external NMI signal. +The pin the NMI signal is multiplexed on, must be configured for the NMI function to +generate the non-maskable interrupt request. +Core modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +74 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 74](pdf-image://page_74_img_1) + +## Page 75 + +3.2.2.3 +Interrupt channel assignments +The interrupt source assignments are defined in the following table. +• Vector number — the value stored on the stack when an interrupt is serviced. +• IRQ number — non-core interrupt source count, which is the vector number minus +16. +The IRQ number is used within ARM's NVIC documentation. +Table 3-4. Interrupt vector assignments +Address +Vector +IRQ1 +NVIC +non-IPR +register +number +2 +NVIC +IPR +register +number +3 +Source module +Source description +ARM Core System Handler Vectors +0x0000\_0000 +0 +– +– +– +ARM core +Initial Stack Pointer +0x0000\_0004 +1 +– +– +– +ARM core +Initial Program Counter +0x0000\_0008 +2 +– +– +– +ARM core +Non-maskable Interrupt (NMI) +0x0000\_000C +3 +– +– +– +ARM core +Hard Fault +0x0000\_0010 +4 +– +– +– +ARM core +MemManage Fault +0x0000\_0014 +5 +– +– +– +ARM core +Bus Fault +0x0000\_0018 +6 +– +– +– +ARM core +Usage Fault +0x0000\_001C +7 +– +– +– +— +— +0x0000\_0020 +8 +– +– +– +— +— +0x0000\_0024 +9 +– +– +– +— +— +0x0000\_0028 +10 +– +– +– +— +— +0x0000\_002C +11 +– +– +– +ARM core +Supervisor call (SVCall) +0x0000\_0030 +12 +– +– +– +ARM core +Debug Monitor +0x0000\_0034 +13 +– +– +– +— +— +0x0000\_0038 +14 +– +– +– +ARM core +Pendable request for system service +(PendableSrvReq) +0x0000\_003C +15 +– +– +– +ARM core +System tick timer (SysTick) +Non-Core Vectors +0x0000\_0040 +16 +0 +0 +0 +DMA +DMA channel 0 transfer complete +0x0000\_0044 +17 +1 +0 +0 +DMA +DMA channel 1 transfer complete +0x0000\_0048 +18 +2 +0 +0 +DMA +DMA channel 2 transfer complete +0x0000\_004C +19 +3 +0 +0 +DMA +DMA channel 3 transfer complete +0x0000\_0050 +20 +4 +0 +1 +DMA +DMA channel 4 transfer complete +0x0000\_0054 +21 +5 +0 +1 +DMA +DMA channel 5 transfer complete +0x0000\_0058 +22 +6 +0 +1 +DMA +DMA channel 6 transfer complete +0x0000\_005C +23 +7 +0 +1 +DMA +DMA channel 7 transfer complete +0x0000\_0060 +24 +8 +0 +2 +DMA +DMA channel 8 transfer complete +Table continues on the next page... +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +75 +General Business Information + +![Image 1 from page 75](pdf-image://page_75_img_1) + +## Page 76 + +Table 3-4. Interrupt vector assignments (continued) +Address +Vector +IRQ1 +NVIC +non-IPR +register +number +2 +NVIC +IPR +register +number +3 +Source module +Source description +0x0000\_0064 +25 +9 +0 +2 +DMA +DMA channel 9 transfer complete +. +0x0000\_0068 +26 +10 +0 +2 +DMA +DMA channel 10 transfer complete +0x0000\_006C +27 +11 +0 +2 +DMA +DMA channel 11 transfer complete +0x0000\_0070 +28 +12 +0 +3 +DMA +DMA channel 12 transfer complete +0x0000\_0074 +29 +13 +0 +3 +DMA +DMA channel 13 transfer complete +0x0000\_0078 +30 +14 +0 +3 +DMA +DMA channel 14 transfer complete +0x0000\_007C +31 +15 +0 +3 +DMA +DMA channel 15 transfer complete +0x0000\_0080 +32 +16 +0 +4 +DMA +DMA error interrupt channels 0-15 +0x0000\_0084 +33 +17 +0 +4 +MCM +Normal interrupt +0x0000\_0088 +34 +18 +0 +4 +Flash memory +Command complete +0x0000\_008C +35 +19 +0 +4 +Flash memory +Read collision +0x0000\_0090 +36 +20 +0 +5 +Mode Controller +Low-voltage detect, low-voltage warning +0x0000\_0094 +37 +21 +0 +5 +LLWU +Low Leakage Wakeup +NOTE: The LLWU interrupt must not be +masked by the interrupt +controller to avoid a scenario +where the system does not fully +exit stop mode on an LLS +recovery. +0x0000\_0098 +38 +22 +0 +5 +WDOG or EWM +Both watchdog modules share this +interrupt. +0x0000\_009C +39 +23 +0 +5 +RNG +Randon Number Generator +0x0000\_00A0 +40 +24 +0 +6 +I2C0 +— +0x0000\_00A4 +41 +25 +0 +6 +I2C1 +— +0x0000\_00A8 +42 +26 +0 +6 +SPI0 +Single interrupt vector for all sources +0x0000\_00AC +43 +27 +0 +6 +SPI1 +Single interrupt vector for all sources +0x0000\_00B0 +44 +28 +0 +7 +SPI2 +Single interrupt vector for all sources +0x0000\_00B4 +45 +29 +0 +7 +CAN0 +OR'ed Message buffer (0-15) +0x0000\_00B8 +46 +30 +0 +7 +CAN0 +Bus Off +0x0000\_00BC +47 +31 +0 +7 +CAN0 +Error +0x0000\_00C0 +48 +32 +1 +8 +CAN0 +Transmit Warning +0x0000\_00C4 +49 +33 +1 +8 +CAN0 +Receive Warning +0x0000\_00C8 +50 +34 +1 +8 +CAN0 +Wake Up +0x0000\_00CC +51 +35 +1 +8 +I2S0 +Transmit +0x0000\_00D0 +52 +36 +1 +9 +I2S0 +Receive +0x0000\_00D4 +53 +37 +1 +9 +CAN1 +OR'ed Message buffer (0-15) +0x0000\_00D8 +54 +38 +1 +9 +CAN1 +Bus off +Table continues on the next page... +Core modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +76 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 76](pdf-image://page_76_img_1) + +## Page 77 + +Table 3-4. Interrupt vector assignments (continued) +Address +Vector +IRQ1 +NVIC +non-IPR +register +number +2 +NVIC +IPR +register +number +3 +Source module +Source description +0x0000\_00DC +55 +39 +1 +9 +CAN1 +Error +0x0000\_00E0 +56 +40 +1 +10 +CAN1 +Transmit Warning +0x0000\_00E4 +57 +41 +1 +10 +CAN1 +Receive Warning +0x0000\_00E8 +58 +42 +1 +10 +CAN1 +Wake Up +0x0000\_00EC +59 +43 +1 +10 +— +— +0x0000\_00F0 +60 +44 +1 +11 +UART0 +Single interrupt vector for UART LON +sources +0x0000\_00F4 +61 +45 +1 +11 +UART0 +Single interrupt vector for UART status +sources +0x0000\_00F8 +62 +46 +1 +11 +UART0 +Single interrupt vector for UART error +sources +0x0000\_00FC +63 +47 +1 +11 +UART1 +Single interrupt vector for UART status +sources +0x0000\_0100 +64 +48 +1 +12 +UART1 +Single interrupt vector for UART error +sources +0x0000\_0104 +65 +49 +1 +12 +UART2 +Single interrupt vector for UART status +sources +0x0000\_0108 +66 +50 +1 +12 +UART2 +Single interrupt vector for UART error +sources +0x0000\_010C +67 +51 +1 +12 +UART3 +Single interrupt vector for UART status +sources +0x0000\_0110 +68 +52 +1 +13 +UART3 +Single interrupt vector for UART error +sources +0x0000\_0114 +69 +53 +1 +13 +UART4 +Single interrupt vector for UART status +sources +0x0000\_0118 +70 +54 +1 +13 +UART4 +Single interrupt vector for UART error +sources +0x0000\_011C +71 +55 +1 +13 +UART5 +Single interrupt vector for UART status +sources +0x0000\_0120 +72 +56 +1 +14 +UART5 +Single interrupt vector for UART error +sources +0x0000\_0124 +73 +57 +1 +14 +ADC0 +— +0x0000\_0128 +74 +58 +1 +14 +ADC1 +— +0x0000\_012C +75 +59 +1 +14 +CMP0 +— +0x0000\_0130 +76 +60 +1 +15 +CMP1 +— +0x0000\_0134 +77 +61 +1 +15 +CMP2 +— +0x0000\_0138 +78 +62 +1 +15 +FTM0 +Single interrupt vector for all sources +0x0000\_013C +79 +63 +1 +15 +FTM1 +Single interrupt vector for all sources +0x0000\_0140 +80 +64 +2 +16 +FTM2 +Single interrupt vector for all sources +0x0000\_0144 +81 +65 +2 +16 +CMT +— +Table continues on the next page... +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +77 +General Business Information + +![Image 1 from page 77](pdf-image://page_77_img_1) + +## Page 78 + +Table 3-4. Interrupt vector assignments (continued) +Address +Vector +IRQ1 +NVIC +non-IPR +register +number +2 +NVIC +IPR +register +number +3 +Source module +Source description +0x0000\_0148 +82 +66 +2 +16 +RTC +Alarm interrupt +0x0000\_014C +83 +67 +2 +16 +RTC +Seconds interrupt +0x0000\_0150 +84 +68 +2 +17 +PIT +Channel 0 +0x0000\_0154 +85 +69 +2 +17 +PIT +Channel 1 +0x0000\_0158 +86 +70 +2 +17 +PIT +Channel 2 +0x0000\_015C +87 +71 +2 +17 +PIT +Channel 3 +0x0000\_0160 +88 +72 +2 +18 +PDB +— +0x0000\_0164 +89 +73 +2 +18 +USB OTG +— +0x0000\_0168 +90 +74 +2 +18 +USB Charger +Detect +— +0x0000\_016C +91 +75 +2 +18 +Ethernet MAC +IEEE 1588 Timer Interrupt +0x0000\_0170 +92 +76 +2 +19 +Ethernet MAC +Transmit interrupt +0x0000\_0174 +93 +77 +2 +19 +Ethernet MAC +Receive interrupt +0x0000\_0178 +94 +78 +2 +19 +Ethernet MAC +Error and miscellaneous interrupt +0x0000\_017C +95 +79 +2 +19 +— +— +0x0000\_0180 +96 +80 +2 +20 +SDHC +— +0x0000\_0184 +97 +81 +2 +20 +DAC0 +— +0x0000\_0188 +98 +82 +2 +20 +DAC1 +— +0x0000\_018C +99 +83 +2 +20 +TSI +Single interrupt vector for all sources +0x0000\_0190 +100 +84 +2 +21 +MCG +— +0x0000\_0194 +101 +85 +2 +21 +Low Power Timer +— +0x0000\_0198 +102 +86 +2 +21 +— +— +0x0000\_019C +103 +87 +2 +21 +Port control module Pin detect (Port A) +0x0000\_01A0 +104 +88 +2 +22 +Port control module Pin detect (Port B) +0x0000\_01A4 +105 +89 +2 +22 +Port control module Pin detect (Port C) +0x0000\_01A8 +106 +90 +2 +22 +Port control module Pin detect (Port D) +0x0000\_01AC +107 +91 +2 +22 +Port control module Pin detect (Port E) +0x0000\_01B0 +108 +92 +2 +23 +— +— +0x0000\_01B4 +109 +93 +2 +23 +— +— +0x0000\_01B8 +110 +94 +2 +23 +Software +Software interrupt4 +1. +Indicates the NVIC's interrupt source number. +2. +Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this +value is: IRQ div 32 +3. +Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 +4. +This interrupt can only be pended or cleared via the NVIC registers. +Core modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +78 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 78](pdf-image://page_78_img_1) + +## Page 79 + +3.2.2.3.1 +Determining the bitfield and register location for configuring a +particular interrupt +Suppose you need to configure the low-power timer (LPTMR) interrupt. The following +table is an excerpt of the LPTMR row from Interrupt channel assignments. +Table 3-5. LPTMR interrupt vector assignment +Address +Vector +IRQ1 +NVIC +non-IPR +register +number +2 +NVIC +IPR +register +number +3 +Source module +Source description +0x0000\_0194 +101 +85 +2 +21 +Low Power Timer +— +1. +Indicates the NVIC's interrupt source number. +2. +Indicates the NVIC's ISER, ICER, ISPR, ICPR, and IABR register number used for this IRQ. The equation to calculate this +value is: IRQ div 32 +3. +Indicates the NVIC's IPR register number used for this IRQ. The equation to calculate this value is: IRQ div 4 +• The NVIC registers you would use to configure the interrupt are: +• NVICISER2 +• NVICICER2 +• NVICISPR2 +• NVICICPR2 +• NVICIABR2 +• NVICIPR21 +• To determine the particular IRQ's bitfield location within these particular registers: +• NVICISER2, NVICICER2, NVICISPR2, NVICICPR2, NVICIABR2 bit +location = IRQ mod 32 = 21 +• NVICIPR21 bitfield starting location = 8 * (IRQ mod 4) + 4 = 12 +Since the NVICIPR bitfields are 4-bit wide (16 priority levels), the NVICIPR21 +bitfield range is 12-15 +Therefore, the following bitfield locations are used to configure the LPTMR interrupts: +• NVICISER2[21] +• NVICICER2[21] +• NVICISPR2[21] +• NVICICPR2[21] +• NVICIABR2[21] +• NVICIPR21[15:12] +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +79 +General Business Information + +![Image 1 from page 79](pdf-image://page_79_img_1) + +## Page 80 + +3.2.3 +Asynchronous Wake-up Interrupt Controller (AWIC) +Configuration +This section summarizes how the module has been configured in the chip. Full +documentation for this module is provided by ARM and can be found at http:// +www.arm.com. +Asynchronous +Wake-up Interrupt +Controller (AWIC) +Nested vectored +interrupt controller +(NVIC) +Wake-up +requests +Module +Module +Clock logic +Figure 3-3. Asynchronous Wake-up Interrupt Controller configuration +Table 3-6. Reference links to related information +Topic +Related module +Reference +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Nested Vectored +Interrupt Controller +(NVIC) +NVIC +Wake-up requests +AWIC wake-up sources +3.2.3.1 +Wake-up sources +The device uses the following internal and external inputs to the AWIC module. +Table 3-7. AWIC Stop and VLPS Wake-up Sources +Wake-up source +Description +Available system resets +RESET pin and WDOG when LPO is its clock source, and JTAG +Low-voltage detect +Mode Controller +Low-voltage warning +Mode Controller +Pin interrupts +Port Control Module - Any enabled pin interrupt is capable of waking the system +ADCx +The ADC is functional when using internal clock source +CMPx +Since no system clocks are available, functionality is limited +I2C +Address match wakeup +Table continues on the next page... +Core modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +80 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 80](pdf-image://page_80_img_1) + +## Page 81 + +Table 3-7. AWIC Stop and VLPS Wake-up Sources (continued) +Wake-up source +Description +UART +Active edge on RXD +USB +Wakeup +LPTMR +Functional in Stop/VLPS modes +RTC +Functional in Stop/VLPS modes +Ethernet +Magic Packet wakeup +SDHC +Wakeup +I2S +Functional when using an external bit clock or external master clock +1588 Timer +Wakeup +TSI +CAN +NMI +Non-maskable interrupt +3.2.4 +JTAG Controller Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +JTAG controller +cJTAG +Figure 3-4. JTAGC Controller configuration +Table 3-8. Reference links to related information +Topic +Related module +Reference +Full description +JTAGC +JTAGC +Signal multiplexing +Port control +Signal multiplexing +3.3 +System modules +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +81 +General Business Information + +![Image 1 from page 81](pdf-image://page_81_img_1) + +## Page 82 + +3.3.1 +SIM Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Register +access +Peripheral +bridge +System integration +module (SIM) +Figure 3-5. SIM configuration +Table 3-9. Reference links to related information +Topic +Related module +Reference +Full description +SIM +SIM +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +3.3.2 +System Mode Controller (SMC) Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +System modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +82 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 82](pdf-image://page_82_img_1) + +## Page 83 + +Power Management +Controller (PMC) +Register +access +Peripheral +bridge +System Mode +Controller (SMC) +Resets +Figure 3-6. System Mode Controller configuration +Table 3-10. Reference links to related information +Topic +Related module +Reference +Full description +System Mode +Controller (SMC) +SMC +System memory map +System memory map +Power management +Power management +Power management +controller (PMC) +PMC +Low-Leakage Wakeup +Unit (LLWU) +LLWU +Reset Control Module +(RCM) +Reset +3.3.3 +PMC Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +83 +General Business Information + +![Image 1 from page 83](pdf-image://page_83_img_1) + +## Page 84 + +Register access +Power Management +Controller (PMC) +Module +signals +Peripheral +bridge +Module +signals +System Mode +Controller (SMC) +Low-Leakage +Wakeup Unit +Figure 3-7. PMC configuration +Table 3-11. Reference links to related information +Topic +Related module +Reference +Full description +PMC +PMC +System memory map +System memory map +Power management +Power management +Full description +System Mode +Controller (SMC) +System Mode Controller +Low-Leakage Wakeup +Unit (LLWU) +LLWU +Reset Control Module +(RCM) +Reset +3.3.4 +Low-Leakage Wake-up Unit (LLWU) Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +System modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +84 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 84](pdf-image://page_84_img_1) + +## Page 85 + +Low-Leakage Wake-up +Unit (LLWU) +Power Management +Controller (PMC) +Peripheral +bridge 0 +Register +access +Wake-up +requests +Module +Module +Figure 3-8. Low-Leakage Wake-up Unit configuration +Table 3-12. Reference links to related information +Topic +Related module +Reference +Full description +LLWU +LLWU +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management chapter +Power Management +Controller (PMC) +Power Management Controller (PMC) +Mode Controller +Mode Controller +Wake-up requests +LLWU wake-up sources +3.3.4.1 +Wake-up Sources +This chip uses the following internal peripheral and external pin inputs as wakeup +sources to the LLWU module: +• LLWU\_P0-15 are external pin inputs. Any digital function multiplexed on the pin +can be selected as the wakeup source. See the chip's signal multiplexing table for the +digital signal options. +• LLWU\_M0IF-M7IF are connections to the internal peripheral interrupt flags. +NOTE +RESET is also a wakeup source, depending on the bit setting in +the LLWU\_RST register. On devices where RESET is not a +dedicated pin, it must also be enabled in the explicit port mux +control. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +85 +General Business Information + +![Image 1 from page 85](pdf-image://page_85_img_1) + +## Page 86 + +Table 3-13. Wakeup sources for LLWU inputs +Input +Wakeup source +Input +Wakeup source +LLWU\_P0 +PTE1/LLWU\_P0 pin +LLWU\_P12 +PTD0/LLWU\_P12 pin +LLWU\_P1 +PTE2/LLWU\_P1 pin +LLWU\_P13 +PTD2/LLWU\_P13 pin +LLWU\_P2 +PTE4/LLWU\_P2 pin +LLWU\_P14 +PTD4/LLWU\_P14 pin +LLWU\_P3 +PTA4/LLWU\_P3 pin1 +LLWU\_P15 +PTD6/LLWU\_P15 pin +LLWU\_P4 +PTA13/LLWU\_P4 pin +LLWU\_M0IF +LPTMR2 +LLWU\_P5 +PTB0/LLWU\_P5 pin +LLWU\_M1IF +CMP02 +LLWU\_P6 +PTC1/LLWU\_P6 pin +LLWU\_M2IF +CMP12 +LLWU\_P7 +PTC3/LLWU\_P7 pin +LLWU\_M3IF +CMP22 +LLWU\_P8 +PTC4/LLWU\_P8 pin +LLWU\_M4IF +TSI2 +LLWU\_P9 +PTC5/LLWU\_P9 pin +LLWU\_M5IF +RTC Alarm2 +LLWU\_P10 +PTC6/LLWU\_P10 pin +LLWU\_M6IF +Reserved +LLWU\_P11 +PTC11/LLWU\_P11 pin +LLWU\_M7IF +RTC Seconds2 +1. +The EZP\_CS signal is checked only on Chip Reset not VLLS, so a VLLS wakeup via a non-reset source does not cause +EzPort mode entry. If NMI was enabled on entry to LLS/VLLS, asserting the NMI pin generates an NMI interrupt on exit +from the low power mode. NMI can also be disabled via the FOPT[NMI\_DIS] bit. +2. +Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag +as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism. +3.3.5 +MCM Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Miscellaneous +Control Module +(MCM) +Transfers +ARM Cortex-M4 +core +PPB +Figure 3-9. MCM configuration +Table 3-14. Reference links to related information +Topic +Related module +Reference +Full description +Miscellaneous control +module (MCM) +MCM +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Transfers +Private Peripheral Bus +(PPB) +ARM Cortex-M4 core +ARM Cortex-M4 core +System modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +86 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 86](pdf-image://page_86_img_1) + +## Page 87 + +3.3.6 +Crossbar Switch Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Crossbar Switch +Slave Modules +SDHC +Master Modules +M2 +M5 +M0 +M1 +S0 +S3 +ARM core +code bus +ARM core +system bus +DMA +EzPort +Mux +Flash +controller +S1 +SRAM +backdoor +S2 +Peripheral +bridge 0 +Memory protection unit +(MPU) +Mux +Peripheral +bridge 1 +GPIO +controller +S4 +FlexBus +MPU +USB +M4 +Ethernet +M3 +Figure 3-10. Crossbar switch configuration +Table 3-15. Reference links to related information +Topic +Related module +Reference +Full description +Crossbar switch +Crossbar Switch +System memory map +System memory map +Clocking +Clock Distribution +Memory protection +MPU +MPU +Crossbar switch master +ARM Cortex-M4 core +ARM Cortex-M4 core +Crossbar switch master +DMA controller +DMA controller +Table continues on the next page... +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +87 +General Business Information + +![Image 1 from page 87](pdf-image://page_87_img_1) + +## Page 88 + +Table 3-15. Reference links to related information (continued) +Topic +Related module +Reference +Crossbar switch master +EzPort +EzPort +Crossbar switch master +Ethernet +Ethernet +Crossbar switch master +USB FS/LS +USB FS/LS +Crossbar switch master +SDHC +SDHC +Crossbar switch slave +Flash +Flash +Crossbar switch slave +SRAM backdoor +SRAM backdoor +Crossbar switch slave +Peripheral bridges +Peripheral bridge +Crossbar switch slave +GPIO controller +GPIO controller +Crossbar switch slave +FlexBus +FlexBus +3.3.6.1 +Crossbar Switch Master Assignments +The masters connected to the crossbar switch are assigned as follows: +Master module +Master port number +ARM core code bus +0 +ARM core system bus +1 +DMA/EzPort +2 +Ethernet +3 +USB OTG +4 +SDHC +5 +NOTE +The DMA and EzPort share a master port. Since these modules +never operate at the same time, no configuration or arbitration +explanations are necessary. +3.3.6.2 +Crossbar Switch Slave Assignments +The slaves connected to the crossbar switch are assigned as follows: +Slave module +Slave port number +Protected by MPU? +Flash memory controller +0 +Yes +SRAM backdoor +1 +Yes +Peripheral bridge 01 +2 +No. Protection built into bridge. +Peripheral bridge 1/GPIO1 +3 +No. Protection built into bridge. +FlexBus +4 +Yes +System modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +88 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 88](pdf-image://page_88_img_1) + +## Page 89 + +1. +See System memory map for access restrictions. +3.3.6.3 +PRS register reset values +The AXBS\_PRSn registers reset to 0054\_3210h. +3.3.7 +Memory Protection Unit (MPU) Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Memory Protection +Unit (MPU) +Transfers +Slave +Slave +Slave +Peripheral +bridge 0 +Register +access +Transfers +Logical +Master +Logical +Master +Logical +Master +Figure 3-11. Memory Protection Unit configuration +Table 3-16. Reference links to related information +Topic +Related module +Reference +Full description +Memory Protection Unit +(MPU) +MPU +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Logical masters +Logical master assignments +Slave modules +Slave module assignments +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +89 +General Business Information + +![Image 1 from page 89](pdf-image://page_89_img_1) + +## Page 90 + +3.3.7.1 +MPU Slave Port Assignments +The memory-mapped resources protected by the MPU are: +Table 3-17. MPU Slave Port Assignments +Source +MPU Slave Port Assignment +Destination +Crossbar slave port 0 +MPU slave port 0 +Flash Controller +Crossbar slave port 1 +MPU slave port 1 +SRAM backdoor +Code Bus +MPU slave port 2 +SRAM\_L frontdoor +System Bus +MPU slave port 3 +SRAM\_U frontdoor +Crossbar slave port 4 +MPU slave port 4 +FlexBus +3.3.7.2 +MPU Logical Bus Master Assignments +The logical bus master assignments for the MPU are: +Table 3-18. MPU Logical Bus Master Assignments +MPU Logical Bus Master Number +Bus Master +0 +Core +1 +Debugger +2 +DMA +3 +ENET +4 +USB +5 +SDHC +6 +none +7 +none +3.3.7.3 +MPU Access Violation Indications +Access violations detected by the MPU are signaled to the appropriate bus master as +shown below: +Table 3-19. Access Violation Indications +Bus Master +Core Indication +Core +Bus fault (interrupt vector \#5) Note: To enable bus faults set the core's System +Handler Control and State Register's BUSFAULTENA bit. If this bit is not set, MPU +violations result in a hard fault (interrupt vector \#3). +Debugger +The STICKYERROR flag is set in the Debug Port Control/Status Register. +DMA +Interrupt vector \#32 +Ethernet +Interrupt vector \#94 +Table continues on the next page... +System modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +90 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 90](pdf-image://page_90_img_1) + +## Page 91 + +Table 3-19. Access Violation Indications (continued) +Bus Master +Core Indication +USB\_OTG +Interrupt vector \#89 +SDHC +Interrupt vector \#96 +3.3.7.4 +Reset Values for RGD0 Registers +At reset, the MPU is enabled with a single region descriptor (RGD0) that maps the entire +4 GB address space with read, write and execute permissions given to the core, debugger +and the DMA bus masters. +The following table shows the chip-specific reset values for RGD0 and RGDAAC0. +Table 3-20. Reset Values for RGD0 Registers +Register +Reset value +RGD0\_WORD0 +0000\_0000h +RGD0\_WORD1 +FFFF\_FFFFh +RGD0\_WORD2 +0061\_F7DFh +RGD0\_WORD3 +0000\_0001h +RGDAAC0 +0061\_F7DFh +3.3.7.5 +Write Access Restrictions for RGD0 Registers +In addition to configuring the initial state of RGD0, the MPU implements further access +control on writes to the RGD0 registers. Specifically, the MPU assigns a priority scheme +where the debugger is treated as the highest priority master followed by the core and then +all the remaining masters. +The MPU does not allow writes from the core to affect the RGD0 start or end addresses +nor the permissions associated with the debugger; it can only write the permission fields +associated with the other masters. +These protections (summarized below) guarantee that the debugger always has access to +the entire address space and those rights cannot be changed by the core or any other bus +master. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +91 +General Business Information + +![Image 1 from page 91](pdf-image://page_91_img_1) + +## Page 92 + +Table 3-21. Write Access to RGD0 Registers +Bus Master +Write Access? +Core +Partial. The Core cannot write to the following registers or +register fields: +• RGD0\_WORD0, RGD0\_WORD1, RGD0\_WORD3 +• RGD0\_WORD2[M1SM, M1UM] +• RGDAAC0[M1SM, M1UM] +NOTE: Changes to the RGD0\_WORD2 alterable fields +should be done via a write to RGDAAC0. +Debugger +Yes +All other masters +No +3.3.8 +Peripheral Bridge Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Peripherals +Transfers +AIPS-Lite +peripheral bridge +Transfers +Crossbar switch +Figure 3-12. Peripheral bridge configuration +Table 3-22. Reference links to related information +Topic +Related module +Reference +Full description +Peripheral bridge +(AIPS-Lite) +Peripheral bridge (AIPS-Lite) +System memory map +System memory map +Clocking +Clock Distribution +Crossbar switch +Crossbar switch +Crossbar switch +3.3.8.1 +Number of peripheral bridges +This device contains two identical peripheral bridges. +System modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +92 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 92](pdf-image://page_92_img_1) + +## Page 93 + +3.3.8.2 +Memory maps +The peripheral bridges are used to access the registers of most of the modules on this +device. See AIPS0 Memory Map and AIPS1 Memory Map for the memory slot +assignment for each module. +3.3.8.3 +MPRA register +Each of the two peripheral bridges supports up to 8 crossbar switch masters, each +assigned to a MPROTx field in the MPRA register. However, fewer are supported on this +device. See Crossbar switch for details of the master port assignments for this device. +3.3.8.4 +AIPS\_Lite MPRA register reset value +• AIPSx\_MPRA reset value is 0x7770\_0000 +Therefore, masters 0, 1, and 2 are trusted bus masters after reset. +3.3.8.5 +PACR registers +Each of the two peripheral bridges support up to 128 peripherals each assigned to an +PACRx field within the PACRA-PACRP registers. However, fewer peripherals are +supported on this device. See AIPS0 Memory MapandAIPS1 Memory Map for details of +the peripheral slot assignments for this device. Unused PACRx fields are reserved. +3.3.8.6 +AIPS\_Lite PACRE-P register reset values +The AIPSx\_PACRE-P reset values depend on if the module is available on your +particular device. For each populated slot in slots 32-127 in Peripheral Bridge 0 (AIPS- +Lite 0) Memory Map and Peripheral Bridge 1 (AIPS-Lite 1) Memory Map, the +corresponding module's PACR[32:127] field resets to 0x4. +3.3.9 +DMA request multiplexer configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +93 +General Business Information + +![Image 1 from page 93](pdf-image://page_93_img_1) + +## Page 94 + +DMA Request +Multiplexer +DMA controller +Requests +Module +Module +Module +Peripheral +bridge 0 +Register +access +Channel +request +Figure 3-13. DMA request multiplexer configuration +Table 3-23. Reference links to related information +Topic +Related module +Reference +Full description +DMA request +multiplexer +DMA Mux +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Channel request +DMA controller +DMA Controller +Requests +DMA request sources +3.3.9.1 +DMA MUX request sources +This device includes a DMA request mux that allows up to 63 DMA request signals to be +mapped to any of the 16 DMA channels. +Because of the mux there is not a hard correlation between any of the DMA request +sources and a specific DMA channel. +Table 3-24. DMA request sources - MUX 0 +Source +number +Source module +Source description +0 +— +Channel disabled1 +1 +Reserved +Not used +2 +UART0 +Receive +3 +UART0 +Transmit +4 +UART1 +Receive +5 +UART1 +Transmit +6 +UART2 +Receive +7 +UART2 +Transmit +8 +UART3 +Receive +Table continues on the next page... +System modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +94 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 94](pdf-image://page_94_img_1) + +## Page 95 + +Table 3-24. DMA request sources - MUX 0 (continued) +Source +number +Source module +Source description +9 +UART3 +Transmit +10 +UART4 +Receive +11 +UART4 +Transmit +12 +UART5 +Receive +13 +UART5 +Transmit +14 +I2S0 +Receive +15 +I2S0 +Transmit +16 +SPI0 +Receive +17 +SPI0 +Transmit +18 +SPI1 +Receive +19 +SPI1 +Transmit +20 +SPI2 +Receive +21 +SPI2 +Transmit +22 +I2C0 +— +23 +I2C1 +— +24 +FTM0 +Channel 0 +25 +FTM0 +Channel 1 +26 +FTM0 +Channel 2 +27 +FTM0 +Channel 3 +28 +FTM0 +Channel 4 +29 +FTM0 +Channel 5 +30 +FTM0 +Channel 6 +31 +FTM0 +Channel 7 +32 +FTM1 +Channel 0 +33 +FTM1 +Channel 1 +34 +FTM2 +Channel 0 +35 +FTM2 +Channel 1 +36 +IEEE 1588 Timers +Timer 0 +37 +IEEE 1588 Timers +Timer 1 +38 +IEEE 1588 Timers +Timer 2 +39 +IEEE 1588 Timers +Timer 3 +40 +ADC0 +— +41 +ADC1 +— +42 +CMP0 +— +43 +CMP1 +— +44 +CMP2 +— +45 +DAC0 +— +46 +DAC1 +— +47 +CMT +— +Table continues on the next page... +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +95 +General Business Information + +![Image 1 from page 95](pdf-image://page_95_img_1) + +## Page 96 + +Table 3-24. DMA request sources - MUX 0 (continued) +Source +number +Source module +Source description +48 +PDB +— +49 +Port control module +Port A +50 +Port control module +Port B +51 +Port control module +Port C +52 +Port control module +Port D +53 +Port control module +Port E +54 +DMA MUX +Always enabled +55 +DMA MUX +Always enabled +56 +DMA MUX +Always enabled +57 +DMA MUX +Always enabled +58 +DMA MUX +Always enabled +59 +DMA MUX +Always enabled +60 +DMA MUX +Always enabled +61 +DMA MUX +Always enabled +62 +DMA MUX +Always enabled +63 +DMA MUX +Always enabled +1. +Configuring a DMA channel to select source 0 or any of the reserved sources disables that DMA channel. +3.3.9.2 +DMA transfers via PIT trigger +The PIT module can trigger a DMA transfer on the first four DMA channels. The +assignments are detailed at PIT/DMA Periodic Trigger Assignments . +3.3.10 +DMA Controller Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +System modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +96 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 96](pdf-image://page_96_img_1) + +## Page 97 + +DMA Controller +Crossbar switch +Requests +Peripheral +bridge 0 +Register +access +Transfers +DMA Multiplexer +Figure 3-14. DMA Controller configuration +Table 3-25. Reference links to related information +Topic +Related module +Reference +Full description +DMA Controller +DMA Controller +System memory map +System memory map +Register access +Peripheral bridge +(AIPS-Lite 0) +AIPS-Lite 0 +Clocking +Clock distribution +Power management +Power management +Transfers +Crossbar switch +Crossbar switch +3.3.11 +External Watchdog Monitor (EWM) Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +97 +General Business Information + +![Image 1 from page 97](pdf-image://page_97_img_1) + +## Page 98 + +External Watchdog +Monitor (EWM) +Peripheral +bridge 0 +Register +access +Signal multiplexing +Module signals +Figure 3-15. External Watchdog Monitor configuration +Table 3-26. Reference links to related information +Topic +Related module +Reference +Full description +External Watchdog +Monitor (EWM) +EWM +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Signal multiplexing +Port Control Module +Signal multiplexing +3.3.11.1 +EWM clocks +This table shows the EWM clocks and the corresponding chip clocks. +Table 3-27. EWM clock connections +Module clock +Chip clock +Low Power Clock +1 kHz LPO Clock +3.3.11.2 +EWM low-power modes +This table shows the EWM low-power modes and the corresponding chip low-power +modes. +Table 3-28. EWM low-power modes +Module mode +Chip mode +Wait +Wait, VLPW +Stop +Stop, VLPS, LLS +Power Down +VLLS3, VLLS2, VLLS1 +System modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +98 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 98](pdf-image://page_98_img_1) + +## Page 99 + +3.3.11.3 +EWM\_OUT pin state in low power modes +During Wait, Stop and Power Down modes the EWM\_OUT pin enters a high-impedance +state. A user has the option to control the logic state of the pin using an external pull +device or by configuring the internal pull device. When the CPU enters a Run mode from +Wait or Stop recovery, the pin resumes its previous state before entering Wait or Stop +mode. When the CPU enters Run mode from Power Down, the pin returns to its reset +state. +3.3.12 +Watchdog Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +WDOG +Mode Controller +Peripheral +bridge 0 +Register +access +Figure 3-16. Watchdog configuration +Table 3-29. Reference links to related information +Topic +Related module +Reference +Full description +Watchdog +Watchdog +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Mode Controller (MC) +System Mode Controller +3.3.12.1 +WDOG clocks +This table shows the WDOG module clocks and the corresponding chip clocks. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +99 +General Business Information + +![Image 1 from page 99](pdf-image://page_99_img_1) + +## Page 100 + +Table 3-30. WDOG clock connections +Module clock +Chip clock +LPO Oscillator +1 kHz LPO Clock +Alt Clock +Bus Clock +Fast Test Clock +Bus Clock +System Bus Clock +Bus Clock +3.3.12.2 +WDOG low-power modes +This table shows the WDOG low-power modes and the corresponding chip low-power +modes. +Table 3-31. WDOG low-power modes +Module mode +Chip mode +Wait +Wait, VLPW +Stop +Stop, VLPS +Power Down +LLS, VLLSx +3.4 +Clock modules +3.4.1 +MCG Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Clock modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +100 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 100](pdf-image://page_100_img_1) + +## Page 101 + +Register +access +Peripheral +bridge +Multipurpose Clock +Generator (MCG) +RTC +oscillator +System +oscillator +System integration +module (SIM) +Figure 3-17. MCG configuration +Table 3-32. Reference links to related information +Topic +Related module +Reference +Full description +MCG +MCG +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Signal multiplexing +Port control +Signal multiplexing +3.4.2 +OSC Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Register +access +Peripheral +bridge +System oscillator +MCG +Module signals +Figure 3-18. OSC configuration +Table 3-33. Reference links to related information +Topic +Related module +Reference +Full description +OSC +OSC +System memory map +System memory map +Clocking +Clock distribution +Table continues on the next page... +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +101 +General Business Information + +![Image 1 from page 101](pdf-image://page_101_img_1) + +## Page 102 + +Table 3-33. Reference links to related information (continued) +Topic +Related module +Reference +Power management +Power management +Signal multiplexing +Port control +Signal multiplexing +Full description +MCG +MCG +3.4.2.1 +OSC modes of operation with MCG +The MCG's C2 register bits configure the oscillator frequency range. See the OSC and +MCG chapters for more details. +3.4.3 +RTC OSC configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +32-kHz RTC oscillator +MCG +Module signals +Figure 3-19. RTC OSC configuration +Table 3-34. Reference links to related information +Topic +Related module +Reference +Full description +RTC OSC +RTC OSC +Signal multiplexing +Port control +Signal multiplexing +Full description +MCG +MCG +3.5 +Memories and memory interfaces +3.5.1 +Flash Memory Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Memories and memory interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +102 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 102](pdf-image://page_102_img_1) + +## Page 103 + +Register +access +Flash memory +Transfers +Flash memory +controller +Peripheral bus +controller 0 +Figure 3-20. Flash memory configuration +Table 3-35. Reference links to related information +Topic +Related module +Reference +Full description +Flash memory +Flash memory +System memory map +System memory map +Clocking +Clock Distribution +Transfers +Flash memory +controller +Flash memory controller +Register access +Peripheral bridge +Peripheral bridge +3.5.1.1 +Flash memory types +This device contains the following types of flash memory: +• Program flash memory — non-volatile flash memory that can execute program code +• FlexMemory — encompasses the following memory types: +• For devices with FlexNVM: FlexNVM — Non-volatile flash memory that can +execute program code, store data, or backup EEPROM data +• For devices with FlexNVM: FlexRAM — RAM memory that can be used as +traditional RAM or as high-endurance EEPROM storage, and also accelerates +flash programming +• For devices with only program flash memory: Programming acceleration RAM +— RAM memory that accelerates flash programming +3.5.1.2 +Flash Memory Sizes +The devices covered in this document contain: +• For devices with program flash only: 2 blocks of program flash consisting of 2 KB +sectors +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +103 +General Business Information + +![Image 1 from page 103](pdf-image://page_103_img_1) + +## Page 104 + +• For devices that contain FlexNVM: 1 block of program flash consisting of 2 KB +sectors +• For devices that contain FlexNVM: 1 block of FlexNVM consisting of 2 KB sectors +• For devices that contain FlexNVM: 1 block of FlexRAM +The amounts of flash memory for the devices covered in this document are: +Device +Program +flash (KB) +Block 0 (P- +Flash) +address +range1 +FlexNVM +(KB) +Block 1 +(FlexNVM/ P- +Flash) +address +range1 +FlexRAM/ +Programming +Acceleration +RAM (KB) +FlexRAM/ +Programming +Acceleration +RAM address +range +MK60DN256VL +Q10 +256 +0x0000\_0000 – +0x0001\_FFFF +— +0x0002\_0000 – +0x0003\_FFFF +4 +0x1400\_0000 – +0x1400\_0FFF +MK60DX256VL +Q10 +256 +0x0000\_0000 – +0x0003\_FFFF +256 +0x1000\_0000 – +0x1003\_FFFF +4 +0x1400\_0000 – +0x1400\_0FFF +MK60DN512VL +Q10 +512 +0x0000\_0000 – +0x0003\_FFFF +— +0x0004\_0000 – +0x0007\_FFFF +4 +0x1400\_0000 – +0x1400\_0FFF +MK60DN256VM +D10 +256 +0x0000\_0000 – +0x0001\_FFFF +— +0x0002\_0000 – +0x0003\_FFFF +4 +0x1400\_0000 – +0x1400\_0FFF +MK60DX256VM +D10 +256 +0x0000\_0000 – +0x0003\_FFFF +256 +0x1000\_0000 – +0x1003\_FFFF +4 +0x1400\_0000 – +0x1400\_0FFF +MK60DN512VM +D10 +512 +0x0000\_0000 – +0x0003\_FFFF +— +0x0004\_0000 – +0x0007\_FFFF +4 +0x1400\_0000 – +0x1400\_0FFF +1. +For program flash only devices: The addresses shown assume program flash swap is disabled (default configuration). +3.5.1.3 +Flash Memory Size Considerations +Since this document covers devices that contain program flash only and devices that +contain program flash and FlexNVM, there are some items to consider when reading the +flash memory chapter. +• The flash memory chapter shows a mixture of information depending on the device +you are using. +• For the program flash only devices: +• Two program flash blocks are supported: program flash 1 and program flash 2. +The two blocks are contiguous in the system memory map. +• The program flash blocks support a swap feature in which the starting address of +the program flash blocks can be swapped. +• The programming acceleration RAM is used for the Program Section command. +• For the devices containing program flash and FlexNVM: +• Since there is only one program flash block, the program flash swap feature is +not available. +Memories and memory interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +104 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 104](pdf-image://page_104_img_1) + +## Page 105 + +3.5.1.4 +Flash Memory Map +The various flash memories and the flash registers are located at different base addresses +as shown in the following figure. The base address for each is specified in System +memory map. +Program flash +Flash configuration field +Program flash base address +Flash memory base address +Registers +RAM +Programming acceleration +RAM base address +Figure 3-21. Flash memory map for devices containing only program flash +Program flash +Flash configuration field +FlexNVM base address +Program flash base address +Flash memory base address +Registers +FlexNVM +FlexRAM +FlexRAM base address +Figure 3-22. Flash memory map for devices containing FlexNVM +3.5.1.5 +Flash Security +How flash security is implemented on this device is described in Chip Security. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +105 +General Business Information + +![Image 1 from page 105](pdf-image://page_105_img_1) + +## Page 106 + +3.5.1.6 +Flash Modes +The flash memory operates in NVM normal and NVM special modes. The flash memory +enters NVM special mode when the EzPort is enabled (EZP\_CS asserted during reset). +Otherwise, flash memory operates in NVM normal mode. +3.5.1.7 +Erase All Flash Contents +In addition to software, the entire flash memory may be erased external to the flash +memory in two ways: +1. Via the EzPort by issuing a bulk erase (BE) command. See the EzPort chapter for +more details. +2. Via the SWJ-DP debug port by setting DAP\_CONTROL[0]. DAP\_STATUS[0] is set +to indicate the mass erase command has been accepted. DAP\_STATUS[0] is cleared +when the mass erase completes. +3.5.1.8 +FTFL\_FOPT Register +The flash memory's FTFL\_FOPT register allows the user to customize the operation of +the MCU at boot time. See FOPT boot options for details of its definition. +3.5.2 +Flash Memory Controller Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Memories and memory interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +106 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 106](pdf-image://page_106_img_1) + +## Page 107 + +Register +access +Flash memory +controller +Transfers +Memory protection +unit +Peripheral bus +controller 0 +Transfers +Flash memory +Crossbar switch +Figure 3-23. Flash memory controller configuration +Table 3-36. Reference links to related information +Topic +Related module +Reference +Full description +Flash memory +controller +Flash memory controller +System memory map +System memory map +Clocking +Clock Distribution +Transfers +Flash memory +Flash memory +Transfers +MPU +MPU +Transfers +Crossbar switch +Crossbar Switch +Register access +Peripheral bridge +Peripheral bridge +3.5.2.1 +Number of masters +The Flash Memory Controller supports up to eight crossbar switch masters. However, +this device has a different number of crossbar switch masters. See Crossbar Switch +Configuration for details on the master port assignments. +3.5.2.2 +Program Flash Swap +On devices that contain program flash memory only, the program flash memory blocks +may swap their base addresses. +While not using swap: +If swap is used, the opposite is true: +3.5.3 +SRAM Configuration +This section summarizes how the module has been configured in the chip. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +107 +General Business Information + +![Image 1 from page 107](pdf-image://page_107_img_1) + +## Page 108 + +SRAM upper +Transfers +SRAM controller +Cortex-M4 +core +MPU +Crossbar +switch +SRAM lower +MPU +Figure 3-24. SRAM configuration +Table 3-37. Reference links to related information +Topic +Related module +Reference +Full description +SRAM +SRAM +System memory map +System memory map +Clocking +Clock Distribution +Transfers +SRAM controller +SRAM controller +ARM Cortex-M4 core +ARM Cortex-M4 core +Memory protection unit +Memory protection unit +3.5.3.1 +SRAM sizes +This device contains SRAM tightly coupled to the ARM Cortex-M4 core. The amount of +SRAM for the devices covered in this document is shown in the following table. +Device +SRAM (KB) +MK60DN256VLQ10 +64 +MK60DX256VLQ10 +64 +MK60DN512VLQ10 +128 +MK60DN256VMD10 +64 +MK60DX256VMD10 +64 +MK60DN512VMD10 +128 +3.5.3.2 +SRAM Arrays +The on-chip SRAM is split into two equally-sized logical arrays, SRAM\_L and +SRAM\_U. +The on-chip RAM is implemented such that the SRAM\_L and SRAM\_U ranges form a +contiguous block in the memory map. As such: +Memories and memory interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +108 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 108](pdf-image://page_108_img_1) + +## Page 109 + +• SRAM\_L is anchored to 0x1FFF\_FFFF and occupies the space before this ending +address. +• SRAM\_U is anchored to 0x2000\_0000 and occupies the space after this beginning +address. +Valid address ranges for SRAM\_L and SRAM\_U are then defined as: +• SRAM\_L = [0x2000\_0000–(SRAM\_size/2)] to 0x1FFF\_FFFF +• SRAM\_U = 0x2000\_0000 to [0x2000\_0000+(SRAM\_size/2)-1] +This is illustrated in the following figure. +SRAM\_U +0x2000\_0000 +SRAM size / 2 +SRAM\_L +0x1FFF\_FFFF +SRAM size / 2 +0x2000\_0000 – SRAM\_size/2 +0x2000 0000 + SRAM size/2 - 1 +Figure 3-25. SRAM blocks memory map +For example, for a device containing 64 KB of SRAM the ranges are: +• SRAM\_L: 0x1FFF\_8000 – 0x1FFF\_FFFF +• SRAM\_U: 0x2000\_0000 – 0x2000\_7FFF +3.5.3.3 +SRAM retention in low power modes +The SRAM is retained down to VLLS3 mode. +In VLLS2 the 4 or 16 KB (user option) region of SRAM\_U from 0x2000\_0000 is +powered. These different regions (or partitions) of SRAM are labeled as follows: +• RAM1: the 4 KB region always powered in VLLS2 +• RAM2: the additional 12 KB region optionally powered in VLLS2 +• RAM3: the rest of system RAM +In VLLS1 no SRAM is retained; however, the 32-byte register file is available. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +109 +General Business Information + +![Image 1 from page 109](pdf-image://page_109_img_1) + +## Page 110 + +3.5.3.4 +SRAM accesses +The SRAM is split into two logical arrays that are 32-bits wide. +• SRAM\_L — Accessible by the code bus of the Cortex-M4 core and by the backdoor +port. +• SRAM\_U — Accessible by the system bus of the Cortex-M4 core and by the +backdoor port. +The backdoor port makes the SRAM accessible to the non-core bus masters (such as +DMA). +The following figure illustrates the SRAM accesses within the device. +Cortex-M4 core +Code bus +System bus +SRAM controller +Backdoor +SRAM\_L +SRAM\_U +Crossbar switch +non-core master +non-core master +non-core master +Frontdoor +MPU +MPU +Figure 3-26. SRAM access diagram +The following simultaneous accesses can be made to different logical halves of the +SRAM: +• Core code and core system +• Core code and non-core master +• Core system and non-core master +NOTE +Two non-core masters cannot access SRAM simultaneously. +The required arbitration and serialization is provided by the +crossbar switch. The SRAM\_{L,U} arbitration is controlled by +the SRAM controller based on the configuration bits in the +MCM module. +NOTE +Burst-access cannot occur across the 0x2000\_0000 boundary +that separates the two SRAM arrays. The two arrays should be +treated as separate memory ranges for burst accesses. +Memories and memory interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +110 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 110](pdf-image://page_110_img_1) + +## Page 111 + +3.5.3.5 +SRAM arbitration and priority control +The MCM's SRAMAP register controls the arbitration and priority schemes for the two +SRAM arrays. +3.5.4 +SRAM Controller Configuration +This section summarizes how the module has been configured in the chip. +Cortex-M4 +core +MPU +Crossbar +switch +SRAM controller +Transfers +SRAM +upper +SRAM +lower +MPU +Figure 3-27. SRAM controller configuration +Table 3-38. Reference links to related information +Topic +Related module +Reference +System memory map +System memory map +Power management +Power management +Power management +controller (PMC) +PMC +Transfers +SRAM +SRAM +ARM Cortex-M4 core +ARM Cortex-M4 core +MPU +Memory protection unit +Configuration +MCM +MCM +3.5.5 +System Register File Configuration +This section summarizes how the module has been configured in the chip. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +111 +General Business Information + +![Image 1 from page 111](pdf-image://page_111_img_1) + +## Page 112 + +Register file +Peripheral +bridge 0 +Register +access +Figure 3-28. System Register file configuration +Table 3-39. Reference links to related information +Topic +Related module +Reference +Full description +Register file +Register file +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +3.5.5.1 +System Register file +This device includes a 32-byte register file that is powered in all power modes. +Also, it retains contents during low-voltage detect (LVD) events and is only reset during +a power-on reset. +3.5.6 +VBAT Register File Configuration +This section summarizes how the module has been configured in the chip. +Memories and memory interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +112 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 112](pdf-image://page_112_img_1) + +## Page 113 + +VBAT register file +Peripheral +bridge +Register +access +Figure 3-29. VBAT Register file configuration +Table 3-40. Reference links to related information +Topic +Related module +Reference +Full description +VBAT register file +VBAT register file +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +3.5.6.1 +VBAT register file +This device includes a 32-byte register file that is powered in all power modes and is +powered by VBAT. +It is only reset during VBAT power-on reset. +3.5.7 +EzPort Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Module signals +EzPort +Transfers +Crossbar switch +Figure 3-30. EzPort configuration +Table 3-41. Reference links to related information +Topic +Related module +Reference +Full description +EzPort +EzPort +Table continues on the next page... +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +113 +General Business Information + +![Image 1 from page 113](pdf-image://page_113_img_1) + +## Page 114 + +Table 3-41. Reference links to related information (continued) +Topic +Related module +Reference +System memory map +System memory map +Clocking +Clock Distribution +Transfers +Crossbar switch +Crossbar switch +Signal Multiplexing +Port control +Signal Multiplexing +3.5.7.1 +JTAG instruction +The system JTAG controller implements an EZPORT instruction. When executing this +instruction, the JTAG controller resets the core logic and asserts the EzPort chip select +signal to force the processor into EzPort mode. +3.5.7.2 +Flash Option Register (FOPT) +The FOPT[EZPORT\_DIS] bit can be used to prevent entry into EzPort mode during +reset. If the FOPT[EZPORT\_DIS] bit is cleared, then the state of the chip select signal +(EZP\_CS) is ignored and the MCU always boots in normal mode. +This option is useful for systems that use the EZP\_CS/NMI signal configured for its NMI +function. Disabling EzPort mode prevents possible unwanted entry into EzPort mode if +the external circuit that drives the NMI signal asserts it during reset. +The FOPT register is loaded from the flash option byte. If the flash option byte is +modified the new value takes effect for any subsequent resets, until the value is changed +again. +3.5.8 +FlexBus Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Memories and memory interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +114 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 114](pdf-image://page_114_img_1) + +## Page 115 + +Signal multiplexing +Module signals +Register +access +FlexBus +Transfers +Memory protection +unit +Peripheral +bridge 0 +Crossbar switch +Figure 3-31. FlexBus configuration +Table 3-42. Reference links to related information +Topic +Related module +Reference +Full description +FlexBus +FlexBus +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Transfers +Memory protection unit +(MPU) +Memory protection unit (MPU) +Signal multiplexing +Port control +Signal multiplexing +3.5.8.1 +FlexBus clocking +The system provides a dedicated clock source to the FlexBus module's external +CLKOUT. Its clock frequency is derived from a divider of the MCGOUTCLK. See +Clock Distribution for more details. +3.5.8.2 +FlexBus signal multiplexing +The multiplexing of the FlexBus address and data signals is controlled by the port control +module. However, the multiplexing of some of the FlexBus control signals are controlled +by the port control and FlexBus modules. The port control module registers control +whether the FlexBus or another module signals are available on the external pin, while +the FlexBus's CSPMCR register configures which FlexBus signals are available from the +module. The control signals are grouped as illustrated: +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +115 +General Business Information + +![Image 1 from page 115](pdf-image://page_115_img_1) + +## Page 116 + +Group3 +Group2 +Group1 +Group4 +Group5 +CSPMCR +FlexBus +Port Control Module +To other modules +To other modules +To other modules +To other modules +To other modules +External Pins +FB\_ALE +Reserved +FB\_TSIZ0 +Reserved +FB\_TSIZ1 +Reserved +Reserved +Reserved +FB\_CS1 +FB\_TS +FB\_CS4 +FB\_BE\_31\_24 +FB\_BE\_23\_16 +FB\_BE\_15\_8 +FB\_BE\_7\_0 +FB\_CS5 +FB\_TBST +FB\_CS2 +FB\_TA +FB\_CS3 +Figure 3-32. FlexBus control signal multiplexing +Memories and memory interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +116 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 116](pdf-image://page_116_img_1) + +## Page 117 + +Therefore, use the CSPMCR and port control registers to configure which control signal +is available on the external pin. All control signals, except for FB\_TA, are assigned to the +ALT5 function in the port control module. Since, unlike the other control signals, FB\_TA +is an input signal, it is assigned to the ALT6 function. +3.5.8.3 +FlexBus CSCR0 reset value +On this device the CSCR0 resets to 0x003F\_FC00. Configure this register as needed +before performing any FlexBus access. +3.5.8.4 +FlexBus Security +When security is enabled on the device, FlexBus accesses may be restricted by +configuring the FBSL field in the SIM's SOPT2 register. See System Integration Module +(SIM) for details. +3.5.8.5 +FlexBus line transfers +Line transfers are not possible from the ARM Cortex-M4 core. Ignore any references to +line transfers in the FlexBus chapter. +3.6 +Security +3.6.1 +CRC Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +117 +General Business Information + +![Image 1 from page 117](pdf-image://page_117_img_1) + +## Page 118 + +Register +access +Peripheral +bridge +CRC +Figure 3-33. CRC configuration +Table 3-43. Reference links to related information +Topic +Related module +Reference +Full description +CRC +CRC +System memory map +System memory map +Power management +Power management +3.6.2 +MMCAU Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +MMCAU +Transfers +ARM Cortex M4 +Core +PPB +Figure 3-34. MMCAU configuration +Table 3-44. Reference links to related information +Topic +Related module +Reference +Full description +MMCAU +MMCAU +System memory map +System memory map +Clocking +Clock Distribution +Power Management +Power Management +Transfers +Private Peripheral Bus +(PPB) +ARM Cortex M4 Core +Security +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +118 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 118](pdf-image://page_118_img_1) + +## Page 119 + +3.6.3 +RNG Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Register +access +Peripheral +bridge +Random number +generator +Figure 3-35. RNG configuration +Table 3-45. Reference links to related information +Topic +Related module +Reference +Full description +RNG +RNG +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +3.7 +Analog +3.7.1 +16-bit SAR ADC with PGA Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +119 +General Business Information + +![Image 1 from page 119](pdf-image://page_119_img_1) + +## Page 120 + +Signal multiplexing +Module signals +Register +access +16-bit SAR ADC +Peripheral bus +controller 0 +Other peripherals +Transfers +Figure 3-36. 16-bit SAR ADC with PGA configuration +Table 3-46. Reference links to related information +Topic +Related module +Reference +Full description +16-bit SAR ADC with +PGA +16-bit SAR ADC with PGA +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Signal multiplexing +Port control +Signal multiplexing +3.7.1.1 +ADC instantiation information +This device contains two ADCs. Each ADC contains a PGA channel for a total of two +separate PGAs. +3.7.1.1.1 +Number of ADC channels +The number of ADC channels present on the device is determined by the pinout of the +specific device package. For details regarding the number of ADC channel available on a +particular package, refer to the signal multiplexing chapter of this MCU. +3.7.1.2 +DMA Support on ADC +Applications may require continuous sampling of the ADC (4K samples/sec) that may +have considerable load on the CPU. Though using PDB to trigger ADC may reduce some +CPU load, The ADC supports DMA request functionality for higher performance when +the ADC is sampled at a very high rate or cases were PDB is bypassed. The ADC can +trigger the DMA (via DMA req) on conversion completion. +Analog +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +120 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 120](pdf-image://page_120_img_1) + +## Page 121 + +3.7.1.3 +Connections/channel assignment +3.7.1.3.1 +ADC0 Connections/Channel Assignment +NOTE +As indicated by the following sections, each ADCx\_DPx input +and certain ADCx\_DMx inputs may operate as single-ended +ADC channels in single-ended mode. +3.7.1.3.1.1 +ADC0 Channel Assignment for 144-Pin Package +ADC Channel +(SC1n[ADCH]) +Channel +Input signal +(SC1n[DIFF]= 1) +Input signal +(SC1n[DIFF]= 0) +00000 +DAD0 +ADC0\_DP0 and ADC0\_DM01 +ADC0\_DP02 +00001 +DAD1 +ADC0\_DP1 and ADC0\_DM1 +ADC0\_DP1 +00010 +DAD2 +PGA0\_DP and PGA0\_DM +PGA0\_DP +00011 +DAD3 +ADC0\_DP3 and ADC0\_DM33 +ADC0\_DP34 +001005 +AD4a +Reserved +Reserved +001015 +AD5a +Reserved +Reserved +001105 +AD6a +Reserved +Reserved +001115 +AD7a +Reserved +Reserved +001005 +AD4b +Reserved +ADC0\_SE4b +001015 +AD5b +Reserved +ADC0\_SE5b +001105 +AD6b +Reserved +ADC0\_SE6b +001115 +AD7b +Reserved +ADC0\_SE7b +01000 +AD8 +Reserved +ADC0\_SE86 +01001 +AD9 +Reserved +ADC0\_SE97 +01010 +AD10 +Reserved +ADC0\_SE10 +01011 +AD11 +Reserved +ADC0\_SE11 +01100 +AD12 +Reserved +ADC0\_SE12 +01101 +AD13 +Reserved +ADC0\_SE13 +01110 +AD14 +Reserved +ADC0\_SE14 +01111 +AD15 +Reserved +ADC0\_SE15 +10000 +AD16 +Reserved +ADC0\_SE16 +10001 +AD17 +Reserved +ADC0\_SE17 +10010 +AD18 +Reserved +ADC0\_SE18 +10011 +AD19 +Reserved +ADC0\_DM08 +10100 +AD20 +Reserved +ADC0\_DM1 +10101 +AD21 +Reserved +ADC0\_SE21 +10110 +AD22 +Reserved +ADC0\_SE22 +Table continues on the next page... +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +121 +General Business Information + +![Image 1 from page 121](pdf-image://page_121_img_1) + +## Page 122 + +ADC Channel +(SC1n[ADCH]) +Channel +Input signal +(SC1n[DIFF]= 1) +Input signal +(SC1n[DIFF]= 0) +10111 +AD23 +Reserved +12-bit DAC0 Output/ +ADC0\_SE23 +11000 +AD24 +Reserved +Reserved +11001 +AD25 +Reserved +Reserved +11010 +AD26 +Temperature Sensor (Diff) +Temperature Sensor (S.E) +11011 +AD27 +Bandgap (Diff)9 +Bandgap (S.E)9 +11100 +AD28 +Reserved +Reserved +11101 +AD29 +-VREFH (Diff) +VREFH (S.E) +11110 +AD30 +Reserved +VREFL +11111 +AD31 +Module Disabled +Module Disabled +1. +Interleaved with ADC1\_DP3 and ADC1\_DM3 +2. +Interleaved with ADC1\_DP3 +3. +Interleaved with ADC1\_DP0 and ADC1\_DM0 +4. +Interleaved with ADC1\_DP0 +5. +ADCx\_CFG2[MUXSEL] bit selects between ADCx\_SEn channels a and b. Refer to MUXSEL description in ADC chapter +for details. +6. +Interleaved with ADC1\_SE8 +7. +Interleaved with ADC1\_SE9 +8. +Interleaved with ADC1\_DM3 +9. +This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this +ADC channel, ensure that you enable the bandgap buffer by setting the PMC\_REGSC[BGBE] bit. Refer to the device data +sheet for the bandgap voltage (VBG) specification. +3.7.1.4 +ADC1 Connections/Channel Assignment +NOTE +As indicated in the following tables, each ADCx\_DPx input +and certain ADCx\_DMx inputs may operate as single-ended +ADC channels in single-ended mode. +3.7.1.4.1 +ADC1 Channel Assignment for 144-Pin Package +ADC Channel +(SC1n[ADCH]) +Channel +Input signal +(SC1n[DIFF]= 1) +Input signal +(SC1n[DIFF]= 0) +00000 +DAD0 +ADC1\_DP0 and ADC1\_DM01 +ADC1\_DP02 +00001 +DAD1 +ADC1\_DP1 and ADC1\_DM1 +ADC1\_DP1 +00010 +DAD2 +PGA1\_DP and PGA1\_DM +PGA1\_DP +00011 +DAD3 +ADC1\_DP3 and ADC1\_DM33 +ADC1\_DP34 +001005 +AD4a +Reserved +ADC1\_SE4a +001015 +AD5a +Reserved +ADC1\_SE5a +001105 +AD6a +Reserved +ADC1\_SE6a +001115 +AD7a +Reserved +ADC1\_SE7a +Table continues on the next page... +Analog +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +122 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 122](pdf-image://page_122_img_1) + +## Page 123 + +ADC Channel +(SC1n[ADCH]) +Channel +Input signal +(SC1n[DIFF]= 1) +Input signal +(SC1n[DIFF]= 0) +001005 +AD4b +Reserved +ADC1\_SE4b +001015 +AD5b +Reserved +ADC1\_SE5b +001105 +AD6b +Reserved +ADC1\_SE6b +001115 +AD7b +Reserved +ADC1\_SE7b +01000 +AD8 +Reserved +ADC1\_SE86 +01001 +AD9 +Reserved +ADC1\_SE97 +01010 +AD10 +Reserved +ADC1\_SE10 +01011 +AD11 +Reserved +ADC1\_SE11 +01100 +AD12 +Reserved +ADC1\_SE12 +01101 +AD13 +Reserved +ADC1\_SE13 +01110 +AD14 +Reserved +ADC1\_SE14 +01111 +AD15 +Reserved +ADC1\_SE15 +10000 +AD16 +Reserved +ADC1\_SE16 +10001 +AD17 +Reserved +ADC1\_SE17 +10010 +AD18 +Reserved +VREF Output +10011 +AD19 +Reserved +ADC1\_DM08 +10100 +AD20 +Reserved +ADC1\_DM1 +10101 +AD21 +Reserved +Reserved +10110 +AD22 +Reserved +10111 +AD23 +Reserved +12-bit DAC1 Output/ +ADC1\_SE23 +11000 +AD24 +Reserved +Reserved +11001 +AD25 +Reserved +Reserved +11010 +AD26 +Temperature Sensor (Diff) +Temperature Sensor (S.E) +11011 +AD27 +Bandgap (Diff)9 +Bandgap (S.E)9 +11100 +AD28 +Reserved +Reserved +11101 +AD29 +-VREFH (Diff) +VREFH (S.E) +11110 +AD30 +Reserved +VREFL +11111 +AD31 +Module Disabled +Module Disabled +1. +Interleaved with ADC0\_DP3 and ADC0\_DM3 +2. +Interleaved with ADC0\_DP3 +3. +Interleaved with ADC0\_DP0 and ADC0\_DM0 +4. +Interleaved with ADC0\_DP0 +5. +ADCx\_CFG2[MUXSEL] bit selects between ADCx\_SEn channels a and b. Refer to MUXSEL description in ADC chapter +for details. +6. +Interleaved with ADC0\_SE8 +7. +Interleaved with ADC0\_SE9 +8. +Interleaved with ADC0\_DM3 +9. +This is the PMC bandgap 1V reference voltage not the VREF module 1.2 V reference voltage. Prior to reading from this +ADC channel, ensure that you enable the bandgap buffer by setting the PMC\_REGSC[BGBE] bit. Refer to the device data +sheet for the bandgap voltage (VBG) specification. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +123 +General Business Information + +![Image 1 from page 123](pdf-image://page_123_img_1) + +## Page 124 + +3.7.1.5 +ADC Channels MUX Selection +The following figure shows the assignment of ADCx\_SEn channels a and b through a +MUX selection to ADC. To select between alternate set of channels, refer to +ADCx\_CFG2[MUXSEL] bit settings for more details. +\#&=? +ADCx\_SE4a +ADCx\_SE5a +ADCx\_SE6a +ADCx\_SE7a +ADCx\_SE4b +ADCx\_SE5b +ADCx\_SE6b +ADCx\_SE7b +\#&=? +\#&=? +\#&=? +ADC +Figure 3-37. ADCx\_SEn channels a and b selection +3.7.1.6 +ADC Hardware Interleaved Channels +The AD8 and AD9 channels on ADCx are interleaved in hardware using the following +configuration. +ADC0 +AD8 +AD9 +ADC1 +AD8 +AD9 +ADC0\_SE8/ADC1\_SE8 +ADC0\_SE9/ADC1\_SE9 +Figure 3-38. ADC hardware interleaved channels integration +Analog +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +124 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 124](pdf-image://page_124_img_1) + +## Page 125 + +3.7.1.7 +ADC and PGA Reference Options +The ADC supports the following references: +• VREFH/VREFL - connected as the primary reference option +• 1.2 V VREF_OUT - connected as the VALT reference option +ADCx\_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to +REFSEL description in ADC chapter for more details. +The only reference option for the PGA is the 1.2 V VREF\_OUT source. The VREF\_OUT +signal can either be driven by an external voltage source via the VREF\_OUT pin or from +the output of the VREF module. Ensure that the VREF module is disabled when an +external voltage source is used instead. For PGA maximum differential input signal +swing range, refer to the device data sheet for 16-bit ADC with PGA characteristics. +3.7.1.8 +ADC triggers +The ADC supports both software and hardware triggers. The primary hardware +mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other +peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The +PDB trigger can receive the RTC (alarm/seconds) trigger input forcing ADC conversions +in run mode (where PDB is enabled). On the other hand, the ADC can conduct +conversions in low power modes, not triggered by PDB. This allows the ADC to do +conversions in low power mode and store the output in the result register. The ADC +generates interrupt when the data is ready in the result register that wakes the system +from low power mode. The PDB can also be bypassed by using the ADCxTRGSEL bits +in the SOPT7 register. +For operation of triggers in different modes, refer to Power Management chapter. +3.7.1.9 +Alternate clock +For this device, the alternate clock is connected to OSCERCLK. +NOTE +This clock option is only usable when OSCERCLK is in the +MHz range. A system with OSCERCLK in the kHz range has +the optional clock source below minimum ADC clock operating +frequency. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +125 +General Business Information + +![Image 1 from page 125](pdf-image://page_125_img_1) + +## Page 126 + +3.7.1.10 +ADC low-power modes +This table shows the ADC low-power modes and the corresponding chip low-power +modes. +Table 3-47. ADC low-power modes +Module mode +Chip mode +Wait +Wait, VLPW +Normal Stop +Stop, VLPS +Low Power Stop +LLS, VLLS3, VLLS2, VLLS1 +3.7.1.11 +PGA Integration +• No additional external pins are required for the PGA as it is part of the ADC and is +selected as a separate channel +• Each PGA connects to the differential ADC channels +• The PGA outputs differential pairs that are connected to ADC differential input +• When the PGA is used, differential input from the pins is connected to differential +input channel 2 on ADCx +Analog +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +126 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 126](pdf-image://page_126_img_1) + +## Page 127 + +ADC0 +DAD1 +DAD0 +DAD2 +DAD3 +ADC1 +DAD3 +DAD2 +DAD0 +DAD1 +PGA1 +PGA0 +PGA0\_DP/ADC0\_DP0/ADC1\_DP3 +PGA0\_DM/ADC0\_DM0/ADC1\_DM3 +PGA1\_DP/ADC1\_DP0/ADC0\_DP3 +PGA1\_DM/ADC1\_DM0/ADC0\_DM3 +ADC1\_DP1 +ADC1\_DM1 +ADC0\_DP1 +ADC0\_DM1 +Figure 3-39. PGA Integration +3.7.2 +CMP Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +127 +General Business Information + +![Image 1 from page 127](pdf-image://page_127_img_1) + +## Page 128 + +Signal multiplexing +Module signals +Register +access +CMP +Peripheral +bridge 0 +Other peripherals +Figure 3-40. CMP configuration +Table 3-48. Reference links to related information +Topic +Related module +Reference +Full description +Comparator (CMP) +Comparator +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Signal multiplexing +Port control +Signal multiplexing +3.7.2.1 +CMP input connections +The following table shows the fixed internal connections to the CMP. +CMP Inputs +CMP0 +CMP1 +CMP2 +IN0 +CMP0\_IN0 +CMP1\_IN0 +CMP2\_IN0 +IN1 +CMP0\_IN1 +CMP1\_IN1 +CMP2\_IN1 +IN2 +CMP0\_IN2 +CMP1\_IN2 +CMP2\_IN2 +IN3 +CMP0\_IN3 +12-bit DAC0\_OUT/ +CMP1\_IN3 +12-bit DAC1\_OUT/ +CMP2\_IN3 +IN4 +12-bit DAC1\_OUT/ +CMP0\_IN4 +— +— +IN5 +VREF output/CMP0\_IN5 +VREF output/CMP1\_IN5 +— +IN6 +Bandgap +Bandgap +Bandgap +IN7 +6b DAC0 reference +6b DAC1 reference +6b DAC2 reference +3.7.2.2 +CMP external references +The 6-bit DAC sub-block supports selection of two references. For this device, the +references are connected as follows: +Analog +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +128 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 128](pdf-image://page_128_img_1) + +## Page 129 + +• VREF_OUT - Vin1 input +• VDD - Vin2 input +3.7.2.3 +External window/sample input +Individual PDB pulse-out signals control each CMP Sample/Window timing. +3.7.3 +12-bit DAC Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Module signals +Register +access +12-bit DAC +Peripheral bus +controller 0 +Other peripherals +Transfers +Figure 3-41. 12-bit DAC configuration +Table 3-49. Reference links to related information +Topic +Related module +Reference +Full description +12-bit DAC +12-bit DAC +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Signal multiplexing +Port control +Signal multiplexing +3.7.3.1 +12-bit DAC Overview +This device contains two 12-bit digital-to-analog converters (DAC) with programmable +reference generator output. The DAC includes a FIFO for DMA support. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +129 +General Business Information + +![Image 1 from page 129](pdf-image://page_129_img_1) + +## Page 130 + +3.7.3.2 +12-bit DAC Output +The output of the DAC can be placed on an external pin or set as one of the inputs to the +analog comparator or ADC. +3.7.3.3 +12-bit DAC Reference +For this device VREF\_OUT and VDDA are selectable as the DAC reference. +VREF\_OUT is connected to the DACREF\_1 input and VDDA is connected to the +DACREF\_2 input. Use DACx\_C0[DACRFS] control bit to select between these two +options. +Be aware that if the DAC and ADC use the VREF\_OUT reference simultaneously, some +degradation of ADC accuracy is to be expected due to DAC switching. +3.7.4 +VREF Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Module signals +Register +access +VREF +Peripheral bus +controller 0 +Other peripherals +Transfers +Figure 3-42. VREF configuration +Table 3-50. Reference links to related information +Topic +Related module +Reference +Full description +VREF +VREF +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Signal multiplexing +Port control +Signal multiplexing +Analog +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +130 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 130](pdf-image://page_130_img_1) + +## Page 131 + +3.7.4.1 +VREF Overview +This device includes a voltage reference (VREF) to supply an accurate 1.2 V voltage +output. +The voltage reference can provide a reference voltage to external peripherals or a +reference to analog peripherals, such as the ADC, DAC, or CMP. +NOTE +PMC\_REGSC[BGEN] bit must be set if the VREF regulator is +required to remain operating in VLPx modes. +NOTE +For either an internal or external reference if the VREF\_OUT +functionality is being used, VREF\_OUT signal must be +connected to an output load capacitor. Refer the device data +sheet for more details. +3.8 +Timers +3.8.1 +PDB Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Module signals +Register +access +PDB +Peripheral bus +controller 0 +Other peripherals +Transfers +Figure 3-43. PDB configuration +Table 3-51. Reference links to related information +Topic +Related module +Reference +Full description +PDB +PDB +System memory map +System memory map +Table continues on the next page... +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +131 +General Business Information + +![Image 1 from page 131](pdf-image://page_131_img_1) + +## Page 132 + +Table 3-51. Reference links to related information (continued) +Topic +Related module +Reference +Clocking +Clock distribution +Power management +Power management +Signal multiplexing +Port control +Signal multiplexing +3.8.1.1 +PDB Instantiation +3.8.1.1.1 +PDB Output Triggers +Table 3-52. PDB output triggers +Number of PDB channels for ADC trigger +2 +Number of pre-triggers per PDB channel +2 +Number of DAC triggers +2 +Number of PulseOut +3 +3.8.1.1.2 +PDB Input Trigger Connections +Table 3-53. PDB Input Trigger Options +PDB Trigger +PDB Input +0000 +External Trigger +0001 +CMP 0 +0010 +CMP 1 +0011 +CMP 2 +0100 +PIT Ch 0 Output +0101 +PIT Ch 1 Output +0110 +PIT Ch 2 Output +0111 +PIT Ch 3 Output +1000 +FTM0 Init and Ext Trigger Outputs +1001 +FTM1 Init and Ext Trigger Outputs +1010 +FTM2 Init and Ext Trigger Outputs +1011 +Reserved +1100 +RTC Alarm +1101 +RTC Seconds +1110 +LPTMR Output +1111 +Software Trigger +Timers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +132 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 132](pdf-image://page_132_img_1) + +## Page 133 + +3.8.1.2 +PDB Module Interconnections +PDB trigger outputs +Connection +Channel 0 triggers +ADC0 trigger +Channel 1 triggers +ADC1 trigger and synchronous input 1 of FTM0 +DAC triggers +DAC0 and DAC1 trigger +Pulse-out +Pulse-out connected to each CMP module's sample/window +input to control sample operation +3.8.1.3 +Back-to-back acknowledgement connections +In this MCU, PDB back-to-back operation acknowledgment connections are +implemented as follows: +• PDB channel 0 pre-trigger 0 acknowledgement input: ADC1SC1B\_COCO +• PDB channel 0 pre-trigger 1 acknowledgement input: ADC0SC1A\_COCO +• PDB channel 1 pre-trigger 0 acknowledgement input: ADC0SC1B\_COCO +• PDB channel 1 pre-trigger 1 acknowledgement input: ADC1SC1A\_COCO +So, the back-to-back chain is connected as a ring: +Channel 0 +pre-trigger 0 +Channel 1 +pre-trigger 0 +Channel 0 +pre-trigger 1 +Channel 1 +pre-trigger 1 +Figure 3-44. PDB back-to-back chain +The application code can set the PDBx\_CHnC1[BB] bits to configure the PDB pre- +triggers as a single chain or several chains. +3.8.1.4 +PDB Interval Trigger Connections to DAC +In this MCU, PDB interval trigger connections to DAC are implemented as follows. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +133 +General Business Information + +![Image 1 from page 133](pdf-image://page_133_img_1) + +## Page 134 + +• PDB interval trigger 0 connects to DAC0 hardware trigger input. +• PDB interval trigger 1 connects to DAC1 hardware trigger input. +3.8.1.5 +DAC External Trigger Input Connections +In this MCU, the following DAC external trigger inputs are implemented. +• DAC external trigger input 0: ADC0SC1A\_COCO +• DAC external trigger input 1: ADC1SC1A\_COCO +NOTE +Application code can set the PDBx\_DACINTCn[EXT] bit to +allow DAC external trigger input when the corresponding ADC +Conversion complete flag, ADCx\_SC1n[COCO], is set. +3.8.1.6 +Pulse-Out Connection +Individual PDB Pulse-Out signals are connected to each CMP block and used for sample +window. +3.8.1.7 +Pulse-Out Enable Register Implementation +The following table shows the comparison of pulse-out enable register at the module and +chip level. +Table 3-54. PDB pulse-out enable register +Register +Module implementation +Chip implementation +POnEN +7:0 - POEN +31:8 - Reserved +0 - POEN[0] for CMP0 +1 - POEN[1] for CMP1 +2 - POEN[2] for CMP2 +31:3 - Reserved +3.8.2 +FlexTimer Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Timers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +134 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 134](pdf-image://page_134_img_1) + +## Page 135 + +Signal multiplexing +Module signals +Register +access +FlexTimer +Peripheral bus +controller 0 +Other peripherals +Transfers +Figure 3-45. FlexTimer configuration +Table 3-55. Reference links to related information +Topic +Related module +Reference +Full description +FlexTimer +FlexTimer +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Signal multiplexing +Port control +Signal multiplexing +3.8.2.1 +Instantiation Information +This device contains three FlexTimer modules. +The following table shows how these modules are configured. +Table 3-56. FTM Instantiations +FTM instance +Number of channels +Features/usage +FTM0 +8 +3-phase motor + 2 general purpose or +stepper motor +FTM1 +21 +Quadrature decoder or general purpose +FTM2 +21 +Quadrature decoder or general purpose +1. +Only channels 0 and 1 are available. +Compared with the FTM0 configuration, the FTM1 and FTM2 configuration adds the +Quadrature decoder feature and reduces the number of channels. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +135 +General Business Information + +![Image 1 from page 135](pdf-image://page_135_img_1) + +## Page 136 + +3.8.2.2 +External Clock Options +By default each FTM is clocked by the internal bus clock (the FTM refers to it as system +clock). Each module contains a register setting that allows the module to be clocked from +an external clock instead. There are two external FTM\_CLKINx pins that can be selected +by any FTM module via the SOPT4 register in the SIM module. +3.8.2.3 +Fixed frequency clock +The fixed frequency clock for each FTM is MCGFFCLK. +3.8.2.4 +FTM Interrupts +The FlexTimer has multiple sources of interrupt. However, these sources are OR'd +together to generate a single interrupt request to the interrupt controller. When an FTM +interrupt occurs, read the FTM status registers (FMS, SC, and STATUS) to determine the +exact interrupt source. +3.8.2.5 +FTM Fault Detection Inputs +The following fault detection input options for the FTM modules are selected via the +SOPT4 register in the SIM module. The external pin option is selected by default. +• FTM0 FAULT0 = FTM0\_FLT0 pin or CMP0 output +• FTM0 FAULT1 = FTM0\_FLT1 pin or CMP1 output +• FTM0 FAULT2 = FTM0\_FLT2 pin or CMP2 output +• FTM0 FAULT3 = FTM0\_FLT3 pin +• FTM1 FAULT0 = FTM1\_FLT0 pin or CMP0 output +• FTM1 FAULT1 = CMP1 output +• FTM1 FAULT2 = CMP2 output +• FTM2 FAULT0 = FTM2\_FLT0 pin or CMP0 output +• FTM2 FAULT1 = CMP1 output +• FTM2 FAULT2 = CMP2 output +3.8.2.6 +FTM Hardware Triggers +The FTM synchronization hardware triggers are connected in the chip as follows: +Timers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +136 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 136](pdf-image://page_136_img_1) + +## Page 137 + +• FTM0 hardware trigger 0 = CMP0 Output or FTM1 Match (when enabled in the +FTM1 External Trigger (EXTTRIG) register) +• FTM0 hardware trigger 1 = PDB channel 1 Trigger Output or FTM2 Match (when +enabled in the FTM2 External Trigger (EXTTRIG) register) +• FTM0 hardware trigger 2 = FTM0\_FLT0 pin +• FTM1 hardware trigger 0 = CMP0 Output +• FTM1 hardware trigger 1 = CMP1 Output +• FTM1 hardware trigger 2 = FTM1\_FLT0 pin +• FTM2 hardware trigger 0 = CMP0 Output +• FTM2 hardware trigger 1 = CMP2 Output +• FTM2 hardware trigger 2 = FTM2\_FLT0 pin +For the triggers with more than one option, the SOPT4 register in the SIM module +controls the selection. +3.8.2.7 +Input capture options for FTM module instances +The following channel 0 input capture source options are selected via the SOPT4 register +in the SIM module. The external pin option is selected by default. +• FTM1 channel 0 input capture = FTM1\_CH0 pin or CMP0 output or CMP1 output +or USB start of frame pulse +• FTM2 channel 0 input capture = FTM2\_CH0 pin or CMP0 output or CMP1 output +NOTE +When the USB start of frame pulse option is selected as an +FTM channel input capture, disable the USB SOF token +interrupt in the USB Interrupt Enable register +(INTEN[SOFTOKEN]) to avoid USB enumeration conflicts. +3.8.2.8 +FTM output triggers for other modules +FTM output triggers can be selected as input triggers for the PDB and ADC modules. See +PDB Instantiation and ADC triggers. +3.8.2.9 +FTM Global Time Base +This chip provides the optional FTM global time base feature (see Global time base +(GTB)). +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +137 +General Business Information + +![Image 1 from page 137](pdf-image://page_137_img_1) + +## Page 138 + +FTM0 provides the only source for the FTM global time base. The other FTM modules +can share the time base as shown in the following figure: +gtb\_in +FTM1 +GTBEEN = 1 +FTM Counter +CONF Register +GTBEOUT = 0 +FTM0 +GTBEEN = 1 +FTM Counter +CONF Register +GTBEOUT = 1 +gtb\_out +gtb\_in +gtb\_in +FTM2 +GTBEEN = 1 +FTM Counter +CONF Register +GTBEOUT = 0 +Figure 3-46. FTM Global Time Base Configuration +3.8.2.10 +FTM BDM and debug halt mode +In the FTM chapter, references to the chip being in "BDM" are the same as the chip being +in “debug halt mode". +3.8.3 +PIT Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Register +access +Peripheral +bridge +Periodic interrupt +timer +Figure 3-47. PIT configuration +Table 3-57. Reference links to related information +Topic +Related module +Reference +Full description +PIT +PIT +Table continues on the next page... +Timers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +138 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 138](pdf-image://page_138_img_1) + +## Page 139 + +Table 3-57. Reference links to related information (continued) +Topic +Related module +Reference +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +3.8.3.1 +PIT/DMA Periodic Trigger Assignments +The PIT generates periodic trigger events to the DMA Mux as shown in the table below. +Table 3-58. PIT channel assignments for periodic DMA triggering +DMA Channel Number +PIT Channel +DMA Channel 0 +PIT Channel 0 +DMA Channel 1 +PIT Channel 1 +DMA Channel 2 +PIT Channel 2 +DMA Channel 3 +PIT Channel 3 +3.8.3.2 +PIT/ADC Triggers +PIT triggers are selected as ADCx trigger sources using the SOPT7[ADCxTRGSEL] bits +in the SIM module. For more details, refer to SIM chapter. +3.8.4 +Low-power timer configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +139 +General Business Information + +![Image 1 from page 139](pdf-image://page_139_img_1) + +## Page 140 + +Signal multiplexing +Register +access +Peripheral +bridge +Module signals +Low-power timer +Figure 3-48. LPT configuration +Table 3-59. Reference links to related information +Topic +Related module +Reference +Full description +Low-power timer +Low-power timer +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +Signal Multiplexing +Port control +Signal Multiplexing +3.8.4.1 +LPTMR prescaler/glitch filter clocking options +The prescaler and glitch filter of the LPTMR module can be clocked from one of four +sources determined by the LPTMR0\_PSR[PCS] bitfield. The following table shows the +chip-specific clock assignments for this bitfield. +NOTE +The chosen clock must remain enabled if the LPTMR is to +continue operating in all required low-power modes. +LPTMR0\_PSR[PCS] +Prescaler/glitch filter clock +number +Chip clock +00 +0 +MCGIRCLK — internal reference clock +(not available in VLPS/LLS/VLLS +modes) +01 +1 +LPO — 1 kHz clock +10 +2 +ERCLK32K — secondary external +reference clock +11 +3 +OSCERCLK — external reference clock +See Clock Distribution for more details on these clocks. +Timers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +140 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 140](pdf-image://page_140_img_1) + +## Page 141 + +3.8.4.2 +LPTMR pulse counter input options +The LPTMR\_CSR[TPS] bitfield configures the input source used in pulse counter mode. +The following table shows the chip-specific input assignments for this bitfield. +LPTMR\_CSR[TPS] +Pulse counter input number +Chip input +00 +0 +CMP0 output +01 +1 +LPTMR\_ALT1 pin +10 +2 +LPTMR\_ALT2 pin +11 +3 +3.8.5 +CMT Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Module signals +Register +access +CMT +Peripheral bus +controller 0 +Figure 3-49. CMT configuration +Table 3-60. Reference links to related information +Topic +Related module +Reference +Full description +Carrier modulator +transmitter (CMT) +CMT +System memory map +System memory map +Clocking +Clock distribution +Power management +Power management +Signal multiplexing +Port control +Signal multiplexing +3.8.5.1 +Instantiation Information +This device contains one CMT module. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +141 +General Business Information + +![Image 1 from page 141](pdf-image://page_141_img_1) + +## Page 142 + +3.8.5.2 +IRO Drive Strength +The IRO pad requires higher current drive than can be obtained from a single pad. For +this device, the pin associated with the CMT\_IRO signal is doubled bonded to two pads. +The SOPT2[PTD7PAD] field in SIM module can be used to configure the pin associated +with the CMT\_IRO signal as a higher current output port pin. +3.8.6 +RTC configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Register +access +Peripheral +bridge +Module signals +Real-time clock +Figure 3-50. RTC configuration +Table 3-61. Reference links to related information +Topic +Related module +Reference +Full description +RTC +RTC +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +3.8.6.1 +RTC\_CLKOUT signal +When the RTC is enabled and the port control module selects the RTC\_CLKOUT +function, the RTC\_CLKOUT signal outputs a 1 Hz or 32 kHz output derived from RTC +oscillator as shown below. +Timers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +142 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 142](pdf-image://page_142_img_1) + +## Page 143 + +SIM\_SOPT2[RTCCLKOUTSEL] +RTC\_CLKOUT +RTC 1Hz clock +RTC 32kHz clock +RTC\_CR[CLKO] +Figure 3-51. RTC_CLKOUT generation +3.9 +Communication interfaces +3.9.1 +Ethernet Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Module signals +Register +access +Ethernet +Peripheral +bridge 1 +Crossbar switch +Transfers +Figure 3-52. Ethernet configuration +Table 3-62. Reference links to related information +Topic +Related module +Reference +Full description +Ethernet +Ethernet +System memory map +System memory map +Clocking +Clock Distribution +Transfers +Crossbar switch +Crossbar switch +Signal Multiplexing +Port control +Signal Multiplexing +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +143 +General Business Information + +![Image 1 from page 143](pdf-image://page_143_img_1) + +## Page 144 + +3.9.1.1 +Ethernet Clocking Options +The Ethernet module uses the following clocks: +• The device's system clock is connected to the module clock, as named in the Ethernet +chapter. The minimum system clock frequency for 100 Mbps operation is 25 MHz. +• An externally-supplied 25 MHz MII clock or 50 MHz RMII clock. This clock is used +as the timing reference for the external MII or RMII interface. +• A time-stamping clock for the IEEE 1588 timers. +For more details on the Ethernet module clocking options, see Ethernet Clocking. +3.9.1.2 +RMII Clocking +On this device, RMII\_REF\_CLK is internally tied to EXTAL. See Clock Distribution for +clocking requirements. +3.9.1.3 +IEEE 1588 Timers +The ethernet module includes a four channel timer module for IEEE 1588 timestamping. +The timer supports input capture (rising, falling, or both edges), output compare (toggle +or pulse with programmable polarity). The timer matches on greater than or equal (the +1588 can skip numbers, so the counter might not ever exactly match the compare value). +The counter is able to operate asynchronously to the ethernet bus by using one of four +clock sources. See Ethernet Clocking for more details. +3.9.1.4 +Ethernet Operation in Low Power Modes +The Ethernet module is not fully operational in any low power modes. However, the +module does support magic packet detection that can generate a wakeup in stop mode if +enabled. +During low power operation: +• The MAC transmit logic is disabled +• The core FIFO receive/transmit functions are disabled +• The MAC receive logic is kept in normal mode, but it ignores all traffic from the line +except magic packets. +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +144 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 144](pdf-image://page_144_img_1) + +## Page 145 + +The recieve logic needed for magic packet detection is clocked using the externally- +supplied MII or RMII clock. This allows for the wakeup functionality in stop mode. No +Ethernet operation, including magic packet wakeup, is supported in VLPx modes. +3.9.1.4.1 +IEEE 1588 Timer Operation in Low Power Modes +The 1588 counter and 1588 timer channels can continue operating in low power modes +provided their clock is enabled in that mode. +The 1588 timer channels can also generate an interrupt to exit the low power mode if the +clock is enabled in that mode. +3.9.1.5 +Ethernet Doze Mode +The doze mode for the Ethernet module is the same as the wait and VLPW modes for the +chip. +3.9.1.6 +Ethernet Interrupts +The Ethernet has multiple sources of interrupt requests. However, some of these sources +are OR'd together to generate an interrupt request. See below for a summary: +Interrupt request +Interrupt source +IEEE 1588 timer interrupt +• Periodic timer overflow +• Time stamp available +• 1588 timer interrupt +Transmit interrupt +• Transmit frame interrupt +• Transmit buffer interrupt +Receive interrupt +• Receive frame interrupt +• Receive buffer interrupt +Error and miscellaneous interrupt +• Wake-up +• Payload receive error +• Babbling receive error +• Babbling transmit error +• Graceful stop complete +• MII interrupt – Data transfer done +• Ethernet bus error +• Late collision +• Collision retry limit +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +145 +General Business Information + +![Image 1 from page 145](pdf-image://page_145_img_1) + +## Page 146 + +3.9.1.7 +Ethernet event signal +The event signal output is not supported on this device. Therefore, ATCR[PINPER] has +no effect. +3.9.2 +Universal Serial Bus (USB) FS Subsystem +The USB FS subsystem includes these components: +• Dual-role USB OTG-capable (On-The-Go) controller that supports a full-speed (FS) +device or FS/LS host. The module complies with the USB 2.0 specification. +• USB transceiver that includes internal 15 kΩ pulldowns on the D+ and D- lines for +host mode functionality. +• A 3.3 V regulator. +• USB device charger detection module. +• VBUS detect signal: To detect a valid VBUS in device mode, use a GPIO signal that +can wake the chip in all power modes. +USB controller +FS/LS +transceiver +USB voltage +regulator +D+ +D- +VREGIN +Device charger +detect +VOUT33 +Figure 3-53. USB Subsystem Overview +3.9.2.1 +USB Wakeup +When the USB detects that there is no activity on the USB bus for more than 3 ms, the +INT\_STAT[SLEEP] bit is set. This bit can cause an interrupt and software decides the +appropriate action. +Waking from a low power mode (except in LLS/VLLS mode where USB is not powered) +occurs through an asynchronous interrupt triggered by activity on the USB bus. Setting +the USBTRC0[USBRESMEN] bit enables this function. +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +146 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 146](pdf-image://page_146_img_1) + +## Page 147 + +*[Error processing page 147: code=7: object is not a stream]* + +## Page 148 + +USB +Regulator +USB +XCVR +USB +Controller +USB0\_DM +USB0\_DP +VDD +VOUT33 +VREGIN +TYPE A +D+ +D- +VBUS +Cstab +To PMC and Pads +Chip +Charger +Detect +VBUS Sense +VSS +Charger +Li-Ion +Si2301 +Figure 3-55. USB regulator Li-ion usecase +3.9.2.2.3 +USB bus power supply +The chip can also be powered by the USB bus directly. In this case, VOUT33 is +connected to VDD. The USB regulator must be enabled by default to power the MCU, +then to power USB transceiver or external sensor. +USB +Regulator +USB +XCVR +USB +Controller +USB0\_DP +USB0\_DM +VDD +VOUT33 +VREGIN +TYPE A +D+ +D- +VBUS +Cstab +To PMC and Pads +Chip +Figure 3-56. USB regulator bus supply +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +148 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 148](pdf-image://page_148_img_1) + +## Page 149 + +3.9.2.3 +USB power management +The regulator should be put into STANDBY mode whenever the chip is in Stop mode. +This can be done by setting the SIM\_SOPT1[USBSTBY] bit. +3.9.2.4 +USB controller configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Module signals +Register +access +USB controller +Peripheral +bridge 0 +Crossbar switch +Transfers +Figure 3-57. USB controller configuration +Table 3-63. Reference links to related information +Topic +Related module +Reference +Full description +USB controller +USB controller +System memory map +System memory map +Clocking +Clock Distribution +Transfers +Crossbar switch +Crossbar switch +Signal Multiplexing +Port control +Signal Multiplexing +NOTE +When USB is not used in the application, it is recommended +that the USB regulator VREGIN and VOUT33 pins remain +floating. +3.9.2.5 +USB DCD Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +149 +General Business Information + +![Image 1 from page 149](pdf-image://page_149_img_1) + +## Page 150 + +Register +access +USB Device Charger +Detect +Peripheral +bridge 0 +USB OTG +Figure 3-58. USB DCD configuration +Table 3-64. Reference links to related information +Topic +Related module +Reference +Full description +USB DCD +USB DCD +System memory map +System memory map +Clocking +Clock Distribution +USB controller +USB controller +3.9.2.6 +USB Voltage Regulator Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Module signals +USB Voltage +Regulator +USB OTG +Figure 3-59. USB Voltage Regulator configuration +Table 3-65. Reference links to related information +Topic +Related module +Reference +Full description +USB Voltage Regulator +USB Voltage Regulator +System memory map +System memory map +Clocking +Clock Distribution +USB controller +USB controller +Signal Multiplexing +Port control +Signal Multiplexing +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +150 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 150](pdf-image://page_150_img_1) + +## Page 151 + +NOTE +When USB is not used in the application, it is recommended +that the USB regulator VREGIN and VOUT33 pins remain +floating. +3.9.3 +CAN Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Register +access +FlexCAN +Peripheral +bridge +Module signals +Figure 3-60. CAN configuration +Table 3-66. Reference links to related information +Topic +Related module +Reference +Full description +CAN +CAN +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +Signal Multiplexing +Port control +Signal Multiplexing +3.9.3.1 +Number of FlexCAN modules +This device contains 2 identical FlexCAN modules. +3.9.3.2 +Reset value of MDIS bit +The CAN\_MCR[MDIS] bit is set after reset. Therefore, FlexCAN module is disabled +following a reset. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +151 +General Business Information + +![Image 1 from page 151](pdf-image://page_151_img_1) + +## Page 152 + +3.9.3.3 +Number of message buffers +Each FlexCAN module contains 16 message buffers. Each message buffer is 16 bytes. +3.9.3.4 +FlexCAN Clocking +3.9.3.4.1 +Clocking Options +The FlexCAN module has a register bit CANCTRL[CLK\_SRC] that selects between +clocking the FlexCAN from the internal bus clock or the input clock (EXTAL). +3.9.3.4.2 +Clock Gating +The clock to each CAN module can be gated on and off using the SCGCn[CANx] bits. +These bits are cleared after any reset, which disables the clock to the corresponding +module. The appropriate clock enable bit should be set by software at the beginning of +the FlexCAN initialization routine to enable the module clock before attempting to +initialize any of the FlexCAN registers. +3.9.3.5 +FlexCAN Interrupts +The FlexCAN has multiple sources of interrupt requests. However, some of these sources +are OR'd together to generate a single interrupt request. See below for the mapping of the +individual interrupt sources to the interrupt request: +Request +Sources +Message buffer +Message buffers 0-15 +Bus off +Bus off +Error +• Bit1 error +• Bit0 error +• Acknowledge error +• Cyclic redundancy check (CRC) error +• Form error +• Stuffing error +• Transmit error warning +• Receive error warning +Transmit Warning +Transmit Warning +Receive Warning +Receive Warning +Wake-up +Wake-up +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +152 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 152](pdf-image://page_152_img_1) + +## Page 153 + +3.9.3.6 +FlexCAN Operation in Low Power Modes +The FlexCAN module is operational in VLPR and VLPW modes. With the 2 MHz bus +clock, the fastest supported FlexCAN transfer rate is 256 kbps. The bit timing parameters +in the module must be adjusted for the new frequency, but full functionality is possible. +The FlexCAN module can be configured to generate a wakeup interrupt in STOP and +VLPS modes. When the FlexCAN is configured to generate a wakeup, a recessive to +dominant transition on the CAN bus generates an interrupt. +3.9.3.7 +FlexCAN Doze Mode +The Doze mode for the FlexCAN module is the same as the Wait and VLPW modes for +the chip. +3.9.4 +SPI configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Register +access +SPI +Peripheral +bridge +Module signals +Figure 3-61. SPI configuration +Table 3-67. Reference links to related information +Topic +Related module +Reference +Full description +SPI +SPI +System memory map +System memory map +Clocking +Clock Distribution +Signal Multiplexing +Port control +Signal Multiplexing +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +153 +General Business Information + +![Image 1 from page 153](pdf-image://page_153_img_1) + +## Page 154 + +3.9.4.1 +SPI Modules Configuration +This device contains three SPI modules. +3.9.4.2 +SPI clocking +The SPI module is clocked by the internal bus clock (the DSPI refers to it as system +clock). The module has an internal divider, with a minimum divide is two. So, the SPI +can run at a maximum frequency of bus clock/2. +3.9.4.3 +Number of CTARs +SPI CTAR registers define different transfer attribute configurations. The SPI module +supports up to eight CTAR registers. This device supports two CTARs on all instances of +the SPI. +In master mode, the CTAR registers define combinations of transfer attributes, such as +frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In +slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer +attributes. +3.9.4.4 +TX FIFO size +Table 3-68. SPI transmit FIFO size +SPI Module +Transmit FIFO size +SPI0 +4 +SPI1 +4 +SPI2 +4 +3.9.4.5 +RX FIFO Size +SPI supports up to 16-bit frame size during reception. +Table 3-69. SPI receive FIFO size +SPI Module +Receive FIFO size +SPI0 +4 +Table continues on the next page... +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +154 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 154](pdf-image://page_154_img_1) + +## Page 155 + +Table 3-69. SPI receive FIFO size (continued) +SPI Module +Receive FIFO size +SPI1 +4 +SPI2 +4 +3.9.4.6 +Number of PCS signals +The following table shows the number of peripheral chip select signals available per SPI +module. +Table 3-70. SPI PCS signals +SPI Module +PCS Signals +SPI0 +SPI\_PCS[5:0] +SPI1 +SPI\_PCS[3:0] +SPI2 +SPI\_PCS[1:0] +3.9.4.7 +SPI Operation in Low Power Modes +In VLPR and VLPW modes the SPI is functional; however, the reduced system +frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW +modes the max SPI\_CLK frequency is 2MHz. +In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not +functional, but it is powered so that it retains state. +There is one way to wake from stop mode via the SPI, which is explained in the +following section. +3.9.4.7.1 +Using GPIO Interrupt to Wake from stop mode +Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave +mode: +1. Point the GPIO interrupt vector to the desired interrupt handler. +2. Enable the GPIO input to generate an interrupt on either the rising or falling edge +(depending on the polarity of the chip select signal). +3. Enter Stop or VLPS mode and Wait for the GPIO interrupt. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +155 +General Business Information + +![Image 1 from page 155](pdf-image://page_155_img_1) + +## Page 156 + +NOTE +It is likely that in using this approach the first word of data from +the SPI host might not be received correctly. This is dependent +on the transfer rate used for the SPI, the delay between chip +select assertion and presentation of data, and the system +interrupt latency. +3.9.4.8 +SPI Doze Mode +The Doze mode for the SPI module is the same as the Wait and VLPW modes for the +chip. +3.9.4.9 +SPI Interrupts +The SPI has multiple sources of interrupt requests. However, these sources are OR'd +together to generate a single interrupt request per SPI module to the interrupt controller. +When an SPI interrupt occurs, read the SPI\_SR to determine the exact interrupt source. +3.9.4.10 +SPI clocks +This table shows the SPI module clocks and the corresponding chip clocks. +Table 3-71. SPI clock connections +Module clock +Chip clock +System Clock +Bus Clock +3.9.5 +I2C Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +156 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 156](pdf-image://page_156_img_1) + +## Page 157 + +Signal multiplexing +Register +access +Peripheral +bridge +Module signals +2I C +Figure 3-62. I2C configuration +Table 3-72. Reference links to related information +Topic +Related module +Reference +Full description +I2C +I2C +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +Signal Multiplexing +Port control +Signal Multiplexing +3.9.5.1 +Number of I2C modules +This device has two I2C modules. +3.9.6 +UART Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +157 +General Business Information + +![Image 1 from page 157](pdf-image://page_157_img_1) + +## Page 158 + +Signal multiplexing +Register +access +Peripheral +bridge +Module signals +UART +Figure 3-63. UART configuration +Table 3-73. Reference links to related information +Topic +Related module +Reference +Full description +UART +UART +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +Signal Multiplexing +Port control +Signal Multiplexing +3.9.6.1 +UART configuration information +This device contains six UART modules. This section describes how each module is +configured on this device. +1. Standard features of all UARTs: +• RS-485 support +• Hardware flow control (RTS/CTS) +• 9-bit UART to support address mark with parity +• MSB/LSB configuration on data +2. UART0 and UART1 are clocked from the core clock, the remaining UARTs are +clocked on the bus clock. The maximum baud rate is 1/16 of related source clock +frequency. +3. IrDA is available on all UARTs +4. UART0 contains the standard features plus ISO7816 +5. AMR support on all UARTs. The pin control and interrupts (PORT) module supports +open-drain for all I/O. +6. UART0 and UART1 contains 8-entry transmit and 8-entry receive FIFOs +7. All other UARTs contain a 1-entry transmit and receive FIFOs +8. CEA709.1-B (LON) is available in UART0 +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +158 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 158](pdf-image://page_158_img_1) + +## Page 159 + +3.9.6.2 +UART wakeup +The UART can be configured to generate an interrupt/wakeup on the first active edge that +it receives. +3.9.6.3 +UART interrupts +The UART has multiple sources of interrupt requests. However, some of these sources +are OR'd together to generate a single interrupt request. See below for the mapping of the +individual interrupt sources to the interrupt request: +The status interrupt combines the following interrupt sources: +Source +UART 0 +UART 1 +UART 2 +UART 3 +UART 4 +UART 5 +Transmit data +empty +x +x +x +x +x +x +Transmit +complete +x +x +x +x +x +x +Idle line +x +x +x +x +x +x +Receive data +full +x +x +x +x +x +x +LIN break +detect +x +x +x +x +x +x +RxD pin active +edge +x +x +x +x +x +x +Initial character +detect +x +— +— +— +— +— +The error interrupt combines the following interrupt sources: +Source +UART 0 +UART 1 +UART 2 +UART 3 +UART 4 +UART 5 +Receiver +overrun +x +x +x +x +x +x +Noise flag +x +x +x +x +x +x +Framing error +x +x +x +x +x +x +Parity error +x +x +x +x +x +x +Transmitter +buffer overflow +x +x +x +x +x +x +Receiver buffer +overflow +x +x +x +x +x +x +Receiver buffer +underflow +x +x +x +x +x +x +Table continues on the next page... +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +159 +General Business Information + +![Image 1 from page 159](pdf-image://page_159_img_1) + +## Page 160 + +Source +UART 0 +UART 1 +UART 2 +UART 3 +UART 4 +UART 5 +Transmit +threshold +(ISO7816) +x +— +— +— +— +— +Receiver +threshold +(ISO7816) +x +— +— +— +— +— +Wait timer +(ISO7816) +x +— +— +— +— +— +Character wait +timer (ISO7816) +x +— +— +— +— +— +Block wait timer +(ISO7816) +x +— +— +— +— +— +Guard time +violation +(ISO7816) +x +— +— +— +— +— +The LON status interrupt combines the following interrupt sources: +Source +UART 0 +UART 1 +UART 2 +UART 3 +UART 4 +UART 5 +Wbase expire +after beta1 time +slots (LON) +x +— +— +— +— +— +Package +received (LON) +x +— +— +— +— +— +Package +transmitted +(LON) +x +— +— +— +— +— +Package cycle +time expired +(LON) +x +— +— +— +— +— +Preamble start +(LON) +x +— +— +— +— +— +Transmission +fail (LON) +x +— +— +— +— +— +Initial sync +detection (LON) +x +— +— +— +— +— +3.9.7 +SDHC Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +160 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 160](pdf-image://page_160_img_1) + +## Page 161 + +Crossbar switch +Register +access +Peripheral +bridge +Module signals +SDHC +Transfers +Signal multiplexing +Figure 3-64. SDHC configuration +Table 3-74. Reference links to related information +Topic +Related module +Reference +Full description +SDHC +SDHC +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +Transfers +Crossbar switch +Crossbar switch +Signal Multiplexing +Port control +Signal Multiplexing +3.9.7.1 +SDHC clocking +In addition to the system clock, the SDHC needs a clock for the base for the external card +clock. There are four possible clock sources for this clock, selected by the SIM’s SOPT2 +register: +• Core/system clock +• MCGPLLCLK or MCGFLLCLK +• EXTAL +• Bypass clock from off-chip (SDHC0\_CLKIN) +3.9.7.2 +SD bus pullup/pulldown constraints +The SD standard requires the SD bus signals (except the SD clock) to be pulled up during +data transfers. The SDHC also provides a feature of detecting card insertion/removal, by +detecting voltage level changes on DAT[3] of the SD bus. To support this DAT[3] must +be pulled down. To avoid a situation where the SDHC detects voltage changes due to +normal data transfers on the SD bus as card insertion/removal, the interrupt relating to +this event must be disabled after the card has been inserted and detected. It can be re- +enabled after the card is removed. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +161 +General Business Information + +![Image 1 from page 161](pdf-image://page_161_img_1) + +## Page 162 + +3.9.8 +I2S configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Signal multiplexing +Register +access +Peripheral +bridge +Module signals +2I S +Figure 3-65. I2S configuration +Table 3-75. Reference links to related information +Topic +Related module +Reference +Full description +I2S +I2S +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +Signal multiplexing +Port control +Signal Multiplexing +3.9.8.1 +Instantiation information +This device contains one I2S module. +As configured on the device, module features include: +• TX data lines: 2 +• RX data lines: 2 +• FIFO size (words): 8 +• Maximum words per frame: 32 +• Maximum bit clock divider: 512 +3.9.8.2 +I2S/SAI clocking +Communication interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +162 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 162](pdf-image://page_162_img_1) + +## Page 163 + +3.9.8.2.1 +Audio Master Clock +The audio master clock (MCLK) is used to generate the bit clock when the receiver or +transmitter is configured for an internally generated bit clock. The audio master clock can +also be output to or input from a pin. The transmitter and receiver have the same audio +master clock inputs. +3.9.8.2.2 +Bit Clock +The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can +be generated internally from the audio master clock or supplied externally. The module +also supports the option for synchronous operation between the receiver and +transmitterproduct. +3.9.8.2.3 +Bus Clock +The bus clock is used by the control registers and to generate synchronous interrupts and +DMA requests. +3.9.8.2.4 +I2S/SAI clock generation +Each SAI peripheral can control the input clock selection, pin direction and divide ratio +of one audio master clock. +The MCLK Input Clock Select bit of the MCLK Control Register (MCR[MICS]) selects +the clock input to the I2S/SAI module’s MCLK divider. +The module's MCLK Divide Register (MDR) configures the MCLK divide ratio. +The module's MCLK Output Enable bit of the MCLK Control Register (MCR[MOE]) +controls the direction of the MCLK pin. The pin is the input from the pin when MOE is 0, +and the pin is the output from the clock divider when MOE is 1. +The transmitter and receiver can independently select between the bus clock and the +audio master clock to generate the bit clock. Each module's Clocking Mode field of the +Transmit Configuration 2 Register and Receive Configuration 2 Register (TCR2[MSEL] +and RCR2[MSEL]) selects the master clock. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +163 +General Business Information + +![Image 1 from page 163](pdf-image://page_163_img_1) + +## Page 164 + +3.9.8.2.5 +Clock gating and I2S/SAI initialization +The clock to the I2S/SAI module can be gated using a bit in the SIM. To minimize power +consumption, these bits are cleared after any reset, which disables the clock to the +corresponding module. The clock enable bit should be set by software at the beginning of +the module initialization routine to enable the module clock before initialization of any of +the I2S/SAI registers. +3.9.8.3 +I2S/SAI operation in low power modes +3.9.8.3.1 +Stop and very low power modes +In VLPS mode, the module behaves as it does in stop mode if VLPS mode is entered +from run mode. However, if VLPS mode is entered from VLPR mode, the FIFO might +underflow or overflow before wakeup from stop mode due to the limits in bus bandwidth. +In VLPW and VLPR modes, the module is limited by the maximum bus clock +frequencies. +When operating from an internally generated bit clock or Audio Master Clock that is +disabled in stop modes: +In Stop mode, the transmitter is disabled after completing the current transmit frame, and, +the receiver is disabled after completing the current receive frame. Entry into Stop mode +is prevented–not acknowledged–while waiting for the transmitter and receiver to be +disabled at the end of the current frame. +3.10 +Human-machine interfaces +3.10.1 +GPIO configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Human-machine interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +164 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 164](pdf-image://page_164_img_1) + +## Page 165 + +Signal multiplexing +Register +access +Peripheral +bridge +Module signals +GPIO controller +Crossbar switch +Transfers +Figure 3-66. GPIO configuration +Table 3-76. Reference links to related information +Topic +Related module +Reference +Full description +GPIO +GPIO +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +Transfers +Crossbar switch +Clock Distribution +Signal Multiplexing +Port control +Signal Multiplexing +3.10.1.1 +GPIO access protection +The GPIO module does not have access protection because it is not connected to a +peripheral bridge slot and is not protected by the MPU. +3.10.1.2 +Number of GPIO signals +The number of GPIO signals available on the devices covered by this document are +detailed in Orderable part numbers. +3.10.2 +TSI Configuration +This section summarizes how the module has been configured in the chip. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +165 +General Business Information + +![Image 1 from page 165](pdf-image://page_165_img_1) + +## Page 166 + +Signal multiplexing +Register +access +Peripheral +bridge +Module signals +Touch sense input +module +Figure 3-67. TSI configuration +Table 3-77. Reference links to related information +Topic +Related module +Reference +Full description +TSI +TSI +System memory map +System memory map +Clocking +Clock Distribution +Power management +Power management +Signal Multiplexing +Port control +Signal Multiplexing +3.10.2.1 +Number of inputs +This device includes one TSI module containing 16 inputs. In low-power modes, one +selectable pin is active. +3.10.2.2 +TSI module functionality in MCU operation modes +Table 3-78. TSI module functionality in MCU operation modes +MCU operation mode +TSI clock sources +TSI operation mode +when GENCS[TSIEN] +is 1 +Functional electrode +pins +Required +GENCS[STPE] state +Run +BUSCLK, MCGIRCLK, +OSCERCLK +Active mode +All +Don’t care +Wait +BUSCLK, MCGIRCLK, +OSCERCLK +Active mode +All +Don’t care +Stop +MCGIRCLK, +OSCERCLK +Active mode +All +1 +VLPR +BUSCLK, MCGIRCLK, +OSCERCLK +Active mode +All +Don’t care +VLPW +BUSCLK, MCGIRCLK, +OSCERCLK +Active mode +All +Don’t care +VLPS +OSCERCLK +Active mode +All +1 +Table continues on the next page... +Human-machine interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +166 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 166](pdf-image://page_166_img_1) + +## Page 167 + +Table 3-78. TSI module functionality in MCU operation modes (continued) +MCU operation mode +TSI clock sources +TSI operation mode +when GENCS[TSIEN] +is 1 +Functional electrode +pins +Required +GENCS[STPE] state +LLS +LPOCLK, VLPOSCCLK Low power mode +Determined by +PEN[LPSP] +1 +VLLS3 +LPOCLK, VLPOSCCLK Low power mode +Determined by +PEN[LPSP] +1 +VLLS2 +LPOCLK, VLPOSCCLK Low power mode +Determined by +PEN[LPSP] +1 +VLLS1 +LPOCLK, VLPOSCCLK Low power mode +Determined by +PEN[LPSP] +1 +3.10.2.3 +TSI clocks +This table shows the TSI clocks and the corresponding chip clocks. +Table 3-79. TSI clock connections +Module clock +Chip clock +BUSCLK +Bus clock +MCGIRCLK +MCGIRCLK +OSCERCLK +OSCERCLK +LPOCLK +1 kHz LPO clock +VLPOSCCLK +ERCLK32K +3.10.2.4 +TSI Interrupts +The TSI has multiple sources of interrupt requests. However, these sources are OR'd +together to generate a single interrupt request. When a TSI interrupt occurs, read the TSI +status register to determine the exact interrupt source. +3.10.2.5 +Shield drive signal +The shield drive signal is not supported on this device. Ignore this feature in the TSI +chapter. +Chapter 3 Chip Configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +167 +General Business Information + +![Image 1 from page 167](pdf-image://page_167_img_1) + +## Page 168 + +Human-machine interfaces +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +168 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 168](pdf-image://page_168_img_1) + +## Page 169 + +Chapter 4 +Memory Map +4.1 +Introduction +This device contains various memories and memory-mapped peripherals which are +located in one 32-bit contiguous memory space. This chapter describes the memory and +peripheral locations within that memory space. +4.2 +System memory map +The following table shows the high-level device memory map. +Table 4-1. System memory map +System 32-bit Address Range +Destination Slave +Access +0x0000\_0000–0x07FF\_FFFF +Program flash and read-only data +(Includes exception vectors in first 1024 bytes) +All masters +0x0800\_0000–0x0FFF\_FFFF +FlexBus (Aliased area) +Cortex-M4 core +(M0) only +0x1000\_0000–0x13FF\_FFFF +• For MK60DN256VLQ10: Reserved +• For MK60DX256VLQ10: FlexNVM +• For MK60DN512VLQ10: Reserved +• For MK60DN256VMD10: Reserved +• For MK60DX256VMD10: FlexNVM +• For MK60DN512VMD10: Reserved +All masters +0x1400\_0000–0x17FF\_FFFF +For devices with FlexNVM: FlexRAM +For devices with program flash only: Programming +acceleration RAM +All masters +0x1800\_0000–0x1BFF\_FFFF +FlexBus (Aliased area) +Cortex-M4 core +(M0) only +0x1C00\_0000–0x1FFF\_FFFF +SRAM\_L: Lower SRAM (ICODE/DCODE) +All masters +0x2000\_0000–0x200F\_FFFF +SRAM\_U: Upper SRAM bitband region +All masters +0x2010\_0000–0x21FF\_FFFF +Reserved +– +Table continues on the next page... +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +169 +General Business Information + +![Image 1 from page 169](pdf-image://page_169_img_1) + +## Page 170 + +Table 4-1. System memory map (continued) +System 32-bit Address Range +Destination Slave +Access +0x2200\_0000–0x23FF\_FFFF +Aliased to SRAM\_U bitband +Cortex-M4 core +only +0x2400\_0000–0x3FFF\_FFFF +Reserved +– +0x4000\_0000–0x4007\_FFFF +Bitband region for peripheral bridge 0 (AIPS-Lite0) +Cortex-M4 core & +DMA/EzPort +0x4008\_0000–0x400F\_EFFF +Bitband region for peripheral bridge 1 (AIPS-Lite1) +Cortex-M4 core & +DMA/EzPort +0x400F\_F000–0x400F\_FFFF +Bitband region for general purpose input/output (GPIO) +Cortex-M4 core & +DMA/EzPort +0x4010\_0000–0x41FF\_FFFF +Reserved +– +0x4200\_0000–0x43FF\_FFFF +Aliased to peripheral bridge (AIPS-Lite) and general purpose +input/output (GPIO) bitband +Cortex-M4 core +only +0x4400\_0000–0x5FFF\_FFFF +Reserved +– +0x6000\_0000–0x7FFF\_FFFF +FlexBus (External Memory - Write-back) +All masters +0x8000\_0000–0x9FFF\_FFFF +FlexBus (External Memory - Write-through) +All masters +0xA000\_0000–0xDFFF\_FFFF +FlexBus (External Peripheral - Not executable) +All masters +0xE000\_0000–0xE00F\_FFFF +Private peripherals +Cortex-M4 core +only +0xE010\_0000–0xFFFF\_FFFF +Reserved +– +NOTE +1. EzPort master port is statically muxed with DMA master +port. Access rights to AIPS-Lite peripheral bridges and +general purpose input/output (GPIO) module address space +is limited to the core, DMA, and EzPort. +2. ARM Cortex-M4 core access privileges also includes +accesses via the debug interface. +4.2.1 +Aliased bit-band regions +The SRAM\_U, AIPS-Lite, and general purpose input/output (GPIO) module resources +reside in the Cortex-M4 processor bit-band regions. +The processor also includes two 32 MB aliased bit-band regions associated with the two +1 MB bit-band spaces. Each 32-bit location in the 32 MB space maps to an individual bit +in the bit-band region. A 32-bit write in the alias region has the same effect as a read- +modify-write operation on the targeted bit in the bit-band region. +Bit 0 of the value written to the alias region determines what value is written to the target +bit: +System memory map +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +170 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 170](pdf-image://page_170_img_1) + +## Page 171 + +• Writing a value with bit 0 set writes a 1 to the target bit. +• Writing a value with bit 0 clear writes a 0 to the target bit. +A 32-bit read in the alias region returns either: +• a value of 0x0000\_0000 to indicate the target bit is clear +• a value of 0x0000\_0001 to indicate the target bit is set +31 +0 +0 +31 +Bit-band region +Alias bit-band region +1 MByte +32 MByte +Figure 4-1. Alias bit-band mapping +NOTE +Each bit in bit-band region has an equivalent bit that can be +manipulated through bit 0 in a corresponding long word in the +alias bit-band region. +4.3 +Flash Memory Map +The various flash memories and the flash registers are located at different base addresses +as shown in the following figure. The base address for each is specified in System +memory map. +Chapter 4 Memory Map +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +171 +General Business Information + +![Image 1 from page 171](pdf-image://page_171_img_1) + +## Page 172 + +Program flash +Flash configuration field +Program flash base address +Flash memory base address +Registers +RAM +Programming acceleration +RAM base address +Figure 4-2. Flash memory map for devices containing only program flash +Program flash +Flash configuration field +FlexNVM base address +Program flash base address +Flash memory base address +Registers +FlexNVM +FlexRAM +FlexRAM base address +Figure 4-3. Flash memory map for devices containing FlexNVM +4.3.1 +Alternate Non-Volatile IRC User Trim Description +The following non-volatile locations (4 bytes) are reserved for custom IRC user trim +supported by some development tools. An alternate IRC trim to the factory loaded trim +can be stored at this location. To override the factory trim, user software must load new +values into the MCG trim registers. +Non-Volatile Byte Address +Alternate IRC Trim Value +0x0000\_03FC +Reserved +0x0000\_03FD +Reserved +0x0000\_03FE (bit 0) +SCFTRIM +0x0000\_03FE (bit 4:1) +FCTRIM +0x0000\_03FF +SCTRIM +Flash Memory Map +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +172 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 172](pdf-image://page_172_img_1) + +## Page 173 + +4.4 +SRAM memory map +The on-chip RAM is split evenly among SRAM\_L and SRAM\_U. The RAM is also +implemented such that the SRAM\_L and SRAM\_U ranges form a contiguous block in +the memory map. See SRAM Arrays for details. +Accesses to the SRAM\_L and SRAM\_U memory ranges outside the amount of RAM on +the device causes the bus cycle to be terminated with an error followed by the appropriate +response in the requesting bus master. +4.5 +Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory +maps +The peripheral memory map is accessible via two slave ports on the crossbar switch in +the 0x4000\_0000–0x400F\_FFFF region. The device implements two peripheral bridges +(AIPS-Lite 0 and 1): +• AIPS-Lite0 covers 512 KB +• AIPS-Lite1 covers 508 KB with 4 KB assigned to the general purpose input/output +module (GPIO) +AIPS-Lite0 is connected to crossbar switch slave port 2, and is accessible at locations +0x4000\_0000–0x4007\_FFFF. +AIPS-Lite1 and the general purpose input/output module share the connection to crossbar +switch slave port 3. The AIPS-Lite1 is accessible at locations 0x4008\_0000– +0x400F\_EFFF. The general purpose input/output module is accessible in a 4-kbyte region +at 0x400F\_F000–0x400F\_FFFF. Its direct connection to the crossbar switch provides +master access without incurring wait states associated with accesses via the AIPS-Lite +controllers. +Modules that are disabled via their clock gate control bits in the SIM registers disable the +associated AIPS slots. Access to any address within an unimplemented or disabled +peripheral bridge slot results in a transfer error termination. +For programming model accesses via the peripheral bridges, there is generally only a +small range within the 4 KB slots that is implemented. Accessing an address that is not +implemented in the peripheral results in a transfer error termination. +Chapter 4 Memory Map +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +173 +General Business Information + +![Image 1 from page 173](pdf-image://page_173_img_1) + +## Page 174 + +4.5.1 +Peripheral Bridge 0 (AIPS-Lite 0) Memory Map +Table 4-2. Peripheral bridge 0 slot assignments +System 32-bit base address +Slot +number +Module +0x4000\_0000 +0 +Peripheral bridge 0 (AIPS-Lite 0) +0x4000\_1000 +1 +— +0x4000\_2000 +2 +— +0x4000\_3000 +3 +— +0x4000\_4000 +4 +Crossbar switch +0x4000\_5000 +5 +— +0x4000\_6000 +6 +— +0x4000\_7000 +7 +— +0x4000\_8000 +8 +DMA controller +0x4000\_9000 +9 +DMA controller transfer control descriptors +0x4000\_A000 +10 +— +0x4000\_B000 +11 +— +0x4000\_C000 +12 +FlexBus +0x4000\_D000 +13 +MPU +0x4000\_E000 +14 +— +0x4000\_F000 +15 +— +0x4001\_0000 +16 +— +0x4001\_1000 +17 +— +0x4001\_2000 +18 +— +0x4001\_3000 +19 +— +0x4001\_4000 +20 +— +0x4001\_5000 +21 +— +0x4001\_6000 +22 +— +0x4001\_7000 +23 +— +0x4001\_8000 +24 +— +0x4001\_9000 +25 +— +0x4001\_A000 +26 +— +0x4001\_B000 +27 +— +0x4001\_C000 +28 +— +0x4001\_D000 +29 +— +0x4001\_E000 +30 +— +0x4001\_F000 +31 +Flash memory controller +0x4002\_0000 +32 +Flash memory +0x4002\_1000 +33 +DMA channel mutiplexer 0 +0x4002\_2000 +34 +— +0x4002\_3000 +35 +— +0x4002\_4000 +36 +FlexCAN 0 +Table continues on the next page... +Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +174 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 174](pdf-image://page_174_img_1) + +## Page 175 + +Table 4-2. Peripheral bridge 0 slot assignments (continued) +System 32-bit base address +Slot +number +Module +0x4002\_5000 +37 +— +0x4002\_6000 +38 +— +0x4002\_7000 +39 +— +0x4002\_8000 +40 +— +0x4002\_9000 +41 +— +0x4002\_A000 +42 +— +0x4002\_B000 +43 +— +0x4002\_C000 +44 +SPI 0 +0x4002\_D000 +45 +SPI 1 +0x4002\_E000 +46 +— +0x4002\_F000 +47 +I2S 0 +0x4003\_0000 +48 +— +0x4003\_1000 +49 +— +0x4003\_2000 +50 +CRC +0x4003\_3000 +51 +— +0x4003\_4000 +52 +— +0x4003\_5000 +53 +USB DCD +0x4003\_6000 +54 +Programmable delay block (PDB) +0x4003\_7000 +55 +Periodic interrupt timers (PIT) +0x4003\_8000 +56 +FlexTimer (FTM) 0 +0x4003\_9000 +57 +FlexTimer (FTM) 1 +0x4003\_A000 +58 +— +0x4003\_B000 +59 +Analog-to-digital converter (ADC) 0 +0x4003\_C000 +60 +— +0x4003\_D000 +61 +Real-time clock (RTC) +0x4003\_E000 +62 +VBAT register file +0x4003\_F000 +63 +— +0x4004\_0000 +64 +Low-power timer (LPTMR) +0x4004\_1000 +65 +System register file +0x4004\_2000 +66 +— +0x4004\_3000 +67 +— +0x4004\_4000 +68 +— +0x4004\_5000 +69 +Touch sense interface (TSI) +0x4004\_6000 +70 +— +0x4004\_7000 +71 +SIM low-power logic +0x4004\_8000 +72 +System integration module (SIM) +0x4004\_9000 +73 +Port A multiplexing control +0x4004\_A000 +74 +Port B multiplexing control +0x4004\_B000 +75 +Port C multiplexing control +Table continues on the next page... +Chapter 4 Memory Map +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +175 +General Business Information + +![Image 1 from page 175](pdf-image://page_175_img_1) + +## Page 176 + +Table 4-2. Peripheral bridge 0 slot assignments (continued) +System 32-bit base address +Slot +number +Module +0x4004\_C000 +76 +Port D multiplexing control +0x4004\_D000 +77 +Port E multiplexing control +0x4004\_E000 +78 +— +0x4004\_F000 +79 +— +0x4005\_0000 +80 +— +0x4005\_1000 +81 +— +0x4005\_2000 +82 +Software watchdog +0x4005\_3000 +83 +— +0x4005\_4000 +84 +— +0x4005\_5000 +85 +— +0x4005\_6000 +86 +— +0x4005\_7000 +87 +— +0x4005\_8000 +88 +— +0x4005\_9000 +89 +— +0x4005\_A000 +90 +— +0x4005\_B000 +91 +— +0x4005\_C000 +92 +— +0x4005\_D000 +93 +— +0x4005\_E000 +94 +— +0x4005\_F000 +95 +— +0x4006\_0000 +96 +— +0x4006\_1000 +97 +External watchdog +0x4006\_2000 +98 +Carrier modulator timer (CMT) +0x4006\_3000 +99 +— +0x4006\_4000 +100 +Multi-purpose Clock Generator (MCG) +0x4006\_5000 +101 +System oscillator (OSC) +0x4006\_6000 +102 +I2C 0 +0x4006\_7000 +103 +I2C 1 +0x4006\_8000 +104 +— +0x4006\_9000 +105 +— +0x4006\_A000 +106 +UART 0 +0x4006\_B000 +107 +UART 1 +0x4006\_C000 +108 +UART 2 +0x4006\_D000 +109 +UART 3 +0x4006\_E000 +110 +— +0x4006\_F000 +111 +— +0x4007\_0000 +112 +— +0x4007\_1000 +113 +— +0x4007\_2000 +114 +USB OTG FS/LS +Table continues on the next page... +Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +176 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 176](pdf-image://page_176_img_1) + +## Page 177 + +Table 4-2. Peripheral bridge 0 slot assignments (continued) +System 32-bit base address +Slot +number +Module +0x4007\_3000 +115 +Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) +0x4007\_4000 +116 +Voltage reference (VREF) +0x4007\_5000 +117 +— +0x4007\_6000 +118 +— +0x4007\_7000 +119 +— +0x4007\_8000 +120 +— +0x4007\_9000 +121 +— +0x4007\_A000 +122 +— +0x4007\_B000 +123 +— +0x4007\_C000 +124 +Low-leakage wakeup unit (LLWU) +0x4007\_D000 +125 +Power management controller (PMC) +0x4007\_E000 +126 +System Mode controller (SMC) +0x4007\_F000 +127 +Reset Control Module (RCM) +4.5.2 +Peripheral Bridge 1 (AIPS-Lite 1) Memory Map +Table 4-3. Peripheral bridge 1 slot assignments +System 32-bit base address +Slot +number +Module +0x4008\_0000 +0 +Peripheral bridge 1 (AIPS-Lite 1) +0x4008\_1000 +1 +— +0x4008\_2000 +2 +— +0x4008\_3000 +3 +— +0x4008\_4000 +4 +— +0x4008\_5000 +5 +— +0x4008\_6000 +6 +— +0x4008\_7000 +7 +— +0x4008\_8000 +8 +— +0x4008\_9000 +9 +— +0x4008\_A000 +10 +— +0x4008\_B000 +11 +— +0x4008\_C000 +12 +— +0x4008\_D000 +13 +— +0x4008\_E000 +14 +— +0x4008\_F000 +15 +— +0x4009\_0000 +16 +— +0x4009\_1000 +17 +— +Table continues on the next page... +Chapter 4 Memory Map +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +177 +General Business Information + +![Image 1 from page 177](pdf-image://page_177_img_1) + +## Page 178 + +Table 4-3. Peripheral bridge 1 slot assignments (continued) +System 32-bit base address +Slot +number +Module +0x4009\_2000 +18 +— +0x4009\_3000 +19 +— +0x4009\_4000 +20 +— +0x4009\_5000 +21 +— +0x4009\_6000 +22 +— +0x4009\_7000 +23 +— +0x4009\_8000 +24 +— +0x4009\_9000 +25 +— +0x4009\_A000 +26 +— +0x4009\_B000 +27 +— +0x4009\_C000 +28 +— +0x4009\_D000 +29 +— +0x4009\_E000 +30 +— +0x4009\_F000 +31 +— +0x400A\_0000 +32 +Random number generator (RNGA) +0x400A\_1000 +33 +— +0x400A\_2000 +34 +— +0x400A\_3000 +35 +— +0x400A\_4000 +36 +FlexCAN 1 +0x400A\_5000 +37 +— +0x400A\_6000 +38 +— +0x400A\_7000 +39 +— +0x400A\_8000 +40 +— +0x400A\_9000 +41 +— +0x400A\_A000 +42 +— +0x400A\_B000 +43 +— +0x400A\_C000 +44 +SPI 2 +0x400A\_D000 +45 +— +0x400A\_E000 +46 +— +0x400A\_F000 +47 +— +0x400B\_0000 +48 +— +0x400B\_1000 +49 +SDHC +0x400B\_2000 +50 +— +0x400B\_3000 +51 +— +0x400B\_4000 +52 +— +0x400B\_5000 +53 +— +0x400B\_6000 +54 +— +0x400B\_7000 +55 +— +0x400B\_8000 +56 +FlexTimer (FTM) 2 +Table continues on the next page... +Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +178 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 178](pdf-image://page_178_img_1) + +## Page 179 + +Table 4-3. Peripheral bridge 1 slot assignments (continued) +System 32-bit base address +Slot +number +Module +0x400B\_9000 +57 +— +0x400B\_A000 +58 +— +0x400B\_B000 +59 +Analog-to-digital converter (ADC) 1 +0x400B\_C000 +60 +— +0x400B\_D000 +61 +— +0x400B\_E000 +62 +— +0x400B\_F000 +63 +— +0x400C\_0000 +64 +Ethernet MAC and IEEE 1588 timers +0x400C\_1000 +65 +— +0x400C\_2000 +66 +— +0x400C\_3000 +67 +— +0x400C\_4000 +68 +— +0x400C\_5000 +69 +— +0x400C\_6000 +70 +— +0x400C\_7000 +71 +— +0x400C\_8000 +72 +— +0x400C\_9000 +73 +— +0x400C\_A000 +74 +— +0x400C\_B000 +75 +— +0x400C\_C000 +76 +12-bit digital-to-analog converter (DAC) 0 +0x400C\_D000 +77 +12-bit digital-to-analog converter (DAC) 1 +0x400C\_E000 +78 +— +0x400C\_F000 +79 +— +0x400D\_0000 +80 +— +0x400D\_1000 +81 +— +0x400D\_2000 +82 +— +0x400D\_3000 +83 +— +0x400D\_4000 +84 +— +0x400D\_5000 +85 +— +0x400D\_6000 +86 +— +0x400D\_7000 +87 +— +0x400D\_8000 +88 +— +0x400D\_9000 +89 +— +0x400D\_A000 +90 +— +0x400D\_B000 +91 +— +0x400D\_C000 +92 +— +0x400D\_D000 +93 +— +0x400D\_E000 +94 +— +0x400D\_F000 +95 +— +Table continues on the next page... +Chapter 4 Memory Map +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +179 +General Business Information + +![Image 1 from page 179](pdf-image://page_179_img_1) + +## Page 180 + +Table 4-3. Peripheral bridge 1 slot assignments (continued) +System 32-bit base address +Slot +number +Module +0x400E\_0000 +96 +— +0x400E\_1000 +97 +— +0x400E\_2000 +98 +— +0x400E\_3000 +99 +— +0x400E\_4000 +100 +— +0x400E\_5000 +101 +— +0x400E\_6000 +102 +— +0x400E\_7000 +103 +— +0x400E\_8000 +104 +— +0x400E\_9000 +105 +— +0x400E\_A000 +106 +UART 4 +0x400E\_B000 +107 +UART 5 +0x400E\_C000 +108 +— +0x400E\_D000 +109 +— +0x400E\_E000 +110 +— +0x400E\_F000 +111 +— +0x400F\_0000 +112 +— +0x400F\_1000 +113 +— +0x400F\_2000 +114 +— +0x400F\_3000 +115 +— +0x400F\_4000 +116 +— +0x400F\_5000 +117 +— +0x400F\_6000 +118 +— +0x400F\_7000 +119 +— +0x400F\_8000 +120 +— +0x400F\_9000 +121 +— +0x400F\_A000 +122 +— +0x400F\_B000 +123 +— +0x400F\_C000 +124 +— +0x400F\_D000 +125 +— +0x400F\_E000 +126 +— +0x400F\_F000 +Not an AIPS-Lite slot. The 32-bit general purpose input/output module that shares the +crossbar switch slave port with the AIPS-Lite is accessed at this address. +Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +180 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 180](pdf-image://page_180_img_1) + +## Page 181 + +4.6 +Private Peripheral Bus (PPB) memory map +The PPB is part of the defined ARM bus architecture and provides access to select +processor-local modules. These resources are only accessible from the core; other system +masters do not have access to them. +Table 4-4. PPB memory map +System 32-bit Address Range +Resource +0xE000\_0000–0xE000\_0FFF +Instrumentation Trace Macrocell (ITM) +0xE000\_1000–0xE000\_1FFF +Data Watchpoint and Trace (DWT) +0xE000\_2000–0xE000\_2FFF +Flash Patch and Breakpoint (FPB) +0xE000\_3000–0xE000\_DFFF +Reserved +0xE000\_E000–0xE000\_EFFF +System Control Space (SCS) (for NVIC) +0xE000\_F000–0xE003\_FFFF +Reserved +0xE004\_0000–0xE004\_0FFF +Trace Port Interface Unit (TPIU) +0xE004\_1000–0xE004\_1FFF +Embedded Trace Macrocell (ETM) +0xE004\_2000–0xE004\_2FFF +Embedded Trace Buffer (ETB) +0xE004\_3000–0xE004\_3FFF +Embedded Trace Funnel +0xE004\_4000–0xE007\_FFFF +Reserved +0xE008\_0000–0xE008\_0FFF +Miscellaneous Control Module (MCM)(including ETB Almost Full) +0xE008\_1000–0xE008\_1FFF +Memory Mapped Cryptographic Acceleration Unit (MMCAU) +0xE008\_2000–0xE00F\_EFFF +Reserved +0xE00F\_F000–0xE00F\_FFFF +ROM Table - allows auto-detection of debug components +Chapter 4 Memory Map +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +181 +General Business Information + +![Image 1 from page 181](pdf-image://page_181_img_1) + +## Page 182 + +Private Peripheral Bus (PPB) memory map +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +182 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 182](pdf-image://page_182_img_1) + +## Page 183 + +Chapter 5 +Clock Distribution +5.1 +Introduction +The MCG module controls which clock source is used to derive the system clocks. The +clock generation logic divides the selected clock source into a variety of clock domains, +including the clocks for the system bus masters, system bus slaves, and flash memory. +The clock generation logic also implements module-specific clock gating to allow +granular shutoff of modules. +The primary clocks for the system are generated from the MCGOUTCLK clock. The +clock generation circuitry provides several clock dividers that allow different portions of +the device to be clocked at different frequencies. This allows for trade-offs between +performance and power dissipation. +Various modules, such as the USB OTG Controller, have module-specific clocks that can +be generated from the MCGPLLCLK or MCGFLLCLK clock. In addition, there are +various other module-specific clocks that have other alternate sources. Clock selection for +most modules is controlled by the SOPT registers in the SIM module. +5.2 +Programming model +The selection and multiplexing of system clock sources is controlled and programmed via +the MCG module. The setting of clock dividers and module clock gating for the system +are programmed via the SIM module. Reference those sections for detailed register and +bit descriptions. +5.3 +High-Level device clocking diagram +The following system oscillator, MCG, and SIM module registers control the +multiplexers, dividers, and clock gates shown in the below figure: +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +183 +General Business Information + +![Image 1 from page 183](pdf-image://page_183_img_1) + +## Page 184 + +OSC +MCG +SIM +Multiplexers +MCG\_Cx +MCG\_Cx +SIM\_SOPT1, SIM\_SOPT2 +Dividers +— +MCG\_Cx +SIM\_CLKDIVx +Clock gates +OSC\_CR +MCG\_C1 +SIM\_SCGCx +32 kHz IRC +PLL +FLL +MCGOUTCLK +MCGPLLCLK +MCG +MCGFLLCLK +OUTDIV1 +Core / system clocks +4 MHz IRC +OUTDIV4 +Flash clock +OUTDIV2 +Bus clock +RTC oscillator +EXTAL32 +XTAL32 +EXTAL0 +XTAL0 +System oscillator +SIM +FRDIV +MCGIRCLK +ERCLK32K +OSC32KCLK +XTAL\_CLK +MCGFFCLK +OSCERCLK +OSC +logic +OSC logic +Clock options for +some peripherals +(see note) +MCGFLLCLK +MCGPLLCLK/ +Note: See subsequent sections for details on where these clocks are used. +PMC logic +PMC +LPO +OSCCLK +CG +CG +CG +CG +CG +CG — Clock gate +RTC clock +Clock options for some +peripherals (see note) +FCRDIV +OUTDIV3 +FlexBus clock +CG +Figure 5-1. Clocking diagram +5.4 +Clock definitions +The following table describes the clocks in the previous block diagram. +Clock name +Description +Core clock +MCGOUTCLK divided by OUTDIV1 clocks the ARM Cortex- +M4 core +Table continues on the next page... +Clock definitions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +184 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 184](pdf-image://page_184_img_1) + +## Page 185 + +Clock name +Description +System clock +MCGOUTCLK divided by OUTDIV1 clocks the crossbar +switch and bus masters directly connected to the crossbar. In +addition, this clock is used for UART0 and UART1. +Bus clock +MCGOUTCLK divided by OUTDIV2 clocks the bus slaves +and peripheral (excluding memories) +FlexBus clock +MCGOUTCLK divided by OUTDIV3 clocks the external +FlexBus interface +Flash clock +MCGOUTCLK divided by OUTDIV4 clocks the flash memory +MCGIRCLK +MCG output of the slow or fast internal reference clock +MCGFFCLK +MCG output of the slow internal reference clock or a divided +MCG external reference clock. +MCGOUTCLK +MCG output of either IRC, MCGFLLCLK, MCGPLLCLK, or +MCG's external reference clock that sources the core, +system, bus, FlexBus, and flash clock. It is also an option for +the debug trace clock. +MCGFLLCLK +MCG output of the FLL. MCGFLLCLK or MCGPLLCLK may +clock some modules. +MCGPLLCLK +MCG output of the PLL. MCGFLLCLK or MCGPLLCLK may +clock some modules. +MCG external reference clock +Input clock to the MCG sourced by the system oscillator +(OSCCLK) or RTC oscillator +OSCCLK +System oscillator output of the internal oscillator or sourced +directly from EXTAL +OSCERCLK +System oscillator output sourced from OSCCLKthat may +clock some on-chip modules +OSC32KCLK +System oscillator 32kHz output +ERCLK32K +Clock source for some modules that is chosen as +OSC32KCLK or the RTC clock. It is VLPOSCCLK for TSI. +RTC clock +RTC oscillator output for the RTC module +LPO +PMC 1kHz output +5.4.1 +Device clock summary +The following table provides more information regarding the on-chip clocks. +Table 5-1. Clock Summary +Clock name +Run mode +clock frequency +VLPR mode +clock frequency +Clock source +Clock is disabled +when… +MCGOUTCLK +Up to 100 MHz +Up to 4 MHz +MCG +In all stop modes +Core clock +Up to 100 MHz +Up to 4 MHz +MCGOUTCLK clock +divider +In all wait and stop +modes +System clock +Up to 100 MHz +Up to 4 MHz +MCGOUTCLK clock +divider +In all stop modes +Table continues on the next page... +Chapter 5 Clock Distribution +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +185 +General Business Information + +![Image 1 from page 185](pdf-image://page_185_img_1) + +## Page 186 + +Table 5-1. Clock Summary (continued) +Clock name +Run mode +clock frequency +VLPR mode +clock frequency +Clock source +Clock is disabled +when… +Bus clock +Up to 50 MHz +Up to 4 MHz +MCGOUTCLK clock +divider +In all stop modes +FlexBus clock +(FB\_CLK) +Up to 50 MHz +Up to 4 MHz +MCGOUTCLK clock +divider +In all stop modes or +FlexBus disabled +Flash clock +Up to 25 MHz +Up to 1 MHz in BLPE, +Up to 800 kHz in BLPI +MCGOUTCLK clock +divider +In all stop modes +Internal reference +(MCGIRCLK) +30-40 kHz or 4 MHz +4 MHz only +MCG +MCG\_C1[IRCLKEN] +cleared, +Stop mode and +MCG\_C1[IREFSTEN] +cleared, or +VLPS/LLS/VLLS mode +External reference +(OSCERCLK) +Up to 50 MHz (bypass), +30-40 kHz, or +3-32 MHz (crystal) +Up to 16 MHz (bypass), +30-40 kHz (low-range +crystal) or +Up to 4 MHz (high- +range crystal) +System OSC +System OSC's +OSC\_CR[ERCLKEN] +cleared, or +Stop mode and +OSC\_CR[EREFSTEN] +cleared +External reference +32kHz +(ERCLK32K) +30-40 kHz +30-40 kHz +System OSC or RTC +OSC depending on +SIM\_SOPT1[OSC32KS +EL] +System OSC's +OSC\_CR[ERCLKEN] +cleared or +RTC's RTC\_CR[OSCE] +cleared +RTC\_CLKOUT +1 Hz or 32 kHz +1 Hz or 32 kHz +RTC clock +Clock is disabled in LLS +and VLLSx modes +LPO +1 kHz +1 kHz +PMC +Available in all power +modes +USB FS clock +48 MHz +N/A +MCGPLLCLK or +MCGFLLCLK with +fractional clock divider, +or +USB\_CLKIN +USB FS OTG is +disabled +I2S master clock +Up to 25 MHz +Up to 12.5 MHz +System clock, +MCGPLLCLK, +OSCERCLK with +fractional clock divider, +or +I2S\_CLKIN +I2S is disabled +SDHC clock +Up to 50 MHz +N/A +System clock, +MCGPLLCLK/ +MCGFLLCLK, or +OSCERCLK +SDHC is disabled +Ethernet RMII clock +50 MHz +N/A +OSCERCLK +Ethernet is disabled +Table continues on the next page... +Clock definitions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +186 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 186](pdf-image://page_186_img_1) + +## Page 187 + +Table 5-1. Clock Summary (continued) +Clock name +Run mode +clock frequency +VLPR mode +clock frequency +Clock source +Clock is disabled +when… +Ethernet IEEE 1588 +clock +Up to 100 MHz +N/A +System clock, +OSCERCLK, +MCGPLLCLK/ +MCGFLLCLK, or +ENET\_1588\_CLKIN +Ethernet is disabled +TRACE clock +Up to 100 MHz +Up to 4 MHz +System clock or +MCGOUTCLK +Trace is disabled +5.5 +Internal clocking requirements +The clock dividers are programmed via the SIM module’s CLKDIV registers. Each +divider is programmable from a divide-by-1 through divide-by-16 setting. The following +requirements must be met when configuring the clocks for this device: +1. The core and system clock frequencies must be 100 MHz or slower. +2. The bus clock frequency must be programmed to 50 MHz or less and an integer +divide of the core clock. +3. The flash clock frequency must be programmed to 25 MHz or less, less than or equal +to the bus clock, and an integer divide of the core clock. +4. The FlexBus clock frequency must be programmed to be less than or equal to the bus +clock frequency. +The following are a few of the more common clock configurations for this device: +Option 1: +Clock +Frequency +Core clock +50 MHz +System clock +50 MHz +Bus clock +50 MHz +FlexBus clock +50 MHz +Flash clock +25 MHz +Option 2: +Chapter 5 Clock Distribution +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +187 +General Business Information + +![Image 1 from page 187](pdf-image://page_187_img_1) + +## Page 188 + +Clock +Frequency +Core clock +100 MHz +System clock +100 MHz +Bus clock +50 MHz +FlexBus clock +25 MHz +Flash clock +25 MHz +Option 3: +Clock +Frequency +Core clock +96 MHz +System clock +96 MHz +Bus clock +48 MHz +FlexBus clock +48 MHz +Flash clock +24 MHz +5.5.1 +Clock divider values after reset +Each clock divider is programmed via the SIM module’s CLKDIVn registers. The flash +memory's FTFL\_FOPT[LPBOOT] bit controls the reset value of the core clock, system +clock, bus clock, and flash clock dividers as shown below: +FTFL\_FOPT +[LPBOOT] +Core/system +clock +Bus clock +FlexBus clock +Flash clock +Description +0 +0x7 (divide by 8) +0x7 (divide by 8) +0xF (divide by 16) +0xF (divide by 16) +Low power boot +1 +0x0 (divide by 1) +0x0 (divide by 1) +0x1 (divide by 2) +0x1 (divide by 2) +Fast clock boot +This gives the user flexibility for a lower frequency, low-power boot option. The flash +erased state defaults to fast clocking mode, since where the low power boot +(FTFL\_FOPT[LPBOOT]) bit resides in flash is logic 1 in the flash erased state. +To enable the low power boot option program FTFL\_FOPT[LPBOOT] to zero. During +the reset sequence, if LPBOOT is cleared, the system is in a slow clock configuration. +Upon any system reset, the clock dividers return to this configurable reset state. +5.5.2 +VLPR mode clocking +The clock dividers cannot be changed while in VLPR mode. They must be programmed +prior to entering VLPR mode to guarantee: +Internal clocking requirements +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +188 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 188](pdf-image://page_188_img_1) + +## Page 189 + +• the core/system, FlexBus, and bus clocks are less than or equal to 4 MHz, and +• the flash memory clock is less than or equal to 1 MHz +NOTE +When the MCG is in BLPI and clocking is derived from the +Fast IRC, the clock divider controls, MCG\_SC[FCRDIV] and +SIM\_CLKDIV1[OUTDIV4], must be programmed such that +the resulting flash clock nominal frequency is 800 kHz or less. +In this case, one example of correct configuration is +MCG\_SC[FCRDIV]=000b and +SIM\_CLKDIV1[OUTDIV4]=0100b, resulting in a divide by 5 +setting. +5.6 +Clock Gating +The clock to each module can be individually gated on and off using the SIM module's +SCGCx registers. These bits are cleared after any reset, which disables the clock to the +corresponding module to conserve power. Prior to initializing a module, set the +corresponding bit in SCGCx register to enable the clock. Before turning off the clock, +make sure to disable the module. +Any bus access to a peripheral that has its clock disabled generates an error termination. +5.7 +Module clocks +The following table summarizes the clocks associated with each module. +Table 5-2. Module clocks +Module +Bus interface clock +Internal clocks +I/O interface clocks +Core modules +ARM Cortex-M4 core +System clock +Core clock +— +NVIC +System clock +— +— +DAP +System clock +— +— +ITM +System clock +— +— +ETM +System clock +TRACE clock +TRACE\_CLKOUT +ETB +System clock +— +— +cJTAG, JTAGC +— +— +JTAG\_CLK +System modules +DMA +System clock +— +— +Table continues on the next page... +Chapter 5 Clock Distribution +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +189 +General Business Information + +![Image 1 from page 189](pdf-image://page_189_img_1) + +## Page 190 + +Table 5-2. Module clocks (continued) +Module +Bus interface clock +Internal clocks +I/O interface clocks +DMA Mux +Bus clock +— +— +Port control +Bus clock +LPO +— +Crossbar Switch +System clock +— +— +Peripheral bridges +System clock +Bus clock, Flash clock +— +MPU +System clock +— +— +LLWU, PMC, SIM, RCM +Flash clock +LPO +— +Mode controller +Flash clock +— +— +MCM +System clock +— +— +EWM +Bus clock +LPO +— +Watchdog timer +Bus clock +LPO +— +Clocks +MCG +Bus clock +MCGOUTCLK, MCGPLLCLK, +MCGFLLCLK, MCGIRCLK, +OSCERCLK, EXTAL32K +— +OSC +Bus clock +OSCERCLK +— +Memory and memory interfaces +Flash Controller +System clock +Flash clock +— +Flash memory +Flash clock +— +— +FlexBus +System clock +— +CLKOUT +EzPort +System clock +— +EZP\_CLK +Security +CRC +Bus clock +— +— +MMCAU +System clock +— +— +RNGA +Bus clock +— +— +Analog +ADC +Bus clock +OSCERCLK +— +CMP +Bus clock +— +— +DAC +Bus clock +— +— +VREF +Bus clock +— +— +Timers +PDB +Bus clock +— +— +FlexTimers +Bus clock +MCGFFCLK +FTM\_CLKINx +PIT +Bus clock +— +— +LPTMR +Flash clock +LPO, OSCERCLK, +MCGIRCLK, ERCLK32K +— +CMT +Bus clock +— +— +RTC +Flash clock +EXTAL32 +— +Communication interfaces +Ethernet +System clock, Bus clock +RMII clock, IEEE 1588 clock +MII\_RXCLK, MII\_TXCLK +USB FS OTG +System clock +USB FS clock +— +Table continues on the next page... +Module clocks +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +190 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 190](pdf-image://page_190_img_1) + +## Page 191 + +Table 5-2. Module clocks (continued) +Module +Bus interface clock +Internal clocks +I/O interface clocks +USB DCD +Bus clock +— +— +FlexCAN +Bus clock +OSCERCLK +— +DSPI +Bus clock +— +DSPI\_SCK +I2C +Bus clock +— +I2C\_SCL +UART0, UART1 +System clock +— +— +UART2-5 +Bus clock +— +— +SDHC +System clock +SDHC clock +SDHC\_DCLK +I2S +Bus clock +I2S master clock +I2S\_TX\_BCLK, +I2S\_RX\_BCLK +Human-machine interfaces +GPIO +System clock +— +— +TSI +Flash clock +LPO, ERCLK32K, +MCGIRCLK +— +5.7.1 +PMC 1-kHz LPO clock +The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all +modes of operation, including all low power modes. This 1-kHz source is commonly +referred to as LPO clock or 1-kHz LPO clock. +5.7.2 +WDOG clocking +The WDOG may be clocked from two clock sources as shown in the following figure. +WDOG\_STCTRLH[CLKSRC] +WDOG clock +Bus clock +LPO +Figure 5-2. WDOG clock generation +Chapter 5 Clock Distribution +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +191 +General Business Information + +![Image 1 from page 191](pdf-image://page_191_img_1) + +## Page 192 + +5.7.3 +Debug trace clock +The debug trace clock source can be clocked as shown in the following figure. +SIM\_SOPT2[TRACECLKSEL] +TRACECLKIN +Core / system clock +MCGOUTCLK +TPIU +÷2 +TRACE\_CLKOUT +Figure 5-3. Trace clock generation +NOTE +The trace clock frequency observed at the TRACE\_CLKOUT +pin will be half that of the selected clock source. +5.7.4 +PORT digital filter clocking +The digital filters in each of the PORTx modules can be clocked as shown in the +following figure. +NOTE +In stop mode, the digital input filters are bypassed unless they +are configured to run from the 1 kHz LPO clock source. +PORTx\_DFCR[CS] +PORTx digital input +filter clock +Bus clock +LPO +Figure 5-4. PORTx digital input filter clock generation +Module clocks +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +192 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 192](pdf-image://page_192_img_1) + +## Page 193 + +5.7.5 +LPTMR clocking +The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown +in the following figure. +NOTE +The chosen clock must remain enabled if the LPTMRx is to +continue operating in all required low-power modes. +LPTMRx\_PSR[PCS] +LPTMRx prescaler/glitch +filter clock +MCGIRCLK +OSCERCLK +ERCLK32K +LPO +Figure 5-5. LPTMRx prescaler/glitch filter clock generation +5.7.6 +Ethernet Clocking +• The RMII clock source is fixed to OSCERCLK and must be 50 MHz +• The MII clocks are supplied from pins and must be 25 MHz +• The IEEE 1588 timestamp clock can run up to 100 MHz, if generated from internal +clock sources. Its period must be an integer number of nanoseconds (eg: 10ns = 100 +MHz, 15ns = 66.67 MHz, 20ns = 50 MHz). Its clock source is chosen as shown in +the following figure. +Chapter 5 Clock Distribution +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +193 +General Business Information + +![Image 1 from page 193](pdf-image://page_193_img_1) + +## Page 194 + +Core / System +clock +OSCERCLK +MCGPLLCLK or +MCGFLLCLK +ENET\_1588\_CLKIN +SIM\_SOPT2[TIMESRC] +Ethernet IEEE 1588 +timestamp clock +Figure 5-6. Ethernet IEEE1588 timestamp clock generation +5.7.7 +USB FS OTG Controller clocking +The USB FS OTG controller is a bus master attached to the crossbar switch. As such, its +clock is connected to the system clock. +NOTE +For the USB FS OTG controller to operate, the minimum +system clock frequency is 20 MHz. +The USB OTG controller also requires a 48 MHz clock. The clock source options are +shown below. +USB 48MHz +USB\_CLKIN +MCGPLLCLK or +MCGFLLCLK +SIM\_CLKDIV2 +[USBFRAC, USBDIV] +SIM\_SOPT2[USBSRC] +Figure 5-7. USB 48 MHz clock source +NOTE +The MCGFLLCLK does not meet the USB jitter specifications +for certification. +Module clocks +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +194 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 194](pdf-image://page_194_img_1) + +## Page 195 + +5.7.8 +FlexCAN clocking +The clock for the FlexCAN's protocol engine can be selected as shown in the following +figure. +CANx\_CTRL1[CLKSRC] +FlexCAN clock +Bus clock +OSCERCLK +Figure 5-8. FlexCAN clock generation +5.7.9 +UART clocking +UART0 and UART1 modules operate from the core/system clock, which provides higher +performance level for these modules. All other UART modules operate from the bus +clock. +5.7.10 +SDHC clocking +The SDHC module has four possible clock sources for the external clock source, as +shown in the following figure. +SIM\_SOPT2[SDHCSRC] +SDHC clock +MCGPLLCLK or +MCGFLLCLK +Core / system clock +OSCERCLK +SDHC0\_CLKIN +Figure 5-9. SDHC clock generation +Chapter 5 Clock Distribution +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +195 +General Business Information + +![Image 1 from page 195](pdf-image://page_195_img_1) + +## Page 196 + +5.7.11 +I2S/SAI clocking +The audio master clock (MCLK) is used to generate the bit clock when the receiver or +transmitter is configured for an internally generated bit clock. The audio master clock can +also be output to or input from a pin. The transmitter and receiver have the same audio +master clock inputs. +Each SAI peripheral can control the input clock selection, pin direction and divide ratio +of one audio master clock. +The I2S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can +be generated internally from the audio master clock or supplied externally. The module +also supports the option for synchronous operation between the receiver and +transmitterproduct. +The transmitter and receiver can independently select between the bus clock and the +audio master clock to generate the bit clock. +The MCLK and BCLK source options appear in the following figure. +Fractional +Clock +Divider +1 +0 +11 +01 +10 +00 +OSC0ERCLK +MCGPLLCLK +SYSCLK +I2Sx\_MCR[MOE] +MCLK +MCLK\_OUT +MCLK\_IN +11 +01 +10 +00 +BUSCLK +[MSEL] +Bit +Clock +Divider +1 +0 +BCLK\_IN +I2S/SAI +BCLK\_OUT +[BCD] +BCLK +I2Sx\_MDR[FRACT,DIVIDE] +I2Sx\_MCR[MICS] +Clock Generation +[DIV] +I2Sx\_TCR2/RCR2 +Figure 5-10. I2S/SAI clock generation +5.7.12 +TSI clocking +In active mode, the TSI can be clocked as shown in the following figure. +Module clocks +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +196 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 196](pdf-image://page_196_img_1) + +## Page 197 + +TSI\_SCANC[AMCLKS] +TSI clock +in active mode +Bus clock +MCGIRCLK +OSCERCLK +Figure 5-11. TSI clock generation +In low-power mode, the TSI can be clocked as shown in the following figure. +NOTE +In the TSI chapter, these two clocks are referred to as LPOCLK +and VLPOSCCLK. +TSI\_GENCS[LPCLKS] +TSI clock +in low-power mode +LPO +ERCLK32K +Figure 5-12. TSI low-power clock generation +Chapter 5 Clock Distribution +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +197 +General Business Information + +![Image 1 from page 197](pdf-image://page_197_img_1) + +## Page 198 + +Module clocks +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +198 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 198](pdf-image://page_198_img_1) + +## Page 199 + +Chapter 6 +Reset and Boot +6.1 +Introduction +The following reset sources are supported in this MCU: +Table 6-1. Reset sources +Reset sources +Description +POR reset +• Power-on reset (POR) +System resets +• External pin reset (PIN) +• Low-voltage detect (LVD) +• Computer operating properly (COP) watchdog reset +• Low leakage wakeup (LLWU) reset +• Multipurpose clock generator loss of clock (LOC) reset +• Multipurpose clock generator loss of lock (LOL) reset +• Stop mode acknowledge error (SACKERR) +• Software reset (SW) +• Lockup reset (LOCKUP) +• EzPort reset +• MDM DAP system reset +Debug reset +• JTAG reset +• nTRST reset +Each of the system reset sources has an associated bit in the system reset status (SRS) +registers. See the Reset Control Module for register details. +The MCU exits reset in functional mode that is controlled by EZP\_CS pin to select +between the single chip (default) or serial flash programming (EzPort) modes. See Boot +options for more details. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +199 +General Business Information + +![Image 1 from page 199](pdf-image://page_199_img_1) + +## Page 200 + +6.2 +Reset +This section discusses basic reset mechanisms and sources. Some modules that cause +resets can be configured to cause interrupts instead. Consult the individual peripheral +chapters for more information. +6.2.1 +Power-on reset (POR) +When power is initially applied to the MCU or when the supply voltage drops below the +power-on reset re-arm voltage level (VPOR), the POR circuit causes a POR reset +condition. +As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has +risen above the LVD low threshold (VLVDL). The POR and LVD bits in SRS0 register are +set following a POR. +6.2.2 +System reset sources +Resetting the MCU provides a way to start processing from a known set of initial +conditions. System reset begins with the on-chip regulator in full regulation and system +clocking generation from an internal reference. When the processor exits reset, it +performs the following: +• Reads the start SP (SP\_main) from vector-table offset 0 +• Reads the start PC from vector-table offset 4 +• LR is set to 0xFFFF\_FFFF +The on-chip peripheral modules are disabled and the non-analog I/O pins are initially +configured as disabled. The pins with analog functions assigned to them default to their +analog function after reset. +During and following a reset, the JTAG pins have their associated input pins configured +as: +• TDI in pull-up (PU) +• TCK in pull-down (PD) +• TMS in PU +and associated output pin configured as: +• TDO with no pull-down or pull-up +Reset +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +200 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 200](pdf-image://page_200_img_1) + +## Page 201 + +Note that the nTRST signal is initially configured as disabled, however once configured +to its JTAG functionality its associated input pin is configured as: +• nTRST in PU +6.2.2.1 +External pin reset (PIN) +On this device, RESET is a dedicated pin. This pin is open drain and has an internal +pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the +RCM's SRS0[PIN] bit is set. +6.2.2.1.1 +Reset pin filter +The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus +clock. A separate filter is implemented for each clock source. In stop and VLPS mode +operation, this logic either switches to bypass operation or has continued filtering +operation depending on the filtering mode selected. In low leakage stop modes, a separate +LPO filter in the LLWU can continue filtering the RESET pin. +The RPFC[RSTFLTSS], RPFC[RSTFLTSRW], and RPFW[RSTFLTSEL] fields in the +reset control (RCM) register set control this functionality; see the RCM chapter. The +filters are asynchronously reset by Chip POR. The reset value for each filter assumes the +RESET pin is negated. +The two clock options for the RESET pin filter when the chip is not in low leakage +modes are the LPO (1 kHz) and bus clock. For low leakage modes VLLS3, VLLS2, +VLLS1, the LLWU provides control (in the LLWU\_RST register) of an optional fixed +digital filter running the LPO. +The LPO filter has a fixed filter value of 3. Due to a synchronizer on the input data, there +is also some associated latency (2 cycles). As a result, 5 cycles are required to complete a +transition from low to high or high to low. +The bus filter initializes to off (logic 1) when the bus filter is not enabled. The bus clock +is used when the filter selects bus clock, and the number of counts is controlled by the +RCM's RPFW[RSTFLTSEL] field. +Chapter 6 Reset and Boot +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +201 +General Business Information + +![Image 1 from page 201](pdf-image://page_201_img_1) + +## Page 202 + +6.2.2.2 +Low-voltage detect (LVD) +The chip includes a system for managing low voltage conditions to protect memory +contents and control MCU system states during supply voltage variations. The system +consists of a power-on reset (POR) circuit and an LVD circuit with a user-selectable trip +voltage. The LVD system is always enabled in normal run, wait, or stop mode. The LVD +system is disabled when entering VLPx, LLS, or VLLSx modes. +The LVD can be configured to generate a reset upon detection of a low voltage condition +by setting the PMC's LVDSC1[LVDRE] bit to 1. The low voltage detection threshold is +determined by the PMC's LVDSC1[LVDV] field. After an LVD reset has occurred, the +LVD system holds the MCU in reset until the supply voltage has risen above the low +voltage detection threshold. The RCM's SRS0[LVD] bit is set following either an LVD +reset or POR. +6.2.2.3 +Computer operating properly (COP) watchdog timer +The computer operating properly (COP) watchdog timer (WDOG) monitors the operation +of the system by expecting periodic communication from the software. This +communication is generally known as servicing (or refreshing) the COP watchdog. If this +periodic refreshing does not occur, the watchdog issues a system reset. The COP reset +causes the RCM's SRS0[WDOG] bit to set. +6.2.2.4 +Low leakage wakeup (LLWU) +The LLWU module provides the means for a number of external pins, the RESET pin, +and a number of internal peripherals to wake the MCU from low leakage power modes. +The LLWU module is functional only in low leakage power modes. +• In LLS mode, only the RESET pin via the LLWU can generate a system reset. +• In VLLSx modes, all enabled inputs to the LLWU can generate a system reset. +After a system reset, the LLWU retains the flags indicating the input source of the last +wakeup until the user clears them. +NOTE +Some flags are cleared in the LLWU and some flags are +required to be cleared in the peripheral module. Refer to the +individual peripheral chapters for more information. +Reset +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +202 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 202](pdf-image://page_202_img_1) + +## Page 203 + +6.2.2.5 +Multipurpose clock generator loss-of-clock (LOC) +The MCG module supports an external reference clock. +If the C6[CME] bit in the MCG module is set, the clock monitor is enabled. If the +external reference falls below floc\_low or floc\_high, as controlled by the C2[RANGE] field +in the MCG module, the MCU resets. The RCM's SRS0[LOC] bit is set to indicate this +reset source. +NOTE +To prevent unexpected loss of clock reset events, all clock +monitors should be disabled before entering any low power +modes, including VLPR and VLPW. +6.2.2.6 +MCG loss-of-lock (LOL) reset +The MCG includes a PLL loss-of-lock detector. The detector is enabled when configured +for PEE and lock has been achieved. If the MCG\_C8[LOLRE] bit in the MCG module is +set and the PLL lock status bit (MCG\_S[LOLS0]) becomes set, the MCU resets. The +RCM\_SRS0[LOL] bit is set to indicate this reset source. +NOTE +This reset source does not cause a reset if the chip is in any stop +mode. +6.2.2.7 +Stop mode acknowledge error (SACKERR) +This reset is generated if the core attempts to enter stop mode, but not all modules +acknowledge stop mode within 1025 cycles of the 1 kHz LPO clock. +A module might not acknowledge the entry to stop mode if an error condition occurs. The +error can be caused by a failure of an external clock input to a module. +6.2.2.8 +Software reset (SW) +The SYSRESETREQ bit in the NVIC application interrupt and reset control register can +be set to force a software reset on the device. (See ARM's NVIC documentation for the +full description of the register fields, especially the VECTKEY field requirements.) +Setting SYSRESETREQ generates a software reset request. This reset forces a system +reset of all major components except for the debug module. A software reset causes the +RCM's SRS1[SW] bit to set. +Chapter 6 Reset and Boot +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +203 +General Business Information + +![Image 1 from page 203](pdf-image://page_203_img_1) + +## Page 204 + +6.2.2.9 +Lockup reset (LOCKUP) +The LOCKUP gives immediate indication of seriously errant kernel software. This is the +result of the core being locked because of an unrecoverable exception following the +activation of the processor’s built in system state protection hardware. +The LOCKUP condition causes a system reset and also causes the RCM's +SRS1[LOCKUP] bit to set. +6.2.2.10 +EzPort reset +The EzPort supports a system reset request via EzPort signaling. The EzPort generates a +system reset request following execution of a Reset Chip (RESET) command via the +EzPort interface. This method of reset allows the chip to boot from flash memory after it +has been programmed by an external source. The EzPort is enabled or disabled by the +EZP\_CS pin. +An EzPort reset causes the RCM's SRS1[EZPT] bit to set. +6.2.2.11 +MDM-AP system reset request +Set the system reset request bit in the MDM-AP control register to initiate a system reset. +This is the primary method for resets via the JTAG/SWD interface. The system reset is +held until this bit is cleared. +Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the +rest of the chip comes out of system reset. +6.2.3 +MCU Resets +A variety of resets are generated by the MCU to reset different modules. +6.2.3.1 +VBAT POR +The VBAT POR asserts on a VBAT POR reset source. It affects only the modules within +the VBAT power domain: RTC and VBAT Register File. These modules are not affected +by the other reset types. +Reset +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +204 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 204](pdf-image://page_204_img_1) + +## Page 205 + +6.2.3.2 +POR Only +The POR Only reset asserts on the POR reset source only. It resets the PMC and System +Register File. +The POR Only reset also causes all other reset types (except VBAT POR) to occur. +6.2.3.3 +Chip POR not VLLS +The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of +the SMC and SIM. It also resets the LPTMR. +The Chip POR not VLLS reset also causes these resets to occur: Chip POR, Chip Reset +not VLLS, and Chip Reset (including Early Chip Reset). +6.2.3.4 +Chip POR +The Chip POR asserts on POR, LVD, and VLLS Wakeup reset sources. It resets the +Reset Pin Filter registers and parts of the SIM and MCG. +The Chip POR also causes the Chip Reset (including Early Chip Reset) to occur. +6.2.3.5 +Chip Reset not VLLS +The Chip Reset not VLLS reset asserts on all reset sources except a VLLS Wakeup that +does not occur via the RESET pin. It resets parts of the SMC, LLWU, and other modules +that remain powered during VLLS mode. +The Chip Reset not VLLS reset also causes the Chip Reset (including Early Chip Reset) +to occur. +6.2.3.6 +Early Chip Reset +The Early Chip Reset asserts on all reset sources. It resets only the flash memory module. +It negates before flash memory initialization begins ("earlier" than when the Chip Reset +negates). +Chapter 6 Reset and Boot +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +205 +General Business Information + +![Image 1 from page 205](pdf-image://page_205_img_1) + +## Page 206 + +6.2.3.7 +Chip Reset +Chip Reset asserts on all reset sources and only negates after flash initialization has +completed and the RESET pin has also negated. It resets the remaining modules (the +modules not reset by other reset types). +6.2.4 +Reset Pin +For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the +RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash +initialization has completed. +After flash initialization has completed, the RESET pin is released, and the internal Chip +Reset negates after the RESET pin is pulled high. Keeping the RESET pin asserted +externally delays the negation of the internal Chip Reset. +6.2.5 +Debug resets +The following sections detail the debug resets available on the device. +6.2.5.1 +JTAG reset +The JTAG module generate a system reset when certain IR codes are selected. This +functional reset is asserted when EzPort, EXTEST, HIGHZ and CLAMP instructions are +active. The reset source from the JTAG module is released when any other IR code is +selected. A JTAG reset causes the RCM's SRS1[JTAG] bit to set. +6.2.5.2 +nTRST reset +The nTRST pin causes a reset of the JTAG logic when asserted. Asserting the nTRST pin +allows the debugger to gain control of the TAP controller state machine (after exiting +LLS or VLLSx) without resetting the state of the debug modules. +The nTRST pin does not cause a system reset. +Reset +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +206 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 206](pdf-image://page_206_img_1) + +## Page 207 + +6.2.5.3 +Resetting the Debug subsystem +Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug +modules. However, as explained below, using the CDBGRSTREQ bit does not reset all +debug-related registers. +CDBGRSTREQ resets the debug-related registers within the following modules: +• SWJ-DP +• AHB-AP +• ETM +• ATB replicators +• ATB upsizers +• ATB funnels +• ETB +• TPIU +• MDM-AP (MDM control and status registers) +• MCM (ETB “Almost Full” logic) +CDBGRSTREQ does not reset the debug-related registers within the following modules: +• CM4 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR) +• FPB +• DWT +• ITM +• NVIC +• Crossbar bus switch1 +• AHB-AP1 +• Private peripheral bus1 +6.3 +Boot +This section describes the boot sequence, including sources and options. +6.3.1 +Boot sources +This device only supports booting from internal flash. Any secondary boot must go +through an initialization sequence in flash. +1. +CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available +during System Reset. +Chapter 6 Reset and Boot +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +207 +General Business Information + +![Image 1 from page 207](pdf-image://page_207_img_1) + +## Page 208 + +6.3.2 +Boot options +The device's functional mode is controlled by the state of the EzPort chip select +(EZP\_CS) pin during reset. +The device can be in single chip (default) or serial flash programming mode (EzPort). +While in single chip mode the device can be in run or various low power modes +mentioned in Power mode transitions. +Table 6-2. Mode select decoding +EzPort chip select (EZP\_CS) +Description +0 +Serial flash programming mode (EzPort) +1 +Single chip (default) +6.3.3 +FOPT boot options +The flash option register (FOPT) in flash memory module (FTFL) allows the user to +customize the operation of the MCU at boot time. The register contains read-only bits +that are loaded from the NVM's option byte in the flash configuration field. The user can +reprogram the option byte in flash to change the FOPT values that are used for +subsequent resets. For more details on programming the option byte, refer to the flash +memory chapter. +The MCU uses the FTFL\_FOPT register bits to configure the device at reset as shown in +the following table. +Table 6-3. Flash Option Register (FTFL\_FOPT) Bit Definitions +Bit +Num +Field +Value +Definition +7-3 +Reserved +Reserved for future expansion. +2 +NMI\_DIS +0 +NMI interrupts are always blocked. The associated pin continues to default to NMI +pin controls with internal pullup enabled. +1 +NMI pin/interrupts reset default to enabled. +1 +EZPORT\_DIS +0 +EzPort operation is disabled. The device always boots to normal CPU execution +and the state of EZP\_CS signal during reset is ignored. This option avoids +inadvertent resets into EzPort mode if the EZP\_CS/NMI pin is used for its NMI +function. +1 +EzPort operation is enabled. The state of EZP\_CS pin during reset determines if +device enters EzPort mode. +Table continues on the next page... +Boot +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +208 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 208](pdf-image://page_208_img_1) + +## Page 209 + +Table 6-3. Flash Option Register (FTFL\_FOPT) Bit Definitions +(continued) +Bit +Num +Field +Value +Definition +0 +LPBOOT +0 +Low-power boot: OUTDIVx values in SIM\_CLKDIV1 register are auto-configured at +reset exit for higher divide values that produce lower power consumption at reset +exit. +• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) +are 0x7 (divide by 8) +• Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0xF +(divide by 16) +1 +Normal boot: OUTDIVx values in SIM\_CLKDIV1 register are auto-configured at +reset exit for higher frequency values that produce faster operating frequencies at +reset exit. +• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2) +are 0x0 (divide by 1) +• Flash clock divider (OUTDIV4) and FlexBus clock divider (OUTDIV3) are 0x1 +(divide by 2) +6.3.4 +Boot sequence +At power up, the on-chip regulator holds the system in a POR state until the input supply +is above the POR threshold. The system continues to be held in this static state until the +internally regulated supplies have reached a safe operating voltage as determined by the +LVD. The Mode Controller reset logic then controls a sequence to exit reset. +1. A system reset is held on internal logic, the RESET pin is driven out low, and the +MCG is enabled in its default clocking mode. +2. Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any Bus +Clocks that do not have clock gate control). +3. The system reset on internal logic continues to be held, but the Flash Controller is +released from reset and begins initialization operation while the Mode Control logic +continues to drive the RESET pin out low for a count of ~128 Bus Clock cycles. +4. The RESET pin is released, but the system reset of internal logic continues to be held +until the Flash Controller finishes initialization. EzPort mode is selected instead of +the normal CPU execution if EZP\_CS is low when the internal reset is deasserted. +EzPort mode can be disabled by programming the FOPT[EZPORT\_DIS] field in the +Flash Memory module. +5. When Flash Initialization completes, the RESET pin is observed. If RESET +continues to be asserted (an indication of a slow rise time on the RESET pin or +external drive in low), the system continues to be held in reset. Once the RESET pin +is detected high, the system is released from reset. +Chapter 6 Reset and Boot +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +209 +General Business Information + +![Image 1 from page 209](pdf-image://page_209_img_1) + +## Page 210 + +6. At release of system reset, clocking is switched to a slow clock if the +FOPT[LPBOOT] field in the Flash Memory module is configured for Low Power +Boot +7. When the system exits reset, the processor sets up the stack, program counter (PC), +and link register (LR). The processor reads the start SP (SP\_main) from vector-table +offset 0. The core reads the start PC from vector-table offset 4. LR is set to +0xFFFF\_FFFF. The CPU begins execution at the PC location. EzPort mode is +entered instead of the normal CPU execution if Ezport mode was latched during the +sequence. +8. If FlexNVM is enabled, the flash controller continues to restore the FlexNVM data. +This data is not available immediately out of reset and the system should not access +this data until the flash controller completes this initialization step as indicated by the +EEERDY flag. +Subsequent system resets follow this reset flow beginning with the step where system +clocks are enabled. +Boot +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +210 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 210](pdf-image://page_210_img_1) + +## Page 211 + +Chapter 7 +Power Management +7.1 +Introduction +This chapter describes the various chip power modes and functionality of the individual +modules in these modes. +7.2 +Power modes +The power management controller (PMC) provides multiple power options to allow the +user to optimize power consumption for the level of functionality needed. +Depending on the stop requirements of the user application, a variety of stop modes are +available that provide state retention, partial power down or full power down of certain +logic and/or memory. I/O states are held in all modes of operation. The following table +compares the various power modes available. +For each run mode there is a corresponding wait and stop mode. Wait modes are similar +to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode. +The very low power run (VLPR) operating mode can drastically reduce runtime power +when the maximum bus frequency is not required to handle the application needs. +The three primary modes of operation are run, wait and stop. The WFI instruction +invokes both wait and stop modes for the chip. The primary modes are augmented in a +number of ways to provide lower power based on application needs. +Table 7-1. Chip power modes +Chip mode +Description +Core mode +Normal +recovery +method +Normal run +Allows maximum performance of chip. Default mode out of reset; on- +chip voltage regulator is on. +Run +- +Table continues on the next page... +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +211 +General Business Information + +![Image 1 from page 211](pdf-image://page_211_img_1) + +## Page 212 + +Table 7-1. Chip power modes (continued) +Chip mode +Description +Core mode +Normal +recovery +method +Normal Wait - +via WFI +Allows peripherals to function while the core is in sleep mode, reducing +power. NVIC remains sensitive to interrupts; peripherals continue to be +clocked. +Sleep +Interrupt +Normal Stop - +via WFI +Places chip in static state. Lowest power mode that retains all registers +while maintaining LVD protection. NVIC is disabled; AWIC is used to +wake up from interrupt; peripheral clocks are stopped. +Sleep Deep +Interrupt +VLPR (Very Low +Power Run) +On-chip voltage regulator is in a low power mode that supplies only +enough power to run the chip at a reduced frequency. Reduced +frequency Flash access mode (1 MHz); LVD off; internal oscillator +provides a low power 4 MHz source for the core, the bus and the +peripheral clocks. +Run +Interrupt +VLPW (Very +Low Power +Wait) -via WFI +Same as VLPR but with the core in sleep mode to further reduce +power; NVIC remains sensitive to interrupts (FCLK = ON). On-chip +voltage regulator is in a low power mode that supplies only enough +power to run the chip at a reduced frequency. +Sleep +Interrupt +VLPS (Very Low +Power Stop)-via +WFI +Places chip in static state with LVD operation off. Lowest power mode +with ADC and pin interrupts functional. Peripheral clocks are stopped, +but LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled +(FCLK = OFF); AWIC is used to wake up from interrupt. On-chip +voltage regulator is in a low power mode that supplies only enough +power to run the chip at a reduced frequency. All SRAM is operating +(content retained and I/O states held). +Sleep Deep +Interrupt +LLS (Low +Leakage Stop) +State retention power mode. Most peripherals are in state retention +mode (with clocks stopped), but LLWU, LPTimer, RTC, CMP, TSI, +DAC can be used. NVIC is disabled; LLWU is used to wake up. +NOTE: The LLWU interrupt must not be masked by the interrupt +controller to avoid a scenario where the system does not fully +exit stop mode on an LLS recovery. +All SRAM is operating (content retained and I/O states held). +Sleep Deep +Wakeup +Interrupt1 +VLLS3 (Very +Low Leakage +Stop3) +Most peripherals are disabled (with clocks stopped), but LLWU, +LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU +is used to wake up. +SRAM\_U and SRAM\_L remain powered on (content retained and I/O +states held). +Sleep Deep +Wakeup Reset2 +VLLS2 (Very +Low Leakage +Stop2) +Most peripherals are disabled (with clocks stopped), but LLWU, +LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU +is used to wake up. +SRAM\_L is powered off. A portion of SRAM\_U remains powered on +(content retained and I/O states held). +Sleep Deep +Wakeup Reset2 +VLLS1 (Very +Low Leakage +Stop1) +Most peripherals are disabled (with clocks stopped), but LLWU, +LPTimer, RTC, CMP, TSI, DAC can be used. NVIC is disabled; LLWU +is used to wake up. +All of SRAM\_U and SRAM\_L are powered off. The 32-byte system +register file and the 32-byte VBAT register file remain powered for +customer-critical data. +Sleep Deep +Wakeup Reset2 +Table continues on the next page... +Power modes +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +212 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 212](pdf-image://page_212_img_1) + +## Page 213 + +Table 7-1. Chip power modes (continued) +Chip mode +Description +Core mode +Normal +recovery +method +BAT (backup +battery only) +The chip is powered down except for the VBAT supply. The RTC and +the 32-byte VBAT register file for customer-critical data remain +powered. +Off +Power-up +Sequence +1. +Resumes normal run mode operation by executing the LLWU interrupt service routine. +2. +Follows the reset flow with the LLWU interrupt flag set for the NVIC. +7.3 +Entering and exiting power modes +The WFI instruction invokes wait and stop modes for the chip. The processor exits the +low-power mode via an interrupt. The Nested Vectored Interrupt Controller (NVIC) +describes interrupt operation and what peripherals can cause interrupts. +NOTE +The WFE instruction can have the side effect of entering a low- +power mode, but that is not its intended usage. See ARM +documentation for more on the WFE instruction. +Recovery from VLLSx is through the wake-up Reset event. The chip wake-ups from +VLLSx by means of reset, an enabled pin or enabled module. See the table "LLWU +inputs" in the LLWU configuration section for a list of the sources. +The wake-up flow from VLLSx is through reset. The wakeup bit in the SRS registers in +the RCM is set indicating that the chip is recovering from a low power mode. Code +execution begins; however, the I/O pins are held in their pre low power mode entry +states, and the system oscillator and MCG registers are reset (even if EREFSTEN had +been set before entering VLLSx). Software must clear this hold by writing a 1 to the +ACKISO bit in the Regulator Status and Control Register in the PMC module. +NOTE +To avoid unwanted transitions on the pins, software must re- +initialize the I/O pins to their pre-low-power mode entry states +before releasing the hold. +If the oscillator was configured to continue running during VLLSx modes, it must be re- +configured before the ACKISO bit is cleared. The oscillator configuration within the +MCG is cleared after VLLSx recovery and the oscillator will stop when ACKISO is +cleared unless the register is re-configured. +Chapter 7 Power Management +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +213 +General Business Information + +![Image 1 from page 213](pdf-image://page_213_img_1) + +## Page 214 + +7.4 +Power mode transitions +The following figure shows the power mode transitions. Any reset always brings the chip +back to the normal run state. In run, wait, and stop modes active power regulation is +enabled. The VLPx modes are limited in frequency, but offer a lower power operating +mode than normal modes. The LLS and VLLSx modes are the lowest power stop modes +based on amount of logic or memory that is required to be retained by the application. +Wait +Stop +Run +LLS +VLLS +3, 2, 1 +VLPS +VLPR +VLPW +Any reset +4 +6 +7 +3 +1 +2 +8 +10 +11 +9 +5 +Figure 7-1. Power mode state transition diagram +Power mode transitions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +214 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 214](pdf-image://page_214_img_1) + +## Page 215 + +7.5 +Power modes shutdown sequencing +When entering stop or other low-power modes, the clocks are shut off in an orderly +sequence to safely place the chip in the targeted low-power state. All low-power entry +sequences are initiated by the core executing an WFI instruction. The ARM core's +outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes: +• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP +• All other low power modes equate to: SLEEPING & SLEEPDEEP +When entering the non-wait modes, the chip performs the following sequence: +• Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately. +• Polls stop acknowledge indications from the non-core crossbar masters (DMA, +Ethernet), supporting peripherals (SPI, PIT, RNG) and the Flash Controller for +indications that System Clocks, Bus Clock and/or Flash Clock need to be left enabled +to complete a previously initiated operation, effectively stalling entry to the targeted +low power mode. When all acknowledges are detected, System Clock, Bus Clock +and Flash Clock are turned off at the same time. +• MCG and Mode Controller shut off clock sources and/or the internal supplies driven +from the on-chip regulator as defined for the targeted low power mode. +In wait modes, most of the system clocks are not affected by the low power mode entry. +The Core Clock to the ARM Cortex-M4 core is shut off. Some modules support stop-in- +wait functionality and have their clocks disabled under these configurations. +The debugger modules support a transition from stop, wait, VLPS, and VLPW back to a +halted state when the debugger is enabled. This transition is initiated by setting the Debug +Request bit in MDM-AP control register. As part of this transition, system clocking is re- +established and is equivalent to normal run/VLPR mode clocking configuration. +7.6 +Module Operation in Low Power Modes +The following table illustrates the functionality of each module while the chip is in each +of the low power modes. (Debug modules are discussed separately; see Debug in Low +Power Modes.) Number ratings (such as 2 MHz and 1 Mbps) represent the maximum +frequencies or maximum data rates per mode. Also, these terms are used: +• FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a +module does not have a limitation in its functionality, it is still listed as FF. +• static = Module register states and associated memories are retained. +Chapter 7 Power Management +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +215 +General Business Information + +![Image 1 from page 215](pdf-image://page_215_img_1) + +## Page 216 + +• powered = Memory is powered to retain contents. +• low power = Flash has a low power state that retains configuration registers to +support faster wakeup. +• OFF = Modules are powered off; module is in reset state upon wakeup. +• wakeup = Modules can serve as a wakeup source for the chip. +Table 7-2. Module operation in low power modes +Modules +Stop +VLPR +VLPW +VLPS +LLS +VLLSx +Core modules +NVIC +static +FF +FF +static +static +OFF +System modules +Mode Controller +FF +FF +FF +FF +FF +FF +LLWU1 +static +static +static +static +FF +FF +Regulator +ON +low power +low power +low power +low power +low power +LVD +ON +disabled +disabled +disabled +disabled +disabled +Brown-out +Detection +ON +ON +ON +ON +ON +ON +DMA +static +FF +FF +static +static +OFF +Watchdog +FF +FF +FF +FF +static +OFF +EWM +static +FF +static +static +static +OFF +Clocks +1kHz LPO +ON +ON +ON +ON +ON +ON +System +oscillator (OSC) +OSCERCLK +optional +OSCERCLK +max of 4MHz +crystal +OSCERCLK +max of 4MHz +crystal +OSCERCLK +max of 4MHz +crystal +limited to low +range/low power +limited to low +range/low power +MCG +static - +MCGIRCLK +optional; PLL +optionally on but +gated +4 MHz IRC +4 MHz IRC +static - no clock +output +static - no clock +output +OFF +Core clock +OFF +4 MHz max +OFF +OFF +OFF +OFF +System clock +OFF +4 MHz max +4 MHz max +OFF +OFF +OFF +Bus clock +OFF +4 MHz max +4 MHz max +OFF +OFF +OFF +Memory and memory interfaces +Flash +powered +1 MHz max +access - no pgm +low power +low power +OFF +OFF +Portion of +SRAM\_U2 +low power +low power +low power +low power +low power +low power in +VLLS3,2; +otherwise OFF +Remaining +SRAM\_U and all +of SRAM\_L +low power +low power +low power +low power +low power +low power in +VLLS3; +otherwise OFF +FlexMemory +low power +low power3 +low power +low power +low power +OFF +Register files4 +powered +powered +powered +powered +powered +powered +FlexBus +static +FF +FF +static +static +OFF +Table continues on the next page... +Module Operation in Low Power Modes +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +216 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 216](pdf-image://page_216_img_1) + +## Page 217 + +Table 7-2. Module operation in low power modes (continued) +Modules +Stop +VLPR +VLPW +VLPS +LLS +VLLSx +EzPort +disabled +disabled +disabled +disabled +disabled +disabled +Communication interfaces +USB FS/LS +static +static +static +static +static +OFF +USB DCD +static +FF +FF +static +static +OFF +USB Voltage +Regulator +optional +optional +optional +optional +optional +optional +Ethernet +wakeup +static +static +static +static +OFF +UART +static, wakeup +on edge +125 kbps +125 kbps +static, wakeup +on edge +static +OFF +SPI +static +1 Mbps +1 Mbps +static +static +OFF +I2C +static, address +match wakeup +100 kbps +100 kbps +static, address +match wakeup +static +OFF +CAN +wakeup +256 kbps +256 kbps +wakeup +static +OFF +I2S +FF with external +clock5 +FF +FF +FF with external +clock5 +static +OFF +SDHC +wakeup +FF +FF +wakeup +static +OFF +Security +CRC +static +FF +FF +static +static +OFF +RNG +static +FF +static +static +static +OFF +Timers +FTM +static +FF +FF +static +static +OFF +PIT +static +FF +FF +static +static +OFF +PDB +static +FF +FF +static +static +OFF +LPTMR +FF +FF +FF +FF +FF +FF +RTC - 32kHz +OSC4 +FF +FF +FF +FF +FF6 +FF6 +CMT +static +FF +FF +static +static +OFF +Analog +16-bit ADC +ADC internal +clock only +FF +FF +ADC internal +clock only +static +OFF +CMP7 +HS or LS level +compare +FF +FF +HS or LS level +compare +LS level +compare +LS level +compare +6-bit DAC +static +FF +FF +static +static +static +VREF +FF +FF +FF +FF +static +OFF +12-bit DAC +static +FF +FF +static +static +static +Human-machine interfaces +GPIO +wakeup +FF +FF +wakeup +static, pins +latched +OFF, pins +latched +TSI +wakeup +FF +FF +wakeup +wakeup8 +wakeup8 +1. +Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be +enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a +transition to occur to the LLWU. +2. +A 4 or 16KB portion of SRAM\_U block is left powered on in low power mode VLLS2. +Chapter 7 Power Management +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +217 +General Business Information + +![Image 1 from page 217](pdf-image://page_217_img_1) + +## Page 218 + +3. +FlexRAM enabled as EEPROM is not writable in VLPR and writes are ignored. Read accesses to FlexRAM as EEPROM +while in VLPR are allowed. There are no access restrictions for FlexRAM configured as traditional RAM. +4. +These components remain powered in BAT power mode. +5. +Use an externally generated bit clock or an externally generated audio master clock (including EXTAL). +6. +RTC\_CLKOUT is not available. +7. +CMP in stop or VLPS supports high speed or low speed external pin to pin or external pin to DAC compares. CMP in LLS +or VLLSx only supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled & filtered +modes of operation are not available while in stop, VLPS, LLS, or VLLSx modes. +8. +TSI wakeup from LLS and VLLSx modes is limited to a single selectable pin. +7.7 +Clock Gating +To conserve power, the clocks to most modules can be turned off using the SCGCx +registers in the SIM module. These bits are cleared after any reset, which disables the +clock to the corresponding module. Prior to initializing a module, set the corresponding +bit in the SCGCx register to enable the clock. Before turning off the clock, make sure to +disable the module. For more details, refer to the clock distribution and SIM chapters. +Clock Gating +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +218 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 218](pdf-image://page_218_img_1) + +## Page 219 + +Chapter 8 +Security +8.1 +Introduction +This device implements security based on the mode selected from the flash module. The +following sections provide an overview of flash security and details the effects of security +on non-flash modules. +8.2 +Flash Security +The flash module provides security information to the MCU based on the state held by +the FSEC[SEC] bits. The MCU, in turn, confirms the security request and limits access to +flash resources. During reset, the flash module initializes the FSEC register using data +read from the security byte of the flash configuration field. +NOTE +The security features apply only to external accesses: debug and +EzPort. CPU accesses to the flash are not affected by the status +of FSEC. +In the unsecured state all flash commands are available to the programming interfaces +(JTAG and EzPort), as well as user code execution of Flash Controller commands. When +the flash is secured (FSEC[SEC] = 00, 01, or 11), programmer interfaces are only +allowed to launch mass erase operations and have no access to memory locations. +Further information regarding the flash security options and enabling/disabling flash +security is available in the Flash Memory Module. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +219 +General Business Information + +![Image 1 from page 219](pdf-image://page_219_img_1) + +## Page 220 + +8.3 +Security Interactions with other Modules +The flash security settings are used by the SoC to determine what resources are available. +The following sections describe the interactions between modules and the flash security +settings or the impact that the flash security has on non-flash modules. +8.3.1 +Security interactions with FlexBus +When flash security is enabled, SIM\_SOPT2[FBSL] enables/disables off-chip accesses +through the FlexBus interface. The FBSL bitfield also has an option to allow opcode and +operand accesses or only operand accesses. +8.3.2 +Security Interactions with EzPort +When flash security is active the MCU can still boot in EzPort mode. The EzPort holds +the flash logic in NVM special mode and thus limits flash operation when flash security +is active. While in EzPort mode and security is active, flash bulk erase (BE) can still be +executed. The write FCCOB registers (WRFCCOB) command is limited to the mass +erase (Erase All Blocks) and verify all 1s (Read 1s All Blocks) commands. Read accesses +to internal memories via the EzPort are blocked when security is enabled. +The mass erase can be used to disable flash security, but all of the flash contents are lost +in the process. A mass erase via the EzPort is allowed even when some memory locations +are protected. +When mass erase has been disabled, mass erase via the EzPort is blocked and cannot be +defeated. +8.3.3 +Security Interactions with Debug +When flash security is active the JTAG port cannot access the memory resources of the +MCU. Boundary scan chain operations work, but debugging capabilities are disabled so +that the debug port cannot read flash contents. +Although most debug functions are disabled, the debugger can write to the Flash Mass +Erase in Progress bit in the MDM-AP Control register to trigger a mass erase (Erase All +Blocks) command. A mass erase via the debugger is allowed even when some memory +locations are protected. +Security Interactions with other Modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +220 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 220](pdf-image://page_220_img_1) + +## Page 221 + +When mass erase is disabled, mass erase via the debugger is blocked. +Chapter 8 Security +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +221 +General Business Information + +![Image 1 from page 221](pdf-image://page_221_img_1) + +## Page 222 + +Security Interactions with other Modules +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +222 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 222](pdf-image://page_222_img_1) + +## Page 223 + +Chapter 9 +Debug +9.1 +Introduction +This device's debug is based on the ARM coresight architecture and is configured in each +device to provide the maximum flexibility as allowed by the restrictions of the pinout and +other available resources. +Four debug interfaces are supported: +• IEEE 1149.1 JTAG +• IEEE 1149.7 JTAG (cJTAG) +• Serial Wire Debug (SWD) +• ARM Real-Time Trace Interface +The basic Cortex-M4 debug architecture is very flexible. The following diagram shows +the topology of the core debug architecture and its components. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +223 +General Business Information + +![Image 1 from page 223](pdf-image://page_223_img_1) + +## Page 224 + +Private Peripheral Bus +(internal) +Trigger +ITM +TPIU +Core +FPB +AHB-AP +NVIC +SWJ-DP +Bus +Matrix +APB +i/f +Trace port +(serial wire +or multi-pin) +Cortex-M4 +SW/ +JTAG +Debug +Sleep +Interrupts +INTNMI +SLEEPING +SLEEPDEEP +INTISR[239:0] +AWIC +DWT +ROM +Table +ETB +ETM +Instr. +Data +MCM +MMCAU +I-code bus +D-code bus +System bus +Code bus +MDM-AP +Figure 9-1. Cortex-M4 Debug Topology +The following table presents a brief description of each one of the debug components. +Table 9-1. Debug Components Description +Module +Description +SWJ-DP+ cJTAG +Modified Debug Port with support for SWD, JTAG, cJTAG +AHB-AP +AHB Master Interface from JTAG to debug module and SOC +system memory maps +MDM-AP +Provides centralized control and status registers for an +external debugger to control the device. +ROM Table +Identifies which debug IP is available. +Core Debug +Singlestep, Register Access, Run, Core Status +CoreSight Trace Funnel (not shown in figure) +The CSTF combines multiple trace streams onto a single ATB +bus. +CoreSight Trace Replicator (not shown in figure) +The ATB replicator enables two trace sinks to be wired +together and operate from the same incoming trace stream. +ETM (Embedded Trace Macrocell) +ETMv3.5 Architecture +CoreSight ETB (Embedded Trace Buffer) +Memory mapped buffer used to store trace data. +ITM +S/W Instrumentation Messaging + Simple Data Trace +Messaging + Watchpoint Messaging +Table continues on the next page... +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +224 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 224](pdf-image://page_224_img_1) + +## Page 225 + +Table 9-1. Debug Components Description (continued) +Module +Description +DWT (Data and Address Watchpoints) +4 data and address watchpoints (configurable for less, but 4 +seems to be accepted) +FPB (Flash Patch and Breakpoints) +The FPB implements hardware breakpoints and patches code +and data from code space to system space. +The FPB unit contains two literal comparators for matching +against literal loads from Code space, and remapping to a +corresponding area in System space. +The FBP also contains six instruction comparators for +matching against instruction fetches from Code space, and +remapping to a corresponding area in System space. +Alternatively, the six instruction comparators can individually +configure the comparators to return a Breakpoint Instruction +(BKPT) to the processor core on a match, so providing +hardware breakpoint capability. +TPIU (Trace Port Inteface Unit) +Synchronous Mode (5-pin) = TRACE\_D[3:0] + +TRACE\_CLKOUT +Synchronous Mode (3-pin) = TRACE\_D[1:0] + +TRACE\_CLKOUT +Asynchronous Mode (1-pin) = TRACE\_SWO (available on +JTAG\_TDO) +MCM (Miscellaneous Control Module) +The MCM provides miscellaneous control functions including +control of the ETB and trace path switching. +9.1.1 +References +For more information on ARM debug components, see these documents: +• ARMv7-M Architecture Reference Manual +• ARM Debug Interface v5.1 +• ARM CoreSight Architecture Specification +• ARM ETM Architecture Specification v3.5 +9.2 +The Debug Port +The configuration of the cJTAG module, JTAG controller, and debug port is illustrated in +the following figure: +Chapter 9 Debug +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +225 +General Business Information + +![Image 1 from page 225](pdf-image://page_225_img_1) + +## Page 226 + +CJTAG +DAP Bus +TDO +TRACESWO +TDO +TDI +TCK +TDI +nSYS\_TRST +nSYS\_TDO +nSYS\_TDI +nSYS\_TCK +nSYS\_TMS +nTRST +TCK +TMS\_OUT +TMS\_IN +TMS\_OUT\_OE +TMS +TDO +TDI +SWCLKTCK +SWDITMS +SWDO +SWDOEN +SWD/JTAG +SELECT +SWCLKTCK +SWDITMS +JTAGSEL +SWDSEL +4’b1111 or 4’b0000 +TDI TDO PEN +JTAGNSW +JTAGC +TDO +TDI +nTRST +TCK +TMS +jtag\_updateinstr[3:0] +4’b1111 or 4’b1110 +JTAGir[3:0] +IR==BYPASS or IDCODE +IR==BYPASS or IDCODE +A +A +(1’b0 = 2-pin cJTAG) +(1’b1 = 4-pin JTAG) +To Test +Resources +1’b1 +MDM-AP +AHB-AP +Figure 9-2. Modified Debug Port +The debug port comes out of reset in standard JTAG mode and is switched into either +cJTAG or SWD mode by the following sequences. Once the mode has been changed, +unused debug pins can be reassigned to any of their alternative muxed functions. +9.2.1 +JTAG-to-SWD change sequence +1. Send more than 50 TCK cycles with TMS (SWDIO) =1 +2. Send the 16-bit sequence on TMS (SWDIO) = 0111\_1001\_1110\_0111 (MSB +transmitted first) +3. Send more than 50 TCK cycles with TMS (SWDIO) =1 +NOTE +See the ARM documentation for the CoreSight DAP Lite for +restrictions. +9.2.2 +JTAG-to-cJTAG change sequence +1. Reset the debug port +The Debug Port +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +226 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 226](pdf-image://page_226_img_1) + +![Image 2 from page 226](pdf-image://page_226_img_2) + +![Image 3 from page 226](pdf-image://page_226_img_3) + +![Image 4 from page 226](pdf-image://page_226_img_4) + +![Image 5 from page 226](pdf-image://page_226_img_5) + +![Image 6 from page 226](pdf-image://page_226_img_6) + +## Page 227 + +2. Set the control level to 2 via zero-bit scans +3. Execute the Store Format (STFMT) command (00011) to set the scan format register +to 1149.7 scan format +9.3 +Debug Port Pin Descriptions +The debug port pins default after POR to their JTAG functionality with the exception of +JTAG\_TRST\_b and can be later reassigned to their alternate functionalities. In cJTAG +and SWD modes JTAG\_TDI and JTAG\_TRST\_b can be configured to alternate GPIO +functions. +Table 9-2. Debug port pins +Pin Name +JTAG Debug Port +cJTAG Debug Port +SWD Debug Port +Internal Pull- +up\Down +Type +Description +Type +Description +Type +Description +JTAG\_TMS/ +SWD\_DIO +I/O +JTAG Test +Mode +Selection +I/O +cJTAG Data +I/O +Serial Wire +Data +Pull-up +JTAG\_TCLK/ +SWD\_CLK +I +JTAG Test +Clock +I +cJTAG Clock +I +Serial Wire +Clock +Pull-down +JTAG\_TDI +I +JTAG Test +Data Input +- +- +- +- +Pull-up +JTAG\_TDO/ +TRACE\_SWO +O +JTAG Test +Data Output +O +Trace output +over a single +pin +O +Trace output +over a single +pin +N/C +JTAG\_TRST\_ +b +I +JTAG Reset +I +cJTAG Reset +- +- +Pull-up +9.4 +System TAP connection +The system JTAG controller is connected in parallel to the ARM TAP controller. The +system JTAG controller IR codes overlay the ARM JTAG controller IR codes without +conflict. Refer to the IR codes table for a list of the available IR codes. The output of the +TAPs (TDO) are muxed based on the IR code which is selected. This design is fully +JTAG compliant and appears to the JTAG chain as a single TAP. At power on reset, +ARM's IDCODE (IR=4'b1110) is selected. +Chapter 9 Debug +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +227 +General Business Information + +![Image 1 from page 227](pdf-image://page_227_img_1) + +## Page 228 + +9.4.1 +IR Codes +Table 9-3. JTAG Instructions +Instruction +Code[3:0] +Instruction Summary +IDCODE +0000 +Selects device identification register for shift +SAMPLE/PRELOAD +0010 +Selects boundary scan register for shifting, sampling, and +preloading without disturbing functional operation +SAMPLE +0011 +Selects boundary scan register for shifting and sampling +without disturbing functional operation +EXTEST +0100 +Selects boundary scan register while applying preloaded +values to output pins and asserting functional reset +HIGHZ +1001 +Selects bypass register while three-stating all output pins and +asserting functional reset +CLAMP +1100 +Selects bypass register while applying preloaded values to +output pins and asserting functional reset +EZPORT +1101 +Enables the EZPORT function for the SoC and asserts +functional reset. +ARM\_IDCODE +1110 +ARM JTAG-DP Instruction +BYPASS +1111 +Selects bypass register for data operations +Factory debug reserved +0101, 0110, 0111 +Intended for factory debug only +ARM JTAG-DP Reserved +1000, 1010, 1011, 1110 These instructions will go the ARM JTAG-DP controller. +Please look at ARM JTAG-DP documentation for more +information on these instructions. +Reserved 1 +All other opcodes +Decoded to select bypass register +1. +The manufacturer reserves the right to change the decoding of reserved instruction codes in the future +9.5 +JTAG status and control registers +Through the ARM Debug Access Port (DAP), the debugger has access to the status and +control elements, implemented as registers on the DAP bus as shown in the following +figure. These registers provide additional control and status for low power mode recovery +and typical run-control scenarios. The status register bits also provide a means for the +debugger to get updated status of the core without having to initiate a bus transaction +across the crossbar switch, thus remaining less intrusive during a debug session. +It is important to note that these DAP control and status registers are not memory mapped +within the system memory map and are only accessible via the Debug Access Port (DAP) +using JTAG, cJTAG, or SWD. The MDM-AP is accessible as Debug Access Port 1 with +the available registers shown in the table below. +Table 9-4. MDM-AP Register Summary +Address +Register +Description +Table continues on the next page... +JTAG status and control registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +228 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 228](pdf-image://page_228_img_1) + +## Page 229 + +Table 9-4. MDM-AP Register Summary (continued) +0x0100\_0000 +Status +See MDM-AP Status Register +0x0100\_0004 +Control +See MDM-AP Control Register +0x0100\_00FC +ID +Read-only identification register that +always reads as 0x001C\_0000 +SWJ-DP +SELECT[31:24] (APSEL) selects the AP +SELECT[7:4] (APBANKSEL) selects the bank +A[3:2] from the APACC selects the register +within the bank +AHB Access Port +(AHB-AP) +MDM-AP +Status +0x00 +Control +0x01 +IDR +0x3F +AHB-AP +SELECT[31:24] = 0x00 selects the AHB-AP +See ARM documentation for further details +MDM-AP +SELECT[31:24] = 0x01 selects the MDM-AP +SELECT[7:4] = 0x0 selects the bank with Status and Ctrl +A[3:2] = 2’b00 selects the Status Register +A[3:2] = 2’b01 selects the Control Register +SELECT[7:4] = 0xF selects the bank with IDR +A[3:2] = 2’b11 selects the IDR Register +(IDR register reads 0x001C\_0000) +Bus Matrix +See Control and Status Register +Descriptions +Debug Port +Internal Bus +Access Port +Data[31:0] +A[7:4] +A[3:2] RnW +APSEL +Decode +Debug Port ID Register (DPIDR) +Control/Status (CTRL/STAT) +AP Select (SELECT) +Read Buffer (REBUFF) +DP Registers +0x00 +0x04 +0x08 +0x0C +Data[31:0] +A[3:2] RnW +DPACC +Data[31:0] +A[3:2] RnW +APACC +Debug Port +(DP) +Generic +See the ARM Debug Interface v5p1 Supplement. +Figure 9-3. MDM AP Addressing +Chapter 9 Debug +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +229 +General Business Information + +![Image 1 from page 229](pdf-image://page_229_img_1) + +## Page 230 + +9.5.1 +MDM-AP Control Register +Table 9-5. MDM-AP Control register assignments +Bit +Name +Secure1 +Description +0 +Flash Mass Erase in Progress +Y +Set to cause mass erase. Cleared by hardware after mass erase +operation completes. +When mass erase is disabled (via MEEN and SEC settings), the erase +request does not occur and the Flash Mass Erase in Progress bit +continues to assert until the next system reset. +1 +Debug Disable +N +Set to disable debug. Clear to allow debug operation. When set it +overrides the C\_DEBUGEN bit within the DHCSR and force disables +Debug logic. +2 +Debug Request +N +Set to force the Core to halt. +If the Core is in a stop or wait mode, this bit can be used to wakeup the +core and transition to a halted state. +3 +System Reset Request +N +Set to force a system reset. The system remains held in reset until this +bit is cleared. +4 +Core Hold Reset +N +Configuration bit to control Core operation at the end of system reset +sequencing. +0 Normal operation - release the Core from reset along with the rest of +the system at the end of system reset sequencing. +1 Suspend operation - hold the Core in reset at the end of reset +sequencing. Once the system enters this suspended state, clearing +this control bit immediately releases the Core from reset and CPU +operation begins. +5 +VLLSx Debug Request +(VLLDBGREQ) +N +Set to configure the system to be held in reset after the next recovery +from a VLLSx mode. This bit is ignored on a VLLS wakeup via the +Reset pin. During a VLLS wakeup via the Reset pin, the system can be +held in reset by holding the reset pin asserted allowing the debugger to +re-initialize the debug modules. +This bit holds the system in reset when VLLSx modes are exited to +allow the debugger time to re-initialize debug IP before the debug +session continues. +The Mode Controller captures this bit logic on entry to VLLSx modes. +Upon exit from VLLSx modes, the Mode Controller will hold the system +in reset until VLLDBGACK is asserted. +The VLLDBGREQ bit clears automatically due to the POR reset +generated as part of the VLLSx recovery. +6 +VLLSx Debug Acknowledge +(VLLDBGACK) +N +Set to release a system being held in reset following a VLLSx recovery +This bit is used by the debugger to release the system reset when it is +being held on VLLSx mode exit. The debugger re-initializes all debug +IP and then assert this control bit to allow the Mode Controller to +release the system from reset and allow CPU operation to begin. +The VLLDBGACK bit is cleared by the debugger or can be left set +because it clears automatically due to the POR reset generated as part +of the next VLLSx recovery. +Table continues on the next page... +JTAG status and control registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +230 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 230](pdf-image://page_230_img_1) + +## Page 231 + +Table 9-5. MDM-AP Control register assignments (continued) +Bit +Name +Secure1 +Description +7 +LLS, VLLSx Status Acknowledge +N +Set this bit to acknowledge the DAP LLS and VLLS Status bits have +been read. This acknowledge automatically clears the status bits. +This bit is used by the debugger to clear the sticky LLS and VLLSx +mode entry status bits. This bit is asserted and cleared by the +debugger. +8 +Timestamp Disable +N +Set this bit to disable the 48-bit global trace timestamp counter during +debug halt mode when the core is halted. +0 The timestamp counter continues to count assuming trace is enabled +and the ETM is enabled. (default) +1 The timestamp counter freezes when the core has halted (debug halt +mode). +9 – +31 +Reserved for future use +N +1. +Command available in secure mode +9.5.2 +MDM-AP Status Register +Table 9-6. MDM-AP Status register assignments +Bit +Name +Description +0 +Flash Mass Erase Acknowledge +The Flash Mass Erase Acknowledge bit is cleared after any system reset. +The bit is also cleared at launch of a mass erase command due to write of +Flash Mass Erase in Progress bit in MDM AP Control Register. The Flash +Mass Erase Acknowledge is set after Flash control logic has started the +mass erase operation. +When mass erase is disabled (via MEEN and SEC settings), an erase +request due to seting of Flash Mass Erase in Progress bit is not +acknowledged. +1 +Flash Ready +Indicate Flash has been initialized and debugger can be configured even if +system is continuing to be held in reset via the debugger. +2 +System Security +Indicates the security state. When secure, the debugger does not have +access to the system bus or any memory mapped peripherals. This bit +indicates when the part is locked and no system bus access is possible. +3 +System Reset +Indicates the system reset state. +0 System is in reset +1 System is not in reset +4 +Reserved +5 +Mass Erase Enable +Indicates if the MCU can be mass erased or not +0 Mass erase is disabled +1 Mass erase is enabled +Table continues on the next page... +Chapter 9 Debug +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +231 +General Business Information + +![Image 1 from page 231](pdf-image://page_231_img_1) + +## Page 232 + +Table 9-6. MDM-AP Status register assignments (continued) +Bit +Name +Description +6 +Backdoor Access Key Enable +Indicates if the MCU has the backdoor access key enabled. +0 Disabled +1 Enabled +7 +LP Enabled +Decode of LPLLSM control bits to indicate that VLPS, LLS, or VLLSx are +the selected power mode the next time the ARM Core enters Deep Sleep. +0 Low Power Stop Mode is not enabled +1 Low Power Stop Mode is enabled +Usage intended for debug operation in which Run to VLPS is attempted. +Per debug definition, the system actually enters the Stop state. A +debugger should interpret deep sleep indication (with SLEEPDEEP and +SLEEPING asserted), in conjuntion with this bit asserted as the debugger- +VLPS status indication. +8 +Very Low Power Mode +Indicates current power mode is VLPx. This bit is not ‘sticky’ and should +always represent whether VLPx is enabled or not. +This bit is used to throttle JTAG TCK frequency up/down. +9 +LLS Mode Exit +This bit indicates an exit from LLS mode has occurred. The debugger will +lose communication while the system is in LLS (including access to this +register). Once communication is reestablished, this bit indicates that the +system had been in LLS. Since the debug modules held their state during +LLS, they do not need to be reconfigured. +This bit is set during the LLS recovery sequence. The LLS Mode Exit bit is +held until the debugger has had a chance to recognize that LLS was exited +and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in +MDM AP Control register. +10 +VLLSx Modes Exit +This bit indicates an exit from VLLSx mode has occurred. The debugger +will lose communication while the system is in VLLSx (including access to +this register). Once communication is reestablished, this bit indicates that +the system had been in VLLSx. Since the debug modules lose their state +during VLLSx modes, they need to be reconfigured. +This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit +bit is held until the debugger has had a chance to recognize that a VLLS +mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status +Acknowledge bit in MDM AP Control register. +11 – 15 +Reserved for future use +Always read 0. +16 +Core Halted +Indicates the Core has entered debug halt mode +17 +Core SLEEPDEEP +Indicates the Core has entered a low power mode +SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode. +SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode. +18 +Core SLEEPING +19 – 31 +Reserved for future use +Always read 0. +9.6 +Debug Resets +The debug system receives the following sources of reset: +Debug Resets +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +232 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 232](pdf-image://page_232_img_1) + +## Page 233 + +• JTAG\_TRST\_b from an external signal. This signal is optional and may not be +available in all packages. +• Debug reset (CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register) in the +TCLK domain that allows the debugger to reset the debug logic. +• TRST asserted via the cJTAG escape command. +• System POR reset +Conversely the debug system is capable of generating system reset using the following +mechanism: +• A system reset in the DAP control register which allows the debugger to hold the +system in reset. +• SYSRESETREQ bit in the NVIC application interrupt and reset control register +• A system reset in the DAP control register which allows the debugger to hold the +Core in reset. +9.7 +AHB-AP +AHB-AP provides the debugger access to all memory and registers in the system, +including processor registers through the NVIC. System access is independent of the +processor status. AHB-AP does not do back-to-back transactions on the bus, so all +transactions are non-sequential. AHB-AP can perform unaligned and bit-band +transactions. AHB-AP transactions bypass the FPB, so the FPB cannot remap AHB-AP +transactions. SWJ/SW-DP-initiated transaction aborts drive an AHB-AP-supported +sideband signal called HABORT. This signal is driven into the Bus Matrix, which resets +the Bus Matrix state, so that AHB-AP can access the Private Peripheral Bus for last ditch +debugging such as read/stop/reset the core. AHB-AP transactions are little endian. +The MPU includes default settings and protections for the Region Descriptor 0 (RGD0) +such that the Debugger always has access to the entire address space and those rights +cannot be changed by the core or any other bus master. +For a short period at the start of a system reset event the system security status is being +determined and debugger access to all AHB-AP transactions is blocked. The MDM-AP +Status register is accessible and can be monitored to determine when this initial period is +completed. After this initial period, if system reset is held via assertion of the RESET pin, +the debugger has access via the bus matrix to the private peripheral bus to configure the +debug IP even while system reset is asserted. While in system reset, access to other +memory and register resources, accessed over the Crossbar Switch, is blocked. +Chapter 9 Debug +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +233 +General Business Information + +![Image 1 from page 233](pdf-image://page_233_img_1) + +## Page 234 + +9.8 +ITM +The ITM is an application-driven trace source that supports printf style debugging to +trace Operating System (OS) and application events, and emits diagnostic system +information. The ITM emits trace information as packets. There are four sources that can +generate packets. If multiple sources generate packets at the same time, the ITM +arbitrates the order in which packets are output. The four sources in decreasing order of +priority are: +1. Software trace -- Software can write directly to ITM stimulus registers. This emits +packets. +2. Hardware trace -- The DWT generates these packets, and the ITM emits them. +3. Time stamping -- Timestamps are emitted relative to packets. The ITM contains a +21-bit counter to generate the timestamp. The Cortex-M4 clock or the bitclock rate of +the Serial Wire Viewer (SWV) output clocks the counter. +4. Global system timestamping. Timestamps can optionally be generated using a +system-wide 48-bit count value. The same count value can be used to insert +timestamps in the ETM trace stream, allowing coarse-grain correlation. +9.9 +Core Trace Connectivity +ETM +Private Peripheral Bus +ATB +UPSIZER +ATB +(8-bit) +ATB +(8-bit) +ATB +(32-bit) +ETM +ETB +TRACE PORT +( +) +ATB +(8-bit) +ATB +FUNNEL +ATB +REPLICATOR +ATB +(32-bit) +ATB +UPSIZER +ATB +(32-bit) +ATB +(8-bit) +TRACE PORT +TRACECLKIN +TRACECLK +TRACEDATA[3:0] +TRACESWO +TPIU +ITM +DWT +ATB +(8-bit) +ATB +REPLICATOR +ATB +(8-bit) +TRACECLKIN +CORE CLOCK +NMI Interrupt +MCM Alert Interrupt +Debug Halt Request +MCM +Figure 9-4. Core Trace Connectivity +ITM +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +234 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 234](pdf-image://page_234_img_1) + +## Page 235 + +The ETM and ITM can route its data to the ETB or the TPIU. (See the MCM +(Miscellaneous Control Module) for controlling the routing to the TPIU.) This +configuration enables the use of trace with low cost tools while maintaining the +compatibility with trace probes. The arbitration between the ETM and ITM is performed +inside the TPIU. +The ETB can not be configured with an interface smaller than 32 bits, making it +necessary to add an ATB upsizer to make it compatible with the ETM operating with an +8-bit interface. The speed of the ETB 32 bit interface and its associated RAM is expected +to be one quarter of the ETB clock. +The following combinations paths are supported: +1. ETM -> ETB +2. ETM -> TPIU(4 pin or 2 pin parallel) +3. ITM->ETB +4. ITM->TPIU(1 pin SWO, 2 pin or 4 pin parallel) +5. ETM & ITM -> ETB +6. ETM & ITM -> TPIU +7. ETM -> ETB & ITM -> TPIU +The following combination paths are NOT supported +1. ETM -> TPIU & ETB +2. ITM -> TPIU & ETB +9.10 +Embedded Trace Macrocell v3.5 (ETM) +The Cortex-M4 Embedded Trace Macrocell (ETM-M4) is a debug component that +enables a debugger to reconstruct program execution. The CoreSight ETM-M4 supports +only instruction trace. You can use it either with the Cortex-M4 Trace Port Interface Unit +(M4-TPIU), or with the CoreSight ETB. +The main features of an ETM are: +• tracing of 16-bit and 32-bit Thumb instructions +• four EmbeddedICE watchpoint inputs +• a Trace Start/Stop block with EmbeddedICE inputs +• one reduced function counter +• two external inputs +• a 24-byte FIFO queue +• global timestamping +Chapter 9 Debug +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +235 +General Business Information + +![Image 1 from page 235](pdf-image://page_235_img_1) + +## Page 236 + +9.11 +Coresight Embedded Trace Buffer (ETB) +The ETB provides on-chip storage of trace data using 32-bit RAM. The ETB accepts +trace data from any CoreSight-compliant component trace source with an ATB master +port, such as a trace source or a trace funnel. It is included in this device to remove +dependencies from the trace pin pad speed, and enable low cost trace solutions. The +TraceRAM size is 2 KB. +APB +i/f +ATB slave port +ATB +i/f +TraceRAM +Control +Trace RAM +interface +TRIGIN +Register Bank +Formatter +APB +(from ETM Trigger out) +Figure 9-5. ETB Block Diagram +The ETB contains the following blocks: +• Formatter -- Inserts source ID signals into the data packet stream so that trace data +can be re-associated with its trace source after the data is read back out of the ETB. +• Control -- Control registers for trace capture and flushing. +• APB interface -- Read, write, and data pointers provide access to ETB registers. In +addition, the APB interface supports wait states through the use of a PREADYDBG +signal output by the ETB. The APB interface is synchronous to the ATB domain. +• Register bank -- Contains the management, control, and status registers for triggers, +flushing behavior, and external control. +• Trace RAM interface -- Controls reads and writes to the Trace RAM. +9.11.1 +Performance Profiling with the ETB +To create a performance profile (e.g. gprof) for the target application, a means to collect +trace over a long period of time is needed. The ETB buffer is too small to capture a +meaningful profile in just one take. What is needed is to collect and concatenate data +from the ETB buffer for multiple sequential runs. Using the ETB packet counter +(described in Miscellaneous Control Module (MCM)), the trace analysis tool can capture +Coresight Embedded Trace Buffer (ETB) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +236 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 236](pdf-image://page_236_img_1) + +## Page 237 + +multiple sequential runs by executing code until the ETB is almost full, and halting or +executing an interrupt handler to allow the buffer to be emptied, and then continuing +executing code. The target halts or executes an interrupt handler when the buffer is +almost full to empty the data and then the debugger runs the target again. +9.11.2 +ETB Counter Control +The ETB packet counter is controlled by the ETB counter control register, ETB reload +register, and ETB counter value register implemented in the Miscellaneous Control +Module (MCM) accessible via the Private Peripheral Bus. Via the ETB counter control +register the ETB control logic can be configured to cause an MCM Alert Interrupt, an +NMI Interrupt, or cause a Debug halt when the down counter reaches 0. Other features of +the ETB control logic include: +• Down counter to count as many as 512 x 32-bit packets. +• Reload request transfers reload value to counter. +• ATB valid and ready signals used to form counter decrement. +• The counter disarms itself when the count reaches 0. +9.12 +TPIU +The TPIU acts as a bridge between the on-chip trace data from the Embedded Trace +Macrocell (ETM) and the Instrumentation Trace Macrocell (ITM), with separate IDs, to a +data stream, encapsulating IDs where required, that is then captured by a Trace Port +Analyzer (TPA). The TPIU is specially designed for low-cost debug. +9.13 +DWT +The DWT is a unit that performs the following debug functionality: +• It contains four comparators that you can configure as a hardware watchpoint, an +ETM trigger, a PC sampler event trigger, or a data address sampler event trigger. The +first comparator, DWT\_COMP0, can also compare against the clock cycle counter, +CYCCNT. The second comparator, DWT\_COMP1, can also be used as a data +comparator. +• The DWT contains counters for: +• Clock cycles (CYCCNT) +• Folded instructions +• Load store unit (LSU) operations +Chapter 9 Debug +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +237 +General Business Information + +![Image 1 from page 237](pdf-image://page_237_img_1) + +## Page 238 + +• Sleep cycles +• CPI (all instruction cycles except for the first cycle) +• Interrupt overhead +NOTE +An event is emitted each time a counter overflows. +• The DWT can be configured to emit PC samples at defined intervals, and to emit +interrupt event information. +9.14 +Debug in Low Power Modes +In low power modes in which the debug modules are kept static or powered off, the +debugger cannot gather any debug data for the duration of the low power mode. In the +case that the debugger is held static, the debug port returns to full functionality as soon as +the low power mode exits and the system returns to a state with active debug. In the case +that the debugger logic is powered off, the debugger is reset on recovery and must be +reconfigured once the low power mode is exited. +Power mode entry logic monitors Debug Power Up and System Power Up signals from +the debug port as indications that a debugger is active. These signals can be changed in +RUN, VLPR, WAIT and VLPW. If the debug signal is active and the system attempts to +enter stop or VLPS, FCLK continues to run to support core register access. In these +modes in which FCLK is left active the debug modules have access to core registers but +not to system memory resources accessed via the crossbar. +With debug enabled, transitions from Run directly to VLPS are not allowed and result in +the system entering Stop mode instead. Status bits within the MDM-AP Status register +can be evaluated to determine this pseudo-VLPS state. Note with the debug enabled, +transitions from Run--> VLPR --> VLPS are still possible but also result in the system +entering Stop mode instead. +In VLLS mode all debug modules are powered off and reset at wakeup. In LLS mode, the +debug modules retain their state but no debug activity is possible. +NOTE +When using cJTAG and entering LLS mode, the cJTAG +controller must be reset on exit from LLS mode. +Going into a VLLSx mode causes all the debug controls and settings to be reset. To give +time to the debugger to sync up with the HW, the MDM-AP Control register can be +configured hold the system in reset on recovery so that the debugger can regain control +and reconfigure debug logic prior to the system exiting reset and resuming operation. +Debug in Low Power Modes +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +238 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 238](pdf-image://page_238_img_1) + +## Page 239 + +9.14.1 +Debug Module State in Low Power Modes +The following table shows the state of the debug modules in low power modes. These +terms are used: +• FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a +module does not have a limitation in its functionality, it is still listed as FF. +• static = Module register states and associated memories are retained. +• OFF = Modules are powered off; module is in reset state upon wakeup. +Table 9-7. Debug Module State in Low Power Modes +Module +STOP +VLPR +VLPW +VLPS +LLS +VLLSx +Debug Port +FF +FF +FF +OFF +static +OFF +AHB-AP +FF +FF +FF +OFF +static +OFF +ITM +FF +FF +FF +OFF +static +OFF +ETM +FF +FF +FF +OFF +static +OFF +ETB +FF +FF +FF +OFF +static +OFF +TPIU +FF +FF +FF +OFF +static +OFF +DWT +FF +FF +FF +OFF +static +OFF +9.15 +Debug & Security +When security is enabled (FSEC[SEC] != 10), the debug port capabilities are limited in +order to prevent exploitation of secure data. In the secure state the debugger still has +access to the MDM-AP Status Register and can determine the current security state of the +device. In the case of a secure device, the debugger also has the capability of performing +a mass erase operation via writes to the MDM-AP Control Register. In the case of a +secure device that has mass erase disabled (FSEC[MEEN] = 10), attempts to mass erase +via the debug interface are blocked. +Chapter 9 Debug +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +239 +General Business Information + +![Image 1 from page 239](pdf-image://page_239_img_1) + +## Page 240 + +Debug & Security +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +240 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 240](pdf-image://page_240_img_1) + +## Page 241 + +Chapter 10 +Signal Multiplexing and Signal Descriptions +10.1 +Introduction +To optimize functionality in small packages, pins have several functions available via +signal multiplexing. This chapter illustrates which of this device's signals are multiplexed +on which external pin. +The Port Control block controls which signal is present on the external pin. Reference +that chapter to find which register controls the operation of a specific pin. +10.2 +Signal Multiplexing Integration +This section summarizes how the module is integrated into the device. For a +comprehensive description of the module itself, see the module’s dedicated chapter. +Register +access +Signal Multiplexing/ +Port Control +Transfers +Module +Peripheral bus +controller 1 +Module +Module +External Pins +Transfers +Figure 10-1. Signal multiplexing integration +Table 10-1. Reference links to related information +Topic +Related module +Reference +Full description +Port control +Port control +System memory map +System memory map +Table continues on the next page... +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +241 +General Business Information + +![Image 1 from page 241](pdf-image://page_241_img_1) + +## Page 242 + +Table 10-1. Reference links to related information (continued) +Topic +Related module +Reference +Clocking +Clock Distribution +Register access +Peripheral bus +controller +Peripheral bridge +10.2.1 +Port control and interrupt module features +• Five 32-pin ports +NOTE +Not all pins are available on the device. See the following +section for details. +• Each 32-pin port is assigned one interrupt. +• The digital filter option has two clock source options: bus clock and 1-kHz LPO. The +1-kHz LPO option gives users this feature in low power modes. +• The digital filter is configurable from 1 to 32 clock cycles when enabled. +10.2.2 +PCRn reset values for port A +PCRn bit reset values for port A are 1 for the following bits: +• For PCR0: bits 1, 6, 8, 9, and 10. +• For PCR1 to PCR4: bits 0, 1, 6, 8, 9, and 10. +• For PCR5 : bits 0, 1, and 6. +All other PCRn bit reset values for port A are 0. +10.2.3 +Clock gating +The clock to the port control module can be gated on and off using the SCGC5[PORTx] +bits in the SIM module. These bits are cleared after any reset, which disables the clock to +the corresponding module to conserve power. Prior to initializing the corresponding +module, set SCGC5[PORTx] in the SIM module to enable the clock. Before turning off +the clock, make sure to disable the module. For more details, refer to the clock +distribution chapter. +Signal Multiplexing Integration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +242 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 242](pdf-image://page_242_img_1) + +## Page 243 + +10.2.4 +Signal multiplexing constraints +1. A given peripheral function must be assigned to a maximum of one package pin. Do +not program the same function to more than one pin. +2. To ensure the best signal timing for a given peripheral's interface, choose the pins in +closest proximity to each other. +10.3 +Pinout +10.3.1 +K60 Signal Multiplexing and Pin Assignments +The following table shows the signals available on each pin and the locations of these +pins on the devices supported by this document. The Port Control Module is responsible +for selecting which ALT functionality is available on each pin. +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +— +L5 +RTC\_ +WAKEUP\_B +RTC\_ +WAKEUP\_B +RTC\_ +WAKEUP\_B +— +M5 +NC +NC +NC +— +A10 +NC +NC +NC +— +B10 +NC +NC +NC +— +C10 +NC +NC +NC +1 +D3 +PTE0 +ADC1\_SE4a +ADC1\_SE4a +PTE0 +SPI1\_PCS1 +UART1\_TX +SDHC0\_D1 +I2C1\_SDA +RTC\_CLKOUT +2 +D2 +PTE1/ +LLWU\_P0 +ADC1\_SE5a +ADC1\_SE5a +PTE1/ +LLWU\_P0 +SPI1\_SOUT +UART1\_RX +SDHC0\_D0 +I2C1\_SCL +SPI1\_SIN +3 +D1 +PTE2/ +LLWU\_P1 +ADC1\_SE6a +ADC1\_SE6a +PTE2/ +LLWU\_P1 +SPI1\_SCK +UART1\_CTS\_ +b +SDHC0\_DCLK +4 +E4 +PTE3 +ADC1\_SE7a +ADC1\_SE7a +PTE3 +SPI1\_SIN +UART1\_RTS\_ +b +SDHC0\_CMD +SPI1\_SOUT +5 +E5 +VDD +VDD +VDD +6 +F6 +VSS +VSS +VSS +7 +E3 +PTE4/ +LLWU\_P2 +DISABLED +PTE4/ +LLWU\_P2 +SPI1\_PCS0 +UART3\_TX +SDHC0\_D3 +8 +E2 +PTE5 +DISABLED +PTE5 +SPI1\_PCS2 +UART3\_RX +SDHC0\_D2 +9 +E1 +PTE6 +DISABLED +PTE6 +SPI1\_PCS3 +UART3\_CTS\_ +b +I2S0\_MCLK +USB\_SOF\_ +OUT +10 +F4 +PTE7 +DISABLED +PTE7 +UART3\_RTS\_ +b +I2S0\_RXD0 +11 +F3 +PTE8 +DISABLED +PTE8 +I2S0\_RXD1 +UART5\_TX +I2S0\_RX\_FS +12 +F2 +PTE9 +DISABLED +PTE9 +I2S0\_TXD1 +UART5\_RX +I2S0\_RX\_ +BCLK +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +243 +General Business Information + +![Image 1 from page 243](pdf-image://page_243_img_1) + +## Page 244 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +13 +F1 +PTE10 +DISABLED +PTE10 +UART5\_CTS\_ +b +I2S0\_TXD0 +14 +G4 +PTE11 +DISABLED +PTE11 +UART5\_RTS\_ +b +I2S0\_TX\_FS +15 +G3 +PTE12 +DISABLED +PTE12 +I2S0\_TX\_ +BCLK +16 +E6 +VDD +VDD +VDD +17 +F7 +VSS +VSS +VSS +18 +H3 +VSS +VSS +VSS +19 +H1 +USB0\_DP +USB0\_DP +USB0\_DP +20 +H2 +USB0\_DM +USB0\_DM +USB0\_DM +21 +G1 +VOUT33 +VOUT33 +VOUT33 +22 +G2 +VREGIN +VREGIN +VREGIN +23 +J1 +ADC0\_DP1 +ADC0\_DP1 +ADC0\_DP1 +24 +J2 +ADC0\_DM1 +ADC0\_DM1 +ADC0\_DM1 +25 +K1 +ADC1\_DP1 +ADC1\_DP1 +ADC1\_DP1 +26 +K2 +ADC1\_DM1 +ADC1\_DM1 +ADC1\_DM1 +27 +L1 +PGA0\_DP/ +ADC0\_DP0/ +ADC1\_DP3 +PGA0\_DP/ +ADC0\_DP0/ +ADC1\_DP3 +PGA0\_DP/ +ADC0\_DP0/ +ADC1\_DP3 +28 +L2 +PGA0\_DM/ +ADC0\_DM0/ +ADC1\_DM3 +PGA0\_DM/ +ADC0\_DM0/ +ADC1\_DM3 +PGA0\_DM/ +ADC0\_DM0/ +ADC1\_DM3 +29 +M1 +PGA1\_DP/ +ADC1\_DP0/ +ADC0\_DP3 +PGA1\_DP/ +ADC1\_DP0/ +ADC0\_DP3 +PGA1\_DP/ +ADC1\_DP0/ +ADC0\_DP3 +30 +M2 +PGA1\_DM/ +ADC1\_DM0/ +ADC0\_DM3 +PGA1\_DM/ +ADC1\_DM0/ +ADC0\_DM3 +PGA1\_DM/ +ADC1\_DM0/ +ADC0\_DM3 +31 +H5 +VDDA +VDDA +VDDA +32 +G5 +VREFH +VREFH +VREFH +33 +G6 +VREFL +VREFL +VREFL +34 +H6 +VSSA +VSSA +VSSA +35 +K3 +ADC1\_SE16/ +CMP2\_IN2/ +ADC0\_SE22 +ADC1\_SE16/ +CMP2\_IN2/ +ADC0\_SE22 +ADC1\_SE16/ +CMP2\_IN2/ +ADC0\_SE22 +36 +J3 +ADC0\_SE16/ +CMP1\_IN2/ +ADC0\_SE21 +ADC0\_SE16/ +CMP1\_IN2/ +ADC0\_SE21 +ADC0\_SE16/ +CMP1\_IN2/ +ADC0\_SE21 +37 +M3 +VREF\_OUT/ +CMP1\_IN5/ +CMP0\_IN5/ +ADC1\_SE18 +VREF\_OUT/ +CMP1\_IN5/ +CMP0\_IN5/ +ADC1\_SE18 +VREF\_OUT/ +CMP1\_IN5/ +CMP0\_IN5/ +ADC1\_SE18 +38 +L3 +DAC0\_OUT/ +CMP1\_IN3/ +ADC0\_SE23 +DAC0\_OUT/ +CMP1\_IN3/ +ADC0\_SE23 +DAC0\_OUT/ +CMP1\_IN3/ +ADC0\_SE23 +Pinout +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +244 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 244](pdf-image://page_244_img_1) + +## Page 245 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +39 +L4 +DAC1\_OUT/ +CMP0\_IN4/ +CMP2\_IN3/ +ADC1\_SE23 +DAC1\_OUT/ +CMP0\_IN4/ +CMP2\_IN3/ +ADC1\_SE23 +DAC1\_OUT/ +CMP0\_IN4/ +CMP2\_IN3/ +ADC1\_SE23 +40 +M7 +XTAL32 +XTAL32 +XTAL32 +41 +M6 +EXTAL32 +EXTAL32 +EXTAL32 +42 +L6 +VBAT +VBAT +VBAT +43 +— +VDD +VDD +VDD +44 +— +VSS +VSS +VSS +45 +M4 +PTE24 +ADC0\_SE17 +ADC0\_SE17 +PTE24 +CAN1\_TX +UART4\_TX +EWM\_OUT\_b +46 +K5 +PTE25 +ADC0\_SE18 +ADC0\_SE18 +PTE25 +CAN1\_RX +UART4\_RX +EWM\_IN +47 +K4 +PTE26 +DISABLED +PTE26 +ENET\_1588\_ +CLKIN +UART4\_CTS\_ +b +RTC\_CLKOUT +USB\_CLKIN +48 +J4 +PTE27 +DISABLED +PTE27 +UART4\_RTS\_ +b +49 +H4 +PTE28 +DISABLED +PTE28 +50 +J5 +PTA0 +JTAG\_TCLK/ +SWD\_CLK/ +EZP\_CLK +TSI0\_CH1 +PTA0 +UART0\_CTS\_ +b/ +UART0\_COL\_ +b +FTM0\_CH5 +JTAG\_TCLK/ +SWD\_CLK +EZP\_CLK +51 +J6 +PTA1 +JTAG\_TDI/ +EZP\_DI +TSI0\_CH2 +PTA1 +UART0\_RX +FTM0\_CH6 +JTAG\_TDI +EZP\_DI +52 +K6 +PTA2 +JTAG\_TDO/ +TRACE\_SWO/ +EZP\_DO +TSI0\_CH3 +PTA2 +UART0\_TX +FTM0\_CH7 +JTAG\_TDO/ +TRACE\_SWO +EZP\_DO +53 +K7 +PTA3 +JTAG\_TMS/ +SWD\_DIO +TSI0\_CH4 +PTA3 +UART0\_RTS\_ +b +FTM0\_CH0 +JTAG\_TMS/ +SWD\_DIO +54 +L7 +PTA4/ +LLWU\_P3 +NMI\_b/ +EZP\_CS\_b +TSI0\_CH5 +PTA4/ +LLWU\_P3 +FTM0\_CH1 +NMI\_b +EZP\_CS\_b +55 +M8 +PTA5 +DISABLED +PTA5 +USB\_CLKIN +FTM0\_CH2 +RMII0\_RXER/ +MII0\_RXER +CMP2\_OUT +I2S0\_TX\_ +BCLK +JTAG\_TRST\_ +b +56 +E7 +VDD +VDD +VDD +57 +G7 +VSS +VSS +VSS +58 +J7 +PTA6 +DISABLED +PTA6 +FTM0\_CH3 +TRACE\_ +CLKOUT +59 +J8 +PTA7 +ADC0\_SE10 +ADC0\_SE10 +PTA7 +FTM0\_CH4 +TRACE\_D3 +60 +K8 +PTA8 +ADC0\_SE11 +ADC0\_SE11 +PTA8 +FTM1\_CH0 +FTM1\_QD\_ +PHA +TRACE\_D2 +61 +L8 +PTA9 +DISABLED +PTA9 +FTM1\_CH1 +MII0\_RXD3 +FTM1\_QD\_ +PHB +TRACE\_D1 +62 +M9 +PTA10 +DISABLED +PTA10 +FTM2\_CH0 +MII0\_RXD2 +FTM2\_QD\_ +PHA +TRACE\_D0 +63 +L9 +PTA11 +DISABLED +PTA11 +FTM2\_CH1 +MII0\_RXCLK +FTM2\_QD\_ +PHB +64 +K9 +PTA12 +CMP2\_IN0 +CMP2\_IN0 +PTA12 +CAN0\_TX +FTM1\_CH0 +RMII0\_RXD1/ +MII0\_RXD1 +I2S0\_TXD0 +FTM1\_QD\_ +PHA +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +245 +General Business Information + +![Image 1 from page 245](pdf-image://page_245_img_1) + +## Page 246 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +65 +J9 +PTA13/ +LLWU\_P4 +CMP2\_IN1 +CMP2\_IN1 +PTA13/ +LLWU\_P4 +CAN0\_RX +FTM1\_CH1 +RMII0\_RXD0/ +MII0\_RXD0 +I2S0\_TX\_FS +FTM1\_QD\_ +PHB +66 +L10 +PTA14 +DISABLED +PTA14 +SPI0\_PCS0 +UART0\_TX +RMII0\_CRS\_ +DV/ +MII0\_RXDV +I2S0\_RX\_ +BCLK +I2S0\_TXD1 +67 +L11 +PTA15 +DISABLED +PTA15 +SPI0\_SCK +UART0\_RX +RMII0\_TXEN/ +MII0\_TXEN +I2S0\_RXD0 +68 +K10 +PTA16 +DISABLED +PTA16 +SPI0\_SOUT +UART0\_CTS\_ +b/ +UART0\_COL\_ +b +RMII0\_TXD0/ +MII0\_TXD0 +I2S0\_RX\_FS +I2S0\_RXD1 +69 +K11 +PTA17 +ADC1\_SE17 +ADC1\_SE17 +PTA17 +SPI0\_SIN +UART0\_RTS\_ +b +RMII0\_TXD1/ +MII0\_TXD1 +I2S0\_MCLK +70 +E8 +VDD +VDD +VDD +71 +G8 +VSS +VSS +VSS +72 +M12 +PTA18 +EXTAL0 +EXTAL0 +PTA18 +FTM0\_FLT2 +FTM\_CLKIN0 +73 +M11 +PTA19 +XTAL0 +XTAL0 +PTA19 +FTM1\_FLT0 +FTM\_CLKIN1 +LPTMR0\_ +ALT1 +74 +L12 +RESET\_b +RESET\_b +RESET\_b +75 +K12 +PTA24 +DISABLED +PTA24 +MII0\_TXD2 +FB\_A29 +76 +J12 +PTA25 +DISABLED +PTA25 +MII0\_TXCLK +FB\_A28 +77 +J11 +PTA26 +DISABLED +PTA26 +MII0\_TXD3 +FB\_A27 +78 +J10 +PTA27 +DISABLED +PTA27 +MII0\_CRS +FB\_A26 +79 +H12 +PTA28 +DISABLED +PTA28 +MII0\_TXER +FB\_A25 +80 +H11 +PTA29 +DISABLED +PTA29 +MII0\_COL +FB\_A24 +81 +H10 +PTB0/ +LLWU\_P5 +ADC0\_SE8/ +ADC1\_SE8/ +TSI0\_CH0 +ADC0\_SE8/ +ADC1\_SE8/ +TSI0\_CH0 +PTB0/ +LLWU\_P5 +I2C0\_SCL +FTM1\_CH0 +RMII0\_MDIO/ +MII0\_MDIO +FTM1\_QD\_ +PHA +82 +H9 +PTB1 +ADC0\_SE9/ +ADC1\_SE9/ +TSI0\_CH6 +ADC0\_SE9/ +ADC1\_SE9/ +TSI0\_CH6 +PTB1 +I2C0\_SDA +FTM1\_CH1 +RMII0\_MDC/ +MII0\_MDC +FTM1\_QD\_ +PHB +83 +G12 +PTB2 +ADC0\_SE12/ +TSI0\_CH7 +ADC0\_SE12/ +TSI0\_CH7 +PTB2 +I2C0\_SCL +UART0\_RTS\_ +b +ENET0\_1588\_ +TMR0 +FTM0\_FLT3 +84 +G11 +PTB3 +ADC0\_SE13/ +TSI0\_CH8 +ADC0\_SE13/ +TSI0\_CH8 +PTB3 +I2C0\_SDA +UART0\_CTS\_ +b/ +UART0\_COL\_ +b +ENET0\_1588\_ +TMR1 +FTM0\_FLT0 +85 +G10 +PTB4 +ADC1\_SE10 +ADC1\_SE10 +PTB4 +ENET0\_1588\_ +TMR2 +FTM1\_FLT0 +86 +G9 +PTB5 +ADC1\_SE11 +ADC1\_SE11 +PTB5 +ENET0\_1588\_ +TMR3 +FTM2\_FLT0 +87 +F12 +PTB6 +ADC1\_SE12 +ADC1\_SE12 +PTB6 +FB\_AD23 +88 +F11 +PTB7 +ADC1\_SE13 +ADC1\_SE13 +PTB7 +FB\_AD22 +89 +F10 +PTB8 +DISABLED +PTB8 +UART3\_RTS\_ +b +FB\_AD21 +Pinout +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +246 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 246](pdf-image://page_246_img_1) + +## Page 247 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +90 +F9 +PTB9 +DISABLED +PTB9 +SPI1\_PCS1 +UART3\_CTS\_ +b +FB\_AD20 +91 +E12 +PTB10 +ADC1\_SE14 +ADC1\_SE14 +PTB10 +SPI1\_PCS0 +UART3\_RX +FB\_AD19 +FTM0\_FLT1 +92 +E11 +PTB11 +ADC1\_SE15 +ADC1\_SE15 +PTB11 +SPI1\_SCK +UART3\_TX +FB\_AD18 +FTM0\_FLT2 +93 +H7 +VSS +VSS +VSS +94 +F5 +VDD +VDD +VDD +95 +E10 +PTB16 +TSI0\_CH9 +TSI0\_CH9 +PTB16 +SPI1\_SOUT +UART0\_RX +FB\_AD17 +EWM\_IN +96 +E9 +PTB17 +TSI0\_CH10 +TSI0\_CH10 +PTB17 +SPI1\_SIN +UART0\_TX +FB\_AD16 +EWM\_OUT\_b +97 +D12 +PTB18 +TSI0\_CH11 +TSI0\_CH11 +PTB18 +CAN0\_TX +FTM2\_CH0 +I2S0\_TX\_ +BCLK +FB\_AD15 +FTM2\_QD\_ +PHA +98 +D11 +PTB19 +TSI0\_CH12 +TSI0\_CH12 +PTB19 +CAN0\_RX +FTM2\_CH1 +I2S0\_TX\_FS +FB\_OE\_b +FTM2\_QD\_ +PHB +99 +D10 +PTB20 +DISABLED +PTB20 +SPI2\_PCS0 +FB\_AD31 +CMP0\_OUT +100 +D9 +PTB21 +DISABLED +PTB21 +SPI2\_SCK +FB\_AD30 +CMP1\_OUT +101 +C12 +PTB22 +DISABLED +PTB22 +SPI2\_SOUT +FB\_AD29 +CMP2\_OUT +102 +C11 +PTB23 +DISABLED +PTB23 +SPI2\_SIN +SPI0\_PCS5 +FB\_AD28 +103 +B12 +PTC0 +ADC0\_SE14/ +TSI0\_CH13 +ADC0\_SE14/ +TSI0\_CH13 +PTC0 +SPI0\_PCS4 +PDB0\_EXTRG +FB\_AD14 +I2S0\_TXD1 +104 +B11 +PTC1/ +LLWU\_P6 +ADC0\_SE15/ +TSI0\_CH14 +ADC0\_SE15/ +TSI0\_CH14 +PTC1/ +LLWU\_P6 +SPI0\_PCS3 +UART1\_RTS\_ +b +FTM0\_CH0 +FB\_AD13 +I2S0\_TXD0 +105 +A12 +PTC2 +ADC0\_SE4b/ +CMP1\_IN0/ +TSI0\_CH15 +ADC0\_SE4b/ +CMP1\_IN0/ +TSI0\_CH15 +PTC2 +SPI0\_PCS2 +UART1\_CTS\_ +b +FTM0\_CH1 +FB\_AD12 +I2S0\_TX\_FS +106 +A11 +PTC3/ +LLWU\_P7 +CMP1\_IN1 +CMP1\_IN1 +PTC3/ +LLWU\_P7 +SPI0\_PCS1 +UART1\_RX +FTM0\_CH2 +CLKOUT +I2S0\_TX\_ +BCLK +107 +H8 +VSS +VSS +VSS +108 +— +VDD +VDD +VDD +109 +A9 +PTC4/ +LLWU\_P8 +DISABLED +PTC4/ +LLWU\_P8 +SPI0\_PCS0 +UART1\_TX +FTM0\_CH3 +FB\_AD11 +CMP1\_OUT +110 +D8 +PTC5/ +LLWU\_P9 +DISABLED +PTC5/ +LLWU\_P9 +SPI0\_SCK +LPTMR0\_ +ALT2 +I2S0\_RXD0 +FB\_AD10 +CMP0\_OUT +111 +C8 +PTC6/ +LLWU\_P10 +CMP0\_IN0 +CMP0\_IN0 +PTC6/ +LLWU\_P10 +SPI0\_SOUT +PDB0\_EXTRG +I2S0\_RX\_ +BCLK +FB\_AD9 +I2S0\_MCLK +112 +B8 +PTC7 +CMP0\_IN1 +CMP0\_IN1 +PTC7 +SPI0\_SIN +USB\_SOF\_ +OUT +I2S0\_RX\_FS +FB\_AD8 +113 +A8 +PTC8 +ADC1\_SE4b/ +CMP0\_IN2 +ADC1\_SE4b/ +CMP0\_IN2 +PTC8 +I2S0\_MCLK +FB\_AD7 +114 +D7 +PTC9 +ADC1\_SE5b/ +CMP0\_IN3 +ADC1\_SE5b/ +CMP0\_IN3 +PTC9 +I2S0\_RX\_ +BCLK +FB\_AD6 +FTM2\_FLT0 +115 +C7 +PTC10 +ADC1\_SE6b +ADC1\_SE6b +PTC10 +I2C1\_SCL +I2S0\_RX\_FS +FB\_AD5 +116 +B7 +PTC11/ +LLWU\_P11 +ADC1\_SE7b +ADC1\_SE7b +PTC11/ +LLWU\_P11 +I2C1\_SDA +I2S0\_RXD1 +FB\_RW\_b +117 +A7 +PTC12 +DISABLED +PTC12 +UART4\_RTS\_ +b +FB\_AD27 +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +247 +General Business Information + +![Image 1 from page 247](pdf-image://page_247_img_1) + +## Page 248 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +118 +D6 +PTC13 +DISABLED +PTC13 +UART4\_CTS\_ +b +FB\_AD26 +119 +C6 +PTC14 +DISABLED +PTC14 +UART4\_RX +FB\_AD25 +120 +B6 +PTC15 +DISABLED +PTC15 +UART4\_TX +FB\_AD24 +121 +— +VSS +VSS +VSS +122 +— +VDD +VDD +VDD +123 +A6 +PTC16 +DISABLED +PTC16 +CAN1\_RX +UART3\_RX +ENET0\_1588\_ +TMR0 +FB\_CS5\_b/ +FB\_TSIZ1/ +FB\_BE23\_16\_ +b +124 +D5 +PTC17 +DISABLED +PTC17 +CAN1\_TX +UART3\_TX +ENET0\_1588\_ +TMR1 +FB\_CS4\_b/ +FB\_TSIZ0/ +FB\_BE31\_24\_ +b +125 +C5 +PTC18 +DISABLED +PTC18 +UART3\_RTS\_ +b +ENET0\_1588\_ +TMR2 +FB\_TBST\_b/ +FB\_CS2\_b/ +FB\_BE15\_8\_b +126 +B5 +PTC19 +DISABLED +PTC19 +UART3\_CTS\_ +b +ENET0\_1588\_ +TMR3 +FB\_CS3\_b/ +FB\_BE7\_0\_b +FB\_TA\_b +127 +A5 +PTD0/ +LLWU\_P12 +DISABLED +PTD0/ +LLWU\_P12 +SPI0\_PCS0 +UART2\_RTS\_ +b +FB\_ALE/ +FB\_CS1\_b/ +FB\_TS\_b +128 +D4 +PTD1 +ADC0\_SE5b +ADC0\_SE5b +PTD1 +SPI0\_SCK +UART2\_CTS\_ +b +FB\_CS0\_b +129 +C4 +PTD2/ +LLWU\_P13 +DISABLED +PTD2/ +LLWU\_P13 +SPI0\_SOUT +UART2\_RX +FB\_AD4 +130 +B4 +PTD3 +DISABLED +PTD3 +SPI0\_SIN +UART2\_TX +FB\_AD3 +131 +A4 +PTD4/ +LLWU\_P14 +DISABLED +PTD4/ +LLWU\_P14 +SPI0\_PCS1 +UART0\_RTS\_ +b +FTM0\_CH4 +FB\_AD2 +EWM\_IN +132 +A3 +PTD5 +ADC0\_SE6b +ADC0\_SE6b +PTD5 +SPI0\_PCS2 +UART0\_CTS\_ +b/ +UART0\_COL\_ +b +FTM0\_CH5 +FB\_AD1 +EWM\_OUT\_b +133 +A2 +PTD6/ +LLWU\_P15 +ADC0\_SE7b +ADC0\_SE7b +PTD6/ +LLWU\_P15 +SPI0\_PCS3 +UART0\_RX +FTM0\_CH6 +FB\_AD0 +FTM0\_FLT0 +134 +M10 +VSS +VSS +VSS +135 +F8 +VDD +VDD +VDD +136 +A1 +PTD7 +DISABLED +PTD7 +CMT\_IRO +UART0\_TX +FTM0\_CH7 +FTM0\_FLT1 +137 +C9 +PTD8 +DISABLED +PTD8 +I2C0\_SCL +UART5\_RX +FB\_A16 +138 +B9 +PTD9 +DISABLED +PTD9 +I2C0\_SDA +UART5\_TX +FB\_A17 +139 +B3 +PTD10 +DISABLED +PTD10 +UART5\_RTS\_ +b +FB\_A18 +140 +B2 +PTD11 +DISABLED +PTD11 +SPI2\_PCS0 +UART5\_CTS\_ +b +SDHC0\_ +CLKIN +FB\_A19 +141 +B1 +PTD12 +DISABLED +PTD12 +SPI2\_SCK +SDHC0\_D4 +FB\_A20 +142 +C3 +PTD13 +DISABLED +PTD13 +SPI2\_SOUT +SDHC0\_D5 +FB\_A21 +Pinout +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +248 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 248](pdf-image://page_248_img_1) + +## Page 249 + +144 +LQFP +144 +MAP +BGA +Pin Name +Default +ALT0 +ALT1 +ALT2 +ALT3 +ALT4 +ALT5 +ALT6 +ALT7 +EzPort +143 +C2 +PTD14 +DISABLED +PTD14 +SPI2\_SIN +SDHC0\_D6 +FB\_A22 +144 +C1 +PTD15 +DISABLED +PTD15 +SPI2\_PCS1 +SDHC0\_D7 +FB\_A23 +10.3.2 +K60 Pinouts +The below figure shows the pinout diagram for the devices supported by this document. +Many signals may be multiplexed onto a single pin. To determine what signals can be +used on which pin, see the previous section. +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +249 +General Business Information + +![Image 1 from page 249](pdf-image://page_249_img_1) + +## Page 250 + +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +75 +74 +73 +60 +59 +58 +57 +56 +55 +54 +53 +52 +51 +72 +71 +70 +69 +68 +67 +66 +65 +64 +63 +62 +61 +25 +24 +23 +22 +21 +40 +39 +38 +37 +50 +49 +48 +47 +46 +45 +44 +43 +42 +41 +36 +35 +34 +33 +32 +31 +30 +29 +28 +27 +26 +99 +79 +78 +77 +76 +98 +97 +96 +95 +94 +93 +92 +91 +90 +89 +88 +80 +81 +82 +83 +84 +85 +86 +87 +100 +108 +VDD +107 +106 +105 +104 +103 +102 +101 +VSS +PTC3/LLWU\_P7 +PTC2 +PTC1/LLWU\_P6 +PTC0 +PTB23 +PTB22 +116 +PTC11/LLWU\_P11 +115 +114 +113 +112 +111 +110 +109 +PTC10 +PTC9 +PTC8 +PTC7 +PTC6/LLWU\_P10 +PTC5/LLWU\_P9 +PTC4/LLWU\_P8 +124 +PTC17 +123 +122 +121 +120 +119 +118 +117 +PTC16 +VDD +VSS +PTC15 +PTC14 +PTC13 +PTC12 +132 +PTD5 +131 +130 +129 +128 +127 +126 +125 +PTD4/LLWU\_P14 +PTD3 +PTD2/LLWU\_P13 +PTD1 +PTD0/LLWU\_P12 +PTC19 +PTC18 +140 +PTD11 +139 +138 +137 +136 +135 +134 +133 +PTD10 +PTD9 +PTD8 +PTD7 +VDD +VSS +PTD6/LLWU\_P15 +144 +143 +142 +141 +PTD15 +PTD14 +PTD13 +PTD12 +PTB20 +PTA28 +PTA27 +PTA26 +PTA25 +PTB19 +PTB18 +PTB17 +PTB16 +VDD +VSS +PTB11 +PTB10 +PTB9 +PTB8 +PTB7 +PTA29 +PTB0/LLWU\_P5 +PTB1 +PTB2 +PTB3 +PTB4 +PTB5 +PTB6 +PTB21 +PTA24 +RESET\_b +PTA19 +PTA18 +VSS +VDD +PTA17 +PTA16 +PTA15 +PTA14 +PTA13/LLWU\_P4 +PTA12 +PTA11 +PTA10 +PTA9 +PTA8 +PTA7 +PTA6 +VSS +VDD +PTA5 +PTA4/LLWU\_P3 +PTA3 +PTA2 +PTA1 +PTA0 +PTE28 +PTE27 +PTE26 +PTE25 +PTE24 +VSS +VDD +VBAT +EXTAL32 +XTAL32 +DAC1\_OUT/CMP0\_IN4/CMP2\_IN3/ADC1\_SE23 +DAC0\_OUT/CMP1\_IN3/ADC0\_SE23 +VREF\_OUT/CMP1\_IN5/CMP0\_IN5/ADC1\_SE18 +USB0\_DM +USB0\_DP +VSS +VSS +VDD +PTE12 +PTE11 +PTE10 +PTE9 +PTE8 +PTE7 +PTE6 +PTE5 +PTE4/LLWU\_P2 +VSS +VDD +PTE3 +PTE2/LLWU\_P1 +PTE1/LLWU\_P0 +PTE0 +ADC1\_DP1 +ADC0\_DM1 +ADC0\_DP1 +VREGIN +VOUT33 +ADC0\_SE16/CMP1\_IN2/ADC0\_SE21 +ADC1\_SE16/CMP2\_IN2/ADC0\_SE22 +VSSA +VREFL +VREFH +VDDA +PGA1\_DM/ADC1\_DM0/ADC0\_DM3 +PGA1\_DP/ADC1\_DP0/ADC0\_DP3 +PGA0\_DM/ADC0\_DM0/ADC1\_DM3 +PGA0\_DP/ADC0\_DP0/ADC1\_DP3 +ADC1\_DM1 +Figure 10-2. K60 144 LQFP Pinout Diagram +Pinout +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +250 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 250](pdf-image://page_250_img_1) + +## Page 251 + +1 +2 +3 +4 +5 +6 +7 +8 +9 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F +G +H +J +A +B +C +D +E +F +G +H +J +10 +K +K +10 +11 +11 +L +L +12 +12 +M +M +PTA18 +PTC8 +PTC4/ +NC +PTC3/ +PTC2 +PTA1 +PTA6 +PTA0 +PTE27 +ADC0\_SE16/ +ADC1\_SE16/ +PTE26 +PTE25 +PTA2 +PTA3 +PTA8 +PTA7 +VSS +VSS +VSSA +VDDA +PTE28 +VSS +USB0\_DM +ADC0\_DM1 +ADC1\_DM1 +PGA0\_DM/ +DAC0\_OUT/ +DAC1\_OUT/ +RTC +VBAT +PTA4/ +PTA9 +PTA11 +PTA12 +PTA13/ +PTB1 +PTA27 +PTB0/ +PTB4 +PTB5 +VSS +VSS +VREFL +VREFH +PTE11 +PTE12 +VREGIN +VOUT33 +USB0\_DP +ADC0\_DP1 +ADC1\_DP1 +PGA0\_DP/ +PGA1\_DP/ +PGA1\_DM/ +VREF\_OUT/ +PTE24 +NC +EXTAL32 +XTAL32 +PTA5 +PTA10 +VSS +PTA16 +PTA14 +PTB3 +PTA29 +PTA26 +PTA17 +PTA15 +PTA19 +RESET\_b +PTA24 +PTA25 +PTA28 +PTB2 +PTB6 +PTB7 +PTB8 +PTB9 +VDD +VDD +PTB17 +PTB16 +PTB10 +PTB11 +PTB19 +PTB18 +PTB22 +PTB23 +NC +PTB20 +PTB21 +PTC5/ +PTD8 +PTC6/ +PTC7 +PTD9 +NC +PTC1/ +PTC0 +VSS +VSS +VDD +VDD +PTC13 +PTC9 +PTC11/ +PTC10 +PTC19 +PTC15 +PTC14 +PTC18 +PTD2/ +PTD3 +PTD10 +PTD13 +PTE0 +PTD1 +PTC17 +VDD +VDD +PTE7 +PTE3 +PTE4/ +PTE8 +PTE9 +PTE10 +PTE6 +PTE5 +PTE1/ +PTE2/ +PTD15 +PTD14 +PTD11 +PTD12 +PTC12 +PTC16 +PTD0/ +PTD4/ +PTD5 +PTD6/ +PTD7 +LLWU\_P15 +LLWU\_P14 +LLWU\_P12 +LLWU\_P8 +LLWU\_P7 +LLWU\_P11 +LLWU\_P6 +LLWU\_P13 +LLWU\_P10 +LLWU\_P1 +LLWU\_P0 +LLWU\_P9 +LLWU\_P2 +LLWU\_P5 +CMP1\_IN2/ +ADC0\_SE21 +LLWU\_P4 +CMP2\_IN2/ +ADC0\_SE22 +ADC0\_DP0/ +ADC1\_DP3 +ADC0\_DM0/ +ADC1\_DM3 +CMP1\_IN3/ +ADC0\_SE23 +CMP0\_IN4/ +CMP2\_IN3/ +ADC1\_SE23 +\_WAKEUP\_B +LLWU\_P3 +CMP1\_IN5/ +CMP0\_IN5/ +ADC1\_SE18 +ADC1\_DP0/ +ADC0\_DP3 +ADC1\_DM0/ +ADC0\_DM3 +Figure 10-3. K60 144 MAPBGA Pinout Diagram +10.4 +Module Signal Description Tables +The following sections correlate the chip-level signal name with the signal name used in +the module's chapter. They also briefly describe the signal function and direction. +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +251 +General Business Information + +![Image 1 from page 251](pdf-image://page_251_img_1) + +## Page 252 + +10.4.1 +Core Modules +Table 10-2. JTAG Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +JTAG\_TMS +JTAG\_TMS/ +SWD\_DIO +JTAG Test Mode Selection +I/O +JTAG\_TCLK +JTAG\_TCLK/ +SWD\_CLK +JTAG Test Clock +I +JTAG\_TDI +JTAG\_TDI +JTAG Test Data Input +I +JTAG\_TDO +JTAG\_TDO/ +TRACE\_SWO +JTAG Test Data Output +O +JTAG\_TRST +JTAG\_TRST\_b +JTAG Reset +I +Table 10-3. SWD Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +SWD\_DIO +JTAG\_TMS/ +SWD\_DIO +Serial Wire Data +I/O +SWD\_CLK +JTAG\_TCLK/ +SWD\_CLK +Serial Wire Clock +I +Table 10-4. TPIU Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +TRACE\_CLKOUT +TRACECLK +Trace clock output from the ARM CoreSight debug block +O +TRACE\_D[3:2] +TRACEDATA +Trace output data from the ARM CoreSight debug block used for 5- +pin interface +O +TRACE\_D[1:0] +TRACEDATA +Trace output data from the ARM CoreSight debug block used for +both 5-pin and 3-pin interfaces +O +TRACE\_SWO +JTAG\_TDO/ +TRACE\_SWO +Trace output data from the ARM CoreSight debug block over a +single pin +O +Module Signal Description Tables +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +252 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 252](pdf-image://page_252_img_1) + +## Page 253 + +10.4.2 +System Modules +Table 10-5. System Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +NMI +— +Non-maskable interrupt +NOTE: Driving the NMI signal low forces a non-maskable +interrupt, if the NMI function is selected on the +corresponding pin. +I +RESET +— +Reset bi-directional signal +I/O +VDD +— +MCU power +I +VSS +— +MCU ground +I +Table 10-6. EWM Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +EWM\_IN +EWM\_in +EWM input for safety status of external safety circuits. The polarity +of EWM\_in is programmable using the EWM\_CTRL[ASSIN] bit. The +default polarity is active-low. +I +EWM\_OUT +EWM\_out +EWM reset out signal +O +10.4.3 +Clock Modules +Table 10-7. OSC Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +EXTAL0 +EXTAL +External clock/Oscillator input +I +XTAL0 +XTAL +Oscillator output +O +Table 10-8. RTC OSC Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +EXTAL32 +EXTAL32 +32.768 kHz oscillator input +I +XTAL32 +XTAL32 +32.768 kHz oscillator output +O +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +253 +General Business Information + +![Image 1 from page 253](pdf-image://page_253_img_1) + +## Page 254 + +10.4.4 +Memories and Memory Interfaces +Table 10-9. EzPort Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +EZP\_CLK +EZP\_CK +EzPort Clock +Input +EZP\_CS +EZP\_CS +EzPort Chip Select +Input +EZP\_DI +EZP\_D +EzPort Serial Data In +Input +EZP\_DO +EZP\_Q +EzPort Serial Data Out +Output +Table 10-10. FlexBus Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +CLKOUT +FB\_CLK +O +FlexBus +Clock +Output +FB\_A[29:16] +FB\_A[29:16] +Address Bus +When FlexBus is used in a nonmultiplexed configuration, this is the +address bus. When FlexBus is used in a multiplexed configuration, +this bus is not used. +O +FB\_AD[31:0] +FB\_D31–FB\_D0 +Data Bus—During the first cycle, this bus drives the upper address +byte, addr[31:24]. +When FlexBus is used in a nonmultiplexed configuration, this is the +data bus, FB\_D. When FlexBus is used in a multiplexed +configuration, this is the address and data bus, FB\_AD. +The number of byte lanes carrying the data is determined by the +port size associated with the matching chip-select. +When FlexBus is used in a multiplexed configuration, the full 32-bit +address is driven on the first clock of a bus cycle (address phase). +After the first clock, the data is driven on the bus (data phase). +During the data phase, the address is driven on the pins not used +for data. For example, in 16-bit mode, the lower address is driven +on FB\_AD15–FB\_AD0, and in 8-bit mode, the lower address is +driven on FB\_AD23–FB\_AD0. +I/O +FB\_CS[5:0] +FB\_CS5–FB\_CS0 +General Purpose Chip-Selects—Indicate which external memory or +peripheral is selected. A particular chip-select is asserted when the +transfer address is within the external memory's or peripheral's +address space, as defined in CSAR[BA] and CSMR[BAM]. +O +FB\_BE31\_24\_BLS7\_ +0, +FB\_BE23\_16\_BLS15 +\_8, +FB\_BE15\_8\_BLS23\_ +16, +FB\_BE7\_0\_BLS31\_2 +4 +FB\_BE\_31\_24 +FB\_BE\_23\_16 +FB\_BE\_15\_8 +FB\_BE\_7\_0 +Byte Enables—Indicate that data is to be latched or driven onto a +specific byte lane of the data bus. CSCR[BEM] determines if these +signals are asserted on reads and writes or on writes only. +For external SRAM or flash devices, the FB\_BE outputs should be +connected to individual byte strobe signals. +O +FB\_OE +FB\_OE +Output Enable—Sent to the external memory or peripheral to +enable a read transfer. This signal is asserted during read accesses +only when a chip-select matches the current address decode. +O +Table continues on the next page... +Module Signal Description Tables +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +254 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 254](pdf-image://page_254_img_1) + +## Page 255 + +Table 10-10. FlexBus Signal Descriptions +(continued) +Chip signal name +Module signal +name +Description +I/O +FB\_R W +FB\_R/W +Read/Write—Indicates whether the current bus operation is a read +operation (FB\_R/W high) or a write operation (FB\_R/W low). +O +FB\_TS/ FB\_ALE +FB\_TS +Transfer Start—Indicates that the chip has begun a bus transaction +and that the address and attributes are valid. +An inverted FB\_TS is available as an address latch enable +(FB\_ALE), which indicates when the address is being driven on the +FB\_AD bus. +FB\_TS/FB\_ALE is asserted for one bus clock cycle. +The chip can extend this signal until the first positive clock edge +after FB\_CS asserts. See CSCR[EXTS] and Extended Transfer +Start/Address Latch Enable. +O +FB\_TSIZ[1:0] +FB\_TSIZ1–FB\_TSIZ0 Transfer Size—Indicates (along with FB\_TBST) the data transfer +size of the current bus operation. The interface supports 8-, 16-, +and 32-bit operand transfers and allows accesses to 8-, 16-, and +32-bit data ports. +• 00b = 4 bytes +• 01b = 1 byte +• 10b = 2 bytes +• 11b = 16 bytes (line) +For misaligned transfers, FB\_TSIZ1–FB\_TSIZ0 indicate the size of +each transfer. For example, if a 32-bit access through a 32-bit port +device occurs at a misaligned offset of 1h, 8 bits are transferred first +(FB\_TSIZ1–FB\_TSIZ0 = 01b), 16 bits are transferred next at offset +2h (FB\_TSIZ1–FB\_TSIZ0 = 10b), and the final 8 bits are transferred +at offset 4h (FB\_TSIZ1–FB\_TSIZ0 = 01b). +For aligned transfers larger than the port size, FB\_TSIZ1– +FB\_TSIZ0 behave as follows: +• If bursting is used, FB\_TSIZ1–FB\_TSIZ0 are driven to the +transfer size. +• If bursting is inhibited, FB\_TSIZ1–FB\_TSIZ0 first show the +entire transfer size and then show the port size. +For burst-inhibited transfers, FB\_TSIZ1–FB\_TSIZ0 change with +each FB\_TS assertion to reflect the next transfer size. +For transfers to port sizes smaller than the transfer size, +FB\_TSIZ1–FB\_TSIZ0 indicate the size of the entire transfer on the +first access and the size of the current port transfer on subsequent +transfers. For example, for a 32-bit write to an 8-bit port, +FB\_TSIZ1–FB\_TSIZ0 are 00b for the first transaction and 01b for +the next three transactions. If bursting is used for a 32-bit write to +an 8-bit port, FB\_TSIZ1–FB\_TSIZ0 are driven to 00b for the entire +transfer. +O +Table continues on the next page... +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +255 +General Business Information + +![Image 1 from page 255](pdf-image://page_255_img_1) + +## Page 256 + +Table 10-10. FlexBus Signal Descriptions +(continued) +Chip signal name +Module signal +name +Description +I/O +FB\_TA +FB\_TA +Transfer Acknowledge—Indicates that the external data transfer is +complete. When FB\_TA is asserted during a read transfer, FlexBus +latches the data and then terminates the transfer. When FB\_TA is +asserted during a write transfer, the transfer is terminated. +If auto-acknowledge is disabled (CSCR[AA] = 0), the external +memory or peripheral drives FB\_TA to terminate the transfer. If +auto-acknowledge is enabled (CSCR[AA] = 1), FB\_TA is generated +internally after a specified number of wait states, or the external +memory or peripheral may assert external FB\_TA before the wait- +state countdown to terminate the transfer early. The chip deasserts +FB\_CS one cycle after the last FB\_TA is asserted. During read +transfers, the external memory or peripheral must continue to drive +data until FB\_TA is recognized. For write transfers, the chip +continues driving data one clock cycle after FB\_CS is deasserted. +The number of wait states is determined by CSCR or the external +FB\_TA input. If the external FB\_TA is used, the external memory or +peripheral has complete control of the number of wait states. +Note: External memory or peripherals should assert FB\_TA only +while the FB\_CS signal to the external memory or +peripheral is asserted. +The CSPMCR register controls muxing of FB\_TA with other +signals. If auto-acknowledge is not used and CSPMCR +does not allow FB\_TA control, FlexBus may hang. +I +FB\_TBST +FB\_TBST +Transfer Burst—Indicates that a burst transfer is in progress as +driven by the chip. A burst transfer can be 2 to 16 beats depending +on FB\_TSIZ1–FB\_TSIZ0 and the port size. +Note: When a burst transfer is in progress (FB\_TBST = 0b), the +transfer size is 16 bytes (FB\_TSIZ1–FB\_TSIZ0 = 11b), and +the address is misaligned within the 16-byte boundary, the +external memory or peripheral must be able to wrap around +the address. +O +10.4.5 +Analog +Table 10-11. ADC 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +ADC0\_DP3, +PGA0\_DP, +ADC0\_DP[1:0] +DADP3–DADP0 +Differential Analog Channel Inputs +I +ADC0\_DM3, +PGA0\_DM, +ADC0\_DM[1:0] +DADM3–DADM0 +Differential Analog Channel Inputs +I +ADC0\_SE[18:4] +AD23–AD4 +Single-Ended Analog Channel Inputs +I +Table continues on the next page... +Module Signal Description Tables +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +256 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 256](pdf-image://page_256_img_1) + +## Page 257 + +Table 10-11. ADC 0 Signal Descriptions (continued) +Chip signal name +Module signal +name +Description +I/O +VREFH +VREFSH +Voltage Reference Select High +I +VREFL +VREFSL +Voltage Reference Select Low +I +VDDA +VDDA +Analog Power Supply +I +VSSA +VSSA +Analog Ground +I +Table 10-12. ADC 1 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +ADC1\_DP3, +PGA1\_DP, +ADC1\_DP[1:0] +DADP3–DADP0 +Differential Analog Channel Inputs +I +ADC1\_DM3, +PGA1\_DM, +ADC1\_DM[1:0] +DADM3–DADM0 +Differential Analog Channel Inputs +I +ADC1\_SE[18:4] +AD23–AD4 +Single-Ended Analog Channel Inputs +I +VREFH +VREFSH +Voltage Reference Select High +I +VREFL +VREFSL +Voltage Reference Select Low +I +VDDA +VDDA +Analog Power Supply +I +VSSA +VSSA +Analog Ground +I +Table 10-13. CMP 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +CMP0\_IN[5:0] +IN[5:0] +Analog voltage inputs +I +CMP0\_OUT +CMPO +Comparator output +O +Table 10-14. CMP 1 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +CMP1\_IN[5:0] +IN[5:0] +Analog voltage inputs +I +CMP1\_OUT +CMPO +Comparator output +O +Table 10-15. CMP 2 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +CMP2\_IN[5:0] +IN[5:0] +Analog voltage inputs +I +CMP2\_OUT +CMPO +Comparator output +O +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +257 +General Business Information + +![Image 1 from page 257](pdf-image://page_257_img_1) + +## Page 258 + +Table 10-16. DAC 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +DAC0\_OUT +— +DAC output +O +Table 10-17. DAC 1 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +DAC1\_OUT +— +DAC output +O +Table 10-18. TRIAMP 1 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +TRI1\_DP +inp\_3v +Amplifier positive input terminal +I +TRI1\_DM +inn\_3v +Amplifier negative input terminal +I +TRI1\_OUT +out\_3v +Amplifier output terminal +O +Table 10-19. VREF Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +VREF\_OUT +VREF\_OUT +Internally-generated Voltage Reference output +O +10.4.6 +Timer Modules +Table 10-20. FTM 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +FTM\_CLKIN[1:0] +EXTCLK +External clock. FTM external clock can be selected to drive the +FTM counter. +I +FTM0\_CH[7:0] +CHn +FTM channel (n), where n can be 7-0 +I/O +FTM0\_FLT[3:0] +FAULTj +Fault input (j), where j can be 3-0 +I +Table 10-21. FTM 1 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +FTM\_CLKIN[1:0] +EXTCLK +External clock. FTM external clock can be selected to drive the +FTM counter. +I +Table continues on the next page... +Module Signal Description Tables +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +258 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 258](pdf-image://page_258_img_1) + +## Page 259 + +Table 10-21. FTM 1 Signal Descriptions (continued) +Chip signal name +Module signal +name +Description +I/O +FTM1\_CH[1:0] +CHn +FTM channel (n), where n can be 7-0 +I/O +FTM1\_FLT0 +FAULTj +Fault input (j), where j can be 3-0 +I +FTM1\_QD\_PHA +PHA +Quadrature decoder phase A input. Input pin associated with +quadrature decoder phase A. +I +FTM1\_QD\_PHB +PHB +Quadrature decoder phase B input. Input pin associated with +quadrature decoder phase B. +I +Table 10-22. FTM 2 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +FTM\_CLKIN[1:0] +EXTCLK +External clock. FTM external clock can be selected to drive the +FTM counter. +I +FTM2\_CH[1:0] +CHn +FTM channel (n), where n can be 7-0 +I/O +FTM2\_FLT0 +FAULTj +Fault input (j), where j can be 3-0 +I +FTM2\_QD\_PHA +PHA +Quadrature decoder phase A input. Input pin associated with +quadrature decoder phase A. +I +FTM2\_QD\_PHB +PHB +Quadrature decoder phase B input. Input pin associated with +quadrature decoder phase B. +I +Table 10-23. CMT Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +CMT\_IRO +CMT\_IRO +Infrared Output +O +Table 10-24. PDB 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +PDB0\_EXTRG +EXTRG +External Trigger Input Source +If the PDB is enabled and external trigger input source is selected, +a positive edge on the EXTRG signal resets and starts the counter. +I +Table 10-25. LPT 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +LPT0\_ALT[2:1] +LPTMR\_ALTn +I +Pulse +Counter +Input pin +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +259 +General Business Information + +![Image 1 from page 259](pdf-image://page_259_img_1) + +## Page 260 + +Table 10-26. RTC Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +VBAT +— +Backup battery supply for RTC and VBAT register file +I +RTC\_CLKOUT +RTC\_CLKOUT +1 Hz square-wave output +O +RTC\_WAKEUP +RTC\_WAKEUP +Wakeup for external device +O +Chip signal name +Module signal name +Description +I/O +ENET0\_1588\_TMR[3:0] +1588\_TMRn +Capture/compare block input/ +output event bus. When +configured for capture and a +rising edge is detected, the +current timer value is latched +and transferred into the +corresponding ENET\_TCCRn +register for inspection by +software. +When configured for +compare, the corresponding +signal 1588\_TMRn is +asserted for one cycle when +the timer reaches the +compare value programmed +in register ENET\_TCCRn. +An interrupt or DMA request +can be triggered if the +corresponding bit in +ENET\_TCSRn[TIE] or +ENET\_TCSRn[TDRE] is set. +I/O +ENET\_1588\_CLKIN +1588\_TMRn +Capture/compare block input/ +output event bus. When +configured for capture and a +rising edge is detected, the +current timer value is latched +and transferred into the +corresponding ENET\_TCCRn +register for inspection by +software. +When configured for +compare, the corresponding +signal 1588\_TMRn is +asserted for one cycle when +the timer reaches the +compare value programmed +in register ENET\_TCCRn. +An interrupt or DMA request +can be triggered if the +corresponding bit in +ENET\_TCSRn[TIE] or +ENET\_TCSRn[TDRE] is set. +I/O +Module Signal Description Tables +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +260 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 260](pdf-image://page_260_img_1) + +## Page 261 + +10.4.7 +Communication Interfaces +Ethernet MII Signal Descriptions +Chip signal name +Module signal name +Description +I/O +MII0\_COL +MII\_COL +Asserted upon detection of a +collision and remains +asserted while the collision +persists. This signal is not +defined for full-duplex mode. +I +MII0\_CRS +MII\_CRS +Carrier sense. When +asserted, indicates transmit +or receive medium is not idle. +In RMII mode, this signal is +present on the +RMII\_CRS\_DV pin. +I +MII0\_MDC +MII\_MDC +Output clock provides a +timing reference to the PHY +for data transfers on the +MDIO signal. +O +MII0\_MDIO +MII\_MDIO +Transfers control information +between the external PHY +and the media-access +controller. Data is +synchronous to MDC. This +signal is an input after reset. +I/O +MII0\_RXCLK +MII\_RXCLK +In MII mode, provides a +timing reference for RXDV, +RXD[3:0], and RXER. +I +MII0\_RXDV +MII\_RXDV +Asserting this input indicates +the PHY has valid nibbles +present on the MII. RXDV +must remain asserted from +the first recovered nibble of +the frame through to the last +nibble. Asserting RXDV must +start no later than the SFD +and exclude any EOF. +In RMII mode, this pin also +generates the CRS signal. +I +MII0\_RXD[3:0] +MII\_RXD[3:0] +Contains the Ethernet input +data transferred from the +PHY to the media-access +controller when RXDV is +asserted. +I +MII0\_RXER +MII\_RXER +When asserted with RXDV, +indicates the PHY detects an +error in the current frame. +I +Table continues on the next page... +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +261 +General Business Information + +![Image 1 from page 261](pdf-image://page_261_img_1) + +## Page 262 + +Chip signal name +Module signal name +Description +I/O +MII0\_TXCLK +MII\_TXCLK +Input clock, which provides a +timing reference for TXEN, +TXD[3:0], and TXER. +I +MII0\_TXD[3:0] +MII\_TXD[3:0] +Serial output Ethernet data. +Only valid during TXEN +assertion. +O +MII0\_TXEN +MII\_TXEN +Indicates when valid nibbles +are present on the MII. This +signal is asserted with the +first nibble of a preamble and +is deasserted before the first +TXCLK following the final +nibble of the frame. +O +MII0\_TXER +MII\_TXER +When asserted for one or +more clock cycles while +TXEN is also asserted, PHY +sends one or more illegal +symbols. +O +Ethernet RMII Signal Descriptions +Chip signal name +Module signal name +Description +I/O +RMII0\_MDC +RMII\_MDC +Output clock provides a +timing reference to the PHY +for data transfers on the +MDIO signal. +O +RMII0\_MDIO +RMII\_MDIO +Transfers control information +between the external PHY +and the media-access +controller. Data is +synchronous to MDC. This +signal is an input after reset. +I/O +RMII0\_CRS\_DV +RMII\_CRS\_DV +Asserting this input indicates +the PHY has valid nibbles +present on the MII. RXDV +must remain asserted from +the first recovered nibble of +the frame through to the last +nibble. Asserting RXDV must +start no later than the SFD +and exclude any EOF. +In RMII mode, this pin also +generates the CRS signal. +I +RMII0\_RXD[1:0] +RMII\_RXD[1:0] +Contains the Ethernet input +data transferred from the +PHY to the media-access +controller when RXDV is +asserted. +I +RMII0\_RXER +RMII\_RXER +When asserted with RXDV, +indicates the PHY detects an +error in the current frame. +I +Table continues on the next page... +Module Signal Description Tables +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +262 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 262](pdf-image://page_262_img_1) + +## Page 263 + +Chip signal name +Module signal name +Description +I/O +RMII0\_TXD[1:0] +RMII\_TXD[1:0] +Serial output Ethernet data. +Only valid during TXEN +assertion. +O +RMII0\_TXEN +RMII\_TXEN +Indicates when valid nibbles +are present on the MII. This +signal is asserted with the +first nibble of a preamble and +is deasserted before the first +TXCLK following the final +nibble of the frame. +O +Internal OSCERCLK clock1 +RMII\_REF\_CLK +In RMII mode, this signal is +the reference clock for +receive, transmit, and the +control interface. +I +Table 10-27. USB FS OTG Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +USB0\_DM +usb\_dm +USB D- analog data signal on the USB bus. +I/O +USB0\_DP +usb\_dp +USB D+ analog data signal on the USB bus. +I/O +USB\_CLKIN +— +Alternate USB clock input +I +Table 10-28. USB VREG Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +VOUT33 +reg33\_out +Regulator output voltage +O +VREGIN +reg33\_in +Unregulated power supply +I +Table 10-29. CAN 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +CAN0\_RX +CAN Rx +CAN Receive Pin +Input +CAN0\_TX +CAN Tx +CAN Transmit Pin +Output +Table 10-30. CAN 1 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +CAN1\_RX +CAN Rx +CAN Receive Pin +Input +CAN1\_TX +CAN Tx +CAN Transmit Pin +Output +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +263 +General Business Information + +![Image 1 from page 263](pdf-image://page_263_img_1) + +## Page 264 + +Table 10-31. SPI 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +SPI0\_PCS0 +PCS0/SS +Peripheral Chip Select 0 output +I/O +SPI0\_PCS[3:1] +PCS[3:1] +Peripheral Chip Select 1 – 3 +O +SPI0\_PCS4 +PCS4 +Peripheral Chip Select 4 +O +SPI0\_SIN +SIN +Serial Data In +I +SPI0\_SOUT +SOUT +Serial Data Out +O +SPI0\_SCK +SCK +Master mode: Serial Clock (output) +I/O +Table 10-32. SPI 1 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +SPI1\_PCS0 +PCS0/SS +Peripheral Chip Select 0 output +I/O +SPI1\_PCS[3:1] +PCS[3:1] +Peripheral Chip Select 1 – 3 +O +SPI1\_SIN +SIN +Serial Data In +I +SPI1\_SOUT +SOUT +Serial Data Out +O +SPI1\_SCK +SCK +Master mode: Serial Clock (output) +I/O +Table 10-33. SPI 2 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +SPI2\_PCS0 +PCS0/SS +Peripheral Chip Select 0 output +I/O +SPI2\_PCS1 +PCS[3:1] +Peripheral Chip Select 1 – 3 +O +SPI2\_SIN +SIN +Serial Data In +I +SPI2\_SOUT +SOUT +Serial Data Out +O +SPI2\_SCK +SCK +Master mode: Serial Clock (output) +I/O +Table 10-34. I2C 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +I2C0\_SCL +SCL +Bidirectional serial clock line of the I2C system. +I/O +I2C0\_SDA +SDA +Bidirectional serial data line of the I2C system. +I/O +Table 10-35. I2C 1 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +I2C1\_SCL +SCL +Bidirectional serial clock line of the I2C system. +I/O +I2C1\_SDA +SDA +Bidirectional serial data line of the I2C system. +I/O +Module Signal Description Tables +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +264 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 264](pdf-image://page_264_img_1) + +## Page 265 + +Table 10-36. UART 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +UART0\_CTS +CTS +Clear to send +I +UART0\_RTS +RTS +Request to send +O +UART0\_TX +TXD +Transmit data +O +UART0\_RX +RXD +Receive data +I +UART0\_COL +Collision +Collision detect +I +Table 10-37. UART 1 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +UART1\_CTS +CTS +Clear to send +I +UART1\_RTS +RTS +Request to send +O +UART1\_TX +TXD +Transmit data +O +UART1\_RX +RXD +Receive data +I +Table 10-38. UART 2 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +UART2\_CTS +CTS +Clear to send +I +UART2\_RTS +RTS +Request to send +O +UART2\_TX +TXD +Transmit data +O +UART2\_RX +RXD +Receive data +I +Table 10-39. UART 3 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +UART3\_CTS +CTS +Clear to send +I +UART3\_RTS +RTS +Request to send +O +UART3\_TX +TXD +Transmit data +O +UART3\_RX +RXD +Receive data +I +Table 10-40. UART 4 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +UART4\_CTS +CTS +Clear to send +I +UART4\_RTS +RTS +Request to send +O +Table continues on the next page... +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +265 +General Business Information + +![Image 1 from page 265](pdf-image://page_265_img_1) + +## Page 266 + +Table 10-40. UART 4 Signal Descriptions (continued) +Chip signal name +Module signal +name +Description +I/O +UART4\_TX +TXD +Transmit data +O +UART4\_RX +RXD +Receive data +I +Table 10-41. UART 5 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +UART5\_CTS +CTS +Clear to send +I +UART5\_RTS +RTS +Request to send +O +UART5\_TX +TXD +Transmit data +O +UART5\_RX +RXD +Receive data +I +Table 10-42. SDHC Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +SDHC0\_CLKIN +— +SDHC clock input +I +SDHC0\_DCLK +SDHC\_DCLK +Generated clock used to drive the MMC, SD, SDIO or CE-ATA +cards. +O +SDHC0\_CMD +SDHC\_CMD +Send commands to and receive responses from the card. +I/O +SDHC0\_D0 +SDHC\_D0 +DAT0 line or busy-state detect +I/O +SDHC0\_D1 +SDHC\_D1 +8-bit mode: DAT1 line +4-bit mode: DAT1 line or interrupt detect +1-bit mode: Interrupt detect +I/O +SDHC0\_D2 +SDHC\_D2 +4-/8-bit mode: DAT2 line or read wait +1-bit mode: Read wait +I/O +SDHC0\_D3 +SDHC\_D3 +4-/8-bit mode: DAT3 line or configured as card detection pin +1-bit mode: May be configured as card detection pin +I/O +SDHC0\_D4 +SDHC\_D4 +DAT4 line in 8-bit mode +Not used in other modes +I/O +SDHC0\_D5 +SDHC\_D5 +DAT5 line in 8-bit mode +Not used in other modes +I/O +SDHC0\_D6 +SDHC\_D6 +DAT6 line in 8-bit mode +Not used in other modes +I/O +SDHC0\_D7 +SDHC\_D7 +DAT7 line in 8-bit mode +Not used in other modes +I/O +Module Signal Description Tables +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +266 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 266](pdf-image://page_266_img_1) + +## Page 267 + +Table 10-43. I2S0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +I2S0\_MCLK +SAI\_MCLK +Audio Master Clock +I/O +I2S0\_RX\_BCLK +SAI\_RX\_BCLK +Receive Bit Clock +I/O +I2S0\_RX\_FS +SAI\_RX\_SYNC +Receive Frame Sync +I/O +I2S0\_RXD +SAI\_RX\_DATA[1:0] +Receive Data +I +I2S0\_TX\_BCLK +SAI\_TX\_BCLK +Transmit Bit Clock +I/O +I2S0\_TX\_FS +SAI\_TX\_SYNC +Transmit Frame Sync +I/O +I2S0\_TXD +SAI\_TX\_DATA[1:0] +Transmit Data +O +10.4.8 +Human-Machine Interfaces (HMI) +Table 10-44. GPIO Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +PTA[31:0]1 +PORTA31–PORTA0 General-purpose input/output +I/O +PTB[31:0]1 +PORTB31–PORTB0 General-purpose input/output +I/O +PTC[31:0]1 +PORTC31–PORTC0 General-purpose input/output +I/O +PTD[31:0]1 +PORTD31–PORTD0 General-purpose input/output +I/O +PTE[31:0]1 +PORTE31–PORTE0 General-purpose input/output +I/O +1. +The available GPIO pins depends on the specific package. See the signal multiplexing section for which exact GPIO +signals are available. +Table 10-45. TSI 0 Signal Descriptions +Chip signal name +Module signal +name +Description +I/O +TSI0\_CH[15:0] +TSI\_IN[15:0] +TSI pins. Switchable driver that connects directly to the electrode +pins TSI[15:0] can operate as GPIO pins +I/O +Chapter 10 Signal Multiplexing and Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +267 +General Business Information + +![Image 1 from page 267](pdf-image://page_267_img_1) + +## Page 268 + +Module Signal Description Tables +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +268 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 268](pdf-image://page_268_img_1) + +## Page 269 + +Chapter 11 +Port control and interrupts (PORT) +11.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +11.2 +Overview +The port control and interrupt (PORT) module provides support for port control, and +external interrupt functions. Most functions can be configured independently for each pin +in the 32-bit port and affect the pin regardless of its pin muxing state. +There is one instance of the PORT module for each port. Not all pins within each port are +implemented on a specific device. +11.2.1 +Features +The PORT module has the following features: +• Pin interrupt +• Interrupt flag and enable registers for each pin +• Support for edge sensitive (rising, falling, both) or level sensitive (low, high) +configured per pin +• Support for interrupt or DMA request configured per pin +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +269 +General Business Information + +![Image 1 from page 269](pdf-image://page_269_img_1) + +## Page 270 + +• Asynchronous wakeup in Low-Power modes +• Pin interrupt is functional in all digital Pin Muxing modes +• Port control +• Individual pull control fields with pullup, pulldown, and pull-disablesupport on +selected pins +• Individual drive strength field supporting high and low drive strength on selected +pins +• Individual slew rate field supporting fast and slow slew rates on selected pins +• Individual input passive filter field supporting enable and disable of the +individual input passive filter on selected pins +• Individual open drain field supporting enable and disable of the individual open +drain output on selected pins +• Individual mux control field supporting analog or pin disabled, GPIO, and up to +six chip-specific digital functions +• Pad configuration fields are functional in all digital Pin Muxing modes +11.2.2 +Modes of operation +11.2.2.1 +Run mode +In Run mode, the PORT operates normally. +11.2.2.2 +Wait mode +In Wait mode, PORT continues to operate normally and may be configured to exit the +Low-Power mode if an enabled interrupt is detected. DMA requests are still generated +during the Wait mode, but do not cause an exit from the Low-Power mode. +11.2.2.3 +Stop mode +In Stop mode, the PORT can be configured to exit the Low-Power mode via an +asynchronous wakeup signal if an enabled interrupt is detected. +11.2.2.4 +Debug mode +In Debug mode, PORT operates normally. +Overview +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +270 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 270](pdf-image://page_270_img_1) + +## Page 271 + +11.3 +External signal description +The following table describes the PORT external signal. +Table 11-1. Signal properties +Name +Function +I/O +Reset +Pull +PORTx[31:0] +External interrupt +I/O +0 +- +NOTE +Not all pins within each port are implemented on each device. +11.4 +Detailed signal description +The following table contains the detailed signal description for the PORT interface. +Table 11-2. PORT interface—detailed signal description +Signal +I/O +Description +PORTx[31:0] +I/O +External interrupt. +State meaning +Asserted—pin is logic one. +Negated—pin is logic zero. +Timing +Assertion—may occur at any time and can assert +asynchronously to the system clock. +Negation—may occur at any time and can assert +asynchronously to the system clock. +11.5 +Memory map and register definition +Any read or write access to the PORT memory space that is outside the valid memory +map results in a bus error. All register accesses complete with zero wait states. +PORT memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4004\_9000 +Pin Control Register n (PORTA\_PCR0) +32 +R/W +See section +11.5.1/277 +4004\_9004 +Pin Control Register n (PORTA\_PCR1) +32 +R/W +See section +11.5.1/277 +4004\_9008 +Pin Control Register n (PORTA\_PCR2) +32 +R/W +See section +11.5.1/277 +Table continues on the next page... +Chapter 11 Port control and interrupts (PORT) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +271 +General Business Information + +![Image 1 from page 271](pdf-image://page_271_img_1) + +## Page 272 + +PORT memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4004\_900C +Pin Control Register n (PORTA\_PCR3) +32 +R/W +See section +11.5.1/277 +4004\_9010 +Pin Control Register n (PORTA\_PCR4) +32 +R/W +See section +11.5.1/277 +4004\_9014 +Pin Control Register n (PORTA\_PCR5) +32 +R/W +See section +11.5.1/277 +4004\_9018 +Pin Control Register n (PORTA\_PCR6) +32 +R/W +See section +11.5.1/277 +4004\_901C +Pin Control Register n (PORTA\_PCR7) +32 +R/W +See section +11.5.1/277 +4004\_9020 +Pin Control Register n (PORTA\_PCR8) +32 +R/W +See section +11.5.1/277 +4004\_9024 +Pin Control Register n (PORTA\_PCR9) +32 +R/W +See section +11.5.1/277 +4004\_9028 +Pin Control Register n (PORTA\_PCR10) +32 +R/W +See section +11.5.1/277 +4004\_902C +Pin Control Register n (PORTA\_PCR11) +32 +R/W +See section +11.5.1/277 +4004\_9030 +Pin Control Register n (PORTA\_PCR12) +32 +R/W +See section +11.5.1/277 +4004\_9034 +Pin Control Register n (PORTA\_PCR13) +32 +R/W +See section +11.5.1/277 +4004\_9038 +Pin Control Register n (PORTA\_PCR14) +32 +R/W +See section +11.5.1/277 +4004\_903C +Pin Control Register n (PORTA\_PCR15) +32 +R/W +See section +11.5.1/277 +4004\_9040 +Pin Control Register n (PORTA\_PCR16) +32 +R/W +See section +11.5.1/277 +4004\_9044 +Pin Control Register n (PORTA\_PCR17) +32 +R/W +See section +11.5.1/277 +4004\_9048 +Pin Control Register n (PORTA\_PCR18) +32 +R/W +See section +11.5.1/277 +4004\_904C +Pin Control Register n (PORTA\_PCR19) +32 +R/W +See section +11.5.1/277 +4004\_9050 +Pin Control Register n (PORTA\_PCR20) +32 +R/W +See section +11.5.1/277 +4004\_9054 +Pin Control Register n (PORTA\_PCR21) +32 +R/W +See section +11.5.1/277 +4004\_9058 +Pin Control Register n (PORTA\_PCR22) +32 +R/W +See section +11.5.1/277 +4004\_905C +Pin Control Register n (PORTA\_PCR23) +32 +R/W +See section +11.5.1/277 +4004\_9060 +Pin Control Register n (PORTA\_PCR24) +32 +R/W +See section +11.5.1/277 +4004\_9064 +Pin Control Register n (PORTA\_PCR25) +32 +R/W +See section +11.5.1/277 +4004\_9068 +Pin Control Register n (PORTA\_PCR26) +32 +R/W +See section +11.5.1/277 +4004\_906C +Pin Control Register n (PORTA\_PCR27) +32 +R/W +See section +11.5.1/277 +4004\_9070 +Pin Control Register n (PORTA\_PCR28) +32 +R/W +See section +11.5.1/277 +4004\_9074 +Pin Control Register n (PORTA\_PCR29) +32 +R/W +See section +11.5.1/277 +4004\_9078 +Pin Control Register n (PORTA\_PCR30) +32 +R/W +See section +11.5.1/277 +4004\_907C +Pin Control Register n (PORTA\_PCR31) +32 +R/W +See section +11.5.1/277 +4004\_9080 +Global Pin Control Low Register (PORTA\_GPCLR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.2/280 +4004\_9084 +Global Pin Control High Register (PORTA\_GPCHR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.3/280 +4004\_90A0 +Interrupt Status Flag Register (PORTA\_ISFR) +32 +w1c +0\_0000 +\_0000h +11.5.4/281 +4004\_A000 +Pin Control Register n (PORTB\_PCR0) +32 +R/W +See section +11.5.1/277 +4004\_A004 +Pin Control Register n (PORTB\_PCR1) +32 +R/W +See section +11.5.1/277 +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +272 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 272](pdf-image://page_272_img_1) + +## Page 273 + +PORT memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4004\_A008 +Pin Control Register n (PORTB\_PCR2) +32 +R/W +See section +11.5.1/277 +4004\_A00C +Pin Control Register n (PORTB\_PCR3) +32 +R/W +See section +11.5.1/277 +4004\_A010 +Pin Control Register n (PORTB\_PCR4) +32 +R/W +See section +11.5.1/277 +4004\_A014 +Pin Control Register n (PORTB\_PCR5) +32 +R/W +See section +11.5.1/277 +4004\_A018 +Pin Control Register n (PORTB\_PCR6) +32 +R/W +See section +11.5.1/277 +4004\_A01C +Pin Control Register n (PORTB\_PCR7) +32 +R/W +See section +11.5.1/277 +4004\_A020 +Pin Control Register n (PORTB\_PCR8) +32 +R/W +See section +11.5.1/277 +4004\_A024 +Pin Control Register n (PORTB\_PCR9) +32 +R/W +See section +11.5.1/277 +4004\_A028 +Pin Control Register n (PORTB\_PCR10) +32 +R/W +See section +11.5.1/277 +4004\_A02C +Pin Control Register n (PORTB\_PCR11) +32 +R/W +See section +11.5.1/277 +4004\_A030 +Pin Control Register n (PORTB\_PCR12) +32 +R/W +See section +11.5.1/277 +4004\_A034 +Pin Control Register n (PORTB\_PCR13) +32 +R/W +See section +11.5.1/277 +4004\_A038 +Pin Control Register n (PORTB\_PCR14) +32 +R/W +See section +11.5.1/277 +4004\_A03C +Pin Control Register n (PORTB\_PCR15) +32 +R/W +See section +11.5.1/277 +4004\_A040 +Pin Control Register n (PORTB\_PCR16) +32 +R/W +See section +11.5.1/277 +4004\_A044 +Pin Control Register n (PORTB\_PCR17) +32 +R/W +See section +11.5.1/277 +4004\_A048 +Pin Control Register n (PORTB\_PCR18) +32 +R/W +See section +11.5.1/277 +4004\_A04C +Pin Control Register n (PORTB\_PCR19) +32 +R/W +See section +11.5.1/277 +4004\_A050 +Pin Control Register n (PORTB\_PCR20) +32 +R/W +See section +11.5.1/277 +4004\_A054 +Pin Control Register n (PORTB\_PCR21) +32 +R/W +See section +11.5.1/277 +4004\_A058 +Pin Control Register n (PORTB\_PCR22) +32 +R/W +See section +11.5.1/277 +4004\_A05C +Pin Control Register n (PORTB\_PCR23) +32 +R/W +See section +11.5.1/277 +4004\_A060 +Pin Control Register n (PORTB\_PCR24) +32 +R/W +See section +11.5.1/277 +4004\_A064 +Pin Control Register n (PORTB\_PCR25) +32 +R/W +See section +11.5.1/277 +4004\_A068 +Pin Control Register n (PORTB\_PCR26) +32 +R/W +See section +11.5.1/277 +4004\_A06C +Pin Control Register n (PORTB\_PCR27) +32 +R/W +See section +11.5.1/277 +4004\_A070 +Pin Control Register n (PORTB\_PCR28) +32 +R/W +See section +11.5.1/277 +4004\_A074 +Pin Control Register n (PORTB\_PCR29) +32 +R/W +See section +11.5.1/277 +4004\_A078 +Pin Control Register n (PORTB\_PCR30) +32 +R/W +See section +11.5.1/277 +4004\_A07C +Pin Control Register n (PORTB\_PCR31) +32 +R/W +See section +11.5.1/277 +4004\_A080 +Global Pin Control Low Register (PORTB\_GPCLR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.2/280 +4004\_A084 +Global Pin Control High Register (PORTB\_GPCHR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.3/280 +4004\_A0A0 +Interrupt Status Flag Register (PORTB\_ISFR) +32 +w1c +0\_0000 +\_0000h +11.5.4/281 +4004\_B000 +Pin Control Register n (PORTC\_PCR0) +32 +R/W +See section +11.5.1/277 +Table continues on the next page... +Chapter 11 Port control and interrupts (PORT) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +273 +General Business Information + +![Image 1 from page 273](pdf-image://page_273_img_1) + +## Page 274 + +PORT memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4004\_B004 +Pin Control Register n (PORTC\_PCR1) +32 +R/W +See section +11.5.1/277 +4004\_B008 +Pin Control Register n (PORTC\_PCR2) +32 +R/W +See section +11.5.1/277 +4004\_B00C +Pin Control Register n (PORTC\_PCR3) +32 +R/W +See section +11.5.1/277 +4004\_B010 +Pin Control Register n (PORTC\_PCR4) +32 +R/W +See section +11.5.1/277 +4004\_B014 +Pin Control Register n (PORTC\_PCR5) +32 +R/W +See section +11.5.1/277 +4004\_B018 +Pin Control Register n (PORTC\_PCR6) +32 +R/W +See section +11.5.1/277 +4004\_B01C +Pin Control Register n (PORTC\_PCR7) +32 +R/W +See section +11.5.1/277 +4004\_B020 +Pin Control Register n (PORTC\_PCR8) +32 +R/W +See section +11.5.1/277 +4004\_B024 +Pin Control Register n (PORTC\_PCR9) +32 +R/W +See section +11.5.1/277 +4004\_B028 +Pin Control Register n (PORTC\_PCR10) +32 +R/W +See section +11.5.1/277 +4004\_B02C +Pin Control Register n (PORTC\_PCR11) +32 +R/W +See section +11.5.1/277 +4004\_B030 +Pin Control Register n (PORTC\_PCR12) +32 +R/W +See section +11.5.1/277 +4004\_B034 +Pin Control Register n (PORTC\_PCR13) +32 +R/W +See section +11.5.1/277 +4004\_B038 +Pin Control Register n (PORTC\_PCR14) +32 +R/W +See section +11.5.1/277 +4004\_B03C +Pin Control Register n (PORTC\_PCR15) +32 +R/W +See section +11.5.1/277 +4004\_B040 +Pin Control Register n (PORTC\_PCR16) +32 +R/W +See section +11.5.1/277 +4004\_B044 +Pin Control Register n (PORTC\_PCR17) +32 +R/W +See section +11.5.1/277 +4004\_B048 +Pin Control Register n (PORTC\_PCR18) +32 +R/W +See section +11.5.1/277 +4004\_B04C +Pin Control Register n (PORTC\_PCR19) +32 +R/W +See section +11.5.1/277 +4004\_B050 +Pin Control Register n (PORTC\_PCR20) +32 +R/W +See section +11.5.1/277 +4004\_B054 +Pin Control Register n (PORTC\_PCR21) +32 +R/W +See section +11.5.1/277 +4004\_B058 +Pin Control Register n (PORTC\_PCR22) +32 +R/W +See section +11.5.1/277 +4004\_B05C +Pin Control Register n (PORTC\_PCR23) +32 +R/W +See section +11.5.1/277 +4004\_B060 +Pin Control Register n (PORTC\_PCR24) +32 +R/W +See section +11.5.1/277 +4004\_B064 +Pin Control Register n (PORTC\_PCR25) +32 +R/W +See section +11.5.1/277 +4004\_B068 +Pin Control Register n (PORTC\_PCR26) +32 +R/W +See section +11.5.1/277 +4004\_B06C +Pin Control Register n (PORTC\_PCR27) +32 +R/W +See section +11.5.1/277 +4004\_B070 +Pin Control Register n (PORTC\_PCR28) +32 +R/W +See section +11.5.1/277 +4004\_B074 +Pin Control Register n (PORTC\_PCR29) +32 +R/W +See section +11.5.1/277 +4004\_B078 +Pin Control Register n (PORTC\_PCR30) +32 +R/W +See section +11.5.1/277 +4004\_B07C +Pin Control Register n (PORTC\_PCR31) +32 +R/W +See section +11.5.1/277 +4004\_B080 +Global Pin Control Low Register (PORTC\_GPCLR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.2/280 +4004\_B084 +Global Pin Control High Register (PORTC\_GPCHR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.3/280 +4004\_B0A0 +Interrupt Status Flag Register (PORTC\_ISFR) +32 +w1c +0\_0000 +\_0000h +11.5.4/281 +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +274 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 274](pdf-image://page_274_img_1) + +## Page 275 + +PORT memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4004\_C000 +Pin Control Register n (PORTD\_PCR0) +32 +R/W +See section +11.5.1/277 +4004\_C004 +Pin Control Register n (PORTD\_PCR1) +32 +R/W +See section +11.5.1/277 +4004\_C008 +Pin Control Register n (PORTD\_PCR2) +32 +R/W +See section +11.5.1/277 +4004\_C00C +Pin Control Register n (PORTD\_PCR3) +32 +R/W +See section +11.5.1/277 +4004\_C010 +Pin Control Register n (PORTD\_PCR4) +32 +R/W +See section +11.5.1/277 +4004\_C014 +Pin Control Register n (PORTD\_PCR5) +32 +R/W +See section +11.5.1/277 +4004\_C018 +Pin Control Register n (PORTD\_PCR6) +32 +R/W +See section +11.5.1/277 +4004\_C01C +Pin Control Register n (PORTD\_PCR7) +32 +R/W +See section +11.5.1/277 +4004\_C020 +Pin Control Register n (PORTD\_PCR8) +32 +R/W +See section +11.5.1/277 +4004\_C024 +Pin Control Register n (PORTD\_PCR9) +32 +R/W +See section +11.5.1/277 +4004\_C028 +Pin Control Register n (PORTD\_PCR10) +32 +R/W +See section +11.5.1/277 +4004\_C02C +Pin Control Register n (PORTD\_PCR11) +32 +R/W +See section +11.5.1/277 +4004\_C030 +Pin Control Register n (PORTD\_PCR12) +32 +R/W +See section +11.5.1/277 +4004\_C034 +Pin Control Register n (PORTD\_PCR13) +32 +R/W +See section +11.5.1/277 +4004\_C038 +Pin Control Register n (PORTD\_PCR14) +32 +R/W +See section +11.5.1/277 +4004\_C03C +Pin Control Register n (PORTD\_PCR15) +32 +R/W +See section +11.5.1/277 +4004\_C040 +Pin Control Register n (PORTD\_PCR16) +32 +R/W +See section +11.5.1/277 +4004\_C044 +Pin Control Register n (PORTD\_PCR17) +32 +R/W +See section +11.5.1/277 +4004\_C048 +Pin Control Register n (PORTD\_PCR18) +32 +R/W +See section +11.5.1/277 +4004\_C04C +Pin Control Register n (PORTD\_PCR19) +32 +R/W +See section +11.5.1/277 +4004\_C050 +Pin Control Register n (PORTD\_PCR20) +32 +R/W +See section +11.5.1/277 +4004\_C054 +Pin Control Register n (PORTD\_PCR21) +32 +R/W +See section +11.5.1/277 +4004\_C058 +Pin Control Register n (PORTD\_PCR22) +32 +R/W +See section +11.5.1/277 +4004\_C05C +Pin Control Register n (PORTD\_PCR23) +32 +R/W +See section +11.5.1/277 +4004\_C060 +Pin Control Register n (PORTD\_PCR24) +32 +R/W +See section +11.5.1/277 +4004\_C064 +Pin Control Register n (PORTD\_PCR25) +32 +R/W +See section +11.5.1/277 +4004\_C068 +Pin Control Register n (PORTD\_PCR26) +32 +R/W +See section +11.5.1/277 +4004\_C06C +Pin Control Register n (PORTD\_PCR27) +32 +R/W +See section +11.5.1/277 +4004\_C070 +Pin Control Register n (PORTD\_PCR28) +32 +R/W +See section +11.5.1/277 +4004\_C074 +Pin Control Register n (PORTD\_PCR29) +32 +R/W +See section +11.5.1/277 +4004\_C078 +Pin Control Register n (PORTD\_PCR30) +32 +R/W +See section +11.5.1/277 +4004\_C07C +Pin Control Register n (PORTD\_PCR31) +32 +R/W +See section +11.5.1/277 +4004\_C080 +Global Pin Control Low Register (PORTD\_GPCLR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.2/280 +4004\_C084 +Global Pin Control High Register (PORTD\_GPCHR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.3/280 +Table continues on the next page... +Chapter 11 Port control and interrupts (PORT) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +275 +General Business Information + +![Image 1 from page 275](pdf-image://page_275_img_1) + +## Page 276 + +PORT memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4004\_C0A0 +Interrupt Status Flag Register (PORTD\_ISFR) +32 +w1c +0\_0000 +\_0000h +11.5.4/281 +4004\_D000 +Pin Control Register n (PORTE\_PCR0) +32 +R/W +See section +11.5.1/277 +4004\_D004 +Pin Control Register n (PORTE\_PCR1) +32 +R/W +See section +11.5.1/277 +4004\_D008 +Pin Control Register n (PORTE\_PCR2) +32 +R/W +See section +11.5.1/277 +4004\_D00C +Pin Control Register n (PORTE\_PCR3) +32 +R/W +See section +11.5.1/277 +4004\_D010 +Pin Control Register n (PORTE\_PCR4) +32 +R/W +See section +11.5.1/277 +4004\_D014 +Pin Control Register n (PORTE\_PCR5) +32 +R/W +See section +11.5.1/277 +4004\_D018 +Pin Control Register n (PORTE\_PCR6) +32 +R/W +See section +11.5.1/277 +4004\_D01C +Pin Control Register n (PORTE\_PCR7) +32 +R/W +See section +11.5.1/277 +4004\_D020 +Pin Control Register n (PORTE\_PCR8) +32 +R/W +See section +11.5.1/277 +4004\_D024 +Pin Control Register n (PORTE\_PCR9) +32 +R/W +See section +11.5.1/277 +4004\_D028 +Pin Control Register n (PORTE\_PCR10) +32 +R/W +See section +11.5.1/277 +4004\_D02C +Pin Control Register n (PORTE\_PCR11) +32 +R/W +See section +11.5.1/277 +4004\_D030 +Pin Control Register n (PORTE\_PCR12) +32 +R/W +See section +11.5.1/277 +4004\_D034 +Pin Control Register n (PORTE\_PCR13) +32 +R/W +See section +11.5.1/277 +4004\_D038 +Pin Control Register n (PORTE\_PCR14) +32 +R/W +See section +11.5.1/277 +4004\_D03C +Pin Control Register n (PORTE\_PCR15) +32 +R/W +See section +11.5.1/277 +4004\_D040 +Pin Control Register n (PORTE\_PCR16) +32 +R/W +See section +11.5.1/277 +4004\_D044 +Pin Control Register n (PORTE\_PCR17) +32 +R/W +See section +11.5.1/277 +4004\_D048 +Pin Control Register n (PORTE\_PCR18) +32 +R/W +See section +11.5.1/277 +4004\_D04C +Pin Control Register n (PORTE\_PCR19) +32 +R/W +See section +11.5.1/277 +4004\_D050 +Pin Control Register n (PORTE\_PCR20) +32 +R/W +See section +11.5.1/277 +4004\_D054 +Pin Control Register n (PORTE\_PCR21) +32 +R/W +See section +11.5.1/277 +4004\_D058 +Pin Control Register n (PORTE\_PCR22) +32 +R/W +See section +11.5.1/277 +4004\_D05C +Pin Control Register n (PORTE\_PCR23) +32 +R/W +See section +11.5.1/277 +4004\_D060 +Pin Control Register n (PORTE\_PCR24) +32 +R/W +See section +11.5.1/277 +4004\_D064 +Pin Control Register n (PORTE\_PCR25) +32 +R/W +See section +11.5.1/277 +4004\_D068 +Pin Control Register n (PORTE\_PCR26) +32 +R/W +See section +11.5.1/277 +4004\_D06C +Pin Control Register n (PORTE\_PCR27) +32 +R/W +See section +11.5.1/277 +4004\_D070 +Pin Control Register n (PORTE\_PCR28) +32 +R/W +See section +11.5.1/277 +4004\_D074 +Pin Control Register n (PORTE\_PCR29) +32 +R/W +See section +11.5.1/277 +4004\_D078 +Pin Control Register n (PORTE\_PCR30) +32 +R/W +See section +11.5.1/277 +4004\_D07C +Pin Control Register n (PORTE\_PCR31) +32 +R/W +See section +11.5.1/277 +4004\_D080 +Global Pin Control Low Register (PORTE\_GPCLR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.2/280 +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +276 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 276](pdf-image://page_276_img_1) + +## Page 277 + +PORT memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4004\_D084 +Global Pin Control High Register (PORTE\_GPCHR) +32 +W +(always +reads 0) +0\_0000 +\_0000h +11.5.3/280 +4004\_D0A0 +Interrupt Status Flag Register (PORTE\_ISFR) +32 +w1c +0\_0000 +\_0000h +11.5.4/281 +11.5.1 +Pin Control Register n (PORTx\_PCRn) +NOTE +Refer to the Signal Multiplexing and Signal Descriptions +chapter for the reset value of this device. +Address: Base address + 0h offset + (4d × i), where i=0d to 31d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +ISF +0 +IRQC +W +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +LK +0 +MUX +0 +DSE +ODE +PFE +0 +SRE +PE +PS +W +Reset +0 +0 +0 +0 +0 +x\* +x\* +x\* +0 +x\* +0 +x\* +0 +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +PORTx\_PCRn field descriptions +Field +Description +31–25 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +24 +ISF +Interrupt Status Flag +The pin interrupt configuration is valid in all digital pin muxing modes. +0 +Configured interrupt is not detected. +1 +Configured interrupt is detected. If the pin is configured to generate a DMA request, then the +corresponding flag will be cleared automatically at the completion of the requested DMA transfer. +Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level +sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is +cleared. +Table continues on the next page... +Chapter 11 Port control and interrupts (PORT) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +277 +General Business Information + +![Image 1 from page 277](pdf-image://page_277_img_1) + +## Page 278 + +PORTx\_PCRn field descriptions (continued) +Field +Description +23–20 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +19–16 +IRQC +Interrupt Configuration +The pin interrupt configuration is valid in all digital pin muxing modes. The corresponding pin is configured +to generate interrupt/DMA request as follows: +0000 +Interrupt/DMA request disabled. +0001 +DMA request on rising edge. +0010 +DMA request on falling edge. +0011 +DMA request on either edge. +0100 +Reserved. +1000 +Interrupt when logic zero. +1001 +Interrupt on rising edge. +1010 +Interrupt on falling edge. +1011 +Interrupt on either edge. +1100 +Interrupt when logic one. +Others +Reserved. +15 +LK +Lock Register +0 +Pin Control Register fields [15:0] are not locked. +1 +Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. +14–11 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +10–8 +MUX +Pin Mux Control +Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in +configuring the pin for a different pin muxing slot. +The corresponding pin is configured in the following pin muxing slot as follows: +000 +Pin disabled (analog). +001 +Alternative 1 (GPIO). +010 +Alternative 2 (chip-specific). +011 +Alternative 3 (chip-specific). +100 +Alternative 4 (chip-specific). +101 +Alternative 5 (chip-specific). +110 +Alternative 6 (chip-specific). +111 +Alternative 7 (chip-specific). +7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +6 +DSE +Drive Strength Enable +This bit is read only for pins that do not support a configurable drive strength. +Drive strength configuration is valid in all digital pin muxing modes. +0 +Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. +1 +High drive strength is configured on the corresponding pin, if pin is configured as a digital output. +5 +ODE +Open Drain Enable +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +278 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 278](pdf-image://page_278_img_1) + +## Page 279 + +PORTx\_PCRn field descriptions (continued) +Field +Description +This bit is read only for pins that do not support a configurable open drain output. +Open drain configuration is valid in all digital pin muxing modes. +0 +Open drain output is disabled on the corresponding pin. +1 +Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output. +4 +PFE +Passive Filter Enable +This bit is read only for pins that do not support a configurable passive input filter. +Passive filter configuration is valid in all digital pin muxing modes. +0 +Passive input filter is disabled on the corresponding pin. +1 +Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low +pass filter of 10 MHz to 30 MHz bandwidth is enabled on the digital input path. Disable the passive +input filter when high speed interfaces of more than 2 MHz are supported on the pin. +3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2 +SRE +Slew Rate Enable +This bit is read only for pins that do not support a configurable slew rate. +Slew rate configuration is valid in all digital pin muxing modes. +0 +Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. +1 +Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. +1 +PE +Pull Enable +This bit is read only for pins that do not support a configurable pull resistor. Refer to the Chapter of Signal +Multiplexing and Signal Descriptions for the pins that support a configurable pull resistor. +Pull configuration is valid in all digital pin muxing modes. +0 +Internal pullup or pulldown resistor is not enabled on the corresponding pin. +1 +Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a +digital input. +0 +PS +Pull Select +This bit is read only for pins that do not support a configurable pull resistor direction. +Pull configuration is valid in all digital pin muxing modes. +0 +Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable +field is set. +1 +Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field +is set. +Chapter 11 Port control and interrupts (PORT) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +279 +General Business Information + +![Image 1 from page 279](pdf-image://page_279_img_1) + +## Page 280 + +11.5.2 +Global Pin Control Low Register (PORTx\_GPCLR) +Only 32-bit writes are supported to this register. +Address: Base address + 80h offset +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +0 +W +GPWE +GPWD +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +PORTx\_GPCLR field descriptions +Field +Description +31–16 +GPWE +Global Pin Write Enable +Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD. If a +selected Pin Control Register is locked then the write to that register is ignored. +0 +Corresponding Pin Control Register is not updated with the value in GPWD. +1 +Corresponding Pin Control Register is updated with the value in GPWD. +15–0 +GPWD +Global Pin Write Data +Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. +11.5.3 +Global Pin Control High Register (PORTx\_GPCHR) +Only 32-bit writes are supported to this register. +Address: Base address + 84h offset +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +0 +W +GPWE +GPWD +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +PORTx\_GPCHR field descriptions +Field +Description +31–16 +GPWE +Global Pin Write Enable +Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. If a +selected Pin Control Register is locked then the write to that register is ignored. +0 +Corresponding Pin Control Register is not updated with the value in GPWD. +1 +Corresponding Pin Control Register is updated with the value in GPWD. +15–0 +GPWD +Global Pin Write Data +Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +280 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 280](pdf-image://page_280_img_1) + +## Page 281 + +11.5.4 +Interrupt Status Flag Register (PORTx\_ISFR) +The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt +Status Flag for each pin is also visible in the corresponding Pin Control Register, and +each flag can be cleared in either location. +Address: Base address + A0h offset +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +ISF +W +w1c +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +PORTx\_ISFR field descriptions +Field +Description +31–0 +ISF +Interrupt Status Flag +Each bit in the field indicates the detection of the configured interrupt of the same number as the field. +0 +Configured interrupt is not detected. +1 +Configured interrupt is detected. If the pin is configured to generate a DMA request, then the +corresponding flag will be cleared automatically at the completion of the requested DMA transfer. +Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level +sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is +cleared. +11.6 +Functional description +11.6.1 +Pin control +Each port pin has a corresponding pin control register, PORT\_PCRn, associated with it. +The upper half of the pin control register configures the pin's capability to either interrupt +the CPU or request a DMA transfer, on a rising/falling edge or both edges as well as a +logic level occurring on the port pin. It also includes a flag to indicate that an interrupt +has occurred. +The lower half of the pin control register configures the following functions for each pin +within the 32-bit port. +• Pullup or pulldown enable on selected pins +• Drive strength and slew rate configuration on selected pins +Chapter 11 Port control and interrupts (PORT) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +281 +General Business Information + +![Image 1 from page 281](pdf-image://page_281_img_1) + +## Page 282 + +• Open drain enable on selected pins +• Passive input filter enable on selected pins +• Pin Muxing mode +The functions apply across all digital Pin Muxing modes and individual peripherals do +not override the configuration in the pin control register. For example, if an I2C function +is enabled on a pin, that does not override the pullup or open drain configuration for that +pin. +When the Pin Muxing mode is configured for analog or is disabled, all the digital +functions on that pin are disabled. This includes the pullup and pulldown enables, digital +output buffer enable, digital input buffer enable, and passive filter enable. +A lock field also exists that allows the configuration for each pin to be locked until the +next system reset. When locked, writes to the lower half of that pin control register are +ignored, although a bus error is not generated on an attempted write to a locked register. +The configuration of each pin control register is retained when the PORT module is +disabled. +11.6.2 +Global pin control +The two global pin control registers allow a single register write to update the lower half +of the pin control register on up to sixteen pins, all with the same value. Registers that are +locked cannot be written using the global pin control registers. +The global pin control registers are designed to enable software to quickly configure +multiple pins within the one port for the same peripheral function. However, the interrupt +functions cannot be configured using the global pin control registers. +The global pin control registers are write-only registers, that always read as zero. +11.6.3 +External interrupts +The external interrupt capability of the PORT module is available in all digital pin +muxing modes provided the PORT module is enabled. +Each pin can be individually configured for any of the following external interrupt +modes: +• Interrupt disabled, default out of reset +• Active high level sensitive interrupt +• Active low level sensitive interrupt +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +282 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 282](pdf-image://page_282_img_1) + +## Page 283 + +• Rising edge sensitive interrupt +• Falling edge sensitive interrupt +• Rising and falling edge sensitive interrupt +• Rising edge sensitive DMA request +• Falling edge sensitive DMA request +• Rising and falling edge sensitive DMA request +The interrupt status flag is set when the configured edge or level is detected on the output +of the pin. When not in Stop mode, the input is first synchronized to the bus clock to +detect the configured level or edge transition. +The PORT module generates a single interrupt that asserts when the interrupt status flag +is set for any enabled interrupt for that port. The interrupt negates after the interrupt status +flags for all enabled interrupts have been cleared by writing a logic 0 to the ISF flag in +the PORT\_PCRn register. +The PORT module generates a single DMA request that asserts when the interrupt status +flag is set for any enabled DMA request in that port. The DMA request negates after the +DMA transfer is completed, because that clears the interrupt status flags for all enabled +DMA requests. +During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously +set if the required level or edge is detected. This also generates an asynchronous wakeup +signal to exit the Low-Power mode. +Chapter 11 Port control and interrupts (PORT) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +283 +General Business Information + +![Image 1 from page 283](pdf-image://page_283_img_1) + +## Page 284 + +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +284 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 284](pdf-image://page_284_img_1) + +## Page 285 + +Chapter 12 +System Integration Module (SIM) +12.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The System Integration Module (SIM) provides system control and chip configuration +registers. +12.1.1 +Features +Features of the SIM include: +• System clocking configuration +• System clock divide values +• Architectural clock gating control +• USB clock selection and divide values +• SDHC clock source selection +• Ethernet 1588 timestamp and RMII clock source selection +• Flash and system RAM size configuration +• USB regulator configuration +• FlexTimer external clock, hardware trigger, and fault source selection +• UART0 and UART1 receive/transmit source selection/configuration +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +285 +General Business Information + +![Image 1 from page 285](pdf-image://page_285_img_1) + +## Page 286 + +12.2 +Memory map and register definition +The SIM module contains many fields for selecting the clock source and dividers for +various module clocks. See the Clock Distribution chapter for more information, +including block diagrams and clock definitions. +NOTE +The SIM\_SOPT1 and SIM\_SOPT1CFG registers are located at +a different base address than the other SIM registers. +SIM memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4004\_7000 +System Options Register 1 (SIM\_SOPT1) +32 +R/W +See section +12.2.1/287 +4004\_7004 +SOPT1 Configuration Register (SIM\_SOPT1CFG) +32 +R/W +0\_0000 +\_0000h +12.2.2/289 +4004\_8004 +System Options Register 2 (SIM\_SOPT2) +32 +R/W +0000\_1000 +\_1000h +12.2.3/290 +4004\_800C +System Options Register 4 (SIM\_SOPT4) +32 +R/W +0\_0000 +\_0000h +12.2.4/293 +4004\_8010 +System Options Register 5 (SIM\_SOPT5) +32 +R/W +0\_0000 +\_0000h +12.2.5/295 +4004\_8018 +System Options Register 7 (SIM\_SOPT7) +32 +R/W +0\_0000 +\_0000h +12.2.6/297 +4004\_8024 +System Device Identification Register (SIM\_SDID) +32 +R +Undefined +12.2.7/299 +4004\_8028 +System Clock Gating Control Register 1 (SIM\_SCGC1) +32 +R/W +0\_0000 +\_0000h +12.2.8/300 +4004\_802C +System Clock Gating Control Register 2 (SIM\_SCGC2) +32 +R/W +0\_0000 +\_0000h +12.2.9/301 +4004\_8030 +System Clock Gating Control Register 3 (SIM\_SCGC3) +32 +R/W +0\_0000 +\_0000h +12.2.10/302 +4004\_8034 +System Clock Gating Control Register 4 (SIM\_SCGC4) +32 +R/W +E010\_0030 +\_E010 +\_0030h +12.2.11/304 +4004\_8038 +System Clock Gating Control Register 5 (SIM\_SCGC5) +32 +R/W +0\_0040\_1824 +\_0182h +12.2.12/306 +4004\_803C +System Clock Gating Control Register 6 (SIM\_SCGC6) +32 +R/W +4000\_0001 +\_4000\_0001h 12.2.13/308 +4004\_8040 +System Clock Gating Control Register 7 (SIM\_SCGC7) +32 +R/W +0\_0000 +\_0077h +12.2.14/310 +4004\_8044 +System Clock Divider Register 1 (SIM\_CLKDIV1) +32 +R/W +See section +12.2.15/311 +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +286 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 286](pdf-image://page_286_img_1) + +## Page 287 + +SIM memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4004\_8048 +System Clock Divider Register 2 (SIM\_CLKDIV2) +32 +R/W +0\_0000 +\_0000h +12.2.16/314 +4004\_804C +Flash Configuration Register 1 (SIM\_FCFG1) +32 +R +See section +12.2.17/314 +4004\_8050 +Flash Configuration Register 2 (SIM\_FCFG2) +32 +R +See section +12.2.18/317 +4004\_8054 +Unique Identification Register High (SIM\_UIDH) +32 +R +See section +12.2.19/318 +4004\_8058 +Unique Identification Register Mid-High (SIM\_UIDMH) +32 +R +See section +12.2.20/319 +4004\_805C +Unique Identification Register Mid Low (SIM\_UIDML) +32 +R +See section +12.2.21/319 +4004\_8060 +Unique Identification Register Low (SIM\_UIDL) +32 +R +See section +12.2.22/320 +12.2.1 +System Options Register 1 (SIM\_SOPT1) +NOTE +The SOPT1 register is only reset on POR or LVD. +Address: 4004\_7000h base + 0h offset = 4004\_7000h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +USBREGEN +USBSSTBY +USBVSTBY +0 +OSC32KSEL +0 +W +Reset +1\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +RAMSIZE +0 +Reserved +W +Reset +1\* +1\* +1\* +1\* +0\* +0\* +0\* +0\* +0\* +0\* +1\* +1\* +1\* +1\* +1\* +1\* +* Notes: +Reset value loaded during System Reset from Flash IFR. +• +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +287 +General Business Information + +![Image 1 from page 287](pdf-image://page_287_img_1) + +## Page 288 + +SIM\_SOPT1 field descriptions +Field +Description +31 +USBREGEN +USB voltage regulator enable +Controls whether the USB voltage regulator is enabled. +0 +USB voltage regulator is disabled. +1 +USB voltage regulator is enabled. +30 +USBSSTBY +USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes. +Controls whether the USB voltage regulator is placed in standby mode during Stop, VLPS, LLS and VLLS +modes. +0 +USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. +1 +USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. +29 +USBVSTBY +USB voltage regulator in standby mode during VLPR and VLPW modes +Controls whether the USB voltage regulator is placed in standby mode during VLPR and VLPW modes. +0 +USB voltage regulator not in standby during VLPR and VLPW modes. +1 +USB voltage regulator in standby during VLPR and VLPW modes. +28–20 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +19–18 +OSC32KSEL +32K oscillator clock select +Selects the 32 kHz clock source (ERCLK32K) for TSI,and LPTMR. This bit is reset only for POR/LVD. +00 +System oscillator (OSC32KCLK) +01 +Reserved +10 +RTC 32.768kHz oscillator +11 +LPO 1 kHz +17–16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15–12 +RAMSIZE +RAM size +This field specifies the amount of system RAM available on the device. +0000 +Undefined +0001 +8 KBytes +0010 +Undefined +0011 +16 KBytes +0100 +Undefined +0101 +32 KBytes +0110 +Undefined +0111 +64 KBytes +1000 +Undefined +1001 +128 KBytes +1010 +Undefined +1011 +Undefined +1100 +Undefined +1101 +Undefined +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +288 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 288](pdf-image://page_288_img_1) + +## Page 289 + +SIM\_SOPT1 field descriptions (continued) +Field +Description +1110 +Undefined +1111 +Undefined +11–6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5–0 +Reserved +This field is reserved. +12.2.2 +SOPT1 Configuration Register (SIM\_SOPT1CFG) +NOTE +The SOPT1CFG register is reset on System Reset not VLLS. +Address: 4004\_7000h base + 4h offset = 4004\_7004h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +USSWE +UVSWE +URWE +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +0 +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +SIM\_SOPT1CFG field descriptions +Field +Description +31–27 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +26 +USSWE +USB voltage regulator stop standby write enable +Writing one to the USSWE bit allows the SOPT1 USBSSTBY bit to be written. This register bit clears after +a write to USBSSTBY. +0 +SOPT1 USBSSTBY cannot be written. +1 +SOPT1 USBSSTBY can be written. +25 +UVSWE +USB voltage regulator VLP standby write enable +Writing one to the UVSWE bit allows the SOPT1 USBVSTBY bit to be written. This register bit clears after +a write to USBVSTBY. +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +289 +General Business Information + +![Image 1 from page 289](pdf-image://page_289_img_1) + +## Page 290 + +SIM\_SOPT1CFG field descriptions (continued) +Field +Description +0 +SOPT1 USBVSTBY cannot be written. +1 +SOPT1 USBVSTBY can be written. +24 +URWE +USB voltage regulator enable write enable +Writing one to the URWE bit allows the SOPT1 USBREGEN bit to be written. This register bit clears after +a write to USBREGEN. +0 +SOPT1 USBREGEN cannot be written. +1 +SOPT1 USBREGEN can be written. +23–10 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +9–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +12.2.3 +System Options Register 2 (SIM\_SOPT2) +SOPT2 contains the controls for selecting many of the module clock source options on +this device. See the Clock Distribution chapter for more information including clocking +diagrams and definitions of device clocks. +Address: 4004\_7000h base + 1004h offset = 4004\_8004h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +SDHCSRC +0 +TIMESRC +RMIISRC +USBSRC +0 +PLLFLLSEL +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +TRACECLKSE +L +PTD7PAD +0 +FBSL +CLKOUTSEL +RTCCLKOUTS +EL +0 +W +Reset +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +290 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 290](pdf-image://page_290_img_1) + +## Page 291 + +SIM\_SOPT2 field descriptions +Field +Description +31–30 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +29–28 +SDHCSRC +SDHC clock source select +Selects the clock source for the SDHC clock . +00 +Core/system clock. +01 +MCGPLLCLK/MCGFLLCLK clock +10 +OSCERCLK clock +11 +External bypass clock (SDHC0\_CLKIN) +27–22 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +21–20 +TIMESRC +IEEE 1588 timestamp clock source select +Selects the clock source for the Ethernet timestamp clock. +00 +Core/system clock. +01 +MCGPLLCLK/MCGFLLCLK clock +10 +OSCERCLK clock +11 +External bypass clock (ENET\_1588\_CLKIN). +19 +RMIISRC +RMII clock source select +Selects the clock source for the Ethernet RMII interface +0 +EXTAL clock +1 +External bypass clock (ENET\_1588\_CLKIN). +18 +USBSRC +USB clock source select +Selects the clock source for the USB 48 MHz clock. +0 +External bypass clock (USB\_CLKIN). +1 +MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the +SIM\_CLKDIV2[USBFRAC, USBDIV] descriptions. +17 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +16 +PLLFLLSEL +PLL/FLL clock select +Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options. +0 +MCGFLLCLK clock +1 +MCGPLLCLK clock +15–13 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +12 +TRACECLKSEL +Debug trace clock select +Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace clock source. +0 +MCGOUTCLK +1 +Core/system clock +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +291 +General Business Information + +![Image 1 from page 291](pdf-image://page_291_img_1) + +## Page 292 + +SIM\_SOPT2 field descriptions (continued) +Field +Description +11 +PTD7PAD +PTD7 pad drive strength +Controls the output drive strength of the PTD7 pin by selecting either one or two pads to drive it. +0 +Single-pad drive strength for PTD7. +1 +Double pad drive strength for PTD7. +10 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +9–8 +FBSL +FlexBus security level +If flash security is enabled, then this field affects what CPU operations can access off-chip via the +FlexBus interface. This field has no effect if flash security is not enabled. +00 +All off-chip accesses (instruction and data) via the FlexBus are disallowed. +01 +All off-chip accesses (instruction and data) via the FlexBus are disallowed. +10 +Off-chip instruction accesses are disallowed. Data accesses are allowed. +11 +Off-chip instruction accesses and data accesses are allowed. +7–5 +CLKOUTSEL +CLKOUT select +Selects the clock to output on the CLKOUT pin. +000 +FlexBus CLKOUT +001 +Reserved +010 +Flash clock +011 +LPO clock (1 kHz) +100 +MCGIRCLK +101 +RTC 32.768kHz clock +110 +OSCERCLK0 +111 +Reserved +4 +RTCCLKOUTSEL +RTC clock out select +Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the RTC\_CLKOUT pin. +0 +RTC 1 Hz clock is output on the RTC\_CLKOUT pin. +1 +RTC 32.768kHz clock is output on the RTC\_CLKOUT pin. +3–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +292 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 292](pdf-image://page_292_img_1) + +## Page 293 + +12.2.4 +System Options Register 4 (SIM\_SOPT4) +Address: 4004\_7000h base + 100Ch offset = 4004\_800Ch +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +FTM0TRG1SR +C +FTM0TRG0SR +C +0 +FTM2CLKSEL +FTM1CLKSEL +FTM0CLKSEL +0 +FTM2CH0SRC +FTM1CH0SRC +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +FTM2FLT0 +0 +FTM1FLT0 +0 +FTM0FLT2 +FTM0FLT1 +FTM0FLT0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +SIM\_SOPT4 field descriptions +Field +Description +31–30 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +29 +FTM0TRG1SRC +FlexTimer 0 Hardware Trigger 1 Source Select +Selects the source of FTM0 hardware trigger 1. +0 +PDB output trigger 1 drives FTM0 hardware trigger 1 +1 +FTM2 channel match drives FTM0 hardware trigger 1 +28 +FTM0TRG0SRC +FlexTimer 0 Hardware Trigger 0 Source Select +Selects the source of FTM0 hardware trigger 0. +0 +HSCMP0 output drives FTM0 hardware trigger 0 +1 +FTM1 channel match drives FTM0 hardware trigger 0 +27 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +26 +FTM2CLKSEL +FlexTimer 2 External Clock Pin Select +Selects the external pin used to drive the clock to the FTM2 module. +NOTE: The selected pin must also be configured for the FTM2 module external clock function through +the appropriate pin control register in the port control module. +0 +FTM2 external clock driven by FTM\_CLK0 pin. +1 +FTM2 external clock driven by FTM\_CLK1 pin. +25 +FTM1CLKSEL +FTM1 External Clock Pin Select +Selects the external pin used to drive the clock to the FTM1 module. +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +293 +General Business Information + +![Image 1 from page 293](pdf-image://page_293_img_1) + +## Page 294 + +SIM\_SOPT4 field descriptions (continued) +Field +Description +NOTE: The selected pin must also be configured for the FTM external clock function through the +appropriate pin control register in the port control module. +0 +FTM\_CLK0 pin +1 +FTM\_CLK1 pin +24 +FTM0CLKSEL +FlexTimer 0 External Clock Pin Select +Selects the external pin used to drive the clock to the FTM0 module. +NOTE: The selected pin must also be configured for the FTM external clock function through the +appropriate pin control register in the port control module. +0 +FTM\_CLK0 pin +1 +FTM\_CLK1 pin +23–22 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +21–20 +FTM2CH0SRC +FTM2 channel 0 input capture source select +Selects the source for FTM2 channel 0 input capture. +NOTE: When the FTM is not in input capture mode, clear this field. +00 +FTM2\_CH0 signal +01 +CMP0 output +10 +CMP1 output +11 +Reserved +19–18 +FTM1CH0SRC +FTM1 channel 0 input capture source select +Selects the source for FTM1 channel 0 input capture. +NOTE: When the FTM is not in input capture mode, clear this field. +00 +FTM1\_CH0 signal +01 +CMP0 output +10 +CMP1 output +11 +USB start of frame pulse +17–9 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +8 +FTM2FLT0 +FTM2 Fault 0 Select +Selects the source of FTM2 fault 0. +NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the +appropriate PORTx pin control register. +0 +FTM2\_FLT0 pin +1 +CMP0 out +7–5 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +4 +FTM1FLT0 +FTM1 Fault 0 Select +Selects the source of FTM1 fault 0. +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +294 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 294](pdf-image://page_294_img_1) + +## Page 295 + +SIM\_SOPT4 field descriptions (continued) +Field +Description +NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the +appropriate pin control register in the port control module. +0 +FTM1\_FLT0 pin +1 +CMP0 out +3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2 +FTM0FLT2 +FTM0 Fault 2 Select +Selects the source of FTM0 fault 2. +NOTE: The pin source for fault 2 must be configured for the FTM module fault function through the +appropriate pin control register in the port control module. +0 +FTM0\_FLT2 pin +1 +CMP2 out +1 +FTM0FLT1 +FTM0 Fault 1 Select +Selects the source of FTM0 fault 1. +NOTE: The pin source for fault 1 must be configured for the FTM module fault function through the +appropriate pin control register in the port control module. +0 +FTM0\_FLT1 pin +1 +CMP1 out +0 +FTM0FLT0 +FTM0 Fault 0 Select +Selects the source of FTM0 fault 0. +NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the +appropriate pin control register in the port control module. +0 +FTM0\_FLT0 pin +1 +CMP0 out +12.2.5 +System Options Register 5 (SIM\_SOPT5) +Address: 4004\_7000h base + 1010h offset = 4004\_8010h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +UART1RXSR +C +UART1TXSR +C +UART0RXSR +C +UART0TXSR +C +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +295 +General Business Information + +![Image 1 from page 295](pdf-image://page_295_img_1) + +## Page 296 + +SIM\_SOPT5 field descriptions +Field +Description +31–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7–6 +UART1RXSRC +UART 1 receive data source select +Selects the source for the UART 1 receive data. +00 +UART1\_RX pin +01 +CMP0 +10 +CMP1 +11 +Reserved +5–4 +UART1TXSRC +UART 1 transmit data source select +Selects the source for the UART 1 transmit data. +00 +UART1\_TX pin +01 +UART1\_TX pin modulated with FTM1 channel 0 output +10 +UART1\_TX pin modulated with FTM2 channel 0 output +11 +Reserved +3–2 +UART0RXSRC +UART 0 receive data source select +Selects the source for the UART 0 receive data. +00 +UART0\_RX pin +01 +CMP0 +10 +CMP1 +11 +Reserved +1–0 +UART0TXSRC +UART 0 transmit data source select +Selects the source for the UART 0 transmit data. +00 +UART0\_TX pin +01 +UART0\_TX pin modulated with FTM1 channel 0 output +10 +UART0\_TX pin modulated with FTM2 channel 0 output +11 +Reserved +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +296 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 296](pdf-image://page_296_img_1) + +## Page 297 + +12.2.6 +System Options Register 7 (SIM\_SOPT7) +Address: 4004\_7000h base + 1018h offset = 4004\_8018h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +ADC1ALTTRGE +N +0 +ADC1PRETRGS +EL +ADC1TRGSEL +ADC0ALTTRGE +N +0 +ADC0PRETRGS +EL +ADC0TRGSEL +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +SIM\_SOPT7 field descriptions +Field +Description +31–16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15 +ADC1ALTTRGEN +ADC1 alternate trigger enable +Enable alternative conversion triggers for ADC1. +0 +PDB trigger selected for ADC1 +1 +Alternate trigger selected for ADC1 as defined by ADC1TRGSEL. +14–13 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +12 +ADC1PRETRGSEL +ADC1 pre-trigger select +Selects the ADC1 pre-trigger source when alternative triggers are enabled through ADC1ALTTRGEN. +0 +Pre-trigger A selected for ADC1. +1 +Pre-trigger B selected for ADC1. +11–8 +ADC1TRGSEL +ADC1 trigger select +Selects the ADC1 trigger source when alternative triggers are functional in stop and VLPS modes. +0000 +PDB external trigger pin input (PDB0\_EXTRG) +0001 +High speed comparator 0 output +0010 +High speed comparator 1 output +0011 +High speed comparator 2 output +0100 +PIT trigger 0 +0101 +PIT trigger 1 +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +297 +General Business Information + +![Image 1 from page 297](pdf-image://page_297_img_1) + +## Page 298 + +SIM\_SOPT7 field descriptions (continued) +Field +Description +0110 +PIT trigger 2 +0111 +PIT trigger 3 +1000 +FTM0 trigger +1001 +FTM1 trigger +1010 +FTM2 trigger +1011 +Unused +1100 +RTC alarm +1101 +RTC seconds +1110 +Low-power timer trigger +1111 +Unused +7 +ADC0ALTTRGEN +ADC0 alternate trigger enable +Enable alternative conversion triggers for ADC0. +0 +PDB trigger selected for ADC0. +1 +Alternate trigger selected for ADC0. +6–5 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +4 +ADC0PRETRGSEL +ADC0 pretrigger select +Selects the ADC0 pre-trigger source when alternative triggers are enabled through ADC0ALTTRGEN. +0 +Pre-trigger A +1 +Pre-trigger B +3–0 +ADC0TRGSEL +ADC0 trigger select +Selects the ADC0 trigger source when alternative triggers are functional in stop and VLPS modes. . +0000 +PDB external trigger pin input (PDB0\_EXTRG) +0001 +High speed comparator 0 output +0010 +High speed comparator 1 output +0011 +High speed comparator 2 output +0100 +PIT trigger 0 +0101 +PIT trigger 1 +0110 +PIT trigger 2 +0111 +PIT trigger 3 +1000 +FTM0 trigger +1001 +FTM1 trigger +1010 +FTM2 trigger +1011 +Unused +1100 +RTC alarm +1101 +RTC seconds +1110 +Low-power timer trigger +1111 +Unused +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +298 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 298](pdf-image://page_298_img_1) + +## Page 299 + +12.2.7 +System Device Identification Register (SIM\_SDID) +Address: 4004\_7000h base + 1024h offset = 4004\_8024h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +REVID +0 +0 +0 +1 +0 +FAMID +PINID +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +SIM\_SDID field descriptions +Field +Description +31–16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15–12 +REVID +Device revision number +Specifies the silicon implementation number for the device. +11 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +10 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +9 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 1. +7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +6–4 +FAMID +Kinetis family identification +Specifies the Kinetis family of the device. +000 +K10 +001 +K20 +010 +K30 +011 +K40 +100 +K60 +101 +Reserved +110 +K50and K52 +111 +K51and K53 +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +299 +General Business Information + +![Image 1 from page 299](pdf-image://page_299_img_1) + +## Page 300 + +SIM\_SDID field descriptions (continued) +Field +Description +3–0 +PINID +Pincount identification +Specifies the pincount of the device. +0000 +Reserved +0001 +Reserved +0010 +Reserved +0011 +Reserved +0100 +Reserved +0101 +Reserved +0110 +80-pin +0111 +81-pin +1000 +100-pin +1001 +121-pin +1010 +144-pin +1011 +Reserved +1100 +Reserved +1101 +Reserved +1110 +Reserved +1111 +Reserved +12.2.8 +System Clock Gating Control Register 1 (SIM\_SCGC1) +Address: 4004\_7000h base + 1028h offset = 4004\_8028h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +0 +0 +0 +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +UART5 +UART4 +0 +0 +0 +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +SIM\_SCGC1 field descriptions +Field +Description +31–25 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +24 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +300 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 300](pdf-image://page_300_img_1) + +## Page 301 + +SIM\_SCGC1 field descriptions (continued) +Field +Description +23–22 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +21 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +20–12 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +11 +UART5 +UART5 Clock Gate Control +This bit controls the clock gate to the UART5 module. +0 +Clock disabled +1 +Clock enabled +10 +UART4 +UART4 Clock Gate Control +This bit controls the clock gate to the UART4 module. +0 +Clock disabled +1 +Clock enabled +9–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +12.2.9 +System Clock Gating Control Register 2 (SIM\_SCGC2) +Address: 4004\_7000h base + 102Ch offset = 4004\_802Ch +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +DAC1 +DAC0 +0 +ENET +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +301 +General Business Information + +![Image 1 from page 301](pdf-image://page_301_img_1) + +## Page 302 + +SIM\_SCGC2 field descriptions +Field +Description +31–14 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +13 +DAC1 +DAC1 Clock Gate Control +This bit controls the clock gate to the DAC1 module. +0 +Clock disabled +1 +Clock enabled +12 +DAC0 +DAC0 Clock Gate Control +This bit controls the clock gate to the DAC0 module. +0 +Clock disabled +1 +Clock enabled +11–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +ENET +ENET Clock Gate Control +This bit controls the clock gate to the ENET module. +0 +Clock disabled +1 +Clock enabled +12.2.10 +System Clock Gating Control Register 3 (SIM\_SCGC3) +Address: 4004\_7000h base + 1030h offset = 4004\_8030h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +0 +0 +ADC1 +0 +0 +FTM2 +0 +SDHC +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +SPI2 +0 +FLEXCAN1 +0 +RNGA +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +SIM\_SCGC3 field descriptions +Field +Description +31 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +302 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 302](pdf-image://page_302_img_1) + +## Page 303 + +SIM\_SCGC3 field descriptions (continued) +Field +Description +30 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +29–28 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +27 +ADC1 +ADC1 Clock Gate Control +This bit controls the clock gate to the ADC1 module. +0 +Clock disabled +1 +Clock enabled +26 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +25 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +24 +FTM2 +FTM2 Clock Gate Control +This bit controls the clock gate to the FTM2 module. +0 +Clock disabled +1 +Clock enabled +23–18 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +17 +SDHC +SDHC Clock Gate Control +This bit controls the clock gate to the SDHC module. +0 +Clock disabled +1 +Clock enabled +16–13 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +12 +SPI2 +SPI2 Clock Gate Control +This bit controls the clock gate to the SPI2 module. +0 +Clock disabled +1 +Clock enabled +11–5 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +4 +FLEXCAN1 +FlexCAN1 Clock Gate Control +This bit controls the clock gate to the FlexCAN1 module. +0 +Clock disabled +1 +Clock enabled +3–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +RNGA +RNGA Clock Gate Control +This bit controls the clock gate to the RNGA module. +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +303 +General Business Information + +![Image 1 from page 303](pdf-image://page_303_img_1) + +## Page 304 + +SIM\_SCGC3 field descriptions (continued) +Field +Description +0 +Clock disabled +1 +Clock enabled +12.2.11 +System Clock Gating Control Register 4 (SIM\_SCGC4) +Address: 4004\_7000h base + 1034h offset = 4004\_8034h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +1 +LLWU +0 +VREF +CMP +USBOTG +0 +W +Reset +1 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +UART3 +UART2 +UART1 +UART0 +0 +I2C1 +I2C0 +1 +0 +CMT +EWM +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +SIM\_SCGC4 field descriptions +Field +Description +31–29 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 1. +28 +LLWU +LLWU Clock Gate Control +This bit controls software access to the LLWU module. +0 +Access disabled +1 +Access enabled +27–21 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +20 +VREF +VREF Clock Gate Control +This bit controls the clock gate to the VREF module. +0 +Clock disabled +1 +Clock enabled +19 +CMP +Comparator Clock Gate Control +This bit controls the clock gate to the comparator module. +0 +Clock disabled +1 +Clock enabled +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +304 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 304](pdf-image://page_304_img_1) + +## Page 305 + +SIM\_SCGC4 field descriptions (continued) +Field +Description +18 +USBOTG +USB Clock Gate Control +This bit controls the clock gate to the USB module. +0 +Clock disabled +1 +Clock enabled +17–14 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +13 +UART3 +UART3 Clock Gate Control +This bit controls the clock gate to the UART3 module. +0 +Clock disabled +1 +Clock enabled +12 +UART2 +UART2 Clock Gate Control +This bit controls the clock gate to the UART2 module. +0 +Clock disabled +1 +Clock enabled +11 +UART1 +UART1 Clock Gate Control +This bit controls the clock gate to the UART1 module. +0 +Clock disabled +1 +Clock enabled +10 +UART0 +UART0 Clock Gate Control +This bit controls the clock gate to the UART0 module. +0 +Clock disabled +1 +Clock enabled +9–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7 +I2C1 +I2C1 Clock Gate Control +This bit controls the clock gate to the I 2 C1 module. +0 +Clock disabled +1 +Clock enabled +6 +I2C0 +I2C0 Clock Gate Control +This bit controls the clock gate to the I 2 C0 module. +0 +Clock disabled +1 +Clock enabled +5–4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 1. +3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +305 +General Business Information + +![Image 1 from page 305](pdf-image://page_305_img_1) + +## Page 306 + +SIM\_SCGC4 field descriptions (continued) +Field +Description +2 +CMT +CMT Clock Gate Control +This bit controls the clock gate to the CMT module. +0 +Clock disabled +1 +Clock enabled +1 +EWM +EWM Clock Gate Control +This bit controls the clock gate to the EWM module. +0 +Clock disabled +1 +Clock enabled +0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +12.2.12 +System Clock Gating Control Register 5 (SIM\_SCGC5) +Address: 4004\_7000h base + 1038h offset = 4004\_8038h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +1 +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +PORTE +PORTD +PORTC +PORTB +PORTA +1 +0 +TSI +0 +0 +1 +LPTIMER +W +Reset +0 +0 +0 +0 +0 +0 +0 +1 +1 +0 +0 +0 +0 +0 +1 +0 +SIM\_SCGC5 field descriptions +Field +Description +31–19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 1. +17–14 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +13 +PORTE +Port E Clock Gate Control +This bit controls the clock gate to the Port E module. +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +306 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 306](pdf-image://page_306_img_1) + +## Page 307 + +SIM\_SCGC5 field descriptions (continued) +Field +Description +0 +Clock disabled +1 +Clock enabled +12 +PORTD +Port D Clock Gate Control +This bit controls the clock gate to the Port D module. +0 +Clock disabled +1 +Clock enabled +11 +PORTC +Port C Clock Gate Control +This bit controls the clock gate to the Port C module. +0 +Clock disabled +1 +Clock enabled +10 +PORTB +Port B Clock Gate Control +This bit controls the clock gate to the Port B module. +0 +Clock disabled +1 +Clock enabled +9 +PORTA +Port A Clock Gate Control +This bit controls the clock gate to the Port A module. +0 +Clock disabled +1 +Clock enabled +8–7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 1. +6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5 +TSI +TSI Clock Gate Control +This bit controls the clock gate to the TSI module. +0 +Clock disabled +1 +Clock enabled +4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3–2 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 1. +0 +LPTIMER +Low Power Timer Access Control +This bit controls software access to the Low Power Timer module. +0 +Access disabled +1 +Access enabled +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +307 +General Business Information + +![Image 1 from page 307](pdf-image://page_307_img_1) + +## Page 308 + +12.2.13 +System Clock Gating Control Register 6 (SIM\_SCGC6) +Address: 4004\_7000h base + 103Ch offset = 4004\_803Ch +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +1 +RTC +0 +ADC0 +0 +FTM1 +FTM0 +PIT +PDB +USBDCD +0 +CRC +0 +W +Reset +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +I2S +0 +SPI1 +SPI0 +0 +0 +0 +FLEXCAN0 +0 +DMAMUX +FTFL +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +SIM\_SCGC6 field descriptions +Field +Description +31 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +30 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 1. +29 +RTC +RTC Access Control +This bit controls software access and interrupts to the RTC module. +0 +Access and interrupts disabled +1 +Access and interrupts enabled +28 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +27 +ADC0 +ADC0 Clock Gate Control +This bit controls the clock gate to the ADC0 module. +0 +Clock disabled +1 +Clock enabled +26 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +25 +FTM1 +FTM1 Clock Gate Control +This bit controls the clock gate to the FTM1 module. +0 +Clock disabled +1 +Clock enabled +24 +FTM0 +FTM0 Clock Gate Control +This bit controls the clock gate to the FTM0 module. +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +308 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 308](pdf-image://page_308_img_1) + +## Page 309 + +SIM\_SCGC6 field descriptions (continued) +Field +Description +0 +Clock disabled +1 +Clock enabled +23 +PIT +PIT Clock Gate Control +This bit controls the clock gate to the PIT module. +0 +Clock disabled +1 +Clock enabled +22 +PDB +PDB Clock Gate Control +This bit controls the clock gate to the PDB module. +0 +Clock disabled +1 +Clock enabled +21 +USBDCD +USB DCD Clock Gate Control +This bit controls the clock gate to the USB DCD module. +0 +Clock disabled +1 +Clock enabled +20–19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18 +CRC +CRC Clock Gate Control +This bit controls the clock gate to the CRC module. +0 +Clock disabled +1 +Clock enabled +17–16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15 +I2S +I2S Clock Gate Control +This bit controls the clock gate to the I 2 S module. +0 +Clock disabled +1 +Clock enabled +14 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +13 +SPI1 +SPI1 Clock Gate Control +This bit controls the clock gate to the SPI1 module. +0 +Clock disabled +1 +Clock enabled +12 +SPI0 +SPI0 Clock Gate Control +This bit controls the clock gate to the SPI0 module. +0 +Clock disabled +1 +Clock enabled +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +309 +General Business Information + +![Image 1 from page 309](pdf-image://page_309_img_1) + +## Page 310 + +SIM\_SCGC6 field descriptions (continued) +Field +Description +11–10 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +9 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +8–5 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +4 +FLEXCAN0 +FlexCAN0 Clock Gate Control +This bit controls the clock gate to the FlexCAN0 module. +0 +Clock disabled +1 +Clock enabled +3–2 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +1 +DMAMUX +DMA Mux Clock Gate Control +This bit controls the clock gate to the DMA Mux module. +0 +Clock disabled +1 +Clock enabled +0 +FTFL +Flash Memory Clock Gate Control +This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory +is clock gated, but entry into low power modes is blocked. +0 +Clock disabled +1 +Clock enabled +12.2.14 +System Clock Gating Control Register 7 (SIM\_SCGC7) +Address: 4004\_7000h base + 1040h offset = 4004\_8040h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +MPU +DMA +FLEXBUS +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +310 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 310](pdf-image://page_310_img_1) + +## Page 311 + +SIM\_SCGC7 field descriptions +Field +Description +31–3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2 +MPU +MPU Clock Gate Control +This bit controls the clock gate to the MPU module. +0 +Clock disabled +1 +Clock enabled +1 +DMA +DMA Clock Gate Control +This bit controls the clock gate to the DMA module. +0 +Clock disabled +1 +Clock enabled +0 +FLEXBUS +FlexBus Clock Gate Control +This bit controls the clock gate to the FlexBus module. +0 +Clock disabled +1 +Clock enabled +12.2.15 +System Clock Divider Register 1 (SIM\_CLKDIV1) +NOTE +The CLKDIV1 register cannot be written to when the device is +in VLPR mode. +Address: 4004\_7000h base + 1044h offset = 4004\_8044h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +OUTDIV1 +OUTDIV2 +OUTDIV3 +OUTDIV4 +0 +W +Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 1* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* +* Notes: +Reset value loaded during Syetem Reset from FTFL\_FOPT[LPBOOT]. +• +SIM\_CLKDIV1 field descriptions +Field +Description +31–28 +OUTDIV1 +Clock 1 output divider value +This field sets the divide value for the core/system clock. At the end of reset, it is loaded with either 0000 +or 0111 depending on FTFL\_FOPT[LPBOOT]. +0000 +Divide-by-1. +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +311 +General Business Information + +![Image 1 from page 311](pdf-image://page_311_img_1) + +## Page 312 + +SIM\_CLKDIV1 field descriptions (continued) +Field +Description +0001 +Divide-by-2. +0010 +Divide-by-3. +0011 +Divide-by-4. +0100 +Divide-by-5. +0101 +Divide-by-6. +0110 +Divide-by-7. +0111 +Divide-by-8. +1000 +Divide-by-9. +1001 +Divide-by-10. +1010 +Divide-by-11. +1011 +Divide-by-12. +1100 +Divide-by-13. +1101 +Divide-by-14. +1110 +Divide-by-15. +1111 +Divide-by-16. +27–24 +OUTDIV2 +Clock 2 output divider value +This field sets the divide value for the bus clock. At the end of reset, it is loaded with either 0000 or 0111 +depending on FTFL\_FOPT[LPBOOT]. +0000 +Divide-by-1. +0001 +Divide-by-2. +0010 +Divide-by-3. +0011 +Divide-by-4. +0100 +Divide-by-5. +0101 +Divide-by-6. +0110 +Divide-by-7. +0111 +Divide-by-8. +1000 +Divide-by-9. +1001 +Divide-by-10. +1010 +Divide-by-11. +1011 +Divide-by-12. +1100 +Divide-by-13. +1101 +Divide-by-14. +1110 +Divide-by-15. +1111 +Divide-by-16. +23–20 +OUTDIV3 +Clock 3 output divider value +This field sets the divide value for the FlexBus clock driven to the external pin (FB\_CLK). At the end of +reset, it is loaded with either 0001 or 1111 depending on FTFL\_FOPT[LPBOOT]. +0000 +Divide-by-1. +0001 +Divide-by-2. +0010 +Divide-by-3. +0011 +Divide-by-4. +0100 +Divide-by-5. +0101 +Divide-by-6. +0110 +Divide-by-7. +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +312 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 312](pdf-image://page_312_img_1) + +## Page 313 + +SIM\_CLKDIV1 field descriptions (continued) +Field +Description +0111 +Divide-by-8. +1000 +Divide-by-9. +1001 +Divide-by-10. +1010 +Divide-by-11. +1011 +Divide-by-12. +1100 +Divide-by-13. +1101 +Divide-by-14. +1110 +Divide-by-15. +1111 +Divide-by-16. +19–16 +OUTDIV4 +Clock 4 output divider value +This field sets the divide value for the flash clock. At the end of reset, it is loaded with either 0001 or 1111 +depending on FTFL\_FOPT[LPBOOT]. +0000 +Divide-by-1. +0001 +Divide-by-2. +0010 +Divide-by-3. +0011 +Divide-by-4. +0100 +Divide-by-5. +0101 +Divide-by-6. +0110 +Divide-by-7. +0111 +Divide-by-8. +1000 +Divide-by-9. +1001 +Divide-by-10. +1010 +Divide-by-11. +1011 +Divide-by-12. +1100 +Divide-by-13. +1101 +Divide-by-14. +1110 +Divide-by-15. +1111 +Divide-by-16. +15–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +313 +General Business Information + +![Image 1 from page 313](pdf-image://page_313_img_1) + +## Page 314 + +12.2.16 +System Clock Divider Register 2 (SIM\_CLKDIV2) +Address: 4004\_7000h base + 1048h offset = 4004\_8048h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +USBDIV +USBFRAC +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +SIM\_CLKDIV2 field descriptions +Field +Description +31–4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3–1 +USBDIV +USB clock divider divisor +This field sets the divide value for the fractional clock divider when the MCGFLLCLK/MCGPLLCLK clock is +the USB clock source (SOPT2[USBSRC] = 1). +Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] +0 +USBFRAC +USB clock divider fraction +This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK/ +MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1). +Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ] +12.2.17 +Flash Configuration Register 1 (SIM\_FCFG1) +For devices with FlexNVM: The reset value of EESIZE and DEPART are based on user +programming in user IFR via the PGMPART flash command. +For devices with program flash only: The EESIZE and DEPART filelds are not +applicable. +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +314 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 314](pdf-image://page_314_img_1) + +## Page 315 + +Address: 4004\_7000h base + 104Ch offset = 4004\_804Ch +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +NVMSIZE +PFSIZE +0 +EESIZE +W +Reset +1\* +1\* +1\* +1\* +1\* +1\* +1\* +1\* +0\* +0\* +0\* +0\* +1\* +1\* +1\* +1\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +DEPART +0 +FLASHDOZE +FLASHDIS +W +Reset +0\* +0\* +0\* +0\* +1\* +1\* +1\* +1\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +* Notes: +Reset value loaded during System Reset from Flash IFR. +• +SIM\_FCFG1 field descriptions +Field +Description +31–28 +NVMSIZE +FlexNVM size +This field specifies the amount of FlexNVM memory available on the device . Undefined values are +reserved. +0000 +0 KB of FlexNVM +0111 +128 KB of FlexNVM, 32 KB protection region +1001 +256 KB of FlexNVM, 32 KB protection region +27–24 +PFSIZE +Program flash size +This field specifies the amount of program flash memory available on the device . Undefined values are +reserved. +0111 +128 KB of program flash, 4 KB protection region +1001 +256 KB of program flash, 8 KB protection region +1011 +512 KB of program flash, 16 KB protection region +23–20 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +315 +General Business Information + +![Image 1 from page 315](pdf-image://page_315_img_1) + +## Page 316 + +SIM\_FCFG1 field descriptions (continued) +Field +Description +19–16 +EESIZE +EEPROM size +EEPROM data size . +0000 +Reserved +0001 +Reserved +0010 +4 KB +0011 +0100 +1 KB +0101 +512 Bytes +0110 +256 Bytes +0111 +128 Bytes +1000 +64 Bytes +1001 +32 Bytes +1010-1110 +Reserved +1111 +0 Bytes +15–12 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +11–8 +DEPART +FlexNVM partition +For devices with FlexNVM: Data flash / EEPROM backup split . See DEPART bit description in FTFL +chapter. +For devices without FlexNVM: Reserved +7–2 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +1 +FLASHDOZE +Flash Doze +When set, Flash memory is disabled for the duration of Wait mode. An attempt by the DMA or other bus +master to access the Flash when the Flash is disabled will result in a bus error. This bit should be clear +during VLP modes. The Flash will be automatically enabled again at the end of Wait mode so interrupt +vectors do not need to be relocated out of Flash memory. The wakeup time from Wait mode is extended +when this bit is set. +0 +Flash remains enabled during Wait mode +1 +Flash is disabled for the duration of Wait mode +0 +FLASHDIS +Flash Disable +Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power +state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash +memory before disabling the Flash. +0 +Flash is enabled +1 +Flash is disabled +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +316 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 316](pdf-image://page_316_img_1) + +## Page 317 + +12.2.18 +Flash Configuration Register 2 (SIM\_FCFG2) +Address: 4004\_7000h base + 1050h offset = 4004\_8050h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +SWAPPFLSH +MAXADDR0 +PFLSH +MAXADDR1 +W +Reset +0\* +1\* +1\* +1\* +1\* +1\* +1\* +1\* +0\* +1\* +1\* +1\* +1\* +1\* +1\* +1\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +W +Reset +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +0\* +* Notes: +Reset value loaded during System Reset from Flash IFR. +• +SIM\_FCFG2 field descriptions +Field +Description +31 +SWAPPFLSH +Swap program flash +For devices without FlexNVM: Indicates that swap is active . +0 +Swap is not active. +1 +Swap is active. +30–24 +MAXADDR0 +Max address block 0 +Table continues on the next page... +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +317 +General Business Information + +![Image 1 from page 317](pdf-image://page_317_img_1) + +## Page 318 + +SIM\_FCFG2 field descriptions (continued) +Field +Description +This field concatenated with leading zeros indicates the first invalid address of flash block 0 (program flash +0). +For example, if MAXADDR0 = 0x20 the first invalid address of flash block 0 is 0x0004\_0000. This would +be the MAXADDR0 value for a device with 256 KB program flash in flash block 0. +23 +PFLSH +Program flash +For devices with FlexNVM, this bit is always clear. +For devices without FlexNVM, this bit is always set. +0 +Physical flash block 1 is used as FlexNVM +Reserved for devices without FlexNVM +1 +Physical flash block 1 is used as program flash +22–16 +MAXADDR1 +Max address block 1 +For devices with FlexNVM: This field concatenated with leading zeros plus the FlexNVM base address +indicates the first invalid address of the FlexNVM (flash block 1). +For example, if MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4\_0000 + 0x1000\_0000 . +This would be the MAXADDR1 value for a device with 256 KB FlexNVM. +For devices with program flash only: This field concatenated with leading zeros plus the value of the +MAXADDR1 field indicates the first invalid address of the second program flash block (flash block 1). +For example, if MAXADDR0 = MAXADDR1 = 0x20 the first invalid address of flash block 1 is 0x4\_0000 + +0x4\_0000. This would be the MAXADDR1 value for a device with 512 KB program flash memory and no +FlexNVM. +15–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +12.2.19 +Unique Identification Register High (SIM\_UIDH) +Address: 4004\_7000h base + 1054h offset = 4004\_8054h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +UID +W +Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* +* Notes: +Reset value loaded during System Reset from Flash IFR. +• +SIM\_UIDH field descriptions +Field +Description +31–0 +UID +Unique Identification +Unique identification for the device. +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +318 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 318](pdf-image://page_318_img_1) + +## Page 319 + +12.2.20 +Unique Identification Register Mid-High (SIM\_UIDMH) +Address: 4004\_7000h base + 1058h offset = 4004\_8058h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +UID +W +Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* +* Notes: +Reset value loaded during System Reset from Flash IFR. +• +SIM\_UIDMH field descriptions +Field +Description +31–0 +UID +Unique Identification +Unique identification for the device. +12.2.21 +Unique Identification Register Mid Low (SIM\_UIDML) +Address: 4004\_7000h base + 105Ch offset = 4004\_805Ch +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +UID +W +Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* +* Notes: +Reset value loaded during System Reset from Flash IFR. +• +SIM\_UIDML field descriptions +Field +Description +31–0 +UID +Unique Identification +Unique identification for the device. +Chapter 12 System Integration Module (SIM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +319 +General Business Information + +![Image 1 from page 319](pdf-image://page_319_img_1) + +## Page 320 + +12.2.22 +Unique Identification Register Low (SIM\_UIDL) +Address: 4004\_7000h base + 1060h offset = 4004\_8060h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +UID +W +Reset 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* +* Notes: +Reset value loaded during System Reset from Flash IFR. +• +SIM\_UIDL field descriptions +Field +Description +31–0 +UID +Unique Identification +Unique identification for the device. +12.3 +Functional description +For more information about the functions of SIM, see the Introduction section. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +320 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 320](pdf-image://page_320_img_1) + +## Page 321 + +Chapter 13 +Reset Control Module (RCM) +13.1 +Introduction +This chapter describes the registers of the Reset Control Module (RCM). The RCM +implements many of the reset functions for the chip. See the chip's reset chapter for more +information. +13.2 +Reset memory map and register descriptions +The Reset Control Module (RCM) registers provide reset status information and reset +filter control. +RCM memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4007\_F000 +System Reset Status Register 0 (RCM\_SRS0) +8 +R +8282h +13.2.1/321 +4007\_F001 +System Reset Status Register 1 (RCM\_SRS1) +8 +R +000h +13.2.2/323 +4007\_F004 +Reset Pin Filter Control register (RCM\_RPFC) +8 +R/W +000h +13.2.3/324 +4007\_F005 +Reset Pin Filter Width register (RCM\_RPFW) +8 +R/W +000h +13.2.4/325 +4007\_F007 +Mode Register (RCM\_MR) +8 +R +000h +13.2.5/327 +13.2.1 +System Reset Status Register 0 (RCM\_SRS0) +This register includes read-only status flags to indicate the source of the most recent +reset. The reset state of these bits depends on what caused the MCU to reset. +NOTE +The reset value of this register depends on the reset source: +• POR (including LVD) — 0x82 +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +321 +General Business Information + +![Image 1 from page 321](pdf-image://page_321_img_1) + +## Page 322 + +• LVD (without POR) — 0x02 +• VLLS mode wakeup due to RESET pin assertion — 0x41 +• VLLS mode wakeup due to other wakeup sources — 0x01 +• Other reset — a bit is set if its corresponding reset source +caused the reset +Address: 4007\_F000h base + 0h offset = 4007\_F000h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +POR +PIN +WDOG +0 +LOL +LOC +LVD +WAKEUP +Write +Reset +1 +0 +0 +0 +0 +0 +1 +0 +RCM\_SRS0 field descriptions +Field +Description +7 +POR +Power-On Reset +Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage +was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset +occurred while the internal supply was below the LVD threshold. +0 +Reset not caused by POR +1 +Reset caused by POR +6 +PIN +External Reset Pin +Indicates a reset has been caused by an active-low level on the external RESET pin. +0 +Reset not caused by external reset pin +1 +Reset caused by external reset pin +5 +WDOG +Watchdog +Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by +disabling the watchdog. +0 +Reset not caused by watchdog timeout +1 +Reset caused by watchdog timeout +4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3 +LOL +Loss-of-Lock Reset +Indicates a reset has been caused by a loss of lock in the MCG PLL. See the MCG description for +information on the loss-of-clock event. +0 +Reset not caused by a loss of lock in the PLL +1 +Reset caused by a loss of lock in the PLL +2 +LOC +Loss-of-Clock Reset +Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled +for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the +clock monitor. +Table continues on the next page... +Reset memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +322 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 322](pdf-image://page_322_img_1) + +## Page 323 + +RCM\_SRS0 field descriptions (continued) +Field +Description +0 +Reset not caused by a loss of external clock. +1 +Reset caused by a loss of external clock. +1 +LVD +Low-Voltage Detect Reset +If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is +also set by POR. +0 +Reset not caused by LVD trip or POR +1 +Reset caused by LVD trip or POR +0 +WAKEUP +Low Leakage Wakeup Reset +Indicates a reset has been caused by an enabled LLWU module wakeup source while the chip was in a +low leakage mode. In LLS mode, the RESET pin is the only wakeup source that can cause this reset. Any +enabled wakeup source in a VLLSx mode causes a reset. This bit is cleared by any reset except +WAKEUP. +0 +Reset not caused by LLWU module wakeup source +1 +Reset caused by LLWU module wakeup source +13.2.2 +System Reset Status Register 1 (RCM\_SRS1) +This register includes read-only status flags to indicate the source of the most recent +reset. The reset state of these bits depends on what caused the MCU to reset. +NOTE +The reset value of this register depends on the reset source: +• POR (including LVD) — 0x00 +• LVD (without POR) — 0x00 +• VLLS mode wakeup — 0x00 +• Other reset — a bit is set if its corresponding reset source +caused the reset +Address: 4007\_F000h base + 1h offset = 4007\_F001h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +SACKERR +EZPT +MDM\_AP +SW +LOCKUP +JTAG +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +RCM\_SRS1 field descriptions +Field +Description +7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Chapter 13 Reset Control Module (RCM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +323 +General Business Information + +![Image 1 from page 323](pdf-image://page_323_img_1) + +## Page 324 + +RCM\_SRS1 field descriptions (continued) +Field +Description +6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5 +SACKERR +Stop Mode Acknowledge Error Reset +Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more +peripherals to acknowledge within approximately one second to enter stop mode. +0 +Reset not caused by peripheral failure to acknowledge attempt to enter stop mode +1 +Reset caused by peripheral failure to acknowledge attempt to enter stop mode +4 +EZPT +EzPort Reset +Indicates a reset has been caused by EzPort receiving the RESET command while the device is in EzPort +mode. +0 +Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode +1 +Reset caused by EzPort receiving the RESET command while the device is in EzPort mode +3 +MDM\_AP +MDM-AP System Reset Request +Indicates a reset has been caused by the host debugger system setting of the System Reset Request bit +in the MDM-AP Control Register. +0 +Reset not caused by host debugger system setting of the System Reset Request bit +1 +Reset caused by host debugger system setting of the System Reset Request bit +2 +SW +Software +Indicates a reset has been caused by software setting of SYSRESETREQ bit in Application Interrupt and +Reset Control Register in the ARM core. +0 +Reset not caused by software setting of SYSRESETREQ bit +1 +Reset caused by software setting of SYSRESETREQ bit +1 +LOCKUP +Core Lockup +Indicates a reset has been caused by the ARM core indication of a LOCKUP event. +0 +Reset not caused by core LOCKUP event +1 +Reset caused by core LOCKUP event +0 +JTAG +JTAG Generated Reset +Indicates a reset has been caused by JTAG selection of certain IR codes: EZPORT, EXTEST, HIGHZ, +and CLAMP. +0 +Reset not caused by JTAG +1 +Reset caused by JTAG +13.2.3 +Reset Pin Filter Control register (RCM\_RPFC) +NOTE +The reset values of bits 2-0 are for Chip POR only. They are +unaffected by other reset types. +Reset memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +324 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 324](pdf-image://page_324_img_1) + +## Page 325 + +NOTE +The bus clock filter is reset when disabled or when entering +stop mode. The LPO filter is reset when disabled or when +entering any low leakage stop mode . +Address: 4007\_F000h base + 4h offset = 4007\_F004h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +RSTFLTSS +RSTFLTSRW +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +RCM\_RPFC field descriptions +Field +Description +7–3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2 +RSTFLTSS +Reset Pin Filter Select in Stop Mode +Selects how the reset pin filter is enabled in Stop and VLPS modes . +0 +All filtering disabled +1 +LPO clock filter enabled +1–0 +RSTFLTSRW +Reset Pin Filter Select in Run and Wait Modes +Selects how the reset pin filter is enabled in run and wait modes. +00 +All filtering disabled +01 +Bus clock filter enabled for normal operation +10 +LPO clock filter enabled for normal operation +11 +Reserved +13.2.4 +Reset Pin Filter Width register (RCM\_RPFW) +NOTE +The reset values of the bits in the RSTFLTSEL field are for +Chip POR only. They are unaffected by other reset types. +Address: 4007\_F000h base + 5h offset = 4007\_F005h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +RSTFLTSEL +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 13 Reset Control Module (RCM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +325 +General Business Information + +![Image 1 from page 325](pdf-image://page_325_img_1) + +## Page 326 + +RCM\_RPFW field descriptions +Field +Description +7–5 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +4–0 +RSTFLTSEL +Reset Pin Filter Bus Clock Select +Selects the reset pin bus clock filter width. +00000 +Bus clock filter count is 1 +00001 +Bus clock filter count is 2 +00010 +Bus clock filter count is 3 +00011 +Bus clock filter count is 4 +00100 +Bus clock filter count is 5 +00101 +Bus clock filter count is 6 +00110 +Bus clock filter count is 7 +00111 +Bus clock filter count is 8 +01000 +Bus clock filter count is 9 +01001 +Bus clock filter count is 10 +01010 +Bus clock filter count is 11 +01011 +Bus clock filter count is 12 +01100 +Bus clock filter count is 13 +01101 +Bus clock filter count is 14 +01110 +Bus clock filter count is 15 +01111 +Bus clock filter count is 16 +10000 +Bus clock filter count is 17 +10001 +Bus clock filter count is 18 +10010 +Bus clock filter count is 19 +10011 +Bus clock filter count is 20 +10100 +Bus clock filter count is 21 +10101 +Bus clock filter count is 22 +10110 +Bus clock filter count is 23 +10111 +Bus clock filter count is 24 +11000 +Bus clock filter count is 25 +11001 +Bus clock filter count is 26 +11010 +Bus clock filter count is 27 +11011 +Bus clock filter count is 28 +11100 +Bus clock filter count is 29 +11101 +Bus clock filter count is 30 +11110 +Bus clock filter count is 31 +11111 +Bus clock filter count is 32 +Reset memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +326 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 326](pdf-image://page_326_img_1) + +## Page 327 + +13.2.5 +Mode Register (RCM\_MR) +This register includes read-only status flags to indicate the state of the mode pins during +the last Chip Reset. +Address: 4007\_F000h base + 7h offset = 4007\_F007h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +EZP\_MS +0 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +RCM\_MR field descriptions +Field +Description +7–2 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +1 +EZP\_MS +EZP\_MS\_B pin state +Reflects the state of the EZP\_MS pin during the last Chip Reset +0 +Pin deasserted (logic 1) +1 +Pin asserted (logic 0) +0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Chapter 13 Reset Control Module (RCM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +327 +General Business Information + +![Image 1 from page 327](pdf-image://page_327_img_1) + +## Page 328 + +Reset memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +328 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 328](pdf-image://page_328_img_1) + +## Page 329 + +Chapter 14 +System Mode Controller +14.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The system mode controller (SMC) is responsible for sequencing the system into and out +of all low power stop and run modes. Specifically, it monitors events to trigger transitions +between power modes while controlling the power, clocks, and memories of the system +to achieve the power consumption and functionality of that mode. +This chapter describes all the available low power modes, the sequence followed to enter/ +exit each mode, and the functionality available while in each of the modes. +The SMC is able to function during even the deepest low power modes. +14.2 +Modes of operation +The ARM CPU has three primary modes of operation: +• Run +• Sleep +• Deep Sleep +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +329 +General Business Information + +![Image 1 from page 329](pdf-image://page_329_img_1) + +## Page 330 + +The WFI or WFE instruction is used to invoke Sleep and Deep Sleep modes. Run, wait +and stop are the common terms used for the primary operating modes of Freescale +microcontrollers. The following table shows the translation between the ARM CPU +modes and the Freescale MCU power modes. +ARM CPU mode +MCU mode +Sleep +Wait +Deep Sleep +Stop +Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the +Freescale MCU documentation normally uses wait and stop. +In addition, Freescale MCUs also augment stop, wait, and run modes in a number of +ways. The power management controller (PMC) contains a run and a stop mode +regulator. Run regulation is used in normal run, wait and stop modes. Stop mode +regulation is used during all very low power and low leakage modes. During stop mode +regulation, the bus frequencies are limited in the very low power modes. +The SMC provides the user with multiple power options. The Very Low Power Run +(VLPR) mode can drastically reduce run time power when maximum bus frequency is +not required to handle the application needs. From Normal Run mode, the Run Mode +(RUNM) field can be modified to change the MCU into VLPR mode when limited +frequency is sufficient for the application. From VLPR mode, a corresponding wait +(VLPW) and stop (VLPS) mode can be entered. +Depending on the needs of the user application, a variety of stop modes are available that +allow the state retention, partial power down or full power down of certain logic and/or +memory. I/O states are held in all modes of operation. Several registers are used to +configure the various modes of operation for the device. +The following table describes the power modes available for the device. +Table 14-1. Power modes +Mode +Description +RUN +The MCU can be run at full speed and the internal supply is fully regulated, that is, in run regulation. +This mode is also referred to as Normal Run mode. +WAIT +The core clock is gated off. The system clock continues to operate. Bus clocks, if enabled, continue +to operate. Run regulation is maintained. +STOP +The core clock is gated off. System clocks to other masters and bus clocks are gated off after all +stop acknowledge signals from supporting peripherals are valid. +VLPR +The core, system, bus, and flash clock maximum frequencies are restricted in this mode. See the +Power Management chapter for details about the maximum allowable frequencies. +Table continues on the next page... +Modes of operation +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +330 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 330](pdf-image://page_330_img_1) + +## Page 331 + +Table 14-1. Power modes (continued) +Mode +Description +VLPW +The core clock is gated off. The system, bus, and flash clocks continue to operate, although their +maximum frequency is restricted. See the Power Management chapter for details on the maximum +allowable frequencies. +VLPS +The core clock is gated off. System clocks to other masters and bus clocks are gated off after all +stop acknowledge signals from supporting peripherals are valid. +LLS +The core clock is gated off. System clocks to other masters and bus clocks are gated off after all +stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low +leakage mode by reducing the voltage to internal logic. Internal logic states are retained. +VLLS3 +The core clock is gated off. System clocks to other masters and bus clocks are gated off after all +stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low +leakage mode by powering down the internal logic. All system RAM contents are retained and I/O +states are held. Internal logic states are not retained. +VLLS2 +The core clock is gated off. System clocks to other masters and bus clocks are gated off after all +stop acknowledge signals from supporting peripherals are valid.The MCU is placed in a low leakage +mode by powering down the internal logic and the system RAM3 partition. The system RAM2 +partition can be optionally retained using VLLSCTRL[RAM2PO]. The system RAM1 partition +contents are retained in this mode. Internal logic states are not retained. 1 +VLLS1 +The core clock is gated off. System clocks to other masters and bus clocks are gated off after all +stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low +leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal +logic states are not retained. +1. +See the devices' chip configuration details for the size and location of the system RAM partitions. +14.3 +Memory map and register descriptions +Details follow about the registers related to the system mode controller. +Different SMC registers reset on different reset types. Each register's description provides +details. For more information about the types of reset on this chip, refer to the Reset +section details. +SMC memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4007\_E000 +Power Mode Protection register (SMC\_PMPROT) +8 +R/W +000h +14.3.1/332 +4007\_E001 +Power Mode Control register (SMC\_PMCTRL) +8 +R/W +000h +14.3.2/333 +4007\_E002 +VLLS Control register (SMC\_VLLSCTRL) +8 +R/W +033h +14.3.3/334 +4007\_E003 +Power Mode Status register (SMC\_PMSTAT) +8 +R +011h +14.3.4/335 +Chapter 14 System Mode Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +331 +General Business Information + +![Image 1 from page 331](pdf-image://page_331_img_1) + +## Page 332 + +14.3.1 +Power Mode Protection register (SMC\_PMPROT) +This register provides protection for entry into any low-power run or stop mode. The +enabling of the low-power run or stop mode occurs by configuring the Power Mode +Control register (PMCTRL). +The PMPROT register can be written only once after any system reset. +If the MCU is configured for a disallowed or reserved power mode, the MCU remains in +its current power mode. For example, if the MCU is in normal RUN mode and AVLP is +0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and the RUNM +bits remain 00b, indicating the MCU is still in Normal Run mode. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the Reset +section details for more information. +Address: 4007\_E000h base + 0h offset = 4007\_E000h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +AVLP +0 +ALLS +0 +AVLLS +0 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +SMC\_PMPROT field descriptions +Field +Description +7–6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5 +AVLP +Allow Very-Low-Power Modes +Provided the appropriate control bits are set up in PMCTRL, this write-once bit allows the MCU to enter +any very-low-power modes: VLPR, VLPW, and VLPS. +0 +VLPR, VLPW and VLPS are not allowed +1 +VLPR, VLPW and VLPS are allowed +4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3 +ALLS +Allow Low-Leakage Stop Mode +This write once bit allows the MCU to enter any low-leakage stop mode (LLS), provided the appropriate +control bits are set up in PMCTRL. +0 +LLS is not allowed +1 +LLS is allowed +Table continues on the next page... +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +332 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 332](pdf-image://page_332_img_1) + +## Page 333 + +SMC\_PMPROT field descriptions (continued) +Field +Description +2 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +1 +AVLLS +Allow Very-Low-Leakage Stop Mode +Provided the appropriate control bits are set up in PMCTRL, this write once bit allows the MCU to enter +any very-low-leakage stop mode (VLLSx). +0 +Any VLLSx mode is not allowed +1 +Any VLLSx mode is allowed +0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +14.3.2 +Power Mode Control register (SMC\_PMCTRL) +The PMCTRL register controls entry into low-power run and stop modes, provided that +the selected power mode is allowed via an appropriate setting of the protection +(PMPROT) register. +NOTE +This register is reset on Chip POR not VLLS and by reset types +that trigger Chip POR not VLLS. It is unaffected by reset types +that do not trigger Chip POR not VLLS. See the Reset section +details for more information. +Address: 4007\_E000h base + 1h offset = 4007\_E001h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +LPWUI +RUNM +0 +STOPA +STOPM +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +SMC\_PMCTRL field descriptions +Field +Description +7 +LPWUI +Low-Power Wake Up On Interrupt +Causes the SMC to exit to normal RUN mode when any active MCU interrupt occurs while in a VLP mode +(VLPR, VLPW or VLPS). +NOTE: If VLPS mode was entered directly from RUN mode, the SMC will always exit back to normal +RUN mode regardless of the LPWUI setting. +NOTE: LPWUI must be modified only while the system is in RUN mode, that is, when PMSTAT=RUN. +0 +The system remains in a VLP mode on an interrupt +1 +The system exits to Normal RUN mode on an interrupt +Table continues on the next page... +Chapter 14 System Mode Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +333 +General Business Information + +![Image 1 from page 333](pdf-image://page_333_img_1) + +## Page 334 + +SMC\_PMCTRL field descriptions (continued) +Field +Description +6–5 +RUNM +Run Mode Control +When written, causes entry into the selected run mode. Writes to this field are blocked if the protection +level has not been enabled using the PMPROT register. This field is cleared by hardware on any exit to +normal RUN mode. +NOTE: RUNM must be set to VLPR only when PMSTAT=RUN. After being written to VLPR, RUNM +should not be written back to RUN until PMSTAT=VLPR. +NOTE: RUNM must be set to RUN only when PMSTAT=VLPR. After being written to RUN, RUNM +should not be written back to VLPR until PMSTAT=RUN. +00 +Normal Run mode (RUN) +01 +Reserved +10 +Very-Low-Power Run mode (VLPR) +11 +Reserved +4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3 +STOPA +Stop Aborted +When set, this read-only status bit indicates an interrupt or reset occured during the previous stop mode +entry sequence, preventing the system from entering that mode. This bit is cleared by hardware at the +beginning of any stop mode entry sequence and is set if the sequence was aborted. +0 +The previous stop mode entry was successsful. +1 +The previous stop mode entry was aborted. +2–0 +STOPM +Stop Mode Control +When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is +entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled +using the PMPROT register. After any system reset, this field is cleared by hardware on any successful +write to the PMPROT register. +NOTE: When set to VLLSx, the VLLSM bits in the VLLSCTRL register is used to further select the +particular VLLS submode which will be entered. +NOTE: +000 +Normal Stop (STOP) +001 +Reserved +010 +Very-Low-Power Stop (VLPS) +011 +Low-Leakage Stop (LLS) +100 +Very-Low-Leakage Stop (VLLSx) +101 +Reserved +110 +Reseved +111 +Reserved +14.3.3 +VLLS Control register (SMC\_VLLSCTRL) +The VLLSCTRL register controls features related to VLLS modes. +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +334 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 334](pdf-image://page_334_img_1) + +## Page 335 + +NOTE +This register is reset on Chip POR not VLLS and by reset types +that trigger Chip POR not VLLS. It is unaffected by reset types +that do not trigger Chip POR not VLLS. See the Reset section +details for more information. +Address: 4007\_E000h base + 2h offset = 4007\_E002h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +RAM2PO +0 +VLLSM +Write +Reset +0 +0 +0 +0 +0 +0 +1 +1 +SMC\_VLLSCTRL field descriptions +Field +Description +7–6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +4 +RAM2PO +RAM2 Power Option +Controls powering of RAM partition 2 in VLLS2 mode. +NOTE: See the device's chip configuration details for the size and location of RAM parition 2 +0 +RAM2 not powered in VLLS2 +1 +RAM2 powered in VLLS2 +3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2–0 +VLLSM +VLLS Mode Control +Controls which VLLS sub-mode to enter if STOPM=VLLS. +000 +Reserved +001 +VLLS1 +010 +VLLS2 +011 +VLLS3 +100 +Reserved +101 +Reserved +110 +Reserved +111 +Reserved +14.3.4 +Power Mode Status register (SMC\_PMSTAT) +PMSTAT is a read-only, one-hot register which indicates the current power mode of the +system. +Chapter 14 System Mode Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +335 +General Business Information + +![Image 1 from page 335](pdf-image://page_335_img_1) + +## Page 336 + +NOTE +This register is reset on Chip POR not VLLS and by reset types +that trigger Chip POR not VLLS. It is unaffected by reset types +that do not trigger Chip POR not VLLS. See the Reset section +details for more information. +Address: 4007\_E000h base + 3h offset = 4007\_E003h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +PMSTAT +Write +Reset +0 +0 +0 +0 +0 +0 +0 +1 +SMC\_PMSTAT field descriptions +Field +Description +7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +6–0 +PMSTAT +NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS +000\_0001 +Current power mode is RUN +000\_0010 +Current power mode is STOP +000\_0100 +Current power mode is VLPR +000\_1000 +Current power mode is VLPW +001\_0000 +Current power mode is VLPS +010\_0000 +Current power mode is LLS +100\_0000 +Current power mode is VLLS +14.4 +Functional description +14.4.1 +Power mode transitions +The following figure shows the power mode state transitions available on the chip. Any +reset always brings the MCU back to the normal run state. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +336 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 336](pdf-image://page_336_img_1) + +## Page 337 + +WAIT +STOP +RUN +LLS +VLLSx +VLPS +VLPR +VLPW +Any reset +4 +6 +7 +3 +1 +2 +8 +10 +11 +9 +5 +Figure 14-5. Power mode state diagram +The following table defines triggers for the various state transitions shown in the previous +figure. +Table 14-7. Power mode transition triggers +Transition \# +From +To +Trigger conditions +1 +RUN +WAIT +Sleep-now or sleep-on-exit modes entered with SLEEPDEEP +clear, controlled in System Control Register in ARM core. +See note.1 +WAIT +RUN +Interrupt or Reset +Table continues on the next page... +Chapter 14 System Mode Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +337 +General Business Information + +![Image 1 from page 337](pdf-image://page_337_img_1) + +## Page 338 + +Table 14-7. Power mode transition triggers (continued) +Transition \# +From +To +Trigger conditions +2 +RUN +STOP +PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 +Sleep-now or sleep-on-exit modes entered with SLEEPDEEP +set, which is controlled in System Control Register in ARM +core. +See note.1 +STOP +RUN +Interrupt or Reset +3 +RUN +VLPR +Reduce system, bus and core frequency to 2 MHz or less, +Flash access limited to 1 MHz. +Set PMPROT[AVLP]=1, PMCTRL[RUNM]=10. +VLPR +RUN +Set PMCTRL[RUNM]=00 or +Interrupt with PMCTRL[LPWUI] =1 or +Reset. +4 +VLPR +VLPW +Sleep-now or sleep-on-exit modes entered with SLEEPDEEP +clear, which is controlled in System Control Register in ARM +core. +See note.1 +VLPW +VLPR +Interrupt with PMCTRL[LPWUI]=0 +5 +VLPW +RUN +Interrupt with PMCTRL[LPWUI]=1 or +Reset +6 +VLPR +VLPS +PMCTRL[STOPM]=000 or 010, +Sleep-now or sleep-on-exit modes entered with SLEEPDEEP +set, which is controlled in System Control Register in ARM +core. +See note.1 +VLPS +VLPR +Interrupt with PMCTRL[LPWUI]=0 +NOTE: If VLPS was entered directly from RUN, hardware +will not allow this transition and will force exit back to +RUN +7 +RUN +VLPS +PMPROT[AVLP]=1, PMCTRL[STOPM]=010, +Sleep-now or sleep-on-exit modes entered with SLEEPDEEP +set, which is controlled in System Control Register in ARM +core. +See note.1 +VLPS +RUN +Interrupt with PMCTRL[LPWUI]=1 or +Interrupt with PMCTRL[LPWUI]=0 and VLPS mode was +entered directly from RUN or +Reset +8 +RUN +VLLSx +PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, +VLLSCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit +modes entered with SLEEPDEEP set, which is controlled in +System Control Register in ARM core. +VLLSx +RUN +Wakeup from enabled LLWU input source or RESET pin +Table continues on the next page... +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +338 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 338](pdf-image://page_338_img_1) + +## Page 339 + +Table 14-7. Power mode transition triggers (continued) +Transition \# +From +To +Trigger conditions +9 +VLPR +VLLSx +PMPROT[AVLLS]=1, PMCTRL[STOPM]=100, +VLLSCTRL[VLLSM]=x (VLLSx), Sleep-now or sleep-on-exit +modes entered with SLEEPDEEP set, which is controlled in +System Control Register in ARM core. +10 +RUN +LLS +PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or +sleep-on-exit modes entered with SLEEPDEEP set, which is +controlled in System Control Register in ARM core. +LLS +RUN +Wakeup from enabled LLWU input source or RESET pin. +11 +VLPR +LLS +PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or +sleep-on-exit modes entered with SLEEPDEEP set, which is +controlled in System Control Register in ARM core. +1. +If debug is enabled, the core clock remains to support debug. +14.4.2 +Power mode entry/exit sequencing +When entering or exiting low-power modes, the system must conform to an orderly +sequence to manage transitions safely. The SMC manages the system's entry into and exit +from all power modes. The following diagram illustrates the connections of the SMC +with other system components in the chip that are necessary to sequence the system +through all power modes. +Chapter 14 System Mode Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +339 +General Business Information + +![Image 1 from page 339](pdf-image://page_339_img_1) + +## Page 340 + +System +Mode +Controller +(SMC) +System +Power +(PMC) +Low- +Leakage +Wakeup +(LLWU) +System +Clocks +(MCG) +LP exit +Flash +CPU +LP exit +Clock +Control +Module +(CCM) +Module +Memory +Bus masters low power bus (non-CPU) +Bus slaves low power bus +Stop/Wait +CCM low power bus +MCG enable +PMC low power bus +Flash low power bus +Reset +Control +(RCM) +Module +Figure 14-6. Low-power system components and connections +14.4.2.1 +Stop mode entry sequence +Entry into a low-power stop mode (Stop, VLPS, LLS, VLLSx) is initiated by CPU +execution of the WFI instruction. After the instruction is executed, the following +sequence occurs: +1. The CPU clock is gated off immediately. +2. Requests are made to all non-CPU bus masters to enter Stop mode. +3. After all masters have acknowledged they are ready to enter Stop mode, requests are +made to all bus slaves to enter Stop mode. +4. After all slaves have acknowledged they are ready to enter Stop mode, all system and +bus clocks are gated off. +5. Clock generators are disabled in the MCG. +6. The on-chip regulator in the PMC and internal power switches are configured to +meet the power consumption goals for the targeted low-power mode. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +340 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 340](pdf-image://page_340_img_1) + +## Page 341 + +14.4.2.2 +Stop mode exit sequence +Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The +following sequence then executes to restore the system to a run mode (RUN or VLPR): +1. The on-chip regulator in the PMC and internal power switches are restored. +2. Clock generators are enabled in the MCG. +3. System and bus clocks are enabled to all masters and slaves. +4. The CPU clock is enabled and the CPU begins servicing the reset or interrupt that +initiated the exit from the low-power stop mode. +14.4.2.3 +Aborted stop mode entry +If an interrupt or a reset occurs during a stop entry sequence, the SMC can abort the +transition early and return to RUN mode without completely entering the stop mode. An +aborted entry is possible only if the reset or interrupt occurs before the PMC begins the +transition to stop mode regulation. After this point, the interrupt or reset is ignored until +the PMC has completed its transition to stop mode regulation. When an aborted stop +mode entry sequence occurs, the SMC's PMCTRL[STOPA] is set to 1. +14.4.2.4 +Transition to wait modes +For wait modes (WAIT and VLPW), the CPU clock is gated off while all other clocking +continues, as in RUN and VLPR mode operation. Some modules that support stop-in- +wait functionality have their clocks disabled in these configurations. +14.4.2.5 +Transition from stop modes to Debug mode +The debugger module supports a transition from STOP, WAIT, VLPS, and VLPW back +to a Halted state when the debugger has been enabled, that is, ENBDM is 1. As part of +this transition, system clocking is re-established and is equivalent to the normal RUN and +VLPR mode clocking configuration. +14.4.3 +Run modes +The device contains two different run modes: +• Run +• Very Low-Power Run (VLPR) +Chapter 14 System Mode Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +341 +General Business Information + +![Image 1 from page 341](pdf-image://page_341_img_1) + +## Page 342 + +14.4.3.1 +RUN mode +This is the normal operating mode for the device. +This mode is selected after any reset. When the ARM processor exits reset, it sets up the +stack, program counter (PC), and link register (LR): +• The processor reads the start SP (SP\_main) from vector-table offset 0x000 +• The processor reads the start PC from vector-table offset 0x004 +• LR is set to 0xFFFF\_FFFF. +To reduce power in this mode, disable the clocks to unused modules using their +corresponding clock gating control bits in the SIM's registers. +14.4.3.2 +Very-Low Power Run (VLPR) mode +In VLPR mode, the on-chip voltage regulator is put into a stop mode regulation state. In +this state, the regulator is designed to supply enough current to the MCU over a reduced +frequency. To further reduce power in this mode, disable the clocks to unused modules +using their corresponding clock gating control bits in the SIM's registers. +Before entering this mode, the following conditions must be met: +• The MCG must be configured in a mode which is supported during VLPR. See the +Power Management details for information about these MCG modes. +• All clock monitors in the MCG must be disabled. +• The maximum frequencies of the system, bus, flash, and core are restricted. See the +Power Management details about which frequencies are supported. +• Mode protection must be set to allow VLP modes, that is, PMPROT[AVLP] is 1. +• PMCTRL[RUNM] is set to 10b to enter VLPR. +• Flash programming/erasing is not allowed. +NOTE +Do not change the clock frequency while in VLPR mode, +because the regulator is slow responding and cannot manage +fast load transitions. In addition, do not modify the clock source +in the MCG module, the module clock enables in the SIM, or +any clock divider registers. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +342 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 342](pdf-image://page_342_img_1) + +## Page 343 + +To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status +register that can be used to determine when the system has completed an exit to RUN +mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at +full speed in any clock mode. If a higher execution frequency is desired, poll the +PMSTAT register until it is set to RUN when returning from VLPR mode. +VLPR mode also provides the option to return to run regulation if any interrupt occurs. +Implement this option by setting Low-Power Wakeup On Interrupt (LPWUI) in the +PMCTRL register. Any reset always causes an exit from VLPR and returns the device to +RUN mode after the MCU exits its reset flow. The RUNM bits are cleared by hardware +on any interrupt when LPWUI is set or on any reset. +14.4.4 +Wait modes +This device contains two different wait modes: +• Wait +• Very-Low Power Wait (VLPW) +14.4.4.1 +WAIT mode +WAIT mode is entered when the ARM core enters the Sleep-Now or Sleep-On-Exit +modes while SLEEDEEP is cleared. The ARM CPU enters a low-power state in which it +is not clocked, but peripherals continue to be clocked provided they are enabled. Clock +gating to the peripheral is enabled via the SIM.. +When an interrupt request occurs, the CPU exits WAIT mode and resumes processing in +RUN mode, beginning with the stacking operations leading to the interrupt service +routine. +A system reset will cause an exit from WAIT mode, returning the device to normal RUN +mode. +14.4.4.2 +Very-Low-Power Wait (VLPW) mode +VLPW is entered by the entering the Sleep-Now or Sleep-On-Exit mode while +SLEEPDEEP is cleared and the MCU is in VLPR mode. +Chapter 14 System Mode Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +343 +General Business Information + +![Image 1 from page 343](pdf-image://page_343_img_1) + +## Page 344 + +In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, +the regulator is designed to supply enough current to the MCU over a reduced frequency. +To further reduce power in this mode, disable the clocks to unused modules by clearing +the peripherals' corresponding clock gating control bits in the SIM. +VLPR mode restrictions also apply to VLPW. +VLPW mode provides the option to return to fully-regulated normal RUN mode if any +enabled interrupt occurs. This is done by setting PMCTRL[LPWUI]. Wait for the +PMSTAT register to set to RUN before increasing the frequency. +If the LPWUI bit is clear, when an interrupt from VLPW occurs, the device returns to +VLPR mode to execute the interrupt service routine. +A system reset will cause an exit from VLPW mode, returning the device to normal RUN +mode. +14.4.5 +Stop modes +This device contains a variety of stop modes to meet your application needs. The stop +modes range from: +• a stopped CPU, with all I/O, logic, and memory states retained, and certain +asynchronous mode peripherals operating +to: +• a powered down CPU, with only I/O and a small register file retained, very few +asynchronous mode peripherals operating, while the remainder of the MCU is +powered down. +The choice of stop mode depends upon the user's application, and how power usage and +state retention versus functional needs may be traded off. +The various stop modes are selected by setting the appropriate fields in PMPROT and +PMCTRL. The selected stop mode mode is entered during the sleep-now or sleep-on-exit +entry with the SLEEPDEEP bit set in the System Control Register in the ARM core. +The available stop modes are: +• Normal Stop (STOP) +• Very-Low Power Stop (VLPS) +• Low-Leakage Stop (LLS) +• Very-Low-Leakage Stop (VLLSx) +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +344 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 344](pdf-image://page_344_img_1) + +## Page 345 + +14.4.5.1 +STOP mode +STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in +the System Control Register in the ARM core. +The MCG module can be configured to leave the reference clocks running. +A module capable of providing an asynchronous interrupt to the device takes the device +out of STOP mode and returns the device to normal RUN mode. Refer to the device's +Power Management chapter for peripheral, I/O, and memory operation in STOP mode. +When an interrupt request occurs, the CPU exits STOP mode and resumes processing, +beginning with the stacking operations leading to the interrupt service routine. +A system reset will cause an exit from STOP mode, returning the device to normal RUN +mode via an MCU reset. +14.4.5.2 +Very-Low-Power Stop (VLPS) mode +VLPS mode can be entered in one of two ways: +• Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the +System Control Register in the ARM core while the MCU is in VLPR mode and +STOPM=010 or 000 in the PMCTRL register. +• Entry into stop via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the +System Control Register in the ARM core while the MCU is in normal RUN mode +and STOPM=010 in the PMCTRL register. When VLPS is entered directly from +RUN mode, exit to VLPR is disabled by hardware and the system will always exit +back to RUN. +In VLPS, the on-chip voltage regulator remains in its stop regulation state as in VLPR. +A module capable of providing an asynchronous interrupt to the device takes the device +out of VLPS and returns the device to VLPR mode, provided LPWUI is clear. +If LPWUI is set, the device returns to normal RUN mode upon an interrupt request. +PMSTAT must be set to RUN before allowing the system to return to a frequency higher +than that allowed in VLPR mode. +A system reset will also cause a VLPS exit, returning the device to normal RUN mode. +Chapter 14 System Mode Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +345 +General Business Information + +![Image 1 from page 345](pdf-image://page_345_img_1) + +## Page 346 + +14.4.5.3 +Low-Leakage Stop (LLS) mode +Low-Leakage Stop (LLS) mode can be entered from normal RUN or VLPR modes. +The MCU enters LLS mode if: +• In Sleep-Now or Sleep-On-Exit mode, SLEEPDEEP is set in the System Control +Register in the ARM core, and +• The device is configured as shown in Table 14-7. +In LLS, the on-chip voltage regulator is in stop regulation. Most of the peripherals are put +in a state-retention mode that does not allow them to operate while in LLS. +Before entering LLS mode, the user should configure the low-leakage wakeup (LLWU) +module to enable the desired wakeup sources. The available wakeup sources in LLS are +detailed in the chip configuration details for this device. +After wakeup from LLS, the device returns to normal RUN mode with a pending LLWU +module interrupt. In the LLWU interrupt service routine (ISR), the user can poll the +LLWU module wakeup flags to determine the source of the wakeup. +NOTE +The LLWU interrupt must not be masked by the interrupt +controller to avoid a scenario where the system does not fully +exit stop mode on an LLS recovery. +An asserted RESET pin will cause an exit from LLS mode, returning the device to +normal RUN mode. When LLS is exiting via the RESET pin, the PIN and WAKEUP bits +are set in the SRS0 register of the reset control module (RCM). +14.4.5.4 +Very-Low-Leakage Stop (VLLSx) modes +This device contains these very low leakage modes: +• VLLS3 +• VLLS2 +• VLLS1 +VLLSx is often used in this document to refer to all of these modes. +All VLLSx modes can be entered from normal RUN or VLPR modes. +The MCU enters the configured VLLS mode if: +• In Sleep-Now or Sleep-On-Exit mode, the SLEEPDEEP bit is set in the System +Control Register in the ARM core, and +• The device is configured as shown in Table 14-7. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +346 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 346](pdf-image://page_346_img_1) + +## Page 347 + +In VLLS, the on-chip voltage regulator is in its stop-regulation state while most digital +logic is powered off. +Before entering VLLS mode, the user should configure the low-leakage wakeup (LLWU) +module to enable the desired wakeup sources. The available wakeup sources in VLLS are +detailed in the chip configuration details for this device. +After wakeup from VLLS, the device returns to normal RUN mode with a pending +LLWU interrupt. In the LLWU interrupt service routine (ISR), the user can poll the +LLWU module wakeup flags to determine the source of the wakeup. +When entering VLLS, each I/O pin is latched as configured before executing VLLS. +Because all digital logic in the MCU is powered off, all port and peripheral data is lost +during VLLS. This information must be restored before the ACKISO bit in the PMC is +set. +An asserted RESET pin will cause an exit from any VLLS mode, returning the device to +normal RUN mode. When exiting VLLS via the RESET pin, the PIN and WAKEUP bits +are set in the SRS0 register of the reset control module (RCM). +14.4.6 +Debug in low power modes +When the MCU is secure, the device disables/limits debugger operation. When the MCU +is unsecure, the ARM debugger can assert two power-up request signals: +• System power up, via SYSPWR in the Debug Port Control/Stat register +• Debug power up, via CDBGPWRUPREQ in the Debug Port Control/Stat register +When asserted while in RUN, WAIT, VLPR, or VLPW, the mode controller drives a +corresponding acknowledge for each signal, that is, both CDBGPWRUPACK and +CSYSPWRUPACK. When both requests are asserted, the mode controller handles +attempts to enter STOP and VLPS by entering an emulated stop state. In this emulated +stop state: +• the regulator is in run regulation, +• the MCG-generated clock source is enabled, +• all system clocks, except the core clock, are disabled, +• the debug module has access to core registers, and +• access to the on-chip peripherals is blocked. +No debug is available while the MCU is in LLS or VLLS modes. LLS is a state-retention +mode and all debug operation can continue after waking from LLS, even in cases where +system wakeup is due to a system reset event. +Chapter 14 System Mode Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +347 +General Business Information + +![Image 1 from page 347](pdf-image://page_347_img_1) + +## Page 348 + +Entering into a VLLS mode causes all of the debug controls and settings to be powered +off. To give time to the debugger to sync with the MCU, the MDM AP Control Register +includes a Very-Low-Leakage Debug Request (VLLDBGREQ) bit that is set to configure +the Reset Controller logic to hold the system in reset after the next recovery from a VLLS +mode. This bit allows the debugger time to reinitialize the debug module before the +debug session continues. +The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge +(VLLDBGACK) bit that is set to release the ARM core being held in reset following a +VLLS recovery. The debugger reinitializes all debug IP, and then asserts the +VLLDBGACK control bit to allow the RCM to release the ARM core from reset and +allow CPU operation to begin. +The VLLDBGACK bit is cleared by the debugger (or can be left set as is) or clears +automatically due to the reset generated as part of the next VLLS recovery. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +348 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 348](pdf-image://page_348_img_1) + +## Page 349 + +Chapter 15 +Power Management Controller +15.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The power management controller (PMC) contains the internal voltage regulator, power +on reset (POR), and low voltage detect system. +15.2 +Features +The PMC features include: +• Internal voltage regulator +• Active POR providing brown-out detect +• Low-voltage detect supporting two low-voltage trip points with four warning levels +per trip point +15.3 +Low-voltage detect (LVD) system +This device includes a system to guard against low-voltage conditions. This protects +memory contents and controls MCU system states during supply voltage variations. The +system is comprised of a power-on reset (POR) circuit and a LVD circuit with a user- +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +349 +General Business Information + +![Image 1 from page 349](pdf-image://page_349_img_1) + +## Page 350 + +selectable trip voltage: high (VLVDH) or low (VLVDL). The trip voltage is selected by the +LVDSC1[LVDV] bits. The LVD is disabled upon entering VLPx, LLS, and VLLSx +modes. +Two flags are available to indicate the status of the low-voltage detect system: +• The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF +bit is set when the supply voltage falls below the selected trip point (VLVD). The +LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal +supply has returned above the trip point; otherwise, the LVDF bit remains set. +• The low voltage warning flag (LVWF) operates in a level sensitive manner. The +LVWF bit is set when the supply voltage falls below the selected monitor trip point +(VLVW). The LVWF bit is cleared by writing one to the LVWACK bit, but only if +the internal supply has returned above the trip point; otherwise, the LVWF bit +remains set. +15.3.1 +LVD reset operation +By setting the LVDRE bit, the LVD generates a reset upon detection of a low voltage +condition. The low voltage detection threshold is determined by the LVDV bits. After an +LVD reset occurs, the LVD system holds the MCU in reset until the supply voltage rises +above this threshold. The LVD bit in the SRS register is set following an LVD or power- +on reset. +15.3.2 +LVD interrupt operation +By configuring the LVD circuit for interrupt operation (LVDIE set and LVDRE clear), +LVDSC1[LVDF] is set and an LVD interrupt request occurs upon detection of a low +voltage condition. The LVDF bit is cleared by writing one to the LVDSC1[LVDACK] +bit. +15.3.3 +Low-voltage warning (LVW) interrupt operation +The LVD system contains a low-voltage warning flag (LVWF) to indicate that the supply +voltage is approaching, but is above, the LVD voltage. The LVW also has an interrupt, +which is enabled by setting the LVDSC2[LVWIE] bit. If enabled, an LVW interrupt +request occurs when the LVWF is set. LVWF is cleared by writing one to the +LVDSC2[LVWACK] bit. +The LVDSC2[LVWV] bits select one of four trip voltages: +Low-voltage detect (LVD) system +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +350 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 350](pdf-image://page_350_img_1) + +## Page 351 + +• Highest: VLVW4 +• Two mid-levels: VLVW3 and VLVW2 +• Lowest: VLVW1 +15.4 +I/O retention +When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the +PMC is re-enabled, goes through a power up sequence to full regulation, and releases the +logic from state retention mode. The I/O are released immediately after a wakeup or reset +event. In the case of LLS exit via a RESET pin, the I/O default to their reset state. +When in VLLS modes, the I/O states are held on a wakeup event (with the exception of +wakeup by reset event) until the wakeup has been acknowledged via a write to the +ACKISO bit. In the case of VLLS exit via a RESET pin, the I/O are released and default +to their reset state. In this case, no write to the ACKISO is needed. +15.5 +Memory map and register descriptions +PMC register details follow. +NOTE +Different portions of PMC registers are reset only by particular +reset types. Each register's description provides details. For +more information about the types of reset on this chip, refer to +the Reset section details. +PMC memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4007\_D000 +Low Voltage Detect Status And Control 1 register +(PMC\_LVDSC1) +8 +R/W +1010h +15.5.1/352 +4007\_D001 +Low Voltage Detect Status And Control 2 register +(PMC\_LVDSC2) +8 +R/W +000h +15.5.2/353 +4007\_D002 +Regulator Status And Control register (PMC\_REGSC) +8 +R/W +044h +15.5.3/354 +Chapter 15 Power Management Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +351 +General Business Information + +![Image 1 from page 351](pdf-image://page_351_img_1) + +## Page 352 + +15.5.1 +Low Voltage Detect Status And Control 1 register +(PMC\_LVDSC1) +This register contains status and control bits to support the low voltage detect function. +This register should be written during the reset initialization program to set the desired +controls even if the desired settings are the same as the reset settings. +While the device is in the very low power or low leakage modes, the LVD system is +disabled regardless of LVDSC1 settings. To protect systems that must have LVD always +on, configure the SMC's power mode protection register (PMPROT) to disallow any very +low power or low leakage modes from being enabled. +See the device's data sheet for the exact LVD trip voltages. +NOTE +The LVDV bits are reset solely on a POR Only event. The +register's other bits are reset on Chip Reset Not VLLS. For +more information about these reset types, refer to the Reset +section details. +Address: 4007\_D000h base + 0h offset = 4007\_D000h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +LVDF +0 +LVDIE +LVDRE +0 +LVDV +Write +LVDACK +Reset +0 +0 +0 +1 +0 +0 +0 +0 +PMC\_LVDSC1 field descriptions +Field +Description +7 +LVDF +Low-Voltage Detect Flag +This read-only status bit indicates a low-voltage detect event. +0 +Low-voltage event not detected +1 +Low-voltage event detected +6 +LVDACK +Low-Voltage Detect Acknowledge +This write-only bit is used to acknowledge low voltage detection errors. Write 1 to clear LVDF. Reads +always return 0. +5 +LVDIE +Low-Voltage Detect Interrupt Enable +Enables hardware interrupt requests for LVDF. +0 +Hardware interrupt disabled (use polling) +1 +Request a hardware interrupt when LVDF = 1 +Table continues on the next page... +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +352 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 352](pdf-image://page_352_img_1) + +## Page 353 + +PMC\_LVDSC1 field descriptions (continued) +Field +Description +4 +LVDRE +Low-Voltage Detect Reset Enable +This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. +0 +LVDF does not generate hardware resets +1 +Force an MCU reset when LVDF = 1 +3–2 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +1–0 +LVDV +Low-Voltage Detect Voltage Select +Selects the LVD trip point voltage (V LVD ). +00 +Low trip point selected (V LVD = V LVDL ) +01 +High trip point selected (V LVD = V LVDH ) +10 +Reserved +11 +Reserved +15.5.2 +Low Voltage Detect Status And Control 2 register +(PMC\_LVDSC2) +This register contains status and control bits to support the low voltage warning function. +While the device is in the very low power or low leakage modes, the LVD system is +disabled regardless of LVDSC2 settings. +See the device's data sheet for the exact LVD trip voltages. +NOTE +The LVW trip voltages depend on LVWV and LVDV bits. +NOTE +The LVWV bits are reset solely on a POR Only event. The +register's other bits are reset on Chip Reset Not VLLS. For +more information about these reset types, refer to the Reset +section details. +Address: 4007\_D000h base + 1h offset = 4007\_D001h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +LVWF +0 +LVWIE +0 +LVWV +Write +LVWACK +Reset +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 15 Power Management Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +353 +General Business Information + +![Image 1 from page 353](pdf-image://page_353_img_1) + +## Page 354 + +PMC\_LVDSC2 field descriptions +Field +Description +7 +LVWF +Low-Voltage Warning Flag +This read-only status bit indicates a low-voltage warning event. LVWF is set when VSupply transitions below +the trip point, or after reset and VSupply is already below VLVW . +0 +Low-voltage warning event not detected +1 +Low-voltage warning event detected +6 +LVWACK +Low-Voltage Warning Acknowledge +This write-only bit is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Reads +always return 0. +5 +LVWIE +Low-Voltage Warning Interrupt Enable +Enables hardware interrupt requests for LVWF. +0 +Hardware interrupt disabled (use polling) +1 +Request a hardware interrupt when LVWF = 1 +4–2 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +1–0 +LVWV +Low-Voltage Warning Voltage Select +Selects the LVW trip point voltage (VLVW). The actual voltage for the warning depends on LVDSC1[LVDV]. +00 +Low trip point selected (VLVW = VLVW1) +01 +Mid 1 trip point selected (VLVW = VLVW2) +10 +Mid 2 trip point selected (VLVW = VLVW3) +11 +High trip point selected (VLVW = VLVW4) +15.5.3 +Regulator Status And Control register (PMC\_REGSC) +The PMC contains an internal voltage regulator. The voltage regulator design uses a +bandgap reference that is also available through a buffer as input to certain internal +peripherals, such as the CMP and ADC. The internal regulator provides a status bit +(REGONS) indicating the regulator is in run regulation. +NOTE +This register is reset on Chip Reset Not VLLS and by reset +types that trigger Chip Reset not VLLS. See the Reset section +for more information. +Address: 4007\_D000h base + 2h offset = 4007\_D002h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +BGEN +ACKISO +REGONS +Reserved +BGBE +Write +w1c +Reset +0 +0 +0 +0 +0 +1 +0 +0 +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +354 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 354](pdf-image://page_354_img_1) + +## Page 355 + +PMC\_REGSC field descriptions +Field +Description +7–5 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +4 +BGEN +Bandgap Enable In VLPx Operation +BGEN controls whether the bandgap is enabled in lower power modes of operation (VLPx, LLS, and +VLLSx). When on-chip peripherals require the bandgap voltage reference in low power modes of +operation, set BGEN to continue to enable the bandgap operation. +NOTE: When the bandgap voltage reference is not needed in low power modes, clear BGEN to avoid +excess power consumption. +0 +Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes +1 +Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes +3 +ACKISO +Acknowledge Isolation +Reading this bit indicates whether certain peripherals and the I/O pads are in a latched state as a result of +having been in a VLLS mode. Writing one to this bit when it is set releases the I/O pads and certain +peripherals to their normal run mode state. +NOTE: After recovering from a VLLS mode, user should restore chip configuration before clearing +ACKISO. In particular, pin configuration for enabled LLWU wakeup pins should be restored to +avoid any LLWU flag from being falsely set when ACKISO is cleared. +0 +Peripherals and I/O pads are in normal run state +1 +Certain peripherals and I/O pads are in an isolated and latched state +2 +REGONS +Regulator In Run Regulation Status +This read-only bit provides the current status of the internal voltage regulator. +0 +Regulator is in stop regulation or in transition to/from it +1 +Regulator is in run regulation +1 +Reserved +This field is reserved. +NOTE: This reserved bit must remain cleared (set to 0). +0 +BGBE +Bandgap Buffer Enable +Enables the bandgap buffer. +0 +Bandgap buffer not enabled +1 +Bandgap buffer enabled +Chapter 15 Power Management Controller +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +355 +General Business Information + +![Image 1 from page 355](pdf-image://page_355_img_1) + +## Page 356 + +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +356 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 356](pdf-image://page_356_img_1) + +## Page 357 + +Chapter 16 +Low-Leakage Wakeup Unit (LLWU) +16.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The LLWU module allows the user to select up to 16 external pin sources and up to 8 +internal modules as a wakeup source from low-leakage power modes. The input sources +are described in the device's chip configuration details. Each of the available wakeup +sources can be individually enabled. +The RESET pin is an additional source for triggering an exit from low-leakage power +modes, and causes the MCU to exit both LLS and VLLS through a reset flow. The +LLWU\_RST[LLRSTE] bit must be set to allow an exit from low-leakage modes via the +RESET pin. On a device where the RESET pin is shared with other functions, the explicit +port mux control register must be set for the RESET pin before the RESET pin can be +used as a low-leakage reset source. +The LLWU module also includes three optional digital pin filters: two for the external +wakeup pins and one for the RESET pin. +16.1.1 +Features +The LLWU module features include: +• Support for up to 16 external input pins and up to 8 internal modules with individual +enable bits +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +357 +General Business Information + +![Image 1 from page 357](pdf-image://page_357_img_1) + +## Page 358 + +• Input sources may be external pins or from internal peripherals capable of running in +LLS or VLLS. See the chip configuration information for wakeup input sources for +this device. +• External pin wakeup inputs, each of which is programmable as falling-edge, rising- +edge, or any change +• Wakeup inputs that are activated if enabled after MCU enters a low-leakage power +mode +• Optional digital filters provided to qualify an external pin detect and RESET pin +detect. +16.1.2 +Modes of operation +The LLWU module becomes functional on entry into a low-leakage power mode. After +recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the +LLWU continues to detect wakeup events until the user has acknowledged the wakeup +via a write to the PMC\_REGSC[ACKISO] bit. +16.1.2.1 +LLS mode +The LLWU module provides up to 16 external wakeup inputs and up to 8 internal module +wakeup inputs. An LLS reset event can be initiated via assertion of the RESET pin. +Wakeup events due to external wakeup inputs and internal module wakeup inputs result +in an interrupt flow when exiting LLS. A reset event due to RESET pin assertion results +in a reset flow when exiting LLS. +NOTE +The LLWU interrupt must not be masked by the interrupt +controller to avoid a scenario where the system does not fully +exit Stop mode on an LLS recovery. +16.1.2.2 +VLLS modes +The LLWU module provides up to 16 external wakeup inputs and up to 8 internal module +wakeup inputs. A VLLS reset event can be initiated via assertion of the RESET pin. All +wakeup and reset events result in VLLS exit via a reset flow. +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +358 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 358](pdf-image://page_358_img_1) + +## Page 359 + +16.1.2.3 +Non-low leakage modes +The LLWU is not active in all non-low leakage modes where detection and control logic +are in a static state. The LLWU registers are accessible in non-low leakage modes and are +available for configuring and reading status when bus transactions are possible. +When theRESET pin filter or wakeup pin filters are enabled, filter operation begins +immediately. If a low leakage mode is entered within 5 LPO clock cycles of an active +edge, the edge event will be detected by the LLWU. For RESET pin filtering, this means +that there is no restart to the minimum LPO cycle duration as the filtering transitions +from a non-low leakage filter, which is implemented in the RCM, to the LLWU filter. +16.1.2.4 +Debug mode +When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic +works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx +mode, the LLWU becomes inactive. +16.1.3 +Block diagram +The following figure is the block diagram for the LLWU module. +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +359 +General Business Information + +![Image 1 from page 359](pdf-image://page_359_img_1) + +## Page 360 + +Module0 interrupt flag +(LLWU\_M0IF) +WUME0 +LLWU\_MWUF0 occurred +Internal +module +sources +LLWU +controller +External +pin sources +exit low leakge mode +interrupt flow +reset flow +reset occurred +RSTFILT +RESET +LLWU\_P0 +LLWU\_P15 +Pin filter 1 +wakeup +occurred +Interrupt module +flag detect +WUPE15 +2 +Edge +detect +enter low leakge mode +WUPE0 +Edge +detect +Module7 interrupt flag +(LLWU\_M7IF) +WUME7 +LLWU\_MWUF7 occurred +Interrupt module +flag detect +LPO +Pin filter 2 +LPO +FILT1[FILTE] +Pin filter 1 +Synchronizer +Synchronizer +Edge +detect +LLWU\_P15 +wakeup occurred +Edge +detect +Pin filter 2 +wakeup +occurred +2 +LLWU\_P0 +wakeup occurred +RESET +Pin filter +LPO +FILT2[FILTSEL] +FILT1[FILTSEL] +FILT2[FILTE] +Figure 16-1. LLWU block diagram +16.2 +LLWU signal descriptions +The signal properties of LLWU are shown in the following table. The external wakeup +input pins can be enabled to detect either rising-edge, falling-edge, or on any change. +Table 16-1. LLWU signal descriptions +Signal +Description +I/O +LLWU\_Pn +Wakeup inputs (n = 0-15) +I +LLWU signal descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +360 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 360](pdf-image://page_360_img_1) + +## Page 361 + +16.3 +Memory map/register definition +The LLWU includes the following registers: +• Five 8-bit wakeup source enable registers +• Enable external pin input sources +• Enable internal peripheral sources +• Three 8-bit wakeup flag registers +• Indication of wakeup source that caused exit from a low-leakage power mode +includes external pin or internal module interrupt +• Two 8-bit wakeup pin filter enable registers +• One 8-bit RESET pin filter enable register +NOTE +All LLWU registers are reset by Chip Reset not VLLS and by +reset types that trigger Chip Reset not VLLS. Each register's +displayed reset value represents this subset of reset types. +LLWU registers are unaffected by reset types that do not trigger +Chip Reset not VLLS. For more information about the types of +reset on this chip, refer to the Introduction details. +LLWU memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4007\_C000 +LLWU Pin Enable 1 register (LLWU\_PE1) +8 +R/W +000h +16.3.1/362 +4007\_C001 +LLWU Pin Enable 2 register (LLWU\_PE2) +8 +R/W +000h +16.3.2/363 +4007\_C002 +LLWU Pin Enable 3 register (LLWU\_PE3) +8 +R/W +000h +16.3.3/364 +4007\_C003 +LLWU Pin Enable 4 register (LLWU\_PE4) +8 +R/W +000h +16.3.4/365 +4007\_C004 +LLWU Module Enable register (LLWU\_ME) +8 +R/W +000h +16.3.5/366 +4007\_C005 +LLWU Flag 1 register (LLWU\_F1) +8 +R/W +000h +16.3.6/368 +4007\_C006 +LLWU Flag 2 register (LLWU\_F2) +8 +R/W +000h +16.3.7/369 +4007\_C007 +LLWU Flag 3 register (LLWU\_F3) +8 +R/W +000h +16.3.8/371 +4007\_C008 +LLWU Pin Filter 1 register (LLWU\_FILT1) +8 +R/W +000h +16.3.9/373 +4007\_C009 +LLWU Pin Filter 2 register (LLWU\_FILT2) +8 +R/W +000h +16.3.10/374 +4007\_C00A +LLWU Reset Enable register (LLWU\_RST) +8 +R/W +022h +16.3.11/375 +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +361 +General Business Information + +![Image 1 from page 361](pdf-image://page_361_img_1) + +## Page 362 + +16.3.1 +LLWU Pin Enable 1 register (LLWU\_PE1) +LLWU\_PE1 contains the field to enable and select the edge detect type for the external +wakeup input pins LLWU\_P3-LLWU\_P0. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 0h offset = 4007\_C000h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +WUPE3 +WUPE2 +WUPE1 +WUPE0 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +LLWU\_PE1 field descriptions +Field +Description +7–6 +WUPE3 +Wakeup Pin Enable For LLWU\_P3 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +5–4 +WUPE2 +Wakeup Pin Enable For LLWU\_P2 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +3–2 +WUPE1 +Wakeup Pin Enable For LLWU\_P1 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +1–0 +WUPE0 +Wakeup Pin Enable For LLWU\_P0 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +362 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 362](pdf-image://page_362_img_1) + +## Page 363 + +LLWU\_PE1 field descriptions (continued) +Field +Description +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +16.3.2 +LLWU Pin Enable 2 register (LLWU\_PE2) +LLWU\_PE2 contains the field to enable and select the edge detect type for the external +wakeup input pins LLWU\_P7-LLWU\_P4. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 1h offset = 4007\_C001h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +WUPE7 +WUPE6 +WUPE5 +WUPE4 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +LLWU\_PE2 field descriptions +Field +Description +7–6 +WUPE7 +Wakeup Pin Enable For LLWU\_P7 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +5–4 +WUPE6 +Wakeup Pin Enable For LLWU\_P6 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +3–2 +WUPE5 +Wakeup Pin Enable For LLWU\_P5 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +Table continues on the next page... +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +363 +General Business Information + +![Image 1 from page 363](pdf-image://page_363_img_1) + +## Page 364 + +LLWU\_PE2 field descriptions (continued) +Field +Description +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +1–0 +WUPE4 +Wakeup Pin Enable For LLWU\_P4 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +16.3.3 +LLWU Pin Enable 3 register (LLWU\_PE3) +LLWU\_PE3 contains the field to enable and select the edge detect type for the external +wakeup input pins LLWU\_P11-LLWU\_P8. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 2h offset = 4007\_C002h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +WUPE11 +WUPE10 +WUPE9 +WUPE8 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +LLWU\_PE3 field descriptions +Field +Description +7–6 +WUPE11 +Wakeup Pin Enable For LLWU\_P11 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +5–4 +WUPE10 +Wakeup Pin Enable For LLWU\_P10 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +364 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 364](pdf-image://page_364_img_1) + +## Page 365 + +LLWU\_PE3 field descriptions (continued) +Field +Description +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +3–2 +WUPE9 +Wakeup Pin Enable For LLWU\_P9 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +1–0 +WUPE8 +Wakeup Pin Enable For LLWU\_P8 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +16.3.4 +LLWU Pin Enable 4 register (LLWU\_PE4) +LLWU\_PE4 contains the field to enable and select the edge detect type for the external +wakeup input pins LLWU\_P15-LLWU\_P12. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 3h offset = 4007\_C003h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +WUPE15 +WUPE14 +WUPE13 +WUPE12 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +LLWU\_PE4 field descriptions +Field +Description +7–6 +WUPE15 +Wakeup Pin Enable For LLWU\_P15 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +Table continues on the next page... +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +365 +General Business Information + +![Image 1 from page 365](pdf-image://page_365_img_1) + +## Page 366 + +LLWU\_PE4 field descriptions (continued) +Field +Description +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +5–4 +WUPE14 +Wakeup Pin Enable For LLWU\_P14 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +3–2 +WUPE13 +Wakeup Pin Enable For LLWU\_P13 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +1–0 +WUPE12 +Wakeup Pin Enable For LLWU\_P12 +Enables and configures the edge detection for the wakeup pin. +00 +External input pin disabled as wakeup input +01 +External input pin enabled with rising edge detection +10 +External input pin enabled with falling edge detection +11 +External input pin enabled with any change detection +16.3.5 +LLWU Module Enable register (LLWU\_ME) +LLWU\_ME contains the bits to enable the internal module flag as a wakeup input source +for inputs MWUF7-MWUF0. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 4h offset = 4007\_C004h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +WUME7 +WUME6 +WUME5 +WUME4 +WUME3 +WUME2 +WUME1 +WUME0 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +366 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 366](pdf-image://page_366_img_1) + +## Page 367 + +LLWU\_ME field descriptions +Field +Description +7 +WUME7 +Wakeup Module Enable For Module 7 +Enables an internal module as a wakeup source input. +0 +Internal module flag not used as wakeup source +1 +Internal module flag used as wakeup source +6 +WUME6 +Wakeup Module Enable For Module 6 +Enables an internal module as a wakeup source input. +0 +Internal module flag not used as wakeup source +1 +Internal module flag used as wakeup source +5 +WUME5 +Wakeup Module Enable For Module 5 +Enables an internal module as a wakeup source input. +0 +Internal module flag not used as wakeup source +1 +Internal module flag used as wakeup source +4 +WUME4 +Wakeup Module Enable For Module 4 +Enables an internal module as a wakeup source input. +0 +Internal module flag not used as wakeup source +1 +Internal module flag used as wakeup source +3 +WUME3 +Wakeup Module Enable For Module 3 +Enables an internal module as a wakeup source input. +0 +Internal module flag not used as wakeup source +1 +Internal module flag used as wakeup source +2 +WUME2 +Wakeup Module Enable For Module 2 +Enables an internal module as a wakeup source input. +0 +Internal module flag not used as wakeup source +1 +Internal module flag used as wakeup source +1 +WUME1 +Wakeup Module Enable for Module 1 +Enables an internal module as a wakeup source input. +0 +Internal module flag not used as wakeup source +1 +Internal module flag used as wakeup source +0 +WUME0 +Wakeup Module Enable For Module 0 +Enables an internal module as a wakeup source input. +0 +Internal module flag not used as wakeup source +1 +Internal module flag used as wakeup source +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +367 +General Business Information + +![Image 1 from page 367](pdf-image://page_367_img_1) + +## Page 368 + +16.3.6 +LLWU Flag 1 register (LLWU\_F1) +LLWU\_F1 contains the wakeup flags indicating which wakeup source caused the MCU +to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. +For VLLS, this is the source causing the MCU reset flow. +The external wakeup flags are read-only and clearing a flag is accomplished by a write of +a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if +the associated WUPEx bit is cleared. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 5h offset = 4007\_C005h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +WUF7 +WUF6 +WUF5 +WUF4 +WUF3 +WUF2 +WUF1 +WUF0 +Write +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +LLWU\_F1 field descriptions +Field +Description +7 +WUF7 +Wakeup Flag For LLWU\_P7 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF7. +0 +LLWU\_P7 input was not a wakeup source +1 +LLWU\_P7 input was a wakeup source +6 +WUF6 +Wakeup Flag For LLWU\_P6 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF6. +0 +LLWU\_P6 input was not a wakeup source +1 +LLWU\_P6 input was a wakeup source +5 +WUF5 +Wakeup Flag For LLWU\_P5 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF5. +0 +LLWU\_P5 input was not a wakeup source +1 +LLWU\_P5 input was a wakeup source +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +368 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 368](pdf-image://page_368_img_1) + +## Page 369 + +LLWU\_F1 field descriptions (continued) +Field +Description +4 +WUF4 +Wakeup Flag For LLWU\_P4 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF4. +0 +LLWU\_P4 input was not a wakeup source +1 +LLWU\_P4 input was a wakeup source +3 +WUF3 +Wakeup Flag For LLWU\_P3 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF3. +0 +LLWU\_P3 input was not a wakeup source +1 +LLWU\_P3 input was a wakeup source +2 +WUF2 +Wakeup Flag For LLWU\_P2 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF2. +0 +LLWU\_P2 input was not a wakeup source +1 +LLWU\_P2 input was a wakeup source +1 +WUF1 +Wakeup Flag For LLWU\_P1 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF1. +0 +LLWU\_P1 input was not a wakeup source +1 +LLWU\_P1 input was a wakeup source +0 +WUF0 +Wakeup Flag For LLWU\_P0 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF0. +0 +LLWU\_P0 input was not a wakeup source +1 +LLWU\_P0 input was a wakeup source +16.3.7 +LLWU Flag 2 register (LLWU\_F2) +LLWU\_F2 contains the wakeup flags indicating which wakeup source caused the MCU +to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. +For VLLS, this is the source causing the MCU reset flow. +The external wakeup flags are read-only and clearing a flag is accomplished by a write of +a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will remain set if +the associated WUPEx bit is cleared. +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +369 +General Business Information + +![Image 1 from page 369](pdf-image://page_369_img_1) + +## Page 370 + +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 6h offset = 4007\_C006h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +WUF15 +WUF14 +WUF13 +WUF12 +WUF11 +WUF10 +WUF9 +WUF8 +Write +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +LLWU\_F2 field descriptions +Field +Description +7 +WUF15 +Wakeup Flag For LLWU\_P15 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF15. +0 +LLWU\_P15 input was not a wakeup source +1 +LLWU\_P15 input was a wakeup source +6 +WUF14 +Wakeup Flag For LLWU\_P14 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF14. +0 +LLWU\_P14 input was not a wakeup source +1 +LLWU\_P14 input was a wakeup source +5 +WUF13 +Wakeup Flag For LLWU\_P13 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF13. +0 +LLWU\_P13 input was not a wakeup source +1 +LLWU\_P13 input was a wakeup source +4 +WUF12 +Wakeup Flag For LLWU\_P12 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF12. +0 +LLWU\_P12 input was not a wakeup source +1 +LLWU\_P12 input was a wakeup source +3 +WUF11 +Wakeup Flag For LLWU\_P11 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF11. +0 +LLWU\_P11 input was not a wakeup source +1 +LLWU\_P11 input was a wakeup source +2 +WUF10 +Wakeup Flag For LLWU\_P10 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +370 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 370](pdf-image://page_370_img_1) + +## Page 371 + +LLWU\_F2 field descriptions (continued) +Field +Description +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF10. +0 +LLWU\_P10 input was not a wakeup source +1 +LLWU\_P10 input was a wakeup source +1 +WUF9 +Wakeup Flag For LLWU\_P9 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF9. +0 +LLWU\_P9 input was not a wakeup source +1 +LLWU\_P9 input was a wakeup source +0 +WUF8 +Wakeup Flag For LLWU\_P8 +Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To +clear the flag write a one to WUF8. +0 +LLWU\_P8 input was not a wakeup source +1 +LLWU\_P8 input was a wakeup source +16.3.8 +LLWU Flag 3 register (LLWU\_F3) +LLWU\_F3 contains the wakeup flags indicating which internal wakeup source caused the +MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt +flow. For VLLS, this is the source causing the MCU reset flow. +For internal peripherals that are capable of running in a low-leakage power mode, such as +RTC or CMP modules, the flag from the associated peripheral is accessible as the +MWUFx bit. The flag will need to be cleared in the peripheral instead of writing a 1 to +the MWUFx bit. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 7h offset = 4007\_C007h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +MWUF7 +MWUF6 +MWUF5 +MWUF4 +MWUF3 +MWUF2 +MWUF1 +MWUF0 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +371 +General Business Information + +![Image 1 from page 371](pdf-image://page_371_img_1) + +## Page 372 + +LLWU\_F3 field descriptions +Field +Description +7 +MWUF7 +Wakeup flag For module 7 +Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear +the flag, follow the internal peripheral flag clearing mechanism. +0 +Module 7 input was not a wakeup source +1 +Module 7 input was a wakeup source +6 +MWUF6 +Wakeup flag For module 6 +Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear +the flag, follow the internal peripheral flag clearing mechanism. +0 +Module 6 input was not a wakeup source +1 +Module 6 input was a wakeup source +5 +MWUF5 +Wakeup flag For module 5 +Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear +the flag, follow the internal peripheral flag clearing mechanism. +0 +Module 5 input was not a wakeup source +1 +Module 5 input was a wakeup source +4 +MWUF4 +Wakeup flag For module 4 +Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear +the flag, follow the internal peripheral flag clearing mechanism. +0 +Module 4 input was not a wakeup source +1 +Module 4 input was a wakeup source +3 +MWUF3 +Wakeup flag For module 3 +Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear +the flag, follow the internal peripheral flag clearing mechanism. +0 +Module 3 input was not a wakeup source +1 +Module 3 input was a wakeup source +2 +MWUF2 +Wakeup flag For module 2 +Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear +the flag, follow the internal peripheral flag clearing mechanism. +0 +Module 2 input was not a wakeup source +1 +Module 2 input was a wakeup source +1 +MWUF1 +Wakeup flag For module 1 +Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear +the flag, follow the internal peripheral flag clearing mechanism. +0 +Module 1 input was not a wakeup source +1 +Module 1 input was a wakeup source +0 +MWUF0 +Wakeup flag For module 0 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +372 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 372](pdf-image://page_372_img_1) + +## Page 373 + +LLWU\_F3 field descriptions (continued) +Field +Description +Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear +the flag, follow the internal peripheral flag clearing mechanism. +0 +Module 0 input was not a wakeup source +1 +Module 0 input was a wakeup source +16.3.9 +LLWU Pin Filter 1 register (LLWU\_FILT1) +LLWU\_FILT1 is a control and status register that is used to enable/disable the digital +filter 1 features for an external pin. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 8h offset = 4007\_C008h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +FILTF +FILTE +0 +FILTSEL +Write +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +LLWU\_FILT1 field descriptions +Field +Description +7 +FILTF +Filter Detect Flag +Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage +power mode. To clear the flag write a one to FILTF. +0 +Pin Filter 1 was not a wakeup source +1 +Pin Filter 1 was a wakeup source +6–5 +FILTE +Digital Filter On External Pin +Controls the digital filter options for the external pin detect. +00 +Filter disabled +01 +Filter posedge detect enabled +10 +Filter negedge detect enabled +11 +Filter any edge detect enabled +4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +373 +General Business Information + +![Image 1 from page 373](pdf-image://page_373_img_1) + +## Page 374 + +LLWU\_FILT1 field descriptions (continued) +Field +Description +3–0 +FILTSEL +Filter Pin Select +Selects 1 out of the 16 wakeup pins to be muxed into the filter. +0000 +Select LLWU\_P0 for filter +... +... +1111 +Select LLWU\_P15 for filter +16.3.10 +LLWU Pin Filter 2 register (LLWU\_FILT2) +LLWU\_FILT2 is a control and status register that is used to enable/disable the digital +filter 2 features for an external pin. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + 9h offset = 4007\_C009h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +FILTF +FILTE +0 +FILTSEL +Write +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +LLWU\_FILT2 field descriptions +Field +Description +7 +FILTF +Filter Detect Flag +Indicates that the filtered external wakeup pin, selected by FILTSEL, was a source of exiting a low-leakage +power mode. To clear the flag write a one to FILTF. +0 +Pin Filter 2 was not a wakeup source +1 +Pin Filter 2 was a wakeup source +6–5 +FILTE +Digital Filter On External Pin +Controls the digital filter options for the external pin detect. +00 +Filter disabled +01 +Filter posedge detect enabled +10 +Filter negedge detect enabled +11 +Filter any edge detect enabled +4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +374 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 374](pdf-image://page_374_img_1) + +## Page 375 + +LLWU\_FILT2 field descriptions (continued) +Field +Description +3–0 +FILTSEL +Filter Pin Select +Selects 1 out of the 16 wakeup pins to be muxed into the filter. +0000 +Select LLWU\_P0 for filter +... +... +1111 +Select LLWU\_P15 for filter +16.3.11 +LLWU Reset Enable register (LLWU\_RST) +LLWU\_RST is a control register that is used to enable/disable the digital filter for the +external pin detect and RESET pin. +NOTE +This register is reset on Chip Reset not VLLS and by reset +types that trigger Chip Reset not VLLS. It is unaffected by reset +types that do not trigger Chip Reset not VLLS. See the +Introduction details for more information. +Address: 4007\_C000h base + Ah offset = 4007\_C00Ah +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +LLRSTE +RSTFILT +Write +Reset +0 +0 +0 +0 +0 +0 +1 +0 +LLWU\_RST field descriptions +Field +Description +7–2 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +1 +LLRSTE +Low-Leakage Mode RESET Enable +This bit must be set to allow the device to be reset while in a low-leakage power mode. On devices where +Reset is not a dedicated pin, the RESET pin must also be enabled in the explicit port mux control. +0 +RESET pin not enabled as a leakage mode exit source +1 +RESET pin enabled as a low leakage mode exit source +0 +RSTFILT +Digital Filter On RESET Pin +Enables the digital filter for the RESET pin during LLS, VLLS3, VLLS2, or VLLS1 modes. +0 +Filter not enabled +1 +Filter enabled +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +375 +General Business Information + +![Image 1 from page 375](pdf-image://page_375_img_1) + +## Page 376 + +16.4 +Functional description +This on-chip peripheral module is called a low-leakage wakeup unit (LLWU) module +because it allows internal peripherals and external input pins as a source of wakeup from +low-leakage modes. It is operational only in LLS and VLLSx modes. +The LLWU module contains pin enables for each external pin and internal module. For +each external pin, the user can disable or select the edge type for the wakeup. Type +options are: +• Falling-edge +• Rising-edge +• Either-edge +When an external pin is enabled as a wakeup source, the pin must be configured as an +input pin. +The LLWU implements optional 3-cycle glitch filters, based on the LPO clock. A +detected external pin, either wakeup or RESET, is required to remain asserted until the +enabled glitch filter times out. Additional latency of up to 2 cycles is due to +synchronization, which results in a total of up to 5 cycles of delay before the detect +circuit alerts the system to the wakeup or reset event when the filter function is enabled. +Two wakeup detect filters are available to detect up to two external pins. A separate reset +filter is on the RESET pin. Glitch filtering is not provided on the internal modules. +For internal module wakeup operation, the WUMEx bit enables the associated module as +a wakeup source. +16.4.1 +LLS mode +Wakeup events triggered from either an external pin input or an internal module input +result in a CPU interrupt flow to begin user code execution. +An LLS reset event due to RESET pin assertion causes an exit via a system reset. State +retention data is lost, and the I/O states return to their reset state. The +RCM\_SRS[WAKEUP] and RCM\_SRS[PIN] bits are set and the system executes a reset +flow before CPU operation begins with a reset vector fetch. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +376 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 376](pdf-image://page_376_img_1) + +## Page 377 + +16.4.2 +VLLS modes +In the case of a wakeup due to external pin or internal module wakeup, recovery is +always via a reset flow and the RCM\_SRS[WAKEUP] is set indicating the low-leakage +mode was active. State retention data is lost and I/O will be restored after +PMC\_REGSC[ACKISO] has been written. +A VLLS exit event due to RESET pin assertion causes an exit via a system reset. State +retention data is lost and the I/O states immediately return to their reset state. The +RCM\_SRS[WAKEUP] and RCM\_SRS[PIN] bits are set and the system executes a reset +flow before CPU operation begins with a reset vector fetch. +16.4.3 +Initialization +For an enabled peripheral wakeup input, the peripheral flag must be cleared by software +before entering LLS or VLLSx mode to avoid an immediate exit from the mode. +Flags associated with external input pins, filtered and unfiltered, must also be cleared by +software prior to entry to LLS or VLLSx mode. +After enabling an external pin filter or changing the source pin, wait at least 5 LPO clock +cycles before entering LLS or VLLSx mode to allow the filter to initialize. +NOTE +After recovering from a VLLS mode, user must restore chip +configuration before clearing ACKISO. In particular, pin +configuration for enabled LLWU wakeup pins must be restored +to avoid any LLWU flag from being falsely set when ACKISO +is cleared. +The signal selected as a wakeup source pin must be a digital +pin, as selected in the pin mux control. +Chapter 16 Low-Leakage Wakeup Unit (LLWU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +377 +General Business Information + +![Image 1 from page 377](pdf-image://page_377_img_1) + +## Page 378 + +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +378 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 378](pdf-image://page_378_img_1) + +## Page 379 + +Chapter 17 +Miscellaneous Control Module (MCM) +17.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control +functions. +17.1.1 +Features +The MCM includes the following features: +• Program-visible information on the platform configuration and revision +• Control and counting logic for embedded trace buffer (ETB) almost full +17.2 +Memory map/register descriptions +The memory map and register descriptions below describe the registers using byte +addresses. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +379 +General Business Information + +![Image 1 from page 379](pdf-image://page_379_img_1) + +## Page 380 + +MCM memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +E008\_0008 +Crossbar Switch (AXBS) Slave Configuration +(MCM\_PLASC) +16 +R +00\_1F1Fh +17.2.1/380 +E008\_000A +Crossbar Switch (AXBS) Master Configuration +(MCM\_PLAMC) +16 +R +00\_3F3Fh +17.2.2/381 +E008\_000C +Control Register (MCM\_CR) +32 +R/W +0\_0000 +\_0000h +17.2.3/381 +E008\_0010 +Interrupt Status Register (MCM\_ISR) +32 +R +0\_0000 +\_0000h +17.2.4/383 +E008\_0014 +ETB Counter Control register (MCM\_ETBCC) +32 +R/W +0\_0000 +\_0000h +17.2.5/384 +E008\_0018 +ETB Reload register (MCM\_ETBRL) +32 +R/W +0\_0000 +\_0000h +17.2.6/385 +E008\_001C +ETB Counter Value register (MCM\_ETBCNT) +32 +R +0\_0000 +\_0000h +17.2.7/385 +E008\_0030 +Process ID register (MCM\_PID) +32 +R/W +0\_0000 +\_0000h +17.2.8/386 +17.2.1 +Crossbar Switch (AXBS) Slave Configuration (MCM\_PLASC) +PLASC is a 16-bit read-only register identifying the presence/absence of bus slave +connections to the device’s crossbar switch. +Address: E008\_0000h base + 8h offset = E008\_0008h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +ASC +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +MCM\_PLASC field descriptions +Field +Description +15–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7–0 +ASC +Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's +slave input port. +0 +A bus slave connection to AXBS input port n is absent +1 +A bus slave connection to AXBS input port n is present +Memory map/register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +380 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 380](pdf-image://page_380_img_1) + +## Page 381 + +17.2.2 +Crossbar Switch (AXBS) Master Configuration (MCM\_PLAMC) +PLAMC is a 16-bit read-only register identifying the presence/absence of bus master +connections to the device's crossbar switch. +Address: E008\_0000h base + Ah offset = E008\_000Ah +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +AMC +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +MCM\_PLAMC field descriptions +Field +Description +15–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7–0 +AMC +Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input +port. +0 +A bus master connection to AXBS input port n is absent +1 +A bus master connection to AXBS input port n is present +17.2.3 +Control Register (MCM\_CR) +CR defines the arbitration and protection schemes for the two system RAM arrays. +NOTE +Bits 23-0 are undefined after reset. +Address: E008\_0000h base + Ch offset = E008\_000Ch +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +SRAMLWP +SRAMLAP +0 +SRAMUWP +SRAMUAP +Reserved +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 17 Miscellaneous Control Module (MCM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +381 +General Business Information + +![Image 1 from page 381](pdf-image://page_381_img_1) + +## Page 382 + +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +Reserved +Reserved +Reserved +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +MCM\_CR field descriptions +Field +Description +31 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +30 +SRAMLWP +SRAM\_L Write Protect +When this bit is set, writes to SRAM\_L array generates a bus error. +29–28 +SRAMLAP +SRAM\_L arbitration priority +Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the +SRAM\_L array. +00 +Round robin +01 +Special round robin (favors SRAM backoor accesses over the processor) +10 +Fixed priority. Processor has highest, backdoor has lowest +11 +Fixed priority. Backdoor has highest, processor has lowest +27 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +26 +SRAMUWP +SRAM\_U write protect +When this bit is set, writes to SRAM\_U array generates a bus error. +25–24 +SRAMUAP +SRAM\_U arbitration priority +Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the +SRAM\_U array. +00 +Round robin +01 +Special round robin (favors SRAM backoor accesses over the processor) +10 +Fixed priority. Processor has highest, backdoor has lowest +11 +Fixed priority. Backdoor has highest, processor has lowest +23–10 +Reserved +This field is reserved. +9 +Reserved +This field is reserved. +8–0 +Reserved +This field is reserved. +Memory map/register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +382 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 382](pdf-image://page_382_img_1) + +## Page 383 + +17.2.4 +Interrupt Status Register (MCM\_ISR) +Address: E008\_0000h base + 10h offset = E008\_0010h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +DHREQ +NMI +IRQ +0 +W +w1c +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +MCM\_ISR field descriptions +Field +Description +31–4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3 +DHREQ +Debug Halt Request Indicator +Indicates that a debug halt request is initiated due to a ETB counter expiration, ETBCC[2:0] = 3b111 & +ETBCV[10:0] = 11h0. This bit is cleared when the counter is disabled or when the ETB counter is +reloaded. +0 +No debug halt request +1 +Debug halt request initiated +2 +NMI +Non-maskable Interrupt Pending +If ETBCC[RSPT] is set to 10b, this bit is set when the ETB counter expires. +0 +No pending NMI +1 +Due to the ETB counter expiring, an NMI is pending +1 +IRQ +Normal Interrupt Pending +If ETBCC[RSPT] is set to 01b, this bit is set when the ETB counter expires. +Table continues on the next page... +Chapter 17 Miscellaneous Control Module (MCM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +383 +General Business Information + +![Image 1 from page 383](pdf-image://page_383_img_1) + +## Page 384 + +MCM\_ISR field descriptions (continued) +Field +Description +0 +No pending interrupt +1 +Due to the ETB counter expiring, a normal interrupt is pending +0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +17.2.5 +ETB Counter Control register (MCM\_ETBCC) +Address: E008\_0000h base + 14h offset = E008\_0014h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +ITDIS +ETDIS +RLRQ +RSPT +CNTEN +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +MCM\_ETBCC field descriptions +Field +Description +31–6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5 +ITDIS +ITM-To-TPIU Disable +Disables the trace path from ITM to TPIU. +0 +ITM-to-TPIU trace path enabled +1 +ITM-to-TPIU trace path disabled +4 +ETDIS +ETM-To-TPIU Disable +Disables the trace path from ETM to TPIU. +0 +ETM-to-TPIU trace path enabled +1 +ETM-to-TPIU trace path disabled +3 +RLRQ +Reload Request +Reloads the ETB packet counter with the MCM\_ETBRL RELOAD value. +If IRQ or NMI interrupts were enabled and an NMI or IRQ interrupt was generated on counter expiration, +setting this bit clears the pending NMI or IRQ interrupt request. +Table continues on the next page... +Memory map/register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +384 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 384](pdf-image://page_384_img_1) + +## Page 385 + +MCM\_ETBCC field descriptions (continued) +Field +Description +If debug halt was enabled and a debug halt request was asserted on counter expiration, setting this bit +clears the debug halt request. +0 +No effect +1 +Clears pending debug halt, NMI, or IRQ interrupt requests +2–1 +RSPT +Response Type +00 +No response when the ETB count expires +01 +Generate a normal interrupt when the ETB count expires +10 +Generate an NMI when the ETB count expires +11 +Generate a debug halt when the ETB count expires +0 +CNTEN +Counter Enable +Enables the ETB counter. +0 +ETB counter disabled +1 +ETB counter enabled +17.2.6 +ETB Reload register (MCM\_ETBRL) +Address: E008\_0000h base + 18h offset = E008\_0018h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +RELOAD +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +MCM\_ETBRL field descriptions +Field +Description +31–11 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +10–0 +RELOAD +Byte Count Reload Value +Indicates the 0-mod-4 value the counter reloads to. Writing a non-0-mod-4 value to this field results in a +bus error. +17.2.7 +ETB Counter Value register (MCM\_ETBCNT) +Address: E008\_0000h base + 1Ch offset = E008\_001Ch +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +COUNTER +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 17 Miscellaneous Control Module (MCM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +385 +General Business Information + +![Image 1 from page 385](pdf-image://page_385_img_1) + +## Page 386 + +MCM\_ETBCNT field descriptions +Field +Description +31–11 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +10–0 +COUNTER +Byte Count Counter Value +Indicates the current 0-mod-4 value of the counter. +17.2.8 +Process ID register (MCM\_PID) +This register drives the M0\_PID and M1\_PID values in the Memory Protection +Unit(MPU). System software loads this register before passing control to a given user +mode process. If the PID of the process does not match the value in this register, a bus +error occurs. See the MPU chapter for more details. +Address: E008\_0000h base + 30h offset = E008\_0030h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +PID +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +MCM\_PID field descriptions +Field +Description +31–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7–0 +PID +M0\_PID And M1\_PID For MPU +Drives the M0\_PID and M1\_PID values in the MPU. +17.3 +Functional description +This section describes the functional description of MCM module. +17.3.1 +Interrupts +The MCM generates two interrupt requests: +• Non-maskable interrupt +• Normal interrupt +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +386 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 386](pdf-image://page_386_img_1) + +## Page 387 + +17.3.1.1 +Non-maskable interrupt +The MCM's NMI is generated if: +• ISCR[ETBN] is set, when +• The ETB counter is enabled, ETBCC[CNTEN] = 1 +• The ETB count expires +• The response to counter expiration is an NMI, MCM\_ETBCC[RSPT] = 10 +17.3.1.2 +Normal interrupt +The MCM's normal interrupt is generated if any of the following is true: +• ISCR[ETBI] is set, when +• The ETB counter is enabled, ETBCC[CNTEN] = 1 +• The ETB count expires +• The response to counter expiration is a normal interrupt, ETBCC[RSPT] = 01 +Chapter 17 Miscellaneous Control Module (MCM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +387 +General Business Information + +![Image 1 from page 387](pdf-image://page_387_img_1) + +## Page 388 + +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +388 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 388](pdf-image://page_388_img_1) + +## Page 389 + +Chapter 18 +Crossbar Switch (AXBS) +18.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +This chapter provides information on the layout, configuration, and programming of the +crossbar switch. The crossbar switch connects bus masters and bus slaves using a +crossbar switch structure. This structure allows all bus masters to access different bus +slaves simultaneously, while providing arbitration among the bus masters when they +access the same slave. A variety of bus arbitration methods and attributes may be +programmed on a slave-by-slave basis. +18.1.1 +Features +The crossbar switch includes these distinctive features: +• Symmetric crossbar bus switch implementation +• Allows concurrent accesses from different masters to different slaves +• Slave arbitration attributes configured on a slave-by-slave basis +• 32-bit width and support for byte, 2-byte, 4-byte, and 16-byte burst transfers +• Operation at a 1-to-1 clock frequency with the bus masters +• Low-Power Park mode support +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +389 +General Business Information + +![Image 1 from page 389](pdf-image://page_389_img_1) + +## Page 390 + +18.2 +Memory Map / Register Definition +Each slave port of the crossbar switch contains configuration registers. Read- and write- +transfers require two bus clock cycles. The registers can be read from and written to only +in supervisor mode. Additionally, these registers can be read from or written to only by +32-bit accesses. +A bus error response is returned if an unimplemented location is accessed within the +crossbar switch. +The slave registers also feature a bit that, when set, prevents the registers from being +written. The registers remain readable, but future write attempts have no effect on the +registers and are terminated with a bus error response to the master initiating the write. +The core, for example, takes a bus error interrupt. +NOTE +This section shows the registers for all eight master and slave +ports. If a master or slave is not used on this particular device, +then unexpected results occur when writing to its registers. See +the chip configuration details for the exact master/slave +assignments for your device. +AXBS memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_4000 +Priority Registers Slave (AXBS\_PRS0) +32 +R/W +See section +18.2.1/391 +4000\_4010 +Control Register (AXBS\_CRS0) +32 +R/W +0\_0000 +\_0000h +18.2.2/394 +4000\_4100 +Priority Registers Slave (AXBS\_PRS1) +32 +R/W +See section +18.2.1/391 +4000\_4110 +Control Register (AXBS\_CRS1) +32 +R/W +0\_0000 +\_0000h +18.2.2/394 +4000\_4200 +Priority Registers Slave (AXBS\_PRS2) +32 +R/W +See section +18.2.1/391 +4000\_4210 +Control Register (AXBS\_CRS2) +32 +R/W +0\_0000 +\_0000h +18.2.2/394 +4000\_4300 +Priority Registers Slave (AXBS\_PRS3) +32 +R/W +See section +18.2.1/391 +4000\_4310 +Control Register (AXBS\_CRS3) +32 +R/W +0\_0000 +\_0000h +18.2.2/394 +4000\_4400 +Priority Registers Slave (AXBS\_PRS4) +32 +R/W +See section +18.2.1/391 +4000\_4410 +Control Register (AXBS\_CRS4) +32 +R/W +0\_0000 +\_0000h +18.2.2/394 +4000\_4500 +Priority Registers Slave (AXBS\_PRS5) +32 +R/W +See section +18.2.1/391 +Table continues on the next page... +Memory Map / Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +390 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 390](pdf-image://page_390_img_1) + +## Page 391 + +AXBS memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_4510 +Control Register (AXBS\_CRS5) +32 +R/W +0\_0000 +\_0000h +18.2.2/394 +4000\_4600 +Priority Registers Slave (AXBS\_PRS6) +32 +R/W +See section +18.2.1/391 +4000\_4610 +Control Register (AXBS\_CRS6) +32 +R/W +0\_0000 +\_0000h +18.2.2/394 +4000\_4700 +Priority Registers Slave (AXBS\_PRS7) +32 +R/W +See section +18.2.1/391 +4000\_4710 +Control Register (AXBS\_CRS7) +32 +R/W +0\_0000 +\_0000h +18.2.2/394 +4000\_4800 +Master General Purpose Control Register (AXBS\_MGPCR0) +32 +R/W +0\_0000 +\_0000h +18.2.3/396 +4000\_4900 +Master General Purpose Control Register (AXBS\_MGPCR1) +32 +R/W +0\_0000 +\_0000h +18.2.3/396 +4000\_4A00 +Master General Purpose Control Register (AXBS\_MGPCR2) +32 +R/W +0\_0000 +\_0000h +18.2.3/396 +4000\_4B00 +Master General Purpose Control Register (AXBS\_MGPCR3) +32 +R/W +0\_0000 +\_0000h +18.2.3/396 +4000\_4C00 +Master General Purpose Control Register (AXBS\_MGPCR4) +32 +R/W +0\_0000 +\_0000h +18.2.3/396 +4000\_4D00 +Master General Purpose Control Register (AXBS\_MGPCR5) +32 +R/W +0\_0000 +\_0000h +18.2.3/396 +4000\_4E00 +Master General Purpose Control Register (AXBS\_MGPCR6) +32 +R/W +0\_0000 +\_0000h +18.2.3/396 +4000\_4F00 +Master General Purpose Control Register (AXBS\_MGPCR7) +32 +R/W +0\_0000 +\_0000h +18.2.3/396 +18.2.1 +Priority Registers Slave (AXBS\_PRSn) +The priority registers (PRSn) set the priority of each master port on a per slave port basis +and reside in each slave port. The priority register can be accessed only with 32-bit +accesses. After the CRSn[RO] bit is set, the PRSn register can only be read; attempts to +write to it have no effect on PRSn and result in a bus-error response to the master +initiating the write. +No two available master ports may be programmed with the same priority level. Attempts +to program two or more masters with the same priority level result in a bus-error response +and the PRSn is not updated. +NOTE +The possible values for the PRSn fields depend on the number +of masters available on the device. See the device's chip +configuration details for the number of masters supported. +Chapter 18 Crossbar Switch (AXBS) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +391 +General Business Information + +![Image 1 from page 391](pdf-image://page_391_img_1) + +## Page 392 + +• If the device contains less than five masters, values 000– +011 are valid and writing other values results in an error. +• If the device contains n masters where n ≥ 5, values 0 to n +-1 are valid and writing other values results in an error. +Address: 4000\_4000h base + 0h offset + (256d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +M7 +0 +M6 +0 +M5 +0 +M4 +W +Reset +0\* +1\* +1\* +1\* +0\* +1\* +1\* +0\* +0\* +1\* +0\* +1\* +0\* +1\* +0\* +0\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +M3 +0 +M2 +0 +M1 +0 +M0 +W +Reset +0\* +0\* +1\* +1\* +0\* +0\* +1\* +0\* +0\* +0\* +0\* +1\* +0\* +0\* +0\* +0\* +* Notes: +See the device configuration details for the reset value of this register. +• +AXBS\_PRSn field descriptions +Field +Description +31 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +30–28 +M7 +Master 7 Priority. Sets the arbitration priority for this port on the associated slave port. +000 +This master has level 1, or highest, priority when accessing the slave port. +001 +This master has level 2 priority when accessing the slave port. +010 +This master has level 3 priority when accessing the slave port. +011 +This master has level 4 priority when accessing the slave port. +100 +This master has level 5 priority when accessing the slave port. +101 +This master has level 6 priority when accessing the slave port. +110 +This master has level 7 priority when accessing the slave port. +111 +This master has level 8, or lowest, priority when accessing the slave port. +27 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +26–24 +M6 +Master 6 Priority. Sets the arbitration priority for this port on the associated slave port. +000 +This master has level 1, or highest, priority when accessing the slave port. +001 +This master has level 2 priority when accessing the slave port. +010 +This master has level 3 priority when accessing the slave port. +011 +This master has level 4 priority when accessing the slave port. +100 +This master has level 5 priority when accessing the slave port. +101 +This master has level 6 priority when accessing the slave port. +110 +This master has level 7 priority when accessing the slave port. +111 +This master has level 8, or lowest, priority when accessing the slave port. +23 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +22–20 +M5 +Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. +Table continues on the next page... +Memory Map / Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +392 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 392](pdf-image://page_392_img_1) + +## Page 393 + +AXBS\_PRSn field descriptions (continued) +Field +Description +000 +This master has level 1, or highest, priority when accessing the slave port. +001 +This master has level 2 priority when accessing the slave port. +010 +This master has level 3 priority when accessing the slave port. +011 +This master has level 4 priority when accessing the slave port. +100 +This master has level 5 priority when accessing the slave port. +101 +This master has level 6 priority when accessing the slave port. +110 +This master has level 7 priority when accessing the slave port. +111 +This master has level 8, or lowest, priority when accessing the slave port. +19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18–16 +M4 +Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. +000 +This master has level 1, or highest, priority when accessing the slave port. +001 +This master has level 2 priority when accessing the slave port. +010 +This master has level 3 priority when accessing the slave port. +011 +This master has level 4 priority when accessing the slave port. +100 +This master has level 5 priority when accessing the slave port. +101 +This master has level 6 priority when accessing the slave port. +110 +This master has level 7 priority when accessing the slave port. +111 +This master has level 8, or lowest, priority when accessing the slave port. +15 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +14–12 +M3 +Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. +000 +This master has level 1, or highest, priority when accessing the slave port. +001 +This master has level 2 priority when accessing the slave port. +010 +This master has level 3 priority when accessing the slave port. +011 +This master has level 4 priority when accessing the slave port. +100 +This master has level 5 priority when accessing the slave port. +101 +This master has level 6 priority when accessing the slave port. +110 +This master has level 7 priority when accessing the slave port. +111 +This master has level 8, or lowest, priority when accessing the slave port. +11 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +10–8 +M2 +Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. +000 +This master has level 1, or highest, priority when accessing the slave port. +001 +This master has level 2 priority when accessing the slave port. +010 +This master has level 3 priority when accessing the slave port. +011 +This master has level 4 priority when accessing the slave port. +100 +This master has level 5 priority when accessing the slave port. +101 +This master has level 6 priority when accessing the slave port. +110 +This master has level 7 priority when accessing the slave port. +111 +This master has level 8, or lowest, priority when accessing the slave port. +7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Chapter 18 Crossbar Switch (AXBS) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +393 +General Business Information + +![Image 1 from page 393](pdf-image://page_393_img_1) + +## Page 394 + +AXBS\_PRSn field descriptions (continued) +Field +Description +6–4 +M1 +Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. +000 +This master has level 1, or highest, priority when accessing the slave port. +001 +This master has level 2 priority when accessing the slave port. +010 +This master has level 3 priority when accessing the slave port. +011 +This master has level 4 priority when accessing the slave port. +100 +This master has level 5 priority when accessing the slave port. +101 +This master has level 6 priority when accessing the slave port. +110 +This master has level 7 priority when accessing the slave port. +111 +This master has level 8, or lowest, priority when accessing the slave port. +3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2–0 +M0 +Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. +000 +This master has level 1, or highest, priority when accessing the slave port. +001 +This master has level 2 priority when accessing the slave port. +010 +This master has level 3 priority when accessing the slave port. +011 +This master has level 4 priority when accessing the slave port. +100 +This master has level 5 priority when accessing the slave port. +101 +This master has level 6 priority when accessing the slave port. +110 +This master has level 7 priority when accessing the slave port. +111 +This master has level 8, or lowest, priority when accessing the slave port. +18.2.2 +Control Register (AXBS\_CRSn) +These registers control several features of each slave port and must be accessed using 32- +bit accesses. After CRSn[RO] is set, the PRSn can only be read; attempts to write to it +have no effect and result in an error response. +Address: 4000\_4000h base + 10h offset + (256d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +RO +HLP +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +ARB +0 +PCTL +0 +PARK +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +AXBS\_CRSn field descriptions +Field +Description +31 +RO +Read Only +Forces the slave port’s CSRn and PRSn registers to be read-only. After set, only a hardware reset clears +it. +Table continues on the next page... +Memory Map / Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +394 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 394](pdf-image://page_394_img_1) + +## Page 395 + +AXBS\_CRSn field descriptions (continued) +Field +Description +0 +The slave port’s registers are writeable +1 +The slave port’s registers are read-only and cannot be written. Attempted writes have no effect on the +registers and result in a bus error response. +30 +HLP +Halt Low Priority +Sets the initial arbitration priority for low power mode requests . Setting this bit will not affect the request +for low power mode from attaining highest priority once it has control of the slave ports. +0 +The low power mode request has the highest priority for arbitration on this slave port +1 +The low power mode request has the lowest initial priority for arbitration on this slave port +29–10 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +9–8 +ARB +Arbitration Mode +Selects the arbitration policy for the slave port. +00 +Fixed priority +01 +Round-robin, or rotating, priority +10 +Reserved +11 +Reserved +7–6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5–4 +PCTL +Parking Control +Determines the slave port’s parking control. The low-power park feature results in an overall power +savings if the slave port is not saturated. However, this forces an extra latency clock when any master +tries to access the slave port while not in use because it is not parked on any master. +00 +When no master makes a request, the arbiter parks the slave port on the master port defined by the +PARK field +01 +When no master makes a request, the arbiter parks the slave port on the last master to be in control +of the slave port +10 +When no master makes a request, the slave port is not parked on a master and the arbiter drives all +outputs to a constant safe state +11 +Reserved +3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2–0 +PARK +Park +Determines which master port the current slave port parks on when no masters are actively making +requests and the PCTL bits are cleared. +NOTE: Only select master ports that are actually present on the device. If not, undefined behavior may +occur. +000 +Park on master port M0 +001 +Park on master port M1 +010 +Park on master port M2 +011 +Park on master port M3 +100 +Park on master port M4 +101 +Park on master port M5 +Table continues on the next page... +Chapter 18 Crossbar Switch (AXBS) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +395 +General Business Information + +![Image 1 from page 395](pdf-image://page_395_img_1) + +## Page 396 + +AXBS\_CRSn field descriptions (continued) +Field +Description +110 +Park on master port M6 +111 +Park on master port M7 +18.2.3 +Master General Purpose Control Register (AXBS\_MGPCRn) +The MGPCR controls only whether the master’s undefined length burst accesses are +allowed to complete uninterrupted or whether they can be broken by requests from higher +priority masters. The MGPCR can be accessed only in Supervisor mode with 32-bit +accesses. +Address: 4000\_4000h base + 800h offset + (256d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +AULB +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +AXBS\_MGPCRn field descriptions +Field +Description +31–3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2–0 +AULB +Arbitrates On Undefined Length Bursts +Determines whether, and when, the crossbar switch arbitrates away the slave port the master owns when +the master is performing undefined length burst accesses. +000 +No arbitration is allowed during an undefined length burst +001 +Arbitration is allowed at any time during an undefined length burst +010 +Arbitration is allowed after four beats of an undefined length burst +011 +Arbitration is allowed after eight beats of an undefined length burst +100 +Arbitration is allowed after 16 beats of an undefined length burst +101 +Reserved +110 +Reserved +111 +Reserved +18.3 +Functional Description +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +396 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 396](pdf-image://page_396_img_1) + +## Page 397 + +18.3.1 +General operation +When a master accesses the crossbar switch the access is immediately taken. If the +targeted slave port of the access is available, then the access is immediately presented on +the slave port. Single-clock, or -zero-wait state, accesses are possible through the +crossbar. If the targeted slave port of the access is busy or parked on a different master +port, the requesting master simply sees wait states inserted until the targeted slave port +can service the master's request. The latency in servicing the request depends on each +master's priority level and the responding peripheral's access time. +Because the crossbar switch appears to be just another slave to the master device, the +master device has no knowledge of whether it actually owns the slave port it is targeting. +While the master does not have control of the slave port it is targeting, it simply waits. +A master is given control of the targeted slave port only after a previous access to a +different slave port completes, regardless of its priority on the newly targeted slave port. +This prevents deadlock from occurring when: +• A higher priority master has: +• An outstanding request to one slave port that has a long response time and +• A pending access to a different slave port, and +• A lower priority master is also making a request to the same slave port as the pending +access of the higher priority master. +After the master has control of the slave port it is targeting, the master remains in control +of that slave port until it gives up the slave port by running an IDLE cycle or by leaving +that slave port for its next access. +The master could also lose control of the slave port if another higher priority master +makes a request to the slave port; however, if the master is running a fixed-length burst +transfer it retains control of the slave port until that transfer completes. Based on +MGPCR[AULB], the master either retains control of the slave port when doing undefined +length incrementing burst transfers or loses the bus to a higher priority master. +The crossbar terminates all master IDLE transfers, as opposed to allowing the termination +to come from one of the slave buses. Additionally, when no master is requesting access to +a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default +master may be granted access to the slave port. +When a slave bus is being idled by the crossbar, it can park the slave port on the master +port indicated by CRSn[PARK]. This is done to save the initial clock of arbitration delay +that otherwise would be seen if the master had to arbitrate to gain control of the slave +port. The slave port can also be put into Low Power Park mode to save power, by using +CRSn[PCTL]. +Chapter 18 Crossbar Switch (AXBS) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +397 +General Business Information + +![Image 1 from page 397](pdf-image://page_397_img_1) + +## Page 398 + +18.3.2 +Register coherency +The operation of the crossbar is affected as soon as a register is written. The values of the +registers do not track with slave-port-related master accesses, but instead track only with +slave accesses. +The MGPCRx[AULB] bits are the exception to this rule. The update of these bits is only +recognized when the master on that master port runs an IDLE cycle, even though the +slave bus cycle to write them will have already terminated successfully. If the +MGPCRx[AULB] bits are written between two burst accesses, the new AULB encodings +do not take effect until an IDLE cycle is initiated by the master on that master port. +18.3.3 +Arbitration +The crossbar switch supports two arbitration schemes: +• A fixed-priority comparison algorithm +• A round-robin fairness algorithm +The arbitration scheme is independently programmable for each slave port. +18.3.3.1 +Arbitration during undefined length bursts +Arbitration points during an undefined length burst are defined by the current master's +MGPCR[AULB] field setting. When a defined length is imposed on the burst via the +AULB bits, the undefined length burst is treated as a single or series of single back-to- +back fixed-length burst accesses. +The following figure illustrates an example: +Lost control +Lost control +Master-to-slave +transfer +1 +2 +3 +4 +5 +6 +7 +8 +9 +10 +11 +12 +1 beat +1 beat +12 beat burst +No arbitration +Arbitration allowed +No arbitration +No arbitration +MGPCR[AULB] +Figure 18-28. Undefined length burst example +In this example, a master runs an undefined length burst and the MGPCR[AULB] bits +indicate arbitration occurs after the fourth beat of the burst. The master runs two +sequential beats and then starts what will be a 12-beat undefined length burst access to a +new address within the same slave port region as the previous access. The crossbar does +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +398 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 398](pdf-image://page_398_img_1) + +## Page 399 + +not allow an arbitration point until the fourth overall access, or the second beat of the +second burst. At that point, all remaining accesses are open for arbitration until the master +loses control of the slave port. +Assume the master loses control of the slave port after the fifth beat of the second burst. +After the master regains control of the slave port no arbitration point is available until +after the master has run four more beats of its burst. After the fourth beat of the now +continued burst, or the ninth beat of the second burst from the master's perspective, is +taken, all beats of the burst are once again open for arbitration until the master loses +control of the slave port. +Assume the master again loses control of the slave port on the fifth beat of the third now +continued burst, or the 10th beat of the second burst from the master's perspective. After +the master regains control of the slave port, it is allowed to complete its final two beats of +its burst without facing arbitration. +Note +Fixed-length burst accesses are not affected by the AULB bits. +All fixed-length burst accesses lock out arbitration until the last +beat of the fixed-length burst. +18.3.3.2 +Fixed-priority operation +When operating in Fixed-Priority mode, each master is assigned a unique priority level in +the priority registers (PRSn) . If two masters request access to a slave port, the master +with the highest priority in the selected priority register gains control over the slave port. +When a master makes a request to a slave port, the slave port checks whether the new +requesting master's priority level is higher than that of the master that currently has +control over the slave port, unless the slave port is in a parked state. The slave port +performs an arbitration check at every clock edge to ensure that the proper master, if any, +has control of the slave port. +The following table describes possible scenarios based on the requesting master port: +Table 18-29. How AXBS grants control of a slave port to a master +When +Then AXBS grants control to the requesting master +Both of the following are true: +• The current master is not running a transfer. +• The new requesting master's priority level is higher than +that of the current master. +At the next clock edge +Table continues on the next page... +Chapter 18 Crossbar Switch (AXBS) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +399 +General Business Information + +![Image 1 from page 399](pdf-image://page_399_img_1) + +## Page 400 + +Table 18-29. How AXBS grants control of a slave port to a master (continued) +When +Then AXBS grants control to the requesting master +Both of the following are true: +• The current master is running a fixed length burst +transfer or a locked transfer. +• The requesting master's priority level is higher than that +of the current master. +At the end of the burst transfer or locked transfer +Both of the following are true: +• The current master is running an undefined length burst +transfer. +• The requesting master's priority level is higher than that +of the current master. +At the next arbitration point for the undefined length burst +transfer +NOTE: Arbitration points for an undefined length burst are +defined in the MGPCR for each master. +The requesting master's priority level is lower than the current +master. +At the conclusion of one of the following cycles: +• An IDLE cycle +• A non-IDLE cycle to a location other than the current +slave port +18.3.3.3 +Round-robin priority operation +When operating in Round-Robin mode, each master is assigned a relative priority based +on the master port number. This relative priority is compared to the master port number +(ID) of the last master to perform a transfer on the slave bus. The highest priority +requesting master becomes owner of the slave bus at the next transfer boundary, +accounting for locked and fixed-length burst transfers. Priority is based on how far ahead +the ID of the requesting master is to the ID of the last master. +After granted access to a slave port, a master may perform as many transfers as desired to +that port until another master makes a request to the same slave port. The next master in +line is granted access to the slave port at the next transfer boundary, or possibly on the +next clock cycle if the current master has no pending access request. +As an example of arbitration in Round-Robin mode, assume the crossbar is implemented +with master ports 0, 1, 4, and 5. If the last master of the slave port was master 1, and +master 0, 4 and 5 make simultaneous requests, they are serviced in the order 4, 5, and +then 0. +Parking may continue to be used in a round-robin mode, but does not affect the round- +robin pointer unless the parked master actually performs a transfer. Handoff occurs to the +next master in line after one cycle of arbitration. If the slave port is put into low-power +park mode, the round-robin pointer is reset to point at master port 0, giving it the highest +priority. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +400 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 400](pdf-image://page_400_img_1) + +## Page 401 + +18.3.3.4 +Priority assignment +Each master port must be assigned a unique 3-bit priority level. If an attempt is made to +program multiple master ports with the same priority level within the priority registers +(PRSn), the crossbar switch responds with a bus error and the registers are not updated. +18.4 +Initialization/application information +No initialization is required by or for the crossbar switch. Hardware reset ensures all the +register bits used by the crossbar switch are properly initialized to a valid state. However, +settings and priorities may be programmed to achieve maximum system performance. +Chapter 18 Crossbar Switch (AXBS) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +401 +General Business Information + +![Image 1 from page 401](pdf-image://page_401_img_1) + +## Page 402 + +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +402 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 402](pdf-image://page_402_img_1) + +## Page 403 + +Chapter 19 +Memory Protection Unit (MPU) +19.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The memory protection unit (MPU) provides hardware access control for all memory +references generated in the device. +19.2 +Overview +The MPU concurrently monitors all system bus transactions and evaluates their +appropriateness using pre-programmed region descriptors that define memory spaces and +their access rights. Memory references that have sufficient access control rights are +allowed to complete, while references that are not mapped to any region descriptor or +have insufficient rights are terminated with a protection error response. +19.2.1 +Block diagram +A simplified block diagram of the MPU module is shown in the following figure. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +403 +General Business Information + +![Image 1 from page 403](pdf-image://page_403_img_1) + +## Page 404 + +Slave Port n +Internal +Region +Descriptor 0 +Region +Descriptor 1 +Region +Descriptor x +Access +Evaluation +Macro +Access +Evaluation +Macro +Access +Evaluation +Macro +Mux +Address Phase Signals +Peripheral Bus +MPU\_EARn +MPU\_EDRn +Figure 19-1. MPU block diagram +The hardware's two-dimensional connection matrix is clearly visible with the basic access +evaluation macro shown as the replicated submodule block. The crossbar switch slave +ports are shown on the left, the region descriptor registers in the middle, and the +peripheral bus interface on the right side. The evaluation macro contains two magnitude +comparators connected to the start and end address registers from each region descriptor +as well as the combinational logic blocks to determine the region hit and the access +protection error. For details of the access evaluation macro, see Access evaluation macro. +19.2.2 +Features +The MPU implements a two-dimensional hardware array of memory region descriptors +and the crossbar slave ports to continuously monitor the legality of every memory +reference generated by each bus master in the system. +The feature set includes: +• 12 program-visible 128-bit region descriptors, accessible by four 32-bit words each +• Each region descriptor defines a modulo-32 byte space, aligned anywhere in +memory +Overview +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +404 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 404](pdf-image://page_404_img_1) + +## Page 405 + +• Region sizes can vary from 32 bytes to 4 Gbytes +• Two access control permissions defined in a single descriptor word +• Masters 0–3: read, write, and execute attributes for supervisor and user +accesses +• Masters 4–7: read and write attributes +• Hardware-assisted maintenance of the descriptor valid bit minimizes coherency +issues +• Alternate programming model view of the access control permissions word +• Priority given to granting permission over denying access for overlapping region +descriptors +• Detects access protection errors if a memory reference does not hit in any memory +region, or if the reference is illegal in all hit memory regions. If an access error +occurs, the reference is terminated with an error response, and the MPU inhibits the +bus cycle being sent to the targeted slave device. +• Error registers, per slave port, capture the last faulting address, attributes, and other +information +• Global MPU enable/disable control bit +19.3 +Memory map/register definition +The programming model is partitioned into three groups: +• Control/status registers +• The data structure containing the region descriptors +• The alternate view of the region descriptor access control values +The programming model can only be referenced using 32-bit accesses. Attempted +references using different access sizes, to undefined, that is, reserved, addresses, or with a +non-supported access type, such as a write to a read-only register, or a read of a write- +only register, generate an error termination. +The programming model can be accessed only in supervisor mode. +NOTE +See the chip configuration details for any chip-specific register +information this module. +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +405 +General Business Information + +![Image 1 from page 405](pdf-image://page_405_img_1) + +## Page 406 + +MPU memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_D000 +Control/Error Status Register (MPU\_CESR) +32 +R/W +00\_8151 +\_0181\_5101h +19.3.1/409 +4000\_D010 +Error Address Register, slave port n (MPU\_EAR0) +32 +R +Undefined +19.3.2/410 +4000\_D014 +Error Detail Register, slave port n (MPU\_EDR0) +32 +R +Undefined +19.3.3/411 +4000\_D018 +Error Address Register, slave port n (MPU\_EAR1) +32 +R +Undefined +19.3.2/410 +4000\_D01C +Error Detail Register, slave port n (MPU\_EDR1) +32 +R +Undefined +19.3.3/411 +4000\_D020 +Error Address Register, slave port n (MPU\_EAR2) +32 +R +Undefined +19.3.2/410 +4000\_D024 +Error Detail Register, slave port n (MPU\_EDR2) +32 +R +Undefined +19.3.3/411 +4000\_D028 +Error Address Register, slave port n (MPU\_EAR3) +32 +R +Undefined +19.3.2/410 +4000\_D02C +Error Detail Register, slave port n (MPU\_EDR3) +32 +R +Undefined +19.3.3/411 +4000\_D030 +Error Address Register, slave port n (MPU\_EAR4) +32 +R +Undefined +19.3.2/410 +4000\_D034 +Error Detail Register, slave port n (MPU\_EDR4) +32 +R +Undefined +19.3.3/411 +4000\_D400 +Region Descriptor n, Word 0 (MPU\_RGD0\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D404 +Region Descriptor n, Word 1 (MPU\_RGD0\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D408 +Region Descriptor n, Word 2 (MPU\_RGD0\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D40C +Region Descriptor n, Word 3 (MPU\_RGD0\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D410 +Region Descriptor n, Word 0 (MPU\_RGD1\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D414 +Region Descriptor n, Word 1 (MPU\_RGD1\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D418 +Region Descriptor n, Word 2 (MPU\_RGD1\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D41C +Region Descriptor n, Word 3 (MPU\_RGD1\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D420 +Region Descriptor n, Word 0 (MPU\_RGD2\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D424 +Region Descriptor n, Word 1 (MPU\_RGD2\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D428 +Region Descriptor n, Word 2 (MPU\_RGD2\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D42C +Region Descriptor n, Word 3 (MPU\_RGD2\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D430 +Region Descriptor n, Word 0 (MPU\_RGD3\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D434 +Region Descriptor n, Word 1 (MPU\_RGD3\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D438 +Region Descriptor n, Word 2 (MPU\_RGD3\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +406 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 406](pdf-image://page_406_img_1) + +## Page 407 + +MPU memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_D43C +Region Descriptor n, Word 3 (MPU\_RGD3\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D440 +Region Descriptor n, Word 0 (MPU\_RGD4\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D444 +Region Descriptor n, Word 1 (MPU\_RGD4\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D448 +Region Descriptor n, Word 2 (MPU\_RGD4\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D44C +Region Descriptor n, Word 3 (MPU\_RGD4\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D450 +Region Descriptor n, Word 0 (MPU\_RGD5\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D454 +Region Descriptor n, Word 1 (MPU\_RGD5\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D458 +Region Descriptor n, Word 2 (MPU\_RGD5\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D45C +Region Descriptor n, Word 3 (MPU\_RGD5\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D460 +Region Descriptor n, Word 0 (MPU\_RGD6\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D464 +Region Descriptor n, Word 1 (MPU\_RGD6\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D468 +Region Descriptor n, Word 2 (MPU\_RGD6\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D46C +Region Descriptor n, Word 3 (MPU\_RGD6\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D470 +Region Descriptor n, Word 0 (MPU\_RGD7\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D474 +Region Descriptor n, Word 1 (MPU\_RGD7\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D478 +Region Descriptor n, Word 2 (MPU\_RGD7\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D47C +Region Descriptor n, Word 3 (MPU\_RGD7\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D480 +Region Descriptor n, Word 0 (MPU\_RGD8\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D484 +Region Descriptor n, Word 1 (MPU\_RGD8\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D488 +Region Descriptor n, Word 2 (MPU\_RGD8\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D48C +Region Descriptor n, Word 3 (MPU\_RGD8\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D490 +Region Descriptor n, Word 0 (MPU\_RGD9\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +Table continues on the next page... +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +407 +General Business Information + +![Image 1 from page 407](pdf-image://page_407_img_1) + +## Page 408 + +MPU memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_D494 +Region Descriptor n, Word 1 (MPU\_RGD9\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D498 +Region Descriptor n, Word 2 (MPU\_RGD9\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D49C +Region Descriptor n, Word 3 (MPU\_RGD9\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D4A0 +Region Descriptor n, Word 0 (MPU\_RGD10\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D4A4 +Region Descriptor n, Word 1 (MPU\_RGD10\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D4A8 +Region Descriptor n, Word 2 (MPU\_RGD10\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D4AC +Region Descriptor n, Word 3 (MPU\_RGD10\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D4B0 +Region Descriptor n, Word 0 (MPU\_RGD11\_WORD0) +32 +R/W +0\_0000 +\_0000h +19.3.4/412 +4000\_D4B4 +Region Descriptor n, Word 1 (MPU\_RGD11\_WORD1) +32 +R/W +00\_0000 +\_1F1Fh +19.3.5/412 +4000\_D4B8 +Region Descriptor n, Word 2 (MPU\_RGD11\_WORD2) +32 +R/W +0\_0000 +\_0000h +19.3.6/413 +4000\_D4BC +Region Descriptor n, Word 3 (MPU\_RGD11\_WORD3) +32 +R/W +0\_0000 +\_0000h +19.3.7/416 +4000\_D800 +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC0) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D804 +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC1) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D808 +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC2) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D80C +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC3) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D810 +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC4) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D814 +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC5) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D818 +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC6) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D81C +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC7) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D820 +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC8) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D824 +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC9) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +4000\_D828 +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC10) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +408 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 408](pdf-image://page_408_img_1) + +## Page 409 + +MPU memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_D82C +Region Descriptor Alternate Access Control n +(MPU\_RGDAAC11) +32 +R/W +0\_0000 +\_0000h +19.3.8/417 +19.3.1 +Control/Error Status Register (MPU\_CESR) +Address: 4000\_D000h base + 0h offset = 4000\_D000h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +SPERR +0 +1 +0 +HRL +W +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +1 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +NSP +NRGD +0 +VLD +W +Reset +0 +1 +0 +1 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +1 +MPU\_CESR field descriptions +Field +Description +31–27 +SPERR +Slave Port n Error +Indicates a captured error in EARn and EDRn. This bit is set when the hardware detects an error and +records the faulting address and attributes. It is cleared by writing one to it. If another error is captured at +the exact same cycle as the write, the flag remains set. A find-first-one instruction or equivalent can detect +the presence of a captured error. +The following shows the correspondence between the bit number and slave port number: +• Bit 31 corresponds to slave port 0. +• Bit 30 corresponds to slave port 1. +• Bit 29 corresponds to slave port 2. +• Bit 28 corresponds to slave port 3. +• Bit 27 corresponds to slave port 4. +0 +No error has occurred for slave port n. +1 +An error has occurred for slave port n. +26–24 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +23 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 1. +22–20 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +19–16 +HRL +Hardware Revision Level +Specifies the MPU’s hardware and definition revision level. It can be read by software to determine the +functional definition of the module. +Table continues on the next page... +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +409 +General Business Information + +![Image 1 from page 409](pdf-image://page_409_img_1) + +## Page 410 + +MPU\_CESR field descriptions (continued) +Field +Description +15–12 +NSP +Number Of Slave Ports +Specifies the number of slave ports connected to the MPU. +11–8 +NRGD +Number Of Region Descriptors +Indicates the number of region descriptors implemented in the MPU. +0000 +8 region descriptors +0001 +12 region descriptors +0010 +16 region descriptors +7–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +VLD +Valid +Global enable/disable for the MPU. +0 +MPU is disabled. All accesses from all bus masters are allowed. +1 +MPU is enabled +19.3.2 +Error Address Register, slave port n (MPU\_EARn) +When the MPU detects an access error on slave port n, the 32-bit reference address is +captured in this read-only register and the corresponding bit in CESR[SPERR] set. +Additional information about the faulting access is captured in the corresponding EDRn +at the same time. This register and the corresponding EDRn contain the most recent +access error; there are no hardware interlocks with CESR[SPERR], as the error registers +are always loaded upon the occurrence of each protection violation. +Address: 4000\_D000h base + 10h offset + (8d × i), where i=0d to 4d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +EADDR +W +Reset x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x* x* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +MPU\_EARn field descriptions +Field +Description +31–0 +EADDR +Error Address +Indicates the reference address from slave port n that generated the access error +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +410 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 410](pdf-image://page_410_img_1) + +## Page 411 + +19.3.3 +Error Detail Register, slave port n (MPU\_EDRn) +When the MPU detects an access error on slave port n, 32 bits of error detail are captured +in this read-only register and the corresponding bit in CESR[SPERR] is set. Information +on the faulting address is captured in the corresponding EARn register at the same time. +This register and the corresponding EARn register contain the most recent access error; +there are no hardware interlocks with CESR[SPERR] as the error registers are always +loaded upon the occurrence of each protection violation. +Address: 4000\_D000h base + 14h offset + (8d × i), where i=0d to 4d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +EACD +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +EMN +EATTR +ERW +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +MPU\_EDRn field descriptions +Field +Description +31–16 +EACD +Error Access Control Detail +Indicates the region descriptor with the access error. +• If EDRn contains a captured error and EACD is cleared, an access did not hit in any region +descriptor. +• If only a single EACD bit is set, the protection error was caused by a single non-overlapping region +descriptor. +• If two or more EACD bits are set, the protection error was caused by an overlapping set of region +descriptors. +15–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7–4 +EMN +Error Master Number +Indicates the bus master that generated the access error. +3–1 +EATTR +Error Attributes +Indicates attribute information about the faulting reference. +NOTE: All other encodings are reserved. +000 +User mode, instruction access +001 +User mode, data access +Table continues on the next page... +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +411 +General Business Information + +![Image 1 from page 411](pdf-image://page_411_img_1) + +## Page 412 + +MPU\_EDRn field descriptions (continued) +Field +Description +010 +Supervisor mode, instruction access +011 +Supervisor mode, data access +0 +ERW +Error Read/Write +Indicates the access type of the faulting reference. +0 +Read +1 +Write +19.3.4 +Region Descriptor n, Word 0 (MPU\_RGDn\_WORD0) +The first word of the region descriptor defines the 0-modulo-32 byte start address of the +memory region. Writes to this register clear the region descriptor’s valid bit +(RGDn\_WORD3[VLD]). +Address: 4000\_D000h base + 400h offset + (16d × i), where i=0d to 11d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +SRTADDR +0 +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +MPU\_RGDn\_WORD0 field descriptions +Field +Description +31–5 +SRTADDR +Start Address +Defines the most significant bits of the 0-modulo-32 byte start address of the memory region. +4–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +19.3.5 +Region Descriptor n, Word 1 (MPU\_RGDn\_WORD1) +The second word of the region descriptor defines the 31-modulo-32 byte end address of +the memory region. Writes to this register clear the region descriptor’s valid bit +(RGDn\_WORD3[VLD]). +Address: 4000\_D000h base + 404h offset + (16d × i), where i=0d to 11d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +ENDADDR +Reserved +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +412 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 412](pdf-image://page_412_img_1) + +## Page 413 + +MPU\_RGDn\_WORD1 field descriptions +Field +Description +31–5 +ENDADDR +End Address +Defines the most significant bits of the 31-modulo-32 byte end address of the memory region. +NOTE: The MPU does not verify that ENDADDR ≥ SRTADDR. +4–0 +Reserved +This field is reserved. +19.3.6 +Region Descriptor n, Word 2 (MPU\_RGDn\_WORD2) +The third word of the region descriptor defines the access control rights of the memory +region. The access control privileges depend on two broad classifications of bus masters: +• Bus masters 0–3 have a 5-bit field defining separate privilege rights for user and +supervisor mode accesses. +• Bus masters 4–7 are limited to separate read and write permissions. +For the privilege rights of bus masters 0–3, there are three flags associated with this +function: +• Read (r) refers to accessing the referenced memory address using an operand (data) +fetch +• Write (w) refers to updating the referenced memory address using a store (data) +instruction +• Execute (x) refers to reading the referenced memory address using an instruction +fetch +Writes to RGDn\_WORD2 clear the region descriptor’s valid bit +(RGDn\_WORD3[VLD]). If only updating the access controls, write to RGDAACn +instead because stores to these locations do not affect the descriptor’s valid bit. +Address: 4000\_D000h base + 408h offset + (16d × i), where i=0d to 11d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +M7RE +M7WE +M6RE +M6WE +M5RE +M5WE +M4RE +M4WE +Reserved +M3SM +M3UM +Reserved +M2S +M +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +413 +General Business Information + +![Image 1 from page 413](pdf-image://page_413_img_1) + +## Page 414 + +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +M2S +M +M2UM +Reserved +M1SM +M1UM +Reserved +M0SM +M0UM +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +MPU\_RGDn\_WORD2 field descriptions +Field +Description +31 +M7RE +Bus Master 7 Read Enable +0 +Bus master 7 reads terminate with an access error and the read is not performed +1 +Bus master 7 reads allowed +30 +M7WE +Bus Master 7 Write Enable +0 +Bus master 7 writes terminate with an access error and the write is not performed +1 +Bus master 7 writes allowed +29 +M6RE +Bus Master 6 Read Enable +0 +Bus master 6 reads terminate with an access error and the read is not performed +1 +Bus master 6 reads allowed +28 +M6WE +Bus Master 6 Write Enable +0 +Bus master 6 writes terminate with an access error and the write is not performed +1 +Bus master 6 writes allowed +27 +M5RE +Bus Master 5 Read Enable +0 +Bus master 5 reads terminate with an access error and the read is not performed +1 +Bus master 5 reads allowed +26 +M5WE +Bus Master 5 Write Enable +0 +Bus master 5 writes terminate with an access error and the write is not performed +1 +Bus master 5 writes allowed +25 +M4RE +Bus Master 4 Read Enable +0 +Bus master 4 reads terminate with an access error and the read is not performed +1 +Bus master 4 reads allowed +24 +M4WE +Bus Master 4 Write Enable +0 +Bus master 4 writes terminate with an access error and the write is not performed +1 +Bus master 4 writes allowed +23 +Reserved +This field is reserved. +This bit must be written with a zero. +22–21 +M3SM +Bus Master 3 Supervisor Mode Access Control +Defines the access controls for bus master 3 in Supervisor mode. +00 +r/w/x; read, write and execute allowed +01 +r/x; read and execute allowed, but no write +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +414 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 414](pdf-image://page_414_img_1) + +## Page 415 + +MPU\_RGDn\_WORD2 field descriptions (continued) +Field +Description +10 +r/w; read and write allowed, but no execute +11 +Same as User mode defined in M3UM +20–18 +M3UM +Bus Master 3 User Mode Access Control +Defines the access controls for bus master 3 in User mode. M3UM consists of three independent bits, +enabling read (r), write (w), and execute (x) permissions. +0 +An attempted access of that mode may be terminated with an access error (if not allowed by another +descriptor) and the access not performed. +1 +Allows the given access type to occur +17 +Reserved +This field is reserved. +This bit must be written with a zero. +16–15 +M2SM +Bus Master 2 Supervisor Mode Access Control +See M3SM description. +14–12 +M2UM +Bus Master 2 User Mode Access control +See M3UM description. +11 +Reserved +This field is reserved. +This bit must be written with a zero. +10–9 +M1SM +Bus Master 1 Supervisor Mode Access Control +See M3SM description. +8–6 +M1UM +Bus Master 1 User Mode Access Control +See M3UM description. +5 +Reserved +This field is reserved. +This bit must be written with a zero. +4–3 +M0SM +Bus Master 0 Supervisor Mode Access Control +See M3SM description. +2–0 +M0UM +Bus Master 0 User Mode Access Control +See M3UM description. +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +415 +General Business Information + +![Image 1 from page 415](pdf-image://page_415_img_1) + +## Page 416 + +19.3.7 +Region Descriptor n, Word 3 (MPU\_RGDn\_WORD3) +The fourth word of the region descriptor contains the region descriptor’s valid bit. +Address: 4000\_D000h base + 40Ch offset + (16d × i), where i=0d to 11d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +VLD +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +MPU\_RGDn\_WORD3 field descriptions +Field +Description +31–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +VLD +Valid +Signals the region descriptor is valid. Any write to RGDn\_WORD0–2 clears this bit. +0 +Region descriptor is invalid +1 +Region descriptor is valid +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +416 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 416](pdf-image://page_416_img_1) + +## Page 417 + +19.3.8 +Region Descriptor Alternate Access Control n +(MPU\_RGDAACn) +Because software may adjust only the access controls within a region descriptor +(RGDn\_WORD2) as different tasks execute, an alternate programming view of this 32- +bit entity is available. Writing to this register does not affect the descriptor’s valid bit. +Address: 4000\_D000h base + 800h offset + (4d × i), where i=0d to 11d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +M7RE +M7WE +M6RE +M6WE +M5RE +M5WE +M4RE +M4WE +Reserved +M3SM +M3UM +Reserved +M2S +M +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +M2S +M +M2UM +Reserved +M1SM +M1UM +Reserved +M0SM +M0UM +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +MPU\_RGDAACn field descriptions +Field +Description +31 +M7RE +Bus Master 7 Read Enable +0 +Bus master 7 reads terminate with an access error and the read is not performed +1 +Bus master 7 reads allowed +30 +M7WE +Bus Master 7 Write Enable +0 +Bus master 7 writes terminate with an access error and the write is not performed +1 +Bus master 7 writes allowed +29 +M6RE +Bus Master 6 Read Enable +0 +Bus master 6 reads terminate with an access error and the read is not performed +1 +Bus master 6 reads allowed +28 +M6WE +Bus Master 6 Write Enable +0 +Bus master 6 writes terminate with an access error and the write is not performed +1 +Bus master 6 writes allowed +27 +M5RE +Bus Master 5 Read Enable +0 +Bus master 5 reads terminate with an access error and the read is not performed +1 +Bus master 5 reads allowed +Table continues on the next page... +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +417 +General Business Information + +![Image 1 from page 417](pdf-image://page_417_img_1) + +## Page 418 + +MPU\_RGDAACn field descriptions (continued) +Field +Description +26 +M5WE +Bus Master 5 Write Enable +0 +Bus master 5 writes terminate with an access error and the write is not performed +1 +Bus master 5 writes allowed +25 +M4RE +Bus Master 4 Read Enable +0 +Bus master 4 reads terminate with an access error and the read is not performed +1 +Bus master 4 reads allowed +24 +M4WE +Bus Master 4 Write Enable +0 +Bus master 4 writes terminate with an access error and the write is not performed +1 +Bus master 4 writes allowed +23 +Reserved +This field is reserved. +This bit must be written with a zero. +22–21 +M3SM +Bus Master 3 Supervisor Mode Access Control +Defines the access controls for bus master 3 in Supervisor mode. +00 +r/w/x; read, write and execute allowed +01 +r/x; read and execute allowed, but no write +10 +r/w; read and write allowed, but no execute +11 +Same as User mode defined in M3UM +20–18 +M3UM +Bus Master 3 User Mode Access Control +Defines the access controls for bus master 3 in user mode. M3UM consists of three independent bits, +enabling read (r), write (w), and execute (x) permissions. +0 +An attempted access of that mode may be terminated with an access error (if not allowed by another +descriptor) and the access not performed. +1 +Allows the given access type to occur +17 +Reserved +This field is reserved. +This bit must be written with a zero. +16–15 +M2SM +Bus Master 2 Supervisor Mode Access Control +See M3SM description. +14–12 +M2UM +Bus Master 2 User Mode Access Control +See M3UM description. +11 +Reserved +This field is reserved. +This bit must be written with a zero. +10–9 +M1SM +Bus Master 1 Supervisor Mode Access Control +See M3SM description. +8–6 +M1UM +Bus Master 1 User Mode Access Control +See M3UM description. +5 +Reserved +This field is reserved. +This bit must be written with a zero. +4–3 +M0SM +Bus Master 0 Supervisor Mode Access Control +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +418 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 418](pdf-image://page_418_img_1) + +## Page 419 + +MPU\_RGDAACn field descriptions (continued) +Field +Description +See M3SM description. +2–0 +M0UM +Bus Master 0 User Mode Access Control +See M3UM description. +19.4 +Functional description +In this section, the functional operation of the MPU is detailed, including the operation of +the access evaluation macro and the handling of error-terminated bus cycles. +19.4.1 +Access evaluation macro +The basic operation of the MPU is performed in the access evaluation macro, a hardware +structure replicated in the two-dimensional connection matrix. As shown in the following +figure, the access evaluation macro inputs the crossbar bus address phase signals and the +contents of a region descriptor (RGDn) and performs two major functions: +• Region hit determination +• Detection of an access protection violation +The following figure shows a functional block diagram. +start +end +error +8 +8 +RGDn +MPU\_EDRn +Access not allowed +8 +7 +hit\_b +Address +(hit AND error) +(no hit OR error) +r,w,x +Figure 19-80. MPU access evaluation macro +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +419 +General Business Information + +![Image 1 from page 419](pdf-image://page_419_img_1) + +## Page 420 + +19.4.1.1 +Hit determination +To determine whether the current reference hits in the given region, two magnitude +comparators are used with the region's start and end addresses. The boolean equation for +this portion of the hit determination is: +region\_hit = ((addr[31:5] >= RGDn\_Word0[SRTADDR]) & (addr[31:5] <= RGDn\_Word1[ENDADDR])) & +RGDn\_Word3[VLD] +where addr is the current reference address, RGDn\_Word0[SRTADDR] and +RGDn\_Word1[ENDADDR] are the start and end addresses, and RGDn\_Word3[VLD] is +the valid bit. +NOTE +The MPU does not verify that ENDADDR ≥ SRTADDR. +19.4.1.2 +Privilege violation determination +While the access evaluation macro is determining region hit, the logic is also evaluating +if the current access is allowed by the permissions defined in the region descriptor. Using +the master and supervisor/user mode signals, a set of effective permissions is generated +from the appropriate fields in the region descriptor. The protection violation logic then +evaluates the access against the effective permissions using the specification shown +below. +Table 19-80. Protection violation definition +Description +MxUM +Protection +violation? +r +w +x +Instruction fetch read +— +— +0 +Yes, no execute permission +— +— +1 +No, access is allowed +Data read +0 +— +— +Yes, no read permission +1 +— +— +No, access is allowed +Data write +— +0 +— +Yes, no write permission +— +1 +— +No, access is allowed +19.4.2 +Putting it all together and error terminations +For each slave port monitored, the MPU performs a reduction-AND of all the individual +terms from each access evaluation macro. This expression then terminates the bus cycle +with an error and reports a protection error for three conditions: +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +420 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 420](pdf-image://page_420_img_1) + +## Page 421 + +• If the access does not hit in any region descriptor, a protection error is reported. +• If the access hits in a single region descriptor and that region signals a protection +violation, a protection error is reported. +• If the access hits in multiple (overlapping) regions and all regions signal protection +violations, a protection error is reported. +As shown in the third condition, granting permission is a higher priority than denying +access for overlapping regions. This approach is more flexible to system software in +region descriptor assignments. For an example of the use of overlapping region +descriptors, see Application information. +19.4.3 +Power management +Disabling the MPU by clearing CESR[VLD] minimizes power dissipation. To minimize +the power dissipation of an enabled MPU, invalidate unused region descriptors by +clearing the associated RGDn\_Word3[VLD] bits. +19.5 +Initialization information +At system startup, load the appropriate number of region descriptors, including setting +RGDn\_Word3[VLD]. Setting CESR[VLD] enables the module. +If the system requires that all the loaded region descriptors be enabled simultaneously, +first ensure that the entire MPU is disabled (CESR[VLD]=0). +Note +A region descriptor must be set to allow access to the MPU +registers if further changes are needed. +19.6 +Application information +In an operational system, interfacing with the MPU is generally classified into the +following activities: +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +421 +General Business Information + +![Image 1 from page 421](pdf-image://page_421_img_1) + +## Page 422 + +• Creating a new memory region—Load the appropriate region descriptor into an +available RGDn, using four sequential 32-bit writes. The hardware assists in the +maintenance of the valid bit, so if this approach is followed, there are no coherency +issues with the multi-cycle descriptor writes. (Clearing RGDn\_Word3[VLD] deletes/ +removes an existing memory region.) +• Altering only access privileges—To not affect the valid bit, write to the alternate +version of the access control word (RGDAACn), so there are no coherency issues +involved with the update. When the write completes, the memory region's access +rights switch instantaneously to the new value. +• Changing a region's start and end addresses—Write a minimum of three words to the +region descriptor (RGDn\_Word{0,1,3}). Word 0 and 1 redefine the start and end +addresses, respectively. Word 3 re-enables the region descriptor valid bit. In most +situations, all four words of the region descriptor are rewritten. +• Accessing the MPU—Allocate a region descriptor to restrict MPU access to +supervisor mode from a specific master. +• Detecting an access error—The current bus cycle is terminated with an error +response and EARn and EDRn capture information on the faulting reference. The +error-terminated bus cycle typically initiates an error response in the originating bus +master. For example, a processor core may respond with a bus error exception, while +a data movement bus master may respond with an error interrupt. The processor can +retrieve the captured error address and detail information simply by reading +E{A,D}Rn. CESR[SPERR] signals which error registers contain captured fault data. +• Overlapping region descriptors—Applying overlapping regions often reduces the +number of descriptors required for a given set of access controls. In the overlapping +memory space, the protection rights of the corresponding region descriptors are +logically summed together (the boolean OR operator). +The following dual-core system example contains four bus masters: +• The two processors: CP0, CP1 +• Two DMA engines: DMA1, a traditional data movement engine transferring data +between RAM and peripherals and DMA2, a second engine transferring data to/ +from the RAM only +Consider the following region descriptor assignments: +Application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +422 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 422](pdf-image://page_422_img_1) + +## Page 423 + +Table 19-81. Overlapping region descriptor example +Region description +RGDn +CP0 +CP1 +DMA1 +DMA2 +CP0 code +0 +rwx +r-- +— +— +Flash +CP1 code +1 +r-- +rwx +— +— +CP0 data & stack +2 +rw- +— +— +— +RAM +CP0 → CP1 shared data +2 +3 +r-- +r-- +— +— +CP1 → CP0 shared data +4 +CP1 data & stack +4 +— +rw- +— +— +Shared DMA data +5 +rw- +rw- +rw +rw +MPU +6 +rw- +rw- +— +— +Peripheral +space +Peripherals +7 +rw- +rw- +rw +— +In this example, there are eight descriptors used to span nine regions in the three main +spaces of the system memory map: flash, RAM, and peripheral space. Each region +indicates the specific permissions for each of the four bus masters and this definition +provides an appropriate set of shared, private and executable memory spaces. +Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4. +The space defined by RGD2 with no overlap is a private data and stack area that provides +read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines +a shared data space for passing data from CP0 to CP1 and the access controls are defined +by the logical OR of the two region descriptors. Thus, CP0 has (rw- | r--) = (rw-) +permissions, while CP1 has (--- | r--) = (r--) permission in this space. Both DMA engines +are excluded from this shared processor data region. The overlapping spaces between +RGD3 and RGD4 defines another shared data space, this one for passing data from CP1 +to CP0. For this overlapping space, CP0 has (r-- | ---) = (r--) permission, while CP1 has +(rw- | r--) = (rw-) permission. The non-overlapped space of RGD4 defines a private data +and stack area for CP1 only. +The space defined by RGD5 is a shared data region, accessible by all four bus masters. +Finally, the slave peripheral space mapped onto the IPS bus is partitioned into two +regions: +• One containing the MPU's programming model accessible only to the two processor +cores +• The remaining peripheral region accessible to both processors and the traditional +DMA1 master +This example shows one possible application of the capabilities of the MPU in a typical +system. +Chapter 19 Memory Protection Unit (MPU) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +423 +General Business Information + +![Image 1 from page 423](pdf-image://page_423_img_1) + +## Page 424 + +Application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +424 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 424](pdf-image://page_424_img_1) + +## Page 425 + +Chapter 20 +Peripheral Bridge (AIPS-Lite) +20.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The peripheral bridge converts the crossbar switch interface to an interface that can +access a majority of slave peripherals on the device. +The peripheral bridge supports up to 128 peripherals, each with a 4K-byte address space. +(Not all peripheral slots might be used. See the chip configuration chapter and memory +map chapter for details on slot assignment.) The bridge includes separate clock enable +inputs for each of the slots to accommodate slower peripherals. +20.1.1 +Features +Key features of the peripheral bridge are: +• Supports up to 128 peripherals +• Supports peripheral slots with 8-, 16-, and 32-bit datapath width +• Dedicated clock enables for independently configurable peripherals allow each on- or +off-platform peripheral to operate at any integer-divisible speed less than or equal to +the system clock frequency. +• Programming model provides memory protection functionality +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +425 +General Business Information + +![Image 1 from page 425](pdf-image://page_425_img_1) + +## Page 426 + +20.1.2 +General operation +The slave devices connected to the peripheral bridge are modules which contain a +programming model of control and status registers. The system masters read and write +these registers through the peripheral bridge. The peripheral bridge performs a bus +protocol conversion of the master transactions and generates the following as inputs to +the peripherals: +• Module enables +• Module addresses +• Transfer attributes +• Byte enables +• Write data +The peripheral bridge selects and captures read data from the peripheral interface and +returns it to the crossbar switch. +The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is +allocated one or more 4-KB block(s) of the memory map. +20.2 +Memory map/register definition +The 32-bit peripheral bridge registers can be accessed only in supervisor mode by trusted +bus masters. Additionally, these registers must be read from or written to only by a 32-bit +aligned access. The peripheral bridge registers are mapped into the PACRA[PACR0] +address space. +NOTE +The number of fields and registers available depends on the +device-specific implementation of the peripheral bridge +module. See the chip configuration chapter for more +information. +AIPS memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_0000 +Master Privilege Register A (AIPS0\_MPRA) +32 +R/W +Undefined +20.2.1/428 +4000\_0020 +Peripheral Access Control Register (AIPS0\_PACRA) +32 +R/W +4444\_4444 +\_4444\_4444h +20.2.2/431 +4000\_0024 +Peripheral Access Control Register (AIPS0\_PACRB) +32 +R/W +4444\_4444 +\_4444\_4444h +20.2.2/431 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +426 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 426](pdf-image://page_426_img_1) + +## Page 427 + +AIPS memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_0028 +Peripheral Access Control Register (AIPS0\_PACRC) +32 +R/W +4444\_4444 +\_4444\_4444h +20.2.2/431 +4000\_002C +Peripheral Access Control Register (AIPS0\_PACRD) +32 +R/W +4444\_4444 +\_4444\_4444h +20.2.2/431 +4000\_0040 +Peripheral Access Control Register (AIPS0\_PACRE) +32 +R/W +Undefined +20.2.3/436 +4000\_0044 +Peripheral Access Control Register (AIPS0\_PACRF) +32 +R/W +Undefined +20.2.3/436 +4000\_0048 +Peripheral Access Control Register (AIPS0\_PACRG) +32 +R/W +Undefined +20.2.3/436 +4000\_004C +Peripheral Access Control Register (AIPS0\_PACRH) +32 +R/W +Undefined +20.2.3/436 +4000\_0050 +Peripheral Access Control Register (AIPS0\_PACRI) +32 +R/W +Undefined +20.2.3/436 +4000\_0054 +Peripheral Access Control Register (AIPS0\_PACRJ) +32 +R/W +Undefined +20.2.3/436 +4000\_0058 +Peripheral Access Control Register (AIPS0\_PACRK) +32 +R/W +Undefined +20.2.3/436 +4000\_005C +Peripheral Access Control Register (AIPS0\_PACRL) +32 +R/W +Undefined +20.2.3/436 +4000\_0060 +Peripheral Access Control Register (AIPS0\_PACRM) +32 +R/W +Undefined +20.2.3/436 +4000\_0064 +Peripheral Access Control Register (AIPS0\_PACRN) +32 +R/W +Undefined +20.2.3/436 +4000\_0068 +Peripheral Access Control Register (AIPS0\_PACRO) +32 +R/W +Undefined +20.2.3/436 +4000\_006C +Peripheral Access Control Register (AIPS0\_PACRP) +32 +R/W +Undefined +20.2.3/436 +4008\_0000 +Master Privilege Register A (AIPS1\_MPRA) +32 +R/W +Undefined +20.2.1/428 +4008\_0020 +Peripheral Access Control Register (AIPS1\_PACRA) +32 +R/W +4444\_4444 +\_4444\_4444h +20.2.2/431 +4008\_0024 +Peripheral Access Control Register (AIPS1\_PACRB) +32 +R/W +4444\_4444 +\_4444\_4444h +20.2.2/431 +4008\_0028 +Peripheral Access Control Register (AIPS1\_PACRC) +32 +R/W +4444\_4444 +\_4444\_4444h +20.2.2/431 +4008\_002C +Peripheral Access Control Register (AIPS1\_PACRD) +32 +R/W +4444\_4444 +\_4444\_4444h +20.2.2/431 +4008\_0040 +Peripheral Access Control Register (AIPS1\_PACRE) +32 +R/W +Undefined +20.2.3/436 +4008\_0044 +Peripheral Access Control Register (AIPS1\_PACRF) +32 +R/W +Undefined +20.2.3/436 +4008\_0048 +Peripheral Access Control Register (AIPS1\_PACRG) +32 +R/W +Undefined +20.2.3/436 +4008\_004C +Peripheral Access Control Register (AIPS1\_PACRH) +32 +R/W +Undefined +20.2.3/436 +4008\_0050 +Peripheral Access Control Register (AIPS1\_PACRI) +32 +R/W +Undefined +20.2.3/436 +4008\_0054 +Peripheral Access Control Register (AIPS1\_PACRJ) +32 +R/W +Undefined +20.2.3/436 +4008\_0058 +Peripheral Access Control Register (AIPS1\_PACRK) +32 +R/W +Undefined +20.2.3/436 +4008\_005C +Peripheral Access Control Register (AIPS1\_PACRL) +32 +R/W +Undefined +20.2.3/436 +4008\_0060 +Peripheral Access Control Register (AIPS1\_PACRM) +32 +R/W +Undefined +20.2.3/436 +4008\_0064 +Peripheral Access Control Register (AIPS1\_PACRN) +32 +R/W +Undefined +20.2.3/436 +4008\_0068 +Peripheral Access Control Register (AIPS1\_PACRO) +32 +R/W +Undefined +20.2.3/436 +4008\_006C +Peripheral Access Control Register (AIPS1\_PACRP) +32 +R/W +Undefined +20.2.3/436 +Chapter 20 Peripheral Bridge (AIPS-Lite) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +427 +General Business Information + +![Image 1 from page 427](pdf-image://page_427_img_1) + +## Page 428 + +20.2.1 +Master Privilege Register A (AIPSx\_MPRA) +The MPRA specifies identical 4-bit fields defining the access-privilege level associated +with a bus master in the device to various peripherals. The register provides one field per +bus master. +NOTE +At reset, the default value loaded into the MPRA fields is +device-specific. See the chip configuration details for the value +of a particular device. +A register field that maps to an unimplemented master or peripheral behaves as read- +only-zero. +Each master is assigned depending on its connection to the crossbar switch master ports. +See device-specific chip configuration details for information about the master +assignments to these registers. +Address: Base address + 0h offset +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +MTR0 +MTW0 +MPL0 +0 +MTR1 +MTW1 +MPL1 +0 +MTR2 +MTW2 +MPL2 +0 +MTR3 +MTW3 +MPL3 +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +MTR4 +MTW4 +MPL4 +0 +MTR5 +MTW5 +MPL5 +0 +0 +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +AIPSx\_MPRA field descriptions +Field +Description +31 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +30 +MTR0 +Master Trusted For Read +Determines whether the master is trusted for read accesses. +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +428 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 428](pdf-image://page_428_img_1) + +## Page 429 + +AIPSx\_MPRA field descriptions (continued) +Field +Description +0 +This master is not trusted for read accesses. +1 +This master is trusted for read accesses. +29 +MTW0 +Master Trusted For Writes +Determines whether the master is trusted for write accesses. +0 +This master is not trusted for write accesses. +1 +This master is trusted for write accesses. +28 +MPL0 +Master Privilege Level +Specifies how the privilege level of the master is determined. +0 +Accesses from this master are forced to user-mode. +1 +Accesses from this master are not forced to user-mode. +27 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +26 +MTR1 +Master trusted for read +Determines whether the master is trusted for read accesses. +0 +This master is not trusted for read accesses. +1 +This master is trusted for read accesses. +25 +MTW1 +Master trusted for writes +Determines whether the master is trusted for write accesses. +0 +This master is not trusted for write accesses. +1 +This master is trusted for write accesses. +24 +MPL1 +Master privilege level +Specifies how the privilege level of the master is determined. +0 +Accesses from this master are forced to user-mode. +1 +Accesses from this master are not forced to user-mode. +23 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +22 +MTR2 +Master Trusted For Read +Determines whether the master is trusted for read accesses. +0 +This master is not trusted for read accesses. +1 +This master is trusted for read accesses. +21 +MTW2 +Master Trusted For Writes +Determines whether the master is trusted for write accesses. +0 +This master is not trusted for write accesses. +1 +This master is trusted for write accesses. +20 +MPL2 +Master Privilege Level +Specifies how the privilege level of the master is determined. +Table continues on the next page... +Chapter 20 Peripheral Bridge (AIPS-Lite) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +429 +General Business Information + +![Image 1 from page 429](pdf-image://page_429_img_1) + +## Page 430 + +AIPSx\_MPRA field descriptions (continued) +Field +Description +0 +Accesses from this master are forced to user-mode. +1 +Accesses from this master are not forced to user-mode. +19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18 +MTR3 +Master Trusted For Read +Determines whether the master is trusted for read accesses. +0 +This master is not trusted for read accesses. +1 +This master is trusted for read accesses. +17 +MTW3 +Master Trusted For Writes +Determines whether the master is trusted for write accesses. +0 +This master is not trusted for write accesses. +1 +This master is trusted for write accesses. +16 +MPL3 +Master Privilege Level +Specifies how the privilege level of the master is determined. +0 +Accesses from this master are forced to user-mode. +1 +Accesses from this master are not forced to user-mode. +15 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +14 +MTR4 +Master Trusted For Read +Determines whether the master is trusted for read accesses. +0 +This master is not trusted for read accesses. +1 +This master is trusted for read accesses. +13 +MTW4 +Master Trusted For Writes +Determines whether the master is trusted for write accesses. +0 +This master is not trusted for write accesses. +1 +This master is trusted for write accesses. +12 +MPL4 +Master Privilege Level +Specifies how the privilege level of the master is determined. +0 +Accesses from this master are forced to user-mode. +1 +Accesses from this master are not forced to user-mode. +11 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +10 +MTR5 +Master Trusted For Read +Determines whether the master is trusted for read accesses. +0 +This master is not trusted for read accesses. +1 +This master is trusted for read accesses. +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +430 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 430](pdf-image://page_430_img_1) + +## Page 431 + +AIPSx\_MPRA field descriptions (continued) +Field +Description +9 +MTW5 +Master Trusted For Writes +Determines whether the master is trusted for write accesses. +0 +This master is not trusted for write accesses. +1 +This master is trusted for write accesses. +8 +MPL5 +Master Privilege Level +Specifies how the privilege level of the master is determined. +0 +Accesses from this master are forced to user-mode. +1 +Accesses from this master are not forced to user-mode. +7–4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +20.2.2 +Peripheral Access Control Register (AIPSx\_PACRn) +Each of the peripherals has a 4-bit PACR[0: 127 ] field which defines the access levels +supported by the given module. Eight PACR fields are grouped together to form a 32-bit +PACR[A: P ] register: +• PACRA- P define the access levels for the 128 peripherals +The peripheral assignments to each PACR are defined by the memory map slot that the +peripherals are assigned. See the device's memory map details for the assignments for a +particular device. +NOTE +The reset value of PACR[A:D] is 0x4444\_4444. +The following table shows the top-level structure of PACRs. +Offset +Register +[31:28] +[27:24] +[23:20] +[19:16] +[15:12] +[11:8] +[7:4] +[3:0] +0x20 +PACRA +PACR0 +PACR1 +PACR2 +PACR3 +PACR4 +PACR5 +PACR6 +PACR7 +0x24 +PACRB +PACR8 +PACR9 +PACR10 +PACR11 +PACR12 +PACR13 +PACR14 +PACR15 +0x28 +PACRC +PACR16 +PACR17 +PACR18 +PACR19 +PACR20 +PACR21 +PACR22 +PACR23 +0x2C +PACRD +PACR24 +PACR25 +PACR26 +PACR27 +PACR28 +PACR29 +PACR30 +PACR31 +0x30 +Reserved +0x34 +Reserved +0x38 +Reserved +0x3C +Reserved +Table continues on the next page... +Chapter 20 Peripheral Bridge (AIPS-Lite) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +431 +General Business Information + +![Image 1 from page 431](pdf-image://page_431_img_1) + +## Page 432 + +Offset +Register +[31:28] +[27:24] +[23:20] +[19:16] +[15:12] +[11:8] +[7:4] +[3:0] +0x40 +PACRE +PACR32 +PACR33 +PACR34 +PACR35 +PACR36 +PACR37 +PACR38 +PACR39 +0x44 +PACRF +PACR40 +PACR41 +PACR42 +PACR43 +PACR44 +PACR45 +PACR46 +PACR47 +0x48 +PACRG +PACR48 +PACR49 +PACR50 +PACR51 +PACR52 +PACR53 +PACR54 +PACR55 +0x4C +PACRH +PACR56 +PACR57 +PACR58 +PACR59 +PACR60 +PACR61 +PACR62 +PACR63 +0x50 +PACRI +PACR64 +PACR65 +PACR66 +PACR67 +PACR68 +PACR69 +PACR70 +PACR71 +0x54 +PACRJ +PACR72 +PACR73 +PACR74 +PACR75 +PACR76 +PACR77 +PACR78 +PACR79 +0x58 +PACRK +PACR80 +PACR81 +PACR82 +PACR83 +PACR84 +PACR85 +PACR86 +PACR87 +0x5C +PACRL +PACR88 +PACR89 +PACR90 +PACR91 +PACR92 +PACR93 +PACR94 +PACR95 +0x60 +PACRM +PACR96 +PACR97 +PACR98 +PACR99 +PACR100 +PACR101 +PACR102 +PACR103 +0x64 +PACRN +PACR104 +PACR105 +PACR106 +PACR107 +PACR108 +PACR109 +PACR110 +PACR111 +0x68 +PACRO +PACR112 +PACR113 +PACR114 +PACR115 +PACR116 +PACR117 +PACR118 +PACR119 +0x6C +PACRP +PACR120 +PACR121 +PACR122 +PACR123 +PACR124 +PACR125 +PACR126 +PACR127 +Address: Base address + 20h offset + (4d × i), where i=0d to 3d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +SP0 +WP0 +TP0 +0 +SP1 +WP1 +TP1 +0 +SP2 +WP2 +TP2 +0 +SP3 +WP3 +TP3 +W +Reset +0 +1 +0 +0 +0 +1 +0 +0 +0 +1 +0 +0 +0 +1 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +SP4 +WP4 +TP4 +0 +SP5 +WP5 +TP5 +0 +SP6 +WP6 +TP6 +0 +SP7 +WP7 +TP7 +W +Reset +0 +1 +0 +0 +0 +1 +0 +0 +0 +1 +0 +0 +0 +1 +0 +0 +AIPSx\_PACRn field descriptions +Field +Description +31 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +30 +SP0 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +29 +WP0 +Write protect +Determines whether the peripheral allows write accesss. When this bit is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +28 +TP0 +Trusted Protect +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +432 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 432](pdf-image://page_432_img_1) + +## Page 433 + +AIPSx\_PACRn field descriptions (continued) +Field +Description +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +27 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +26 +SP1 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +25 +WP1 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +24 +TP1 +Trusted protect +Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an +access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +23 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +22 +SP2 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +21 +WP2 +Write protect +Determines whether the peripheral allows write accesss. When this bit is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +20 +TP2 +Trusted Protect +Table continues on the next page... +Chapter 20 Peripheral Bridge (AIPS-Lite) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +433 +General Business Information + +![Image 1 from page 433](pdf-image://page_433_img_1) + +## Page 434 + +AIPSx\_PACRn field descriptions (continued) +Field +Description +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18 +SP3 +Supervisor protect +Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the +master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control bit for +the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +17 +WP3 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +16 +TP3 +Trusted protect +Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an +access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +15 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +14 +SP4 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +13 +WP4 +Write protect +Determines whether the peripheral allows write accesss. When this bit is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +12 +TP4 +Trusted protect +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +434 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 434](pdf-image://page_434_img_1) + +## Page 435 + +AIPSx\_PACRn field descriptions (continued) +Field +Description +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +11 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +10 +SP5 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +9 +WP5 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +8 +TP5 +Trusted Protect +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +6 +SP6 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +5 +WP6 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +4 +TP6 +Trusted Protect +Table continues on the next page... +Chapter 20 Peripheral Bridge (AIPS-Lite) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +435 +General Business Information + +![Image 1 from page 435](pdf-image://page_435_img_1) + +## Page 436 + +AIPSx\_PACRn field descriptions (continued) +Field +Description +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2 +SP7 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +1 +WP7 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +0 +TP7 +Trusted Protect +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +20.2.3 +Peripheral Access Control Register (AIPSx\_PACRn) +Each of the peripherals has a 4-bit PACR[0: 127 ] field which defines the access levels +supported by this module. Eight PACR fields are grouped together to form a 32-bit +PACR[A: P ]: +• PACRA- P define the access levels for the 128 peripherals +The peripheral assignments to each PACR are defined by the memory map slot that the +peripherals are assigned. See the device's memory map details for the assignments for a +particular device. +NOTE +The reset value of the PACRE- P depends on the device's +configuration. +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +436 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 436](pdf-image://page_436_img_1) + +## Page 437 + +Address: Base address + 40h offset + (4d × i), where i=0d to 11d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +SP0 +WP0 +TP0 +0 +SP1 +WP1 +TP1 +0 +SP2 +WP2 +TP2 +0 +SP3 +WP3 +TP3 +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +SP4 +WP4 +TP4 +0 +SP5 +WP5 +TP5 +0 +SP6 +WP6 +TP6 +0 +SP7 +WP7 +TP7 +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +AIPSx\_PACRn field descriptions +Field +Description +31 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +30 +SP0 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +29 +WP0 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +28 +TP0 +Trusted protect +Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an +access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +27 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +26 +SP1 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for access. When this field is set, the +master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control field +for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +Table continues on the next page... +Chapter 20 Peripheral Bridge (AIPS-Lite) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +437 +General Business Information + +![Image 1 from page 437](pdf-image://page_437_img_1) + +## Page 438 + +AIPSx\_PACRn field descriptions (continued) +Field +Description +25 +WP1 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +24 +TP1 +Trusted Protect +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +23 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +22 +SP2 +Supervisor protect +Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the +master privilege level must indicate the supervisor access attributeMPR x [MPL n ], and the MPR x [MPL +n ] control bit for the master must be set. If not, access terminates with an error response and no +peripheral access initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +21 +WP2 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +20 +TP2 +Trusted protect +Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an +access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18 +SP3 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +438 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 438](pdf-image://page_438_img_1) + +## Page 439 + +AIPSx\_PACRn field descriptions (continued) +Field +Description +17 +WP3 +Write protect +Determines whether the peripheral allows write accesss. When this bit is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +16 +TP3 +Trusted Protect +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +15 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +14 +SP4 +Supervisor protect +Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the +master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control bit for +the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +13 +WP4 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +12 +TP4 +Trusted protect +Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an +access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +11 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +10 +SP5 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +Table continues on the next page... +Chapter 20 Peripheral Bridge (AIPS-Lite) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +439 +General Business Information + +![Image 1 from page 439](pdf-image://page_439_img_1) + +## Page 440 + +AIPSx\_PACRn field descriptions (continued) +Field +Description +9 +WP5 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +8 +TP5 +Trusted Protect +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +6 +SP6 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +5 +WP6 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +4 +TP6 +Trusted Protect +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2 +SP7 +Supervisor Protect +Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set, +the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control +field for the master must be set. If not, access terminates with an error response and no peripheral access +initiates . +0 +This peripheral does not require supervisor privilege level for accesses. +1 +This peripheral requires supervisor privilege level for accesses. +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +440 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 440](pdf-image://page_440_img_1) + +## Page 441 + +AIPSx\_PACRn field descriptions (continued) +Field +Description +1 +WP7 +Write Protect +Determines whether the peripheral allows write accessses. When this field is set and a write access is +attempted, access terminates with an error response and no peripheral access initiates . +0 +This peripheral allows write accesses. +1 +This peripheral is write protected. +0 +TP7 +Trusted Protect +Determines whether the peripheral allows accesses from an untrusted master. When this field is set and +an access is attempted by an untrusted master, the access terminates with an error response and no +peripheral access initiates . +0 +Accesses from an untrusted master are allowed. +1 +Accesses from an untrusted master are not allowed. +20.3 +Functional description +The peripheral bridge functions as a bus protocol translator between the crossbar switch +and the slave peripheral bus. +The peripheral bridge manages all transactions destined for the attached slave devices and +generates select signals for modules on the peripheral bus by decoding accesses within +the attached address space. +By default, reads and writes on the crossbar side of the peripheral bridge take two data- +phase cycles. On the IPS side, accesses complete in one cycle. If wait states are inserted +by the slave peripheral, access time will be extended accordingly. +20.3.1 +Access support +All accesses to the peripheral slots must be sized less than or equal to the designated +peripheral slot size. If an access is attempted which is larger than the targeted port, an +error response is generated. +Chapter 20 Peripheral Bridge (AIPS-Lite) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +441 +General Business Information + +![Image 1 from page 441](pdf-image://page_441_img_1) + +## Page 442 + +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +442 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 442](pdf-image://page_442_img_1) + +## Page 443 + +Chapter 21 +Direct Memory Access Multiplexer (DMAMUX) +21.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +21.1.1 +Overview +The direct memory access multiplexer (DMAMUX) routes DMA sources, called slots, to +any of the 16 DMA channels. This process is illustrated in the following figure. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +443 +General Business Information + +![Image 1 from page 443](pdf-image://page_443_img_1) + +## Page 444 + +DMA Channel \#0 +Source \#1 +Source \#2 +Source \#3 +Always \#1 +DMA Channel \#n +Always \#y +Source \#x +Trigger \#1 +Trigger \#z +DMA Channel \#1 +DMAMUX +Figure 21-1. DMAMUX block diagram +21.1.2 +Features +The DMA channel MUX provides these features: +• 52 peripheral slots and 10 always-on slots can be routed to 16 channels. +• 16 independently selectable DMA channel routers. +• The first 4 channels additionally provide a trigger functionality. +• Each channel router can be assigned to one of the 52 possible peripheral DMA slots +or to one of the 10 always-on slots. +21.1.3 +Modes of operation +The following operating modes are available: +• Disabled mode +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +444 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 444](pdf-image://page_444_img_1) + +## Page 445 + +In this mode, the DMA channel is disabled. Because disabling and enabling of DMA +channels is done primarily via the DMA configuration registers, this mode is used +mainly as the reset state for a DMA channel in the DMA channel MUX. It may also +be used to temporarily suspend a DMA channel while reconfiguration of the system +takes place, for example, changing the period of a DMA trigger. +• Normal mode +In this mode, a DMA source is routed directly to the specified DMA channel. The +operation of the DMA MUX in this mode is completely transparent to the system. +• Periodic Trigger mode +In this mode, a DMA source may only request a DMA transfer, such as when a +transmit buffer becomes empty or a receive buffer becomes full, periodically. +Configuration of the period is done in the registers of the periodic interrupt timer +(PIT). This mode is available only for channels 0-3. +21.2 +External signal description +The DMA MUX has no external pins. +21.3 +Memory map/register definition +This section provides a detailed description of all memory-mapped registers in the DMA +MUX. +DMAMUX memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4002\_1000 +Channel Configuration register (DMAMUX\_CHCFG0) +8 +R/W +000h +21.3.1/446 +4002\_1001 +Channel Configuration register (DMAMUX\_CHCFG1) +8 +R/W +000h +21.3.1/446 +4002\_1002 +Channel Configuration register (DMAMUX\_CHCFG2) +8 +R/W +000h +21.3.1/446 +4002\_1003 +Channel Configuration register (DMAMUX\_CHCFG3) +8 +R/W +000h +21.3.1/446 +4002\_1004 +Channel Configuration register (DMAMUX\_CHCFG4) +8 +R/W +000h +21.3.1/446 +4002\_1005 +Channel Configuration register (DMAMUX\_CHCFG5) +8 +R/W +000h +21.3.1/446 +4002\_1006 +Channel Configuration register (DMAMUX\_CHCFG6) +8 +R/W +000h +21.3.1/446 +4002\_1007 +Channel Configuration register (DMAMUX\_CHCFG7) +8 +R/W +000h +21.3.1/446 +4002\_1008 +Channel Configuration register (DMAMUX\_CHCFG8) +8 +R/W +000h +21.3.1/446 +Table continues on the next page... +Chapter 21 Direct Memory Access Multiplexer (DMAMUX) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +445 +General Business Information + +![Image 1 from page 445](pdf-image://page_445_img_1) + +## Page 446 + +DMAMUX memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4002\_1009 +Channel Configuration register (DMAMUX\_CHCFG9) +8 +R/W +000h +21.3.1/446 +4002\_100A +Channel Configuration register (DMAMUX\_CHCFG10) +8 +R/W +000h +21.3.1/446 +4002\_100B +Channel Configuration register (DMAMUX\_CHCFG11) +8 +R/W +000h +21.3.1/446 +4002\_100C +Channel Configuration register (DMAMUX\_CHCFG12) +8 +R/W +000h +21.3.1/446 +4002\_100D +Channel Configuration register (DMAMUX\_CHCFG13) +8 +R/W +000h +21.3.1/446 +4002\_100E +Channel Configuration register (DMAMUX\_CHCFG14) +8 +R/W +000h +21.3.1/446 +4002\_100F +Channel Configuration register (DMAMUX\_CHCFG15) +8 +R/W +000h +21.3.1/446 +21.3.1 +Channel Configuration register (DMAMUX\_CHCFGn) +Each of the DMA channels can be independently enabled/disabled and associated with +one of the DMA slots (peripheral slots or always-on slots) in the system. +NOTE +Setting multiple CHCFG registers with the same Source value +will result in unpredictable behavior. +NOTE +Before changing the trigger or source settings a DMA channel +must be disabled via the CHCFGn[ENBL] bit. +Address: 4002\_1000h base + 0h offset + (1d × i), where i=0d to 15d +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +ENBL +TRIG +SOURCE +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +DMAMUX\_CHCFGn field descriptions +Field +Description +7 +ENBL +DMA Channel Enable +Enables the DMA channel. +0 +DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA +has separate channel enables/disables, which should be used to disable or re-configure a DMA +channel. +1 +DMA channel is enabled +6 +TRIG +DMA Channel Trigger Enable +Enables the periodic trigger capability for the triggered DMA channel. +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +446 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 446](pdf-image://page_446_img_1) + +## Page 447 + +DMAMUX\_CHCFGn field descriptions (continued) +Field +Description +0 +Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply +route the specified source to the DMA channel. (Normal mode) +1 +Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in Periodic +Trigger mode. +5–0 +SOURCE +DMA Channel Source (Slot) +Specifies which DMA source, if any, is routed to a particular DMA channel. See your device's chip +configuration details for further details about the peripherals and their slot numbers. +21.4 +Functional description +The primary purpose of the DMA MUX is to provide flexibility in the system's use of the +available DMA channels. As such, configuration of the DMA MUX is intended to be a +static procedure done during execution of the system boot code. However, if the +procedure outlined in Enabling and configuring sources is followed, the configuration of +the DMA MUX may be changed during the normal operation of the system. +Functionally, the DMA MUX channels may be divided into two classes: +• Channels which implement the normal routing functionality plus periodic triggering +capability +• Channels which implement only the normal routing functionality +21.4.1 +DMA channels with periodic triggering capability +Besides the normal routing functionality, the first 4 channels of the DMA MUX provide a +special periodic triggering capability that can be used to provide an automatic mechanism +to transmit bytes, frames, or packets at fixed intervals without the need for processor +intervention. The trigger is generated by the periodic interrupt timer (PIT); as such, the +configuration of the periodic triggering interval is done via configuration registers in the +PIT. See the section on periodic interrupt timer for more information on this topic. +Note +Because of the dynamic nature of the system (i.e. DMA channel +priorities, bus arbitration, interrupt service routine lengths, etc.), +the number of clock cycles between a trigger and the actual +DMA transfer cannot be guaranteed. +Chapter 21 Direct Memory Access Multiplexer (DMAMUX) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +447 +General Business Information + +![Image 1 from page 447](pdf-image://page_447_img_1) + +## Page 448 + +DMA Channel \#0 +Trigger \#2 +Source \#1 +Source \#2 +Source \#3 +Always \#1 +DMA Channel \#3 +Always \#y +Trigger \#4 +Source \#x +Trigger \#1 +DMA Channel \#1 +Figure 21-19. DMA MUX triggered channels +The DMA channel triggering capability allows the system to "schedule" regular DMA +transfers, usually on the transmit side of certain peripherals, without the intervention of +the processor. This trigger works by gating the request from the peripheral to the DMA +until a trigger event has been seen. This is illustrated in the following figure. +DMA Request +Peripheral Request +Trigger +Figure 21-20. DMA MUX channel triggering: normal operation +After the DMA request has been serviced, the peripheral will negate its request, +effectively resetting the gating mechanism until the peripheral re-asserts its request AND +the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not +requesting a transfer, then that trigger will be ignored. This situation is illustrated in the +following figure. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +448 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 448](pdf-image://page_448_img_1) + +## Page 449 + +DMA Request +Peripheral Request +Trigger +Figure 21-21. DMA MUX channel triggering: ignored trigger +This triggering capability may be used with any peripheral that supports DMA transfers, +and is most useful for two types of situations: +• Periodically polling external devices on a particular bus. As an example, the transmit +side of an SPI is assigned to a DMA channel with a trigger, as described above. After +it has been setup, the SPI will request DMA transfers, presumably from memory, as +long as its transmit buffer is empty. By using a trigger on this channel, the SPI +transfers can be automatically performed every 5μs (as an example). On the receive +side of the SPI, the SPI and DMA can be configured to transfer receive data into +memory, effectively implementing a method to periodically read data from external +devices and transfer the results into memory without processor intervention. +• Using the GPIO ports to drive or sample waveforms. By configuring the DMA to +transfer data to one or more GPIO ports, it is possible to create complex waveforms +using tabular data stored in on-chip memory. Conversely, using the DMA to +periodically transfer data from one or more GPIO ports, it is possible to sample +complex waveforms and store the results in tabular form in on-chip memory. +A more detailed description of the capability of each trigger, including resolution, range +of values, and so on, may be found in the periodic interrupt timer section. +21.4.2 +DMA channels with no triggering capability +The other channels of the DMA MUX provide the normal routing functionality as +described in Modes of operation. +21.4.3 +"Always enabled" DMA sources +In addition to the peripherals that can be used as DMA sources, there are 10 additional +DMA sources that are "always enabled". Unlike the peripheral DMA sources, where the +peripheral controls the flow of data during DMA transfers, the "always enabled" sources +provide no such "throttling" of the data transfers. These sources are most useful in the +following cases: +Chapter 21 Direct Memory Access Multiplexer (DMAMUX) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +449 +General Business Information + +![Image 1 from page 449](pdf-image://page_449_img_1) + +## Page 450 + +• Performing DMA transfers to/from GPIO—Moving data from/to one or more GPIO +pins, either unthrottled (that is as fast as possible), or periodically (using the DMA +triggering capability). +• Performing DMA transfers from memory to memory—Moving data from memory to +memory, typically as fast as possible, sometimes with software activation. +• Performing DMA transfers from memory to the external bus, or vice-versa—Similar +to memory to memory transfers, this is typically done as quickly as possible. +• Any DMA transfer that requires software activation—Any DMA transfer that should +be explicitly started by software. +In cases where software should initiate the start of a DMA transfer, an "always enabled" +DMA source can be used to provide maximum flexibility. When activating a DMA +channel via software, subsequent executions of the minor loop require a new "start" event +be sent. This can either be a new software activation, or a transfer request from the DMA +channel MUX. The options for doing this are: +• Transfer all data in a single minor loop. By configuring the DMA to transfer all of +the data in a single minor loop (that is major loop counter = 1), no reactivation of the +channel is necessary. The disadvantage to this option is the reduced granularity in +determining the load that the DMA transfer will incur on the system. For this option, +the DMA channel must be disabled in the DMA channel MUX. +• Use explicit software reactivation. In this option, the DMA is configured to transfer +the data using both minor and major loops, but the processor is required to reactivate +the channel by writing to the DMA registers after every minor loop. For this option, +the DMA channel must be disabled in the DMA channel MUX. +• Use an "always enabled" DMA source. In this option, the DMA is configured to +transfer the data using both minor and major loops, and the DMA channel MUX does +the channel re-activation. For this option, the DMA channel should be enabled and +pointing to an "always enabled" source. Note that the reactivation of the channel can +be continuous (DMA triggering is disabled) or can use the DMA triggering +capability. In this manner, it is possible to execute periodic transfers of packets of +data from one source to another, without processor intervention. +21.5 +Initialization/application information +This section provides instructions for initializing the DMA channel MUX. +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +450 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 450](pdf-image://page_450_img_1) + +## Page 451 + +21.5.1 +Reset +The reset state of each individual bit is shown in Memory map/register definition. In +summary, after reset, all channels are disabled and must be explicitly enabled before use. +21.5.2 +Enabling and configuring sources +To enable a source with periodic triggering: +1. Determine with which DMA channel the source will be associated. Note that only the +first 4 DMA channels have periodic triggering capability. +2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. +3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel +may be enabled at this point. +4. Configure the corresponding timer. +5. Select the source to be routed to the DMA channel. Write to the corresponding +CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set. +NOTE +The following is an example. See Chip configuration section +for the number of this device's DMA channels that have +triggering capability. +To configure source \#5 transmit for use with DMA channel 2, with periodic triggering +capability: +1. Write 0x00 to CHCFG2 (base address + 0x02). +2. Configure channel 2 in the DMA, including enabling the channel. +3. Configure a timer for the desired trigger interval. +4. Write 0xC5 to CHCFG2 (base address + 0x02). +The following code example illustrates steps 1 and 4 above: +In File registers.h: +#define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ +/* Following example assumes char is 8-bits */ +volatile unsigned char \*CHCONFIG0 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0000); +volatile unsigned char \*CHCONFIG1 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0001); +volatile unsigned char \*CHCONFIG2 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0002); +volatile unsigned char \*CHCONFIG3 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0003); +volatile unsigned char \*CHCONFIG4 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0004); +volatile unsigned char \*CHCONFIG5 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0005); +volatile unsigned char \*CHCONFIG6 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0006); +volatile unsigned char \*CHCONFIG7 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0007); +volatile unsigned char \*CHCONFIG8 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0008); +volatile unsigned char \*CHCONFIG9 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0009); +volatile unsigned char \*CHCONFIG10= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000A); +volatile unsigned char \*CHCONFIG11= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000B); +volatile unsigned char \*CHCONFIG12= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000C); +Chapter 21 Direct Memory Access Multiplexer (DMAMUX) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +451 +General Business Information + +![Image 1 from page 451](pdf-image://page_451_img_1) + +## Page 452 + +volatile unsigned char \*CHCONFIG13= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000D); +volatile unsigned char \*CHCONFIG14= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000E); +volatile unsigned char \*CHCONFIG15= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000F); +In File main.c: +\#include "registers.h" +: +: +\*CHCONFIG2 = 0x00; +\*CHCONFIG2 = 0xC5; +To enable a source without periodic triggering: +1. Determine with which DMA channel the source will be associated. Note that only the +first 4 DMA channels have periodic triggering capability. +2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. +3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel +may be enabled at this point. +4. Select the source to be routed to the DMA channel. Write to the corresponding +CHCFG register, ensuring that the CHCFG[ENBL] is set while the CHCFG[TRIG] +bit is cleared. +NOTE +The following is an example. See Chip configuration section +for the number of this device's DMA channels that have +triggering capability. +To configure source \#5 Transmit for use with DMA channel 2, with no periodic +triggering capability: +1. Write 0x00 to CHCFG2 (base address + 0x02). +2. Configure channel 2 in the DMA, including enabling the channel. +3. Write 0x85 to CHCFG2 (base address + 0x02). +The following code example illustrates steps 1 and 3 above: +In File registers.h: +#define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ +/* Following example assumes char is 8-bits */ +volatile unsigned char \*CHCONFIG0 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0000); +volatile unsigned char \*CHCONFIG1 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0001); +volatile unsigned char \*CHCONFIG2 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0002); +volatile unsigned char \*CHCONFIG3 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0003); +volatile unsigned char \*CHCONFIG4 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0004); +volatile unsigned char \*CHCONFIG5 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0005); +volatile unsigned char \*CHCONFIG6 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0006); +volatile unsigned char \*CHCONFIG7 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0007); +volatile unsigned char \*CHCONFIG8 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0008); +volatile unsigned char \*CHCONFIG9 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0009); +volatile unsigned char \*CHCONFIG10= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000A); +volatile unsigned char \*CHCONFIG11= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000B); +volatile unsigned char \*CHCONFIG12= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000C); +volatile unsigned char \*CHCONFIG13= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000D); +volatile unsigned char \*CHCONFIG14= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000E); +volatile unsigned char \*CHCONFIG15= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000F); +In File main.c: +\#include "registers.h" +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +452 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 452](pdf-image://page_452_img_1) + +## Page 453 + +: +: +\*CHCONFIG2 = 0x00; +\*CHCONFIG2 = 0x85; +Disabling a source +A particular DMA source may be disabled by not writing the corresponding source value +into any of the CHCFG registers. Additionally, some module-specific configuration may +be necessary. See the appropriate section for more details. +To switch the source of a DMA channel: +1. Disable the DMA channel in the DMA and re-configure the channel for the new +source. +2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. +3. Select the source to be routed to the DMA channel. Write to the corresponding +CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] bits are set. +To switch DMA channel 8 from source \#5 transmit to source \#7 transmit: +1. In the DMA configuration registers, disable DMA channel 8 and re-configure it to +handle the transfers to peripheral slot 7. This example assumes channel 8 doesn't +have triggering capability. +2. Write 0x00 to CHCFG8 (base address + 0x08). +3. Write 0x87 to CHCFG8 (base address + 0x08). (In this example, setting the +CHCFG[TRIG] bit would have no effect, due to the assumption that channels 8 does +not support the periodic triggering functionality). +The following code example illustrates steps 2 and 3 above: +In File registers.h: +#define DMAMUX_BASE_ADDR 0xFC084000/* Example only ! */ +/* Following example assumes char is 8-bits */ +volatile unsigned char \*CHCONFIG0 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0000); +volatile unsigned char \*CHCONFIG1 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0001); +volatile unsigned char \*CHCONFIG2 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0002); +volatile unsigned char \*CHCONFIG3 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0003); +volatile unsigned char \*CHCONFIG4 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0004); +volatile unsigned char \*CHCONFIG5 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0005); +volatile unsigned char \*CHCONFIG6 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0006); +volatile unsigned char \*CHCONFIG7 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0007); +volatile unsigned char \*CHCONFIG8 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0008); +volatile unsigned char \*CHCONFIG9 = (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x0009); +volatile unsigned char \*CHCONFIG10= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000A); +volatile unsigned char \*CHCONFIG11= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000B); +volatile unsigned char \*CHCONFIG12= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000C); +volatile unsigned char \*CHCONFIG13= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000D); +volatile unsigned char \*CHCONFIG14= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000E); +volatile unsigned char \*CHCONFIG15= (volatile unsigned char \*) (DMAMUX\_BASE\_ADDR+0x000F); +In File main.c: +\#include "registers.h" +: +: +\*CHCONFIG8 = 0x00; +\*CHCONFIG8 = 0x87; +Chapter 21 Direct Memory Access Multiplexer (DMAMUX) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +453 +General Business Information + +![Image 1 from page 453](pdf-image://page_453_img_1) + +## Page 454 + +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +454 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 454](pdf-image://page_454_img_1) + +## Page 455 + +Chapter 22 +Direct Memory Access Controller (eDMA) +22.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The enhanced direct memory access (eDMA) controller is a second-generation module +capable of performing complex data transfers with minimal intervention from a host +processor. The hardware microarchitecture includes: +• A DMA engine that performs: +• Source- and destination-address calculations +• Data-movement operations +• Local memory containing transfer control descriptors for each of the 16 channels +22.1.1 +Block diagram +This diagram illustrates the eDMA module. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +455 +General Business Information + +![Image 1 from page 455](pdf-image://page_455_img_1) + +## Page 456 + +1 +Transfer Control +Descriptor (TCD) +eDMA Engine +Data Path +eDMA +0 +Program Model/ +64 +Control +n-1 +To/From Crossbar Switch +2 +Channel Arbitration +Address Path +Read Data +Write Data +Address +Read Data +Write Data +Write Address +Internal Peripheral Bus +eDMA Peripheral +Request +eDMA Done +Figure 22-1. eDMA block diagram +22.1.2 +Block parts +The eDMA module is partitioned into two major modules: the eDMA engine and the +transfer-control descriptor local memory. +The eDMA engine is further partitioned into four submodules: +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +456 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 456](pdf-image://page_456_img_1) + +## Page 457 + +Table 22-1. eDMA engine submodules +Submodule +Function +Address path +This block implements registered versions of two channel transfer control descriptors, channel x +and channel y, and manages all master bus-address calculations. All the channels provide the +same functionality. This structure allows data transfers associated with one channel to be +preempted after the completion of a read/write sequence if a higher priority channel activation is +asserted while the first channel is active. After a channel is activated, it runs until the minor loop is +completed, unless preempted by a higher priority channel. This provides a mechanism (enabled +by DCHPRIn[ECP]) where a large data move operation can be preempted to minimize the time +another channel is blocked from execution. +When any channel is selected to execute, the contents of its TCD are read from local memory and +loaded into the address path channel x registers for a normal start and into channel y registers for +a preemption start. After the minor loop completes execution, the address path hardware writes +the new values for the TCDn\_{SADDR, DADDR, CITER} back to local memory. If the major +iteration count is exhausted, additional processing is performed, including the final address pointer +updates, reloading the TCDn\_CITER field, and a possible fetch of the next TCDn from memory as +part of a scatter/gather operation. +Data path +This block implements the bus master read/write datapath. It includes 16 bytes of register storage +and the necessary multiplex logic to support any required data alignment. The internal read data +bus is the primary input, and the internal write data bus is the primary output. +The address and data path modules directly support the 2-stage pipelined internal bus. The +address path module represents the 1st stage of the bus pipeline (address phase), while the data +path module implements the 2nd stage of the pipeline (data phase). +Program model/channel +arbitration +This block implements the first section of the eDMA programming model as well as the channel +arbitration logic. The programming model registers are connected to the internal peripheral bus. +The eDMA peripheral request inputs and interrupt request outputs are also connected to this block +(via control logic). +Control +This block provides all the control functions for the eDMA engine. For data transfers where the +source and destination sizes are equal, the eDMA engine performs a series of source read/ +destination write operations until the number of bytes specified in the minor loop byte count has +moved. For descriptors where the sizes are not equal, multiple accesses of the smaller size data +are required for each reference of the larger size. As an example, if the source size references 16- +bit data and the destination is 32-bit data, two reads are performed, then one 32-bit write. +The transfer-control descriptor local memory is further partitioned into: +Table 22-2. Transfer control descriptor memory +Submodule +Description +Memory controller +This logic implements the required dual-ported controller, managing accesses from the eDMA +engine as well as references from the internal peripheral bus. As noted earlier, in the event of +simultaneous accesses, the eDMA engine is given priority and the peripheral transaction is +stalled. +Memory array +TCD storage is implemented using a single-port, synchronous RAM array. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +457 +General Business Information + +![Image 1 from page 457](pdf-image://page_457_img_1) + +## Page 458 + +22.1.3 +Features +The eDMA is a highly-programmable data-transfer engine optimized to minimize the +required intervention from the host processor. It is intended for use in applications where +the data size to be transferred is statically known and not defined within the data packet +itself. The eDMA module features: +• All data movement via dual-address transfers: read from source, write to destination +• Programmable source and destination addresses and transfer size +• Support for enhanced addressing modes +• 16-channel implementation that performs complex data transfers with minimal +intervention from a host processor +• Internal data buffer, used as temporary storage to support 16-byte transfers +• Connections to the crossbar switch for bus mastering the data movement +• Transfer control descriptor (TCD) organized to support two-deep, nested transfer +operations +• 32-byte TCD stored in local memory for each channel +• An inner data transfer loop defined by a minor byte transfer count +• An outer data transfer loop defined by a major iteration count +• Channel activation via one of three methods: +• Explicit software initiation +• Initiation via a channel-to-channel linking mechanism for continuous transfers +• Peripheral-paced hardware requests, one per channel +• Fixed-priority and round-robin channel arbitration +• Channel completion reported via optional interrupt requests +• One interrupt per channel, optionally asserted at completion of major iteration +count +• Optional error terminations per channel and logically summed together to form +one error interrupt to the interrupt controller +• Optional support for scatter/gather DMA processing +• Support for complex data structures +• Support to cancel transfers via software +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +458 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 458](pdf-image://page_458_img_1) + +## Page 459 + +In the discussion of this module, n is used to reference the channel number. +22.2 +Modes of operation +The eDMA operates in the following modes: +Table 22-3. Modes of operation +Mode +Description +Normal +In Normal mode, the eDMA transfers data between a source and a destination. The source and +destination can be a memory block or an I/O block capable of operation with the eDMA. +A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the +transfer control descriptor (TCD). The minor loop is the sequence of read-write operations that +transfers these NBYTES per service request. Each service request executes one iteration of the +major loop, which transfers NBYTES of data. +Debug +DMA operation is configurable in Debug mode via the control register: +• If CR[EDBG] is cleared, the DMA continues to operate. +• If CR[EDBG] is set, the eDMA stops transferring data. If Debug mode is entered while a +channel is active, the eDMA continues operation until the channel retires. +Wait +Before entering Wait mode, the DMA attempts to complete its current transfer. After the transfer +completes, the device enters Wait mode. +22.3 +Memory map/register definition +The eDMA's programming model is partitioned into two regions: +• The first region defines a number of registers providing control functions +• The second region corresponds to the local transfer control descriptor memory +Each channel requires a 32-byte transfer control descriptor for defining the desired data +movement operation. The channel descriptors are stored in the local memory in +sequential order: channel 0, channel 1,... channel 15 . Each TCDn definition is presented +as 11 registers of 16 or 32 bits. +Reading reserved bits in a register returns the value of zero. Writes to reserved bits in a +register are ignored. Reading or writing a reserved memory location generates a bus +error. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +459 +General Business Information + +![Image 1 from page 459](pdf-image://page_459_img_1) + +## Page 460 + +DMA memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_8000 +Control Register (DMA\_CR) +32 +R/W +0\_0000 +\_0000h +22.3.1/470 +4000\_8004 +Error Status Register (DMA\_ES) +32 +R +0\_0000 +\_0000h +22.3.2/472 +4000\_800C +Enable Request Register (DMA\_ ERQ ) +32 +R/W +0\_0000 +\_0000h +22.3.3/474 +4000\_8014 +Enable Error Interrupt Register (DMA\_ EEI ) +32 +R/W +0\_0000 +\_0000h +22.3.4/476 +4000\_8018 +Clear Enable Error Interrupt Register (DMA\_CEEI) +8 +W +(always +reads 0) +000h +22.3.5/479 +4000\_8019 +Set Enable Error Interrupt Register (DMA\_SEEI) +8 +W +(always +reads 0) +000h +22.3.6/480 +4000\_801A +Clear Enable Request Register (DMA\_CERQ) +8 +W +(always +reads 0) +000h +22.3.7/481 +4000\_801B +Set Enable Request Register (DMA\_SERQ) +8 +W +(always +reads 0) +000h +22.3.8/482 +4000\_801C +Clear DONE Status Bit Register (DMA\_CDNE) +8 +W +(always +reads 0) +000h +22.3.9/483 +4000\_801D +Set START Bit Register (DMA\_SSRT) +8 +W +(always +reads 0) +000h +22.3.10/484 +4000\_801E +Clear Error Register (DMA\_CERR) +8 +W +(always +reads 0) +000h +22.3.11/485 +4000\_801F +Clear Interrupt Request Register (DMA\_CINT) +8 +W +(always +reads 0) +000h +22.3.12/486 +4000\_8024 +Interrupt Request Register (DMA\_ INT ) +32 +R/W +0\_0000 +\_0000h +22.3.13/487 +4000\_802C +Error Register (DMA\_ ERR ) +32 +R/W +0\_0000 +\_0000h +22.3.14/489 +4000\_8034 +Hardware Request Status Register (DMA\_ HRS ) +32 +R/W +0\_0000 +\_0000h +22.3.15/492 +4000\_8100 +Channel n Priority Register (DMA\_DCHPRI3) +8 +R/W +See section +22.3.16/494 +4000\_8101 +Channel n Priority Register (DMA\_DCHPRI2) +8 +R/W +See section +22.3.16/494 +4000\_8102 +Channel n Priority Register (DMA\_DCHPRI1) +8 +R/W +See section +22.3.16/494 +4000\_8103 +Channel n Priority Register (DMA\_DCHPRI0) +8 +R/W +See section +22.3.16/494 +4000\_8104 +Channel n Priority Register (DMA\_DCHPRI7) +8 +R/W +See section +22.3.16/494 +4000\_8105 +Channel n Priority Register (DMA\_DCHPRI6) +8 +R/W +See section +22.3.16/494 +4000\_8106 +Channel n Priority Register (DMA\_DCHPRI5) +8 +R/W +See section +22.3.16/494 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +460 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 460](pdf-image://page_460_img_1) + +## Page 461 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_8107 +Channel n Priority Register (DMA\_DCHPRI4) +8 +R/W +See section +22.3.16/494 +4000\_8108 +Channel n Priority Register (DMA\_DCHPRI11) +8 +R/W +See section +22.3.16/494 +4000\_8109 +Channel n Priority Register (DMA\_DCHPRI10) +8 +R/W +See section +22.3.16/494 +4000\_810A +Channel n Priority Register (DMA\_DCHPRI9) +8 +R/W +See section +22.3.16/494 +4000\_810B +Channel n Priority Register (DMA\_DCHPRI8) +8 +R/W +See section +22.3.16/494 +4000\_810C +Channel n Priority Register (DMA\_DCHPRI15) +8 +R/W +See section +22.3.16/494 +4000\_810D +Channel n Priority Register (DMA\_DCHPRI14) +8 +R/W +See section +22.3.16/494 +4000\_810E +Channel n Priority Register (DMA\_DCHPRI13) +8 +R/W +See section +22.3.16/494 +4000\_810F +Channel n Priority Register (DMA\_DCHPRI12) +8 +R/W +See section +22.3.16/494 +4000\_9000 +TCD Source Address (DMA\_TCD0\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9004 +TCD Signed Source Address Offset (DMA\_TCD0\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_9006 +TCD Transfer Attributes (DMA\_TCD0\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9008 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD0\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9008 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD0\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_9008 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD0\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_900C +TCD Last Source Address Adjustment +(DMA\_TCD0\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9010 +TCD Destination Address (DMA\_TCD0\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_9014 +TCD Signed Destination Address Offset +(DMA\_TCD0\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9016 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD0\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9016 +DMA\_TCD0\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_9018 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD0\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_901C +TCD Control and Status (DMA\_TCD0\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_901E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD0\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_901E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD0\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_9020 +TCD Source Address (DMA\_TCD1\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9024 +TCD Signed Source Address Offset (DMA\_TCD1\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_9026 +TCD Transfer Attributes (DMA\_TCD1\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9028 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD1\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9028 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD1\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +461 +General Business Information + +![Image 1 from page 461](pdf-image://page_461_img_1) + +## Page 462 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_9028 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD1\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_902C +TCD Last Source Address Adjustment +(DMA\_TCD1\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9030 +TCD Destination Address (DMA\_TCD1\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_9034 +TCD Signed Destination Address Offset +(DMA\_TCD1\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9036 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD1\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9036 +DMA\_TCD1\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_9038 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD1\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_903C +TCD Control and Status (DMA\_TCD1\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_903E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD1\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_903E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD1\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_9040 +TCD Source Address (DMA\_TCD2\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9044 +TCD Signed Source Address Offset (DMA\_TCD2\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_9046 +TCD Transfer Attributes (DMA\_TCD2\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9048 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD2\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9048 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD2\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_9048 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD2\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_904C +TCD Last Source Address Adjustment +(DMA\_TCD2\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9050 +TCD Destination Address (DMA\_TCD2\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_9054 +TCD Signed Destination Address Offset +(DMA\_TCD2\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9056 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD2\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9056 +DMA\_TCD2\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_9058 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD2\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_905C +TCD Control and Status (DMA\_TCD2\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_905E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD2\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_905E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD2\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +462 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 462](pdf-image://page_462_img_1) + +## Page 463 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_9060 +TCD Source Address (DMA\_TCD3\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9064 +TCD Signed Source Address Offset (DMA\_TCD3\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_9066 +TCD Transfer Attributes (DMA\_TCD3\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9068 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD3\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9068 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD3\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_9068 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD3\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_906C +TCD Last Source Address Adjustment +(DMA\_TCD3\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9070 +TCD Destination Address (DMA\_TCD3\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_9074 +TCD Signed Destination Address Offset +(DMA\_TCD3\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9076 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD3\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9076 +DMA\_TCD3\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_9078 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD3\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_907C +TCD Control and Status (DMA\_TCD3\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_907E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD3\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_907E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD3\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_9080 +TCD Source Address (DMA\_TCD4\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9084 +TCD Signed Source Address Offset (DMA\_TCD4\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_9086 +TCD Transfer Attributes (DMA\_TCD4\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9088 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD4\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9088 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD4\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_9088 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD4\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_908C +TCD Last Source Address Adjustment +(DMA\_TCD4\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9090 +TCD Destination Address (DMA\_TCD4\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_9094 +TCD Signed Destination Address Offset +(DMA\_TCD4\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9096 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD4\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9096 +DMA\_TCD4\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +463 +General Business Information + +![Image 1 from page 463](pdf-image://page_463_img_1) + +## Page 464 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_9098 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD4\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_909C +TCD Control and Status (DMA\_TCD4\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_909E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD4\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_909E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD4\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_90A0 +TCD Source Address (DMA\_TCD5\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_90A4 +TCD Signed Source Address Offset (DMA\_TCD5\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_90A6 +TCD Transfer Attributes (DMA\_TCD5\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_90A8 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD5\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_90A8 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD5\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_90A8 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD5\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_90AC +TCD Last Source Address Adjustment +(DMA\_TCD5\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_90B0 +TCD Destination Address (DMA\_TCD5\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_90B4 +TCD Signed Destination Address Offset +(DMA\_TCD5\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_90B6 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD5\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_90B6 +DMA\_TCD5\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_90B8 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD5\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_90BC +TCD Control and Status (DMA\_TCD5\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_90BE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD5\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_90BE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD5\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_90C0 +TCD Source Address (DMA\_TCD6\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_90C4 +TCD Signed Source Address Offset (DMA\_TCD6\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_90C6 +TCD Transfer Attributes (DMA\_TCD6\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_90C8 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD6\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_90C8 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD6\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_90C8 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD6\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +464 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 464](pdf-image://page_464_img_1) + +## Page 465 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_90CC +TCD Last Source Address Adjustment +(DMA\_TCD6\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_90D0 +TCD Destination Address (DMA\_TCD6\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_90D4 +TCD Signed Destination Address Offset +(DMA\_TCD6\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_90D6 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD6\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_90D6 +DMA\_TCD6\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_90D8 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD6\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_90DC +TCD Control and Status (DMA\_TCD6\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_90DE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD6\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_90DE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD6\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_90E0 +TCD Source Address (DMA\_TCD7\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_90E4 +TCD Signed Source Address Offset (DMA\_TCD7\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_90E6 +TCD Transfer Attributes (DMA\_TCD7\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_90E8 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD7\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_90E8 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD7\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_90E8 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD7\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_90EC +TCD Last Source Address Adjustment +(DMA\_TCD7\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_90F0 +TCD Destination Address (DMA\_TCD7\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_90F4 +TCD Signed Destination Address Offset +(DMA\_TCD7\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_90F6 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD7\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_90F6 +DMA\_TCD7\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_90F8 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD7\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_90FC +TCD Control and Status (DMA\_TCD7\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_90FE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD7\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_90FE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD7\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_9100 +TCD Source Address (DMA\_TCD8\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9104 +TCD Signed Source Address Offset (DMA\_TCD8\_SOFF) +16 +R/W +Undefined +22.3.18/495 +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +465 +General Business Information + +![Image 1 from page 465](pdf-image://page_465_img_1) + +## Page 466 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_9106 +TCD Transfer Attributes (DMA\_TCD8\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9108 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD8\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9108 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD8\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_9108 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD8\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_910C +TCD Last Source Address Adjustment +(DMA\_TCD8\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9110 +TCD Destination Address (DMA\_TCD8\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_9114 +TCD Signed Destination Address Offset +(DMA\_TCD8\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9116 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD8\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9116 +DMA\_TCD8\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_9118 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD8\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_911C +TCD Control and Status (DMA\_TCD8\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_911E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD8\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_911E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD8\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_9120 +TCD Source Address (DMA\_TCD9\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9124 +TCD Signed Source Address Offset (DMA\_TCD9\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_9126 +TCD Transfer Attributes (DMA\_TCD9\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9128 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD9\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9128 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD9\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_9128 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD9\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_912C +TCD Last Source Address Adjustment +(DMA\_TCD9\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9130 +TCD Destination Address (DMA\_TCD9\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_9134 +TCD Signed Destination Address Offset +(DMA\_TCD9\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9136 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD9\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9136 +DMA\_TCD9\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_9138 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD9\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_913C +TCD Control and Status (DMA\_TCD9\_CSR) +16 +R/W +Undefined +22.3.29/504 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +466 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 466](pdf-image://page_466_img_1) + +## Page 467 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_913E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD9\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_913E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) (DMA\_TCD9\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_9140 +TCD Source Address (DMA\_TCD10\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9144 +TCD Signed Source Address Offset (DMA\_TCD10\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_9146 +TCD Transfer Attributes (DMA\_TCD10\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9148 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD10\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9148 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD10\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_9148 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD10\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_914C +TCD Last Source Address Adjustment +(DMA\_TCD10\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9150 +TCD Destination Address (DMA\_TCD10\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_9154 +TCD Signed Destination Address Offset +(DMA\_TCD10\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9156 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD10\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9156 +DMA\_TCD10\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_9158 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD10\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_915C +TCD Control and Status (DMA\_TCD10\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_915E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD10\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_915E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) +(DMA\_TCD10\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_9160 +TCD Source Address (DMA\_TCD11\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9164 +TCD Signed Source Address Offset (DMA\_TCD11\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_9166 +TCD Transfer Attributes (DMA\_TCD11\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9168 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD11\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9168 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD11\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_9168 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD11\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_916C +TCD Last Source Address Adjustment +(DMA\_TCD11\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9170 +TCD Destination Address (DMA\_TCD11\_DADDR) +32 +R/W +Undefined +22.3.24/500 +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +467 +General Business Information + +![Image 1 from page 467](pdf-image://page_467_img_1) + +## Page 468 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_9174 +TCD Signed Destination Address Offset +(DMA\_TCD11\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9176 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD11\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9176 +DMA\_TCD11\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_9178 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD11\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_917C +TCD Control and Status (DMA\_TCD11\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_917E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD11\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_917E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) +(DMA\_TCD11\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_9180 +TCD Source Address (DMA\_TCD12\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_9184 +TCD Signed Source Address Offset (DMA\_TCD12\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_9186 +TCD Transfer Attributes (DMA\_TCD12\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_9188 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD12\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_9188 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD12\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_9188 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD12\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_918C +TCD Last Source Address Adjustment +(DMA\_TCD12\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_9190 +TCD Destination Address (DMA\_TCD12\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_9194 +TCD Signed Destination Address Offset +(DMA\_TCD12\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_9196 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD12\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_9196 +DMA\_TCD12\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_9198 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD12\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_919C +TCD Control and Status (DMA\_TCD12\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_919E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD12\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_919E +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) +(DMA\_TCD12\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_91A0 +TCD Source Address (DMA\_TCD13\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_91A4 +TCD Signed Source Address Offset (DMA\_TCD13\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_91A6 +TCD Transfer Attributes (DMA\_TCD13\_ATTR) +16 +R/W +Undefined +22.3.19/496 +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +468 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 468](pdf-image://page_468_img_1) + +## Page 469 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_91A8 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD13\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_91A8 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD13\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_91A8 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD13\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_91AC +TCD Last Source Address Adjustment +(DMA\_TCD13\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_91B0 +TCD Destination Address (DMA\_TCD13\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_91B4 +TCD Signed Destination Address Offset +(DMA\_TCD13\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_91B6 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD13\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_91B6 +DMA\_TCD13\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_91B8 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD13\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_91BC +TCD Control and Status (DMA\_TCD13\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_91BE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD13\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_91BE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) +(DMA\_TCD13\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_91C0 +TCD Source Address (DMA\_TCD14\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_91C4 +TCD Signed Source Address Offset (DMA\_TCD14\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_91C6 +TCD Transfer Attributes (DMA\_TCD14\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_91C8 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD14\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_91C8 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD14\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_91C8 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD14\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_91CC +TCD Last Source Address Adjustment +(DMA\_TCD14\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_91D0 +TCD Destination Address (DMA\_TCD14\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_91D4 +TCD Signed Destination Address Offset +(DMA\_TCD14\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_91D6 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD14\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_91D6 +DMA\_TCD14\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_91D8 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD14\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_91DC +TCD Control and Status (DMA\_TCD14\_CSR) +16 +R/W +Undefined +22.3.29/504 +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +469 +General Business Information + +![Image 1 from page 469](pdf-image://page_469_img_1) + +## Page 470 + +DMA memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_91DE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD14\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_91DE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) +(DMA\_TCD14\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +4000\_91E0 +TCD Source Address (DMA\_TCD15\_SADDR) +32 +R/W +Undefined +22.3.17/495 +4000\_91E4 +TCD Signed Source Address Offset (DMA\_TCD15\_SOFF) +16 +R/W +Undefined +22.3.18/495 +4000\_91E6 +TCD Transfer Attributes (DMA\_TCD15\_ATTR) +16 +R/W +Undefined +22.3.19/496 +4000\_91E8 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCD15\_NBYTES\_MLNO) +32 +R/W +Undefined +22.3.20/497 +4000\_91E8 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCD15\_NBYTES\_MLOFFNO) +32 +R/W +Undefined +22.3.21/497 +4000\_91E8 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCD15\_NBYTES\_MLOFFYES) +32 +R/W +Undefined +22.3.22/498 +4000\_91EC +TCD Last Source Address Adjustment +(DMA\_TCD15\_SLAST) +32 +R/W +Undefined +22.3.23/500 +4000\_91F0 +TCD Destination Address (DMA\_TCD15\_DADDR) +32 +R/W +Undefined +22.3.24/500 +4000\_91F4 +TCD Signed Destination Address Offset +(DMA\_TCD15\_DOFF) +16 +R/W +Undefined +22.3.25/501 +4000\_91F6 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCD15\_CITER\_ELINKYES) +16 +R/W +Undefined +22.3.26/501 +4000\_91F6 +DMA\_TCD15\_CITER\_ELINKNO +16 +R/W +Undefined +22.3.27/502 +4000\_91F8 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCD15\_DLASTSGA) +32 +R/W +Undefined +22.3.28/503 +4000\_91FC +TCD Control and Status (DMA\_TCD15\_CSR) +16 +R/W +Undefined +22.3.29/504 +4000\_91FE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Enabled) +(DMA\_TCD15\_BITER\_ELINKYES) +16 +R/W +Undefined +22.3.30/506 +4000\_91FE +TCD Beginning Minor Loop Link, Major Loop Count +(Channel Linking Disabled) +(DMA\_TCD15\_BITER\_ELINKNO) +16 +R/W +Undefined +22.3.31/507 +22.3.1 +Control Register (DMA\_CR) +The CR defines the basic operating configuration of the DMA. +Arbitration can be configured to use either a fixed-priority or a round-robin scheme. For +fixed-priority arbitration, the highest priority channel requesting service is selected to +execute. The channel priority registers assign the priorities; see the DCHPRIn registers. +For round-robin arbitration, the channel priorities are ignored and channels are cycled +through (from high to low channel number) without regard to priority. +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +470 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 470](pdf-image://page_470_img_1) + +## Page 471 + +NOTE +For proper operation, writes to the CR register must be +performed only when the DMA channels are inactive; that is, +when TCDn\_CSR[ACTIVE] bits are cleared. +Address: 4000\_8000h base + 0h offset = 4000\_8000h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +CX +ECX +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +EMLM +CLM +HALT +HOE +0 +ERCA +EDBG +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_CR field descriptions +Field +Description +31–18 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +17 +CX +Cancel Transfer +0 +Normal operation +1 +Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The +cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after +the cancel has been honored. This cancel retires the channel normally as if the minor loop was +completed. +16 +ECX +Error Cancel Transfer +0 +Normal operation +1 +Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and +force the minor loop to finish. The cancel takes effect after the last write of the current read/write +sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, +ECX treats the cancel as an error condition, thus updating the ES register and generating an optional +error interrupt. +15–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7 +EMLM +Enable Minor Loop Mapping +0 +Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. +1 +Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES +field. The individual enable fields allow the minor loop offset to be applied to the source address, the +destination address, or both. The NBYTES field is reduced when either offset is enabled. +6 +CLM +Continuous Link Mode +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +471 +General Business Information + +![Image 1 from page 471](pdf-image://page_471_img_1) + +## Page 472 + +DMA\_CR field descriptions (continued) +Field +Description +0 +A minor loop channel link made to itself goes through channel arbitration before being activated again. +1 +A minor loop channel link made to itself does not go through channel arbitration before being activated +again. Upon minor loop completion, the channel activates again if that channel has a minor loop +channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and +restarts the next minor loop. +5 +HALT +Halt DMA Operations +0 +Normal operation +1 +Stall the start of any new channels. Executing channels are allowed to complete. Channel execution +resumes when this bit is cleared. +4 +HOE +Halt On Error +0 +Normal operation +1 +Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit +is cleared. +3 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +2 +ERCA +Enable Round Robin Channel Arbitration +0 +Fixed priority arbitration is used for channel selection . +1 +Round robin arbitration is used for channel selection . +1 +EDBG +Enable Debug +0 +When in debug mode, the DMA continues to operate. +1 +When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to +complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. +0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +22.3.2 +Error Status Register (DMA\_ES) +The ES provides information concerning the last recorded channel error. Channel errors +can be caused by: +• A configuration error, that is: +• An illegal setting in the transfer-control descriptor, or +• An illegal priority register setting in fixed-arbitration +• An error termination to a bus master read or write cycle +See the Error Reporting and Handling section for more details. +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +472 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 472](pdf-image://page_472_img_1) + +## Page 473 + +Address: 4000\_8000h base + 4h offset = 4000\_8004h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +VLD +0 +ECX +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +CPE +0 +ERRCHN +SAE +SOE +DAE +DOE +NCE +SGE +SBE +DBE +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_ES field descriptions +Field +Description +31 +VLD +Logical OR of all ERR status bits +0 +No ERR bits are set +1 +At least one ERR bit is set indicating a valid error exists that has not been cleared +30–17 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +16 +ECX +Transfer Cancelled +0 +No cancelled transfers +1 +The last recorded entry was a cancelled transfer by the error cancel transfer input +15 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +14 +CPE +Channel Priority Error +0 +No channel priority error +1 +The last recorded error was a configuration error in the channel priorities . Channel priorities are not +unique. +13–12 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +11–8 +ERRCHN +Error Channel Number or Cancelled Channel Number +The channel number of the last recorded error (excluding CPE errors) or last recorded error cancelled +transfer . +7 +SAE +Source Address Error +0 +No source address configuration error. +1 +The last recorded error was a configuration error detected in the TCDn\_SADDR field. TCDn\_SADDR +is inconsistent with TCDn\_ATTR[SSIZE]. +6 +SOE +Source Offset Error +0 +No source offset configuration error +1 +The last recorded error was a configuration error detected in the TCDn\_SOFF field. TCDn\_SOFF is +inconsistent with TCDn\_ATTR[SSIZE]. +5 +DAE +Destination Address Error +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +473 +General Business Information + +![Image 1 from page 473](pdf-image://page_473_img_1) + +## Page 474 + +DMA\_ES field descriptions (continued) +Field +Description +0 +No destination address configuration error +1 +The last recorded error was a configuration error detected in the TCDn\_DADDR field. TCDn\_DADDR +is inconsistent with TCDn\_ATTR[DSIZE]. +4 +DOE +Destination Offset Error +0 +No destination offset configuration error +1 +The last recorded error was a configuration error detected in the TCDn\_DOFF field. TCDn\_DOFF is +inconsistent with TCDn\_ATTR[DSIZE]. +3 +NCE +NBYTES/CITER Configuration Error +0 +No NBYTES/CITER configuration error +1 +The last recorded error was a configuration error detected in the TCDn\_NBYTES or TCDn\_CITER +fields. +• TCDn\_NBYTES is not a multiple of TCDn\_ATTR[SSIZE] and TCDn\_ATTR[DSIZE], or +• TCDn\_CITER[CITER] is equal to zero, or +• TCDn\_CITER[ELINK] is not equal to TCDn\_BITER[ELINK] +2 +SGE +Scatter/Gather Configuration Error +0 +No scatter/gather configuration error +1 +The last recorded error was a configuration error detected in the TCDn\_DLASTSGA field. This field is +checked at the beginning of a scatter/gather operation after major loop completion if TCDn\_CSR[ESG] +is enabled. TCDn\_DLASTSGA is not on a 32 byte boundary. +1 +SBE +Source Bus Error +0 +No source bus error +1 +The last recorded error was a bus error on a source read +0 +DBE +Destination Bus Error +0 +No destination bus error +1 +The last recorded error was a bus error on a destination write +22.3.3 +Enable Request Register (DMA\_ ERQ ) +The ERQ register provide s a bit map for the 16 implemented channels to enable the +request signal for each channel. The state of any given channel enable is directly affected +by writes to this register; it is also affected by writes to the SERQ and CERQ. The +{S,C}ERQ registers are provided so the request enable for a single channel can easily be +modified without needing to perform a read-modify-write sequence to the ERQ . +DMA request input signals and this enable request flag must be asserted before a +channel’s hardware service request is accepted. The state of the DMA enable request flag +does not affect a channel service request made explicitly through software or a linked +channel request. +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +474 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 474](pdf-image://page_474_img_1) + +## Page 475 + +Address: 4000\_8000h base + Ch offset = 4000\_800Ch +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +ERQ15 +ERQ14 +ERQ13 +ERQ12 +ERQ11 +ERQ10 +ERQ9 ERQ8 ERQ7 ERQ6 ERQ5 ERQ4 ERQ3 ERQ2 ERQ1 ERQ0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_ ERQ field descriptions +Field +Description +31–16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15 +ERQ15 +Enable DMA Request 15 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +14 +ERQ14 +Enable DMA Request 14 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +13 +ERQ13 +Enable DMA Request 13 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +12 +ERQ12 +Enable DMA Request 12 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +11 +ERQ11 +Enable DMA Request 11 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +10 +ERQ10 +Enable DMA Request 10 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +9 +ERQ9 +Enable DMA Request 9 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +8 +ERQ8 +Enable DMA Request 8 +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +475 +General Business Information + +![Image 1 from page 475](pdf-image://page_475_img_1) + +## Page 476 + +DMA\_ ERQ field descriptions (continued) +Field +Description +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +7 +ERQ7 +Enable DMA Request 7 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +6 +ERQ6 +Enable DMA Request 6 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +5 +ERQ5 +Enable DMA Request 5 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +4 +ERQ4 +Enable DMA Request 4 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +3 +ERQ3 +Enable DMA Request 3 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +2 +ERQ2 +Enable DMA Request 2 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +1 +ERQ1 +Enable DMA Request 1 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +0 +ERQ0 +Enable DMA Request 0 +0 +The DMA request signal for the corresponding channel is disabled +1 +The DMA request signal for the corresponding channel is enabled +22.3.4 +Enable Error Interrupt Register (DMA\_ EEI ) +The EEI register provides a bit map for the 16 channels to enable the error interrupt +signal for each channel. The state of any given channel’s error interrupt enable is directly +affected by writes to this register; it is also affected by writes to the SEEI and CEEI. The +{S,C}EEI are provided so the error interrupt enable for a single channel can easily be +modified without the need to perform a read-modify-write sequence to the EEI register . +The DMA error indicator and the error interrupt enable flag must be asserted before an +error interrupt request for a given channel is asserted to the interrupt controller. +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +476 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 476](pdf-image://page_476_img_1) + +## Page 477 + +Address: 4000\_8000h base + 14h offset = 4000\_8014h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +EEI15 +EEI14 +EEI13 +EEI12 +EEI11 +EEI10 +EEI9 +EEI8 +EEI7 +EEI6 +EEI5 +EEI4 +EEI3 +EEI2 +EEI1 +EEI0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_ EEI field descriptions +Field +Description +31–16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15 +EEI15 +Enable Error Interrupt 15 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +14 +EEI14 +Enable Error Interrupt 14 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +13 +EEI13 +Enable Error Interrupt 13 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +12 +EEI12 +Enable Error Interrupt 12 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +11 +EEI11 +Enable Error Interrupt 11 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +10 +EEI10 +Enable Error Interrupt 10 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +9 +EEI9 +Enable Error Interrupt 9 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +8 +EEI8 +Enable Error Interrupt 8 +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +477 +General Business Information + +![Image 1 from page 477](pdf-image://page_477_img_1) + +## Page 478 + +DMA\_ EEI field descriptions (continued) +Field +Description +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +7 +EEI7 +Enable Error Interrupt 7 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +6 +EEI6 +Enable Error Interrupt 6 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +5 +EEI5 +Enable Error Interrupt 5 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +4 +EEI4 +Enable Error Interrupt 4 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +3 +EEI3 +Enable Error Interrupt 3 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +2 +EEI2 +Enable Error Interrupt 2 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +1 +EEI1 +Enable Error Interrupt 1 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +0 +EEI0 +Enable Error Interrupt 0 +0 +The error signal for corresponding channel does not generate an error interrupt +1 +The assertion of the error signal for corresponding channel generates an error interrupt request +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +478 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 478](pdf-image://page_478_img_1) + +## Page 479 + +22.3.5 +Clear Enable Error Interrupt Register (DMA\_CEEI) +The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI +to disable the error interrupt for a given channel. The data value on a register write causes +the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global +clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs. +If the NOP bit is set, the command is ignored. This allows you to write multiple-byte +registers as a 32-bit word. Reads of this register return all zeroes. +Address: 4000\_8000h base + 18h offset = 4000\_8018h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +0 +Write +NOP +CAEE +0 +CEEI +Reset +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_CEEI field descriptions +Field +Description +7 +NOP +No Op enable +0 +Normal operation +1 +No operation, ignore the other bits in this register +6 +CAEE +Clear All Enable Error Interrupts +0 +Clear only the EEI bit specified in the CEEI field +1 +Clear all bits in EEI +5–4 +Reserved +This field is reserved. +3–0 +CEEI +Clear Enable Error Interrupt +Clears the corresponding bit in EEI +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +479 +General Business Information + +![Image 1 from page 479](pdf-image://page_479_img_1) + +## Page 480 + +22.3.6 +Set Enable Error Interrupt Register (DMA\_SEEI) +The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to +enable the error interrupt for a given channel. The data value on a register write causes +the corresponding bit in the EEI to be set. Setting the SAEE bit provides a global set +function, forcing the entire EEI contents to be set. If the NOP bit is set, the command is +ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this +register return all zeroes. +Address: 4000\_8000h base + 19h offset = 4000\_8019h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +0 +Write +NOP +SAEE +0 +SEEI +Reset +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_SEEI field descriptions +Field +Description +7 +NOP +No Op enable +0 +Normal operation +1 +No operation, ignore the other bits in this register +6 +SAEE +Sets All Enable Error Interrupts +0 +Set only the EEI bit specified in the SEEI field. +1 +Sets all bits in EEI +5–4 +Reserved +This field is reserved. +3–0 +SEEI +Set Enable Error Interrupt +Sets the corresponding bit in EEI +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +480 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 480](pdf-image://page_480_img_1) + +## Page 481 + +22.3.7 +Clear Enable Request Register (DMA\_CERQ) +The CERQ provides a simple memory-mapped mechanism to clear a given bit in the +ERQ to disable the DMA request for a given channel. The data value on a register write +causes the corresponding bit in the ERQ to be cleared. Setting the CAER bit provides a +global clear function, forcing the entire contents of the ERQ to be cleared, disabling all +DMA request inputs. If NOP is set, the command is ignored. This allows you to write +multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. +Address: 4000\_8000h base + 1Ah offset = 4000\_801Ah +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +0 +Write +NOP +CAER +0 +CERQ +Reset +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_CERQ field descriptions +Field +Description +7 +NOP +No Op enable +0 +Normal operation +1 +No operation, ignore the other bits in this register +6 +CAER +Clear All Enable Requests +0 +Clear only the ERQ bit specified in the CERQ field +1 +Clear all bits in ERQ +5–4 +Reserved +This field is reserved. +3–0 +CERQ +Clear Enable Request +Clears the corresponding bit in ERQ +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +481 +General Business Information + +![Image 1 from page 481](pdf-image://page_481_img_1) + +## Page 482 + +22.3.8 +Set Enable Request Register (DMA\_SERQ) +The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ +to enable the DMA request for a given channel. The data value on a register write causes +the corresponding bit in the ERQ to be set. Setting the SAER bit provides a global set +function, forcing the entire contents of ERQ to be set. If the NOP bit is set, the command +is ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this +register return all zeroes. +Address: 4000\_8000h base + 1Bh offset = 4000\_801Bh +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +0 +Write +NOP +SAER +0 +SERQ +Reset +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_SERQ field descriptions +Field +Description +7 +NOP +No Op enable +0 +Normal operation +1 +No operation, ignore the other bits in this register +6 +SAER +Set All Enable Requests +0 +Set only the ERQ bit specified in the SERQ field +1 +Set all bits in ERQ +5–4 +Reserved +This field is reserved. +3–0 +SERQ +Set enable request +Sets the corresponding bit in ERQ +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +482 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 482](pdf-image://page_482_img_1) + +## Page 483 + +22.3.9 +Clear DONE Status Bit Register (DMA\_CDNE) +The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the +TCD of the given channel. The data value on a register write causes the DONE bit in the +corresponding transfer control descriptor to be cleared. Setting the CADN bit provides a +global clear function, forcing all DONE bits to be cleared. If the NOP bit is set, the +command is ignored. This allows you to write multiple-byte registers as a 32-bit word. +Reads of this register return all zeroes. +Address: 4000\_8000h base + 1Ch offset = 4000\_801Ch +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +0 +Write +NOP +CADN +0 +CDNE +Reset +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_CDNE field descriptions +Field +Description +7 +NOP +No Op enable +0 +Normal operation +1 +No operation, ignore the other bits in this register +6 +CADN +Clears All DONE Bits +0 +Clears only the TCDn\_CSR[DONE] bit specified in the CDNE field +1 +Clears all bits in TCDn\_CSR[DONE] +5–4 +Reserved +This field is reserved. +3–0 +CDNE +Clear DONE Bit +Clears the corresponding bit in TCDn\_CSR[DONE] +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +483 +General Business Information + +![Image 1 from page 483](pdf-image://page_483_img_1) + +## Page 484 + +22.3.10 +Set START Bit Register (DMA\_SSRT) +The SSRT provides a simple memory-mapped mechanism to set the START bit in the +TCD of the given channel. The data value on a register write causes the START bit in the +corresponding transfer control descriptor to be set. Setting the SAST bit provides a global +set function, forcing all START bits to be set. If the NOP bit is set, the command is +ignored. This allows you to write multiple-byte registers as a 32-bit word. Reads of this +register return all zeroes. +Address: 4000\_8000h base + 1Dh offset = 4000\_801Dh +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +0 +Write +NOP +SAST +0 +SSRT +Reset +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_SSRT field descriptions +Field +Description +7 +NOP +No Op enable +0 +Normal operation +1 +No operation, ignore the other bits in this register +6 +SAST +Set All START Bits (activates all channels) +0 +Set only the TCDn\_CSR[START] bit specified in the SSRT field +1 +Set all bits in TCDn\_CSR[START] +5–4 +Reserved +This field is reserved. +3–0 +SSRT +Set START Bit +Sets the corresponding bit in TCDn\_CSR[START] +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +484 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 484](pdf-image://page_484_img_1) + +## Page 485 + +22.3.11 +Clear Error Register (DMA\_CERR) +The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR +to disable the error condition flag for a given channel. The given value on a register write +causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a +global clear function, forcing the ERR contents to be cleared, clearing all channel error +indicators. If the NOP bit is set, the command is ignored. This allows you to write +multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. +Address: 4000\_8000h base + 1Eh offset = 4000\_801Eh +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +0 +Write +NOP +CAEI +0 +CERR +Reset +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_CERR field descriptions +Field +Description +7 +NOP +No Op enable +0 +Normal operation +1 +No operation, ignore the other bits in this register +6 +CAEI +Clear All Error Indicators +0 +Clear only the ERR bit specified in the CERR field +1 +Clear all bits in ERR +5–4 +Reserved +This field is reserved. +3–0 +CERR +Clear Error Indicator +Clears the corresponding bit in ERR +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +485 +General Business Information + +![Image 1 from page 485](pdf-image://page_485_img_1) + +## Page 486 + +22.3.12 +Clear Interrupt Request Register (DMA\_CINT) +The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT +to disable the interrupt request for a given channel. The given value on a register write +causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a +global clear function, forcing the entire contents of the INT to be cleared, disabling all +DMA interrupt requests. If the NOP bit is set, the command is ignored. This allows you +to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes. +Address: 4000\_8000h base + 1Fh offset = 4000\_801Fh +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +0 +Write +NOP +CAIR +0 +CINT +Reset +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_CINT field descriptions +Field +Description +7 +NOP +No Op enable +0 +Normal operation +1 +No operation, ignore the other bits in this register +6 +CAIR +Clear All Interrupt Requests +0 +Clear only the INT bit specified in the CINT field +1 +Clear all bits in INT +5–4 +Reserved +This field is reserved. +3–0 +CINT +Clear Interrupt Request +Clears the corresponding bit in INT +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +486 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 486](pdf-image://page_486_img_1) + +## Page 487 + +22.3.13 +Interrupt Request Register (DMA\_ INT ) +The INT register provides a bit map for the 16 channels signaling the presence of an +interrupt request for each channel. Depending on the appropriate bit setting in the +transfer-control descriptors, the eDMA engine generates an interrupt on data transfer +completion. The outputs of this register are directly routed to the interrupt controller +(INTC). During the interrupt-service routine associated with any given channel, it is the +software’s responsibility to clear the appropriate bit, negating the interrupt request. +Typically, a write to the CINT register in the interrupt service routine is used for this +purpose. +The state of any given channel’s interrupt request is directly affected by writes to this +register; it is also affected by writes to the CINT register. On writes to INT, a 1 in any bit +position clears the corresponding channel’s interrupt request. A zero in any bit position +has no affect on the corresponding channel’s current interrupt status. The CINT register is +provided so the interrupt request for a single channel can easily be cleared without the +need to perform a read-modify-write sequence to the INT register. +Address: 4000\_8000h base + 24h offset = 4000\_8024h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +INT15 +INT14 +INT13 +INT12 +INT11 +INT10 +INT9 +INT8 +INT7 +INT6 +INT5 +INT4 +INT3 +INT2 +INT1 +INT0 +W +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_ INT field descriptions +Field +Description +31–16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +487 +General Business Information + +![Image 1 from page 487](pdf-image://page_487_img_1) + +## Page 488 + +DMA\_ INT field descriptions (continued) +Field +Description +15 +INT15 +Interrupt Request 15 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +14 +INT14 +Interrupt Request 14 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +13 +INT13 +Interrupt Request 13 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +12 +INT12 +Interrupt Request 12 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +11 +INT11 +Interrupt Request 11 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +10 +INT10 +Interrupt Request 10 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +9 +INT9 +Interrupt Request 9 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +8 +INT8 +Interrupt Request 8 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +7 +INT7 +Interrupt Request 7 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +6 +INT6 +Interrupt Request 6 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +5 +INT5 +Interrupt Request 5 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +4 +INT4 +Interrupt Request 4 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +488 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 488](pdf-image://page_488_img_1) + +## Page 489 + +DMA\_ INT field descriptions (continued) +Field +Description +3 +INT3 +Interrupt Request 3 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +2 +INT2 +Interrupt Request 2 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +1 +INT1 +Interrupt Request 1 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +0 +INT0 +Interrupt Request 0 +0 +The interrupt request for corresponding channel is cleared +1 +The interrupt request for corresponding channel is active +22.3.14 +Error Register (DMA\_ ERR ) +The ERR provides a bit map for the 16 channels, signaling the presence of an error for +each channel. The eDMA engine signals the occurrence of an error condition by setting +the appropriate bit in this register. The outputs of this register are enabled by the contents +of the EEI, and then routed to the interrupt controller. During the execution of the +interrupt-service routine associated with any DMA errors, it is software’s responsibility +to clear the appropriate bit, negating the error-interrupt request. Typically, a write to the +CERR in the interrupt-service routine is used for this purpose. The normal DMA channel +completion indicators (setting the transfer control descriptor DONE flag and the possible +assertion of an interrupt request) are not affected when an error is detected. +The contents of this register can also be polled because a non-zero value indicates the +presence of a channel error regardless of the state of the EEI. The state of any given +channel’s error indicators is affected by writes to this register; it is also affected by writes +to the CERR. On writes to the ERR, a one in any bit position clears the corresponding +channel’s error status. A zero in any bit position has no affect on the corresponding +channel’s current error status. The CERR is provided so the error indicator for a single +channel can easily be cleared. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +489 +General Business Information + +![Image 1 from page 489](pdf-image://page_489_img_1) + +## Page 490 + +Address: 4000\_8000h base + 2Ch offset = 4000\_802Ch +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +ERR15 +ERR14 +ERR13 +ERR12 +ERR11 +ERR10 +ERR9 +ERR8 +ERR7 +ERR6 +ERR5 +ERR4 +ERR3 +ERR2 +ERR1 +ERR0 +W +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_ ERR field descriptions +Field +Description +31–16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15 +ERR15 +Error In Channel 15 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +14 +ERR14 +Error In Channel 14 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +13 +ERR13 +Error In Channel 13 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +12 +ERR12 +Error In Channel 12 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +11 +ERR11 +Error In Channel 11 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +10 +ERR10 +Error In Channel 10 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +490 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 490](pdf-image://page_490_img_1) + +## Page 491 + +DMA\_ ERR field descriptions (continued) +Field +Description +9 +ERR9 +Error In Channel 9 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +8 +ERR8 +Error In Channel 8 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +7 +ERR7 +Error In Channel 7 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +6 +ERR6 +Error In Channel 6 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +5 +ERR5 +Error In Channel 5 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +4 +ERR4 +Error In Channel 4 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +3 +ERR3 +Error In Channel 3 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +2 +ERR2 +Error In Channel 2 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +1 +ERR1 +Error In Channel 1 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +0 +ERR0 +Error In Channel 0 +0 +An error in the corresponding channel has not occurred +1 +An error in the corresponding channel has occurred +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +491 +General Business Information + +![Image 1 from page 491](pdf-image://page_491_img_1) + +## Page 492 + +22.3.15 +Hardware Request Status Register (DMA\_ HRS ) +The HRS provide s a bit map for the DMA channels, signaling the presence of a +hardware request for each channel. The hardware request status bits reflect the current +state of the register and qualified (via the ERQ fields) DMA request signals as seen by +the DMA’s arbitration logic. This view into the hardware request signals may be used for +debug purposes. +NOTE +These bits reflect the state of the request as seen by the +arbitration logic. Therefore, this status is affected by the ERQ +bits. +Address: 4000\_8000h base + 34h offset = 4000\_8034h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +HRS15 +HRS14 +HRS13 +HRS12 +HRS11 +HRS10 +HRS9 HRS8 HRS7 HRS6 HRS5 HRS4 HRS3 HRS2 HRS1 HRS0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +DMA\_ HRS field descriptions +Field +Description +31–16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15 +HRS15 +Hardware Request Status Channel 15 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +14 +HRS14 +Hardware Request Status Channel 14 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +13 +HRS13 +Hardware Request Status Channel 13 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +492 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 492](pdf-image://page_492_img_1) + +## Page 493 + +DMA\_ HRS field descriptions (continued) +Field +Description +12 +HRS12 +Hardware Request Status Channel 12 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +11 +HRS11 +Hardware Request Status Channel 11 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +10 +HRS10 +Hardware Request Status Channel 10 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +9 +HRS9 +Hardware Request Status Channel 9 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +8 +HRS8 +Hardware Request Status Channel 8 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +7 +HRS7 +Hardware Request Status Channel 7 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +6 +HRS6 +Hardware Request Status Channel 6 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +5 +HRS5 +Hardware Request Status Channel 5 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +4 +HRS4 +Hardware Request Status Channel 4 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +3 +HRS3 +Hardware Request Status Channel 3 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +2 +HRS2 +Hardware Request Status Channel 2 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +1 +HRS1 +Hardware Request Status Channel 1 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +493 +General Business Information + +![Image 1 from page 493](pdf-image://page_493_img_1) + +## Page 494 + +DMA\_ HRS field descriptions (continued) +Field +Description +0 +HRS0 +Hardware Request Status Channel 0 +0 +A hardware service request for the corresponding channel is not present +1 +A hardware service request for the corresponding channel is present +22.3.16 +Channel n Priority Register (DMA\_DCHPRIn) +When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these +registers define the unique priorities associated with each channel . The channel priorities +are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next +priority, then 2, 3, etc. Software must program the channel priorities with unique values; +otherwise, a configuration error is reported. The range of the priority value is limited to +the values of 0 through 15 . +Address: 4000\_8000h base + 100h offset + (1d × i), where i=0d to 15d +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +ECP +DPA +0 +CHPRI +Write +Reset +0 +0 +0 +0 +\* +\* +\* +\* +* Notes: +CHPRI field: See bit field description +• +DMA\_DCHPRIn field descriptions +Field +Description +7 +ECP +Enable Channel Preemption +0 +Channel n cannot be suspended by a higher priority channel’s service request +1 +Channel n can be temporarily suspended by the service request of a higher priority channel +6 +DPA +Disable Preempt Ability +0 +Channel n can suspend a lower priority channel +1 +Channel n cannot suspend any channel, regardless of channel priority +5–4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3–0 +CHPRI +Channel n Arbitration Priority +Channel priority when fixed-priority arbitration is enabled +NOTE: Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number +for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111. +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +494 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 494](pdf-image://page_494_img_1) + +## Page 495 + +22.3.17 +TCD Source Address (DMA\_TCDn\_SADDR) +Address: 4000\_8000h base + 1000h offset + (32d × i), where i=0d to 15d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +SADDR +W +Reset x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x* x* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_SADDR field descriptions +Field +Description +31–0 +SADDR +Source Address +Memory address pointing to the source data. +22.3.18 +TCD Signed Source Address Offset (DMA\_TCDn\_SOFF) +Address: 4000\_8000h base + 1004h offset + (32d × i), where i=0d to 15d +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +SOFF +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_SOFF field descriptions +Field +Description +15–0 +SOFF +Source address signed offset +Sign-extended offset applied to the current source address to form the next-state value as each source +read is completed. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +495 +General Business Information + +![Image 1 from page 495](pdf-image://page_495_img_1) + +## Page 496 + +22.3.19 +TCD Transfer Attributes (DMA\_TCDn\_ATTR) +Address: 4000\_8000h base + 1006h offset + (32d × i), where i=0d to 15d +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +SMOD +SSIZE +DMOD +DSIZE +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_ATTR field descriptions +Field +Description +15–11 +SMOD +Source Address Modulo. +0 +Source address modulo feature is disabled +≠0 +This value defines a specific address range specified to be the value after SADDR + SOFF +calculation is performed or the original register value. The setting of this field provides the ability to +implement a circular data queue easily. For data queues requiring power-of-2 size bytes, the queue +should start at a 0-modulo-size address and the SMOD field should be set to the appropriate value +for the queue, freezing the desired number of upper address bits. The value programmed into this +field specifies the number of lower address bits allowed to change. For a circular queue application, +the SOFF is typically set to the transfer size to implement post-increment addressing with the SMOD +function constraining the addresses to a 0-modulo-size range. +10–8 +SSIZE +Source data transfer size +The attempted use of a Reserved encoding causes a configuration error. +000 +8-bit +001 +16-bit +010 +32-bit +011 +Reserved +100 +16-byte +101 +32-byte +110 +Reserved +111 +Reserved +7–3 +DMOD +Destination Address Modulo +See the SMOD definition +2–0 +DSIZE +Destination Data Transfer Size +See the SSIZE definition +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +496 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 496](pdf-image://page_496_img_1) + +## Page 497 + +22.3.20 +TCD Minor Byte Count (Minor Loop Disabled) +(DMA\_TCDn\_NBYTES\_MLNO) +TCD word 2's register definition depends on the status of minor loop mapping. If minor +loop mapping is disabled (CR[EMLM] = 0), TCD word 2 is defined as follows. If minor +loop mapping is enabled, see the TCD\_NBYTES\_MLOFFNO and +TCD\_NBYTES\_MLOFFYES register descriptions for TCD word 2's register definition. +Address: 4000\_8000h base + 1008h offset + (32d × i), where i=0d to 15d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +NBYTES +W +Reset x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x* x* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_NBYTES\_MLNO field descriptions +Field +Description +31–0 +NBYTES +Minor Byte Transfer Count +Number of bytes to be transferred in each service request of the channel. As a channel activates, the +appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until +the minor byte transfer count has transferred. This is an indivisible operation and cannot be halted. +(Although, it may be stalled by using the bandwidth control field, or via preemption.) After the minor count +is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration +count is decremented and restored to the TCD memory. If the major iteration count is completed, +additional processing is performed. +NOTE: An NBYTES value of 0x0000\_0000 is interpreted as a 4 GB transfer. +22.3.21 +TCD Signed Minor Loop Offset (Minor Loop Enabled and +Offset Disabled) (DMA\_TCDn\_NBYTES\_MLOFFNO) +TCD word 2 is defined as follows if: +• Minor loop mapping is enabled (CR[EMLM] = 1) and +• SMLOE = 0 and DMLOE = 0 +If minor loop mapping is enabled and SMLOE or DMLOE is set then refer to the +TCD\_NBYTES\_MLOFFYES register description. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +497 +General Business Information + +![Image 1 from page 497](pdf-image://page_497_img_1) + +## Page 498 + +Address: 4000\_8000h base + 1008h offset + (32d × i), where i=0d to 15d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +SMLOE +DMLOE +NBYTES +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +NBYTES +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_NBYTES\_MLOFFNO field descriptions +Field +Description +31 +SMLOE +Source Minor Loop Offset Enable +Selects whether the minor loop offset is applied to the source address upon minor loop completion. +0 +The minor loop offset is not applied to the SADDR +1 +The minor loop offset is applied to the SADDR +30 +DMLOE +Destination Minor Loop Offset enable +Selects whether the minor loop offset is applied to the destination address upon minor loop completion. +0 +The minor loop offset is not applied to the DADDR +1 +The minor loop offset is applied to the DADDR +29–0 +NBYTES +Minor Byte Transfer Count +Number of bytes to be transferred in each service request of the channel. +As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate +reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation +and cannot be halted; although, it may be stalled by using the bandwidth control field, or via preemption. +After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD +memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration +count is completed, additional processing is performed. +22.3.22 +TCD Signed Minor Loop Offset (Minor Loop and Offset +Enabled) (DMA\_TCDn\_NBYTES\_MLOFFYES) +TCD word 2 is defined as follows if: +• Minor loop mapping is enabled (CR[EMLM] = 1) and +• Minor loop offset enabled (SMLOE or DMLOE = 1) +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +498 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 498](pdf-image://page_498_img_1) + +## Page 499 + +If minor loop mapping is enabled and SMLOE and DMLOE are cleared then refer to the +TCD\_NBYTES\_MLOFFNO register description. +Address: 4000\_8000h base + 1008h offset + (32d × i), where i=0d to 15d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +SMLOE +DMLOE +MLOFF +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +MLOFF +NBYTES +W +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_NBYTES\_MLOFFYES field descriptions +Field +Description +31 +SMLOE +Source Minor Loop Offset Enable +Selects whether the minor loop offset is applied to the source address upon minor loop completion. +0 +The minor loop offset is not applied to the SADDR +1 +The minor loop offset is applied to the SADDR +30 +DMLOE +Destination Minor Loop Offset enable +Selects whether the minor loop offset is applied to the destination address upon minor loop completion. +0 +The minor loop offset is not applied to the DADDR +1 +The minor loop offset is applied to the DADDR +29–10 +MLOFF +If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or +destination address to form the next-state value after the minor loop completes. +9–0 +NBYTES +Minor Byte Transfer Count +Number of bytes to be transferred in each service request of the channel. +As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate +reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation +and cannot be halted. (Although, it may be stalled by using the bandwidth control field, or via preemption.) +After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD +memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration +count is completed, additional processing is performed. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +499 +General Business Information + +![Image 1 from page 499](pdf-image://page_499_img_1) + +## Page 500 + +22.3.23 +TCD Last Source Address Adjustment (DMA\_TCDn\_SLAST) +Address: 4000\_8000h base + 100Ch offset + (32d × i), where i=0d to 15d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +SLAST +W +Reset x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x* x* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_SLAST field descriptions +Field +Description +31–0 +SLAST +Last source Address Adjustment +Adjustment value added to the source address at the completion of the major iteration count. This value +can be applied to restore the source address to the initial value, or adjust the address to reference the +next data structure. +22.3.24 +TCD Destination Address (DMA\_TCDn\_DADDR) +Address: 4000\_8000h base + 1010h offset + (32d × i), where i=0d to 15d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +DADDR +W +Reset x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x* x* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_DADDR field descriptions +Field +Description +31–0 +DADDR +Destination Address +Memory address pointing to the destination data. +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +500 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 500](pdf-image://page_500_img_1) + +## Page 501 + +22.3.25 +TCD Signed Destination Address Offset (DMA\_TCDn\_DOFF) +Address: 4000\_8000h base + 1014h offset + (32d × i), where i=0d to 15d +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +DOFF +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_DOFF field descriptions +Field +Description +15–0 +DOFF +Destination Address Signed offset +Sign-extended offset applied to the current destination address to form the next-state value as each +destination write is completed. +22.3.26 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCDn\_CITER\_ELINKYES) +If TCDn\_CITER[ELINK] is set, the TCDn\_CITER register is defined as follows. +Address: 4000\_8000h base + 1016h offset + (32d × i), where i=0d to 15d +Bit +15 +14 +13 +12 +11 +10 +9 +8 +Read +ELINK +0 +LINKCH +CITER +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +CITER +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_CITER\_ELINKYES field descriptions +Field +Description +15 +ELINK +Enable channel-to-channel linking on minor-loop complete +As the channel completes the minor loop, this flag enables linking to another channel, defined by the +LINKCH field. The link target channel initiates a channel service request via an internal mechanism that +sets the TCDn\_CSR[START] bit of the specified channel. +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +501 +General Business Information + +![Image 1 from page 501](pdf-image://page_501_img_1) + +## Page 502 + +DMA\_TCDn\_CITER\_ELINKYES field descriptions (continued) +Field +Description +If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If +the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel +linking. +NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported. +0 +The channel-to-channel linking is disabled +1 +The channel-to-channel linking is enabled +14–13 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +12–9 +LINKCH +Link Channel Number +If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA +engine initiates a channel service request to the channel defined by these four bits by setting that +channel’s TCDn\_CSR[START] bit. +8–0 +CITER +Current Major Iteration Count +This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. +It is decremented each time the minor loop is completed and updated in the transfer control descriptor +memory. After the major iteration count is exhausted, the channel performs a number of operations (e.g., +final source and destination address calculations), optionally generating an interrupt to signal channel +completion before reloading the CITER field from the beginning iteration count (BITER) field. +NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that +contained in the BITER field. +NOTE: If the channel is configured to execute a single service request, the initial values of BITER and +CITER should be 0x0001. +22.3.27 +TCD Current Minor Loop Link, Major Loop Count (Channel +Linking Disabled) (DMA\_TCDn\_CITER\_ELINKNO) +If TCDn\_CITER[ELINK] is cleared, the TCDn\_CITER register is defined as follows. +Address: 4000\_8000h base + 1016h offset + (32d × i), where i=0d to 15d +Bit +15 +14 +13 +12 +11 +10 +9 +8 +Read +ELINK +CITER +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +CITER +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +502 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 502](pdf-image://page_502_img_1) + +## Page 503 + +DMA\_TCDn\_CITER\_ELINKNO field descriptions +Field +Description +15 +ELINK +Enable channel-to-channel linking on minor-loop complete +As the channel completes the minor loop, this flag enables linking to another channel, defined by the +LINKCH field. The link target channel initiates a channel service request via an internal mechanism that +sets the TCDn\_CSR[START] bit of the specified channel. +If channel linking is disabled, the CITER value is extended to 15 bits in place of a link channel number. If +the major loop is exhausted, this link mechanism is suppressed in favor of the MAJORELINK channel +linking. +NOTE: This bit must be equal to the BITER[ELINK] bit; otherwise, a configuration error is reported. +0 +The channel-to-channel linking is disabled +1 +The channel-to-channel linking is enabled +14–0 +CITER +Current Major Iteration Count +This 9-bit (ELINK = 1) or 15-bit (ELINK = 0) count represents the current major loop count for the channel. +It is decremented each time the minor loop is completed and updated in the transfer control descriptor +memory. After the major iteration count is exhausted, the channel performs a number of operations (e.g., +final source and destination address calculations), optionally generating an interrupt to signal channel +completion before reloading the CITER field from the beginning iteration count (BITER) field. +NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that +contained in the BITER field. +NOTE: If the channel is configured to execute a single service request, the initial values of BITER and +CITER should be 0x0001. +22.3.28 +TCD Last Destination Address Adjustment/Scatter Gather +Address (DMA\_TCDn\_DLASTSGA) +Address: 4000\_8000h base + 1018h offset + (32d × i), where i=0d to 15d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +DLASTSGA +W +Reset x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x* x* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_DLASTSGA field descriptions +Field +Description +31–0 +DLASTSGA +Destination last address adjustment or the memory address for the next transfer control descriptor to be +loaded into this channel (scatter/gather). +If (TCDn\_CSR[ESG] = 0) then +• Adjustment value added to the destination address at the completion of the major iteration count. +This value can apply to restore the destination address to the initial value or adjust the address to +reference the next data structure. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +503 +General Business Information + +![Image 1 from page 503](pdf-image://page_503_img_1) + +## Page 504 + +DMA\_TCDn\_DLASTSGA field descriptions (continued) +Field +Description +else +• This address points to the beginning of a 0-modulo-32-byte region containing the next transfer +control descriptor to be loaded into this channel. This channel reload is performed as the major +iteration count completes. The scatter/gather address must be 0-modulo-32-byte, else a +configuration error is reported. +22.3.29 +TCD Control and Status (DMA\_TCDn\_CSR) +Address: 4000\_8000h base + 101Ch offset + (32d × i), where i=0d to 15d +Bit +15 +14 +13 +12 +11 +10 +9 +8 +Read +BWC +0 +MAJORLINKCH +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +DONE +ACTIVE +MAJORELI +NK +ESG +DREQ +INTHALF +INTMAJOR +START +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_CSR field descriptions +Field +Description +15–14 +BWC +Bandwidth Control +Throttles the amount of bus bandwidth consumed by the eDMA. In general, as the eDMA processes the +minor loop, it continuously generates read/write sequences until the minor count is exhausted. This field +forces the eDMA to stall after the completion of each read/write access to control the bus request +bandwidth seen by the crossbar switch. +NOTE: If the source and destination sizes are equal, this field is ignored between the first and second +transfers and after the last write of each minor loop. This behavior is a side effect of reducing +start-up latency. +00 +No eDMA engine stalls +01 +Reserved +10 +eDMA engine stalls for 4 cycles after each r/w +11 +eDMA engine stalls for 8 cycles after each r/w +13–12 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +11–8 +MAJORLINKCH +Link Channel Number +If (MAJORELINK = 0) then +• No channel-to-channel linking (or chaining) is performed after the major loop counter is exhausted. +else +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +504 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 504](pdf-image://page_504_img_1) + +## Page 505 + +DMA\_TCDn\_CSR field descriptions (continued) +Field +Description +• After the major loop counter is exhausted, the eDMA engine initiates a channel service request at +the channel defined by these six bits by setting that channel’s TCDn\_CSR[START] bit. +7 +DONE +Channel Done +This flag indicates the eDMA has completed the major loop. The eDMA engine sets it as the CITER count +reaches zero; The software clears it, or the hardware when the channel is activated. +NOTE: This bit must be cleared to write the MAJORELINK or ESG bits. +6 +ACTIVE +Channel Active +This flag signals the channel is currently in execution. It is set when channel service begins, and the +eDMA clears it as the minor loop completes or if any error condition is detected. This bit resets to zero. +5 +MAJORELINK +Enable channel-to-channel linking on major loop complete +As the channel completes the major loop, this flag enables the linking to another channel, defined by +MAJORLINKCH. The link target channel initiates a channel service request via an internal mechanism that +sets the TCDn\_CSR[START] bit of the specified channel. +NOTE: To support the dynamic linking coherency model, this field is forced to zero when written to while +the TCDn\_CSR[DONE] bit is set. +0 +The channel-to-channel linking is disabled +1 +The channel-to-channel linking is enabled +4 +ESG +Enable Scatter/Gather Processing +As the channel completes the major loop, this flag enables scatter/gather processing in the current +channel. If enabled, the eDMA engine uses DLASTSGA as a memory pointer to a 0-modulo-32 address +containing a 32-byte data structure loaded as the transfer control descriptor into the local memory. +NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written +to while the TCDn\_CSR[DONE] bit is set. +0 +The current channel’s TCD is normal format. +1 +The current channel’s TCD specifies a scatter gather format. The DLASTSGA field provides a memory +pointer to the next TCD to be loaded into this channel after the major loop completes its execution. +3 +DREQ +Disable Request +If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current +major iteration count reaches zero. +0 +The channel’s ERQ bit is not affected +1 +The channel’s ERQ bit is cleared when the major loop is complete +2 +INTHALF +Enable an interrupt when major counter is half complete. +If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT +register when the current major iteration count reaches the halfway point. Specifically, the comparison +performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is +provided to support double-buffered (aka ping-pong) schemes or other types of data movement where the +processor needs an early indication of the transfer’s progress. If BITER is set, do not use INTHALF. Use +INTMAJOR instead. +0 +The half-point interrupt is disabled +1 +The half-point interrupt is enabled +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +505 +General Business Information + +![Image 1 from page 505](pdf-image://page_505_img_1) + +## Page 506 + +DMA\_TCDn\_CSR field descriptions (continued) +Field +Description +1 +INTMAJOR +Enable an interrupt when major iteration count completes +If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when +the current major iteration count reaches zero. +0 +The end-of-major loop interrupt is disabled +1 +The end-of-major loop interrupt is enabled +0 +START +Channel Start +If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after +the channel begins execution. +0 +The channel is not explicitly started +1 +The channel is explicitly started via a software initiated service request +22.3.30 +TCD Beginning Minor Loop Link, Major Loop Count (Channel +Linking Enabled) (DMA\_TCDn\_BITER\_ELINKYES) +If the TCDn\_BITER[ELINK] bit is set, the TCDn\_BITER register is defined as follows. +Address: 4000\_8000h base + 101Eh offset + (32d × i), where i=0d to 15d +Bit +15 +14 +13 +12 +11 +10 +9 +8 +Read +ELINK +0 +LINKCH +BITER +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +BITER +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_BITER\_ELINKYES field descriptions +Field +Description +15 +ELINK +Enables channel-to-channel linking on minor loop complete +As the channel completes the minor loop, this flag enables the linking to another channel, defined by +BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that +sets the TCDn\_CSR[START] bit of the specified channel. If channel linking disables, the BITER value +extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is +suppressed in favor of the MAJORELINK channel linking. +NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; +otherwise, a configuration error is reported. As the major iteration count is exhausted, the +contents of this field is reloaded into the CITER field. +Table continues on the next page... +Memory map/register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +506 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 506](pdf-image://page_506_img_1) + +## Page 507 + +DMA\_TCDn\_BITER\_ELINKYES field descriptions (continued) +Field +Description +0 +The channel-to-channel linking is disabled +1 +The channel-to-channel linking is enabled +14–13 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +12–9 +LINKCH +Link Channel Number +If channel-to-channel linking is enabled (ELINK = 1), then after the minor loop is exhausted, the eDMA +engine initiates a channel service request at the channel defined by these four bits by setting that +channel’s TCDn\_CSR[START] bit. +NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; +otherwise, a configuration error is reported. As the major iteration count is exhausted, the +contents of this field is reloaded into the CITER field. +8–0 +BITER +Starting Major Iteration Count +As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) +field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents +of this field are reloaded into the CITER field. +NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; +otherwise, a configuration error is reported. As the major iteration count is exhausted, the +contents of this field is reloaded into the CITER field. If the channel is configured to execute a +single service request, the initial values of BITER and CITER should be 0x0001. +22.3.31 +TCD Beginning Minor Loop Link, Major Loop Count (Channel +Linking Disabled) (DMA\_TCDn\_BITER\_ELINKNO) +If the TCDn\_BITER[ELINK] bit is cleared, the TCDn\_BITER register is defined as +follows. +Address: 4000\_8000h base + 101Eh offset + (32d × i), where i=0d to 15d +Bit +15 +14 +13 +12 +11 +10 +9 +8 +Read +ELINK +BITER +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +BITER +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +DMA\_TCDn\_BITER\_ELINKNO field descriptions +Field +Description +15 +ELINK +Enables channel-to-channel linking on minor loop complete +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +507 +General Business Information + +![Image 1 from page 507](pdf-image://page_507_img_1) + +## Page 508 + +DMA\_TCDn\_BITER\_ELINKNO field descriptions (continued) +Field +Description +As the channel completes the minor loop, this flag enables the linking to another channel, defined by +BITER[LINKCH]. The link target channel initiates a channel service request via an internal mechanism that +sets the TCDn\_CSR[START] bit of the specified channel. If channel linking is disabled, the BITER value +extends to 15 bits in place of a link channel number. If the major loop is exhausted, this link mechanism is +suppressed in favor of the MAJORELINK channel linking. +NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; +otherwise, a configuration error is reported. As the major iteration count is exhausted, the +contents of this field is reloaded into the CITER field. +0 +The channel-to-channel linking is disabled +1 +The channel-to-channel linking is enabled +14–0 +BITER +Starting Major Iteration Count +As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) +field must be equal to the value in the CITER field. As the major iteration count is exhausted, the contents +of this field are reloaded into the CITER field. +NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; +otherwise, a configuration error is reported. As the major iteration count is exhausted, the +contents of this field is reloaded into the CITER field. If the channel is configured to execute a +single service request, the initial values of BITER and CITER should be 0x0001. +22.4 +Functional description +22.4.1 +eDMA basic data flow +The basic flow of a data transfer can be partitioned into three segments. +As shown in the following diagram, the first segment involves the channel activation: +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +508 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 508](pdf-image://page_508_img_1) + +## Page 509 + +1 +eDMA Engine +Data Path +eDMA +0 +Program Model/ +64 +Control +n-1 +To/From Crossbar Switch +2 +Channel Arbitration +Address Path +Read Data +Write Data +Address +Read Data +Write Data +Write Address +Internal Peripheral Bus +eDMA Peripheral +Request +eDMA Done +Transfer +Control +Descriptor (TCD) +Figure 22-289. eDMA operation, part 1 +This example uses the assertion of the eDMA peripheral request signal to request service +for channel n. Channel activation via software and the TCDn\_CSR[START] bit follows +the same basic flow as peripheral requests. The eDMA request input signal is registered +internally and then routed through the eDMA engine: first through the control module, +then into the program model and channel arbitration. In the next cycle, the channel +arbitration performs, using the fixed-priority or round-robin algorithm. After arbitration is +complete, the activated channel number is sent through the address path and converted +into the required address to access the local memory for TCDn. Next, the TCD memory +is accessed and the required descriptor read from the local memory and loaded into the +eDMA engine address path channel x or y registers. The TCD memory is 64 bits wide to +minimize the time needed to fetch the activated channel descriptor and load it into the +address path channel x or y registers. +The following diagram illustrates the second part of the basic data flow: +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +509 +General Business Information + +![Image 1 from page 509](pdf-image://page_509_img_1) + +## Page 510 + +1 +eDMA Engine +Data Path +eDMA +0 +Program Model/ +64 +Control +n-1 +To/From Crossbar Switch +2 +Channel Arbitration +Address Path +Read Data +Write Data +Address +Read Data +Write Data +Write Address +eDMA Peripheral +Request +eDMA Done +Transfer +Control +Descriptor (TCD) +Internal Peripheral Bus +Figure 22-290. eDMA operation, part 2 +The modules associated with the data transfer (address path, data path, and control) +sequence through the required source reads and destination writes to perform the actual +data movement. The source reads are initiated and the fetched data is temporarily stored +in the data path block until it is gated onto the internal bus during the destination write. +This source read/destination write processing continues until the minor byte count has +transferred. +After the minor byte count has moved, the final phase of the basic data flow is performed. +In this segment, the address path logic performs the required updates to certain fields in +the appropriate TCD, e.g., SADDR, DADDR, CITER. If the major iteration count is +exhausted, additional operations are performed. These include the final address +adjustments and reloading of the BITER field into the CITER. Assertion of an optional +interrupt request also occurs at this time, as does a possible fetch of a new TCD from +memory using the scatter/gather address pointer included in the descriptor (if scatter/ +gather is enabled). The updates to the TCD memory and the assertion of an interrupt +request are shown in the following diagram. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +510 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 510](pdf-image://page_510_img_1) + +## Page 511 + +1 +eDMA Engine +Data Path +eDMA +0 +Program Model/ +64 +Control +n-1 +To/From Crossbar Switch +2 +Channel Arbitration +Address Path +Read Data +Write Data +Address +Read Data +Write Data +Write Address +eDMA Peripheral +Request +eDMA Done +Transfer +Control +Descriptor (TCD) +Internal Peripheral Bus +Figure 22-291. eDMA operation, part 3 +22.4.2 +Error reporting and handling +Channel errors are reported in the ES register and can be caused by: +• A configuration error, which is an illegal setting in the transfer-control descriptor or +an illegal priority register setting in Fixed-Arbitration mode, or +• An error termination to a bus master read or write cycle +A configuration error is reported when the starting source or destination address, source +or destination offsets, minor loop byte count, or the transfer size represent an inconsistent +state. Each of these possible causes are detailed below: +• The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries. +• The minor loop byte count must be a multiple of the source and destination transfer +sizes. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +511 +General Business Information + +![Image 1 from page 511](pdf-image://page_511_img_1) + +## Page 512 + +• All source reads and destination writes must be configured to the natural boundary of +the programmed transfer size respectively. +• In fixed arbitration mode, a configuration error is caused by any two channel +priorities being equal. All channel priority levels must be unique when fixed +arbitration mode is enabled. +• If a scatter/gather operation is enabled upon channel completion, a configuration +error is reported if the scatter/gather address (DLAST\_SGA) is not aligned on a 32- +byte boundary. +• If minor loop channel linking is enabled upon channel completion, a configuration +error is reported when the link is attempted if the TCDn\_CITER[E\_LINK] bit does +not equal the TCDn\_BITER[E\_LINK] bit. +If enabled, all configuration error conditions, except the scatter/gather and minor-loop +link errors, report as the channel activates and asserts an error interrupt request. A scatter/ +gather configuration error is reported when the scatter/gather operation begins at major +loop completion when properly enabled. A minor loop channel link configuration error is +reported when the link operation is serviced at minor loop completion. +If a system bus read or write is terminated with an error, the data transfer is stopped and +the appropriate bus error flag set. In this case, the state of the channel's transfer control +descriptor is updated by the eDMA engine with the current source address, destination +address, and current iteration count at the point of the fault. When a system bus error +occurs, the channel terminates after the next transfer. Due to pipeline effect, the next +transfer is already in progress when the bus error is received by the eDMA. If a bus error +occurs on the last read prior to beginning the write sequence, the write executes using the +data captured during the bus error. If a bus error occurs on the last write prior to +switching to the next read sequence, the read sequence executes before the channel +terminates due to the destination bus error. +A transfer may be cancelled by software with the CR[CX] bit. When a cancel transfer +request is recognized, the DMA engine stops processing the channel. The current read- +write sequence is allowed to finish. If the cancel occurs on the last read-write sequence of +a major or minor loop, the cancel request is discarded and the channel retires normally. +The error cancel transfer is the same as a cancel transfer except the ES register is updated +with the cancelled channel number and ECX is set. The TCD of a cancelled channel +contains the source and destination addresses of the last transfer saved in the TCD. If the +channel needs to be restarted, you must re-initialize the TCD because the aforementioned +fields no longer represent the original parameters. When a transfer is cancelled by the +error cancel transfer mechanism, the channel number is loaded into DMA\_ES[ERRCHN] +and ECX and VLD are set. In addition, an error interrupt may be generated if enabled. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +512 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 512](pdf-image://page_512_img_1) + +## Page 513 + +The occurrence of any error causes the eDMA engine to stop normal processing of the +active channel immediately (it goes to its error processing states and the transaction to the +system bus still has peipeline effect), and the appropriate channel bit in the eDMA error +register is asserted. At the same time, the details of the error condition are loaded into the +ES register. The major loop complete indicators, setting the transfer control descriptor +DONE flag and the possible assertion of an interrupt request, are not affected when an +error is detected. After the error status has been updated, the eDMA engine continues +operating by servicing the next appropriate channel. A channel that experiences an error +condition is not automatically disabled. If a channel is terminated by an error and then +issues another service request before the error is fixed, that channel executes and +terminates with the same error condition. +22.4.3 +Channel preemption +Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit. +Channel preemption allows the executing channel’s data transfers to temporarily suspend +in favor of starting a higher priority channel. After the preempting channel has completed +all its minor loop data transfers, the preempted channel is restored and resumes +execution. After the restored channel completes one read/write sequence, it is again +eligible for preemption. If any higher priority channel is requesting service, the restored +channel is suspended and the higher priority channel is serviced. Nested preemption, that +is, attempting to preempt a preempting channel, is not supported. After a preempting +channel begins execution, it cannot be preempted. Preemption is available only when +fixed arbitration is selected. +A channel’s ability to preempt another channel can be disabled by setting +DCHPRIn[DPA]. When a channel’s preempt ability is disabled, that channel cannot +suspend a lower priority channel’s data transfer, regardless of the lower priority channel’s +ECP setting. This allows for a pool of low priority, large data-moving channels to be +defined. These low priority channels can be configured to not preempt each other, thus +preventing a low priority channel from consuming the preempt slot normally available to +a true, high priority channel. +22.4.4 +Performance +This section addresses the performance of the eDMA module, focusing on two separate +metrics: +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +513 +General Business Information + +![Image 1 from page 513](pdf-image://page_513_img_1) + +## Page 514 + +• In the traditional data movement context, performance is best expressed as the peak +data transfer rates achieved using the eDMA. In most implementations, this transfer +rate is limited by the speed of the source and destination address spaces. +• In a second context where device-paced movement of single data values to/from +peripherals is dominant, a measure of the requests that can be serviced in a fixed time +is a more relevant metric. In this environment, the speed of the source and destination +address spaces remains important. However, the microarchitecture of the eDMA also +factors significantly into the resulting metric. +22.4.4.1 +Peak transfer rates +The peak transfer rates for several different source and destination transfers are shown in +the following tables. These tables assume: +• Internal SRAM can be accessed with zero wait-states when viewed from the system +bus data phase +• All internal peripheral bus reads require two wait-states, and internal peripheral bus +writes three wait-states, when viewed from the system bus data phase +• All internal peripheral bus accesses are 32-bits in size +This table presents a peak transfer rate comparison. +Table 22-292. eDMA peak transfer rates (Mbytes/sec) +System Speed, Width +Internal SRAM-to- +Internal SRAM +32b internal peripheral bus- +to-Internal SRAM +Internal SRAM-to-32b +internal peripheral bus +66.7 MHz, 32b +133.3 +66.7 +53.3 +83.3 MHz, 32b +166.7 +83.3 +66.7 +100.0 MHz, 32b +200.0 +100.0 +80.0 +133.3 MHz, 32b +266.7 +133.3 +106.7 +150.0 MHz, 32b +300.0 +150.0 +120.0 +Internal-SRAM-to-internal-SRAM transfers occur at the core's datapath width. For all +transfers involving the internal peripheral bus, 32-bit transfer sizes are used. In all cases, +the transfer rate includes the time to read the source plus the time to write the destination. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +514 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 514](pdf-image://page_514_img_1) + +## Page 515 + +22.4.4.2 +Peak request rates +The second performance metric is a measure of the number of DMA requests that can be +serviced in a given amount of time. For this metric, assume that the peripheral request +causes the channel to move a single internal peripheral bus-mapped operand to/from +internal SRAM. The same timing assumptions used in the previous example apply to this +calculation. In particular, this metric also reflects the time required to activate the +channel. +The eDMA design supports the following hardware service request sequence. Note that +the exact timing from Cycle 7 is a function of the response times for the channel's read +and write accesses. In the case of an internal peripheral bus read and internal SRAM +write, the combined data phase time is 4 cycles. For an SRAM read and internal +peripheral bus write, it is 5 cycles. +Table 22-293. Hardware service request process +Cycle +Description +With internal peripheral +bus read and internal +SRAM write +With SRAM read and +internal peripheral bus +write +1 +eDMA peripheral request is asserted. +2 +The eDMA peripheral request is registered locally in the +eDMA module and qualified. TCDn\_CSR[START] bit initiated +requests start at this point with the registering of the user +write to TCDn word 7. +3 +Channel arbitration begins. +4 +Channel arbitration completes. The transfer control descriptor +local memory read is initiated. +5–6 +The first two parts of the activated channel's TCD is read from +the local memory. The memory width to the eDMA engine is +64 bits, so the entire descriptor can be accessed in four +cycles +7 +The first system bus read cycle is initiated, as the third part of +the channel's TCD is read from the local memory. Depending +on the state of the crossbar switch, arbitration at the system +bus may insert an additional cycle of delay here. +8–11 +8–12 +The last part of the TCD is read in. This cycle represents the +first data phase for the read, and the address phase for the +destination write. +12 +13 +This cycle represents the data phase of the last destination +write. +13 +14 +The eDMA engine completes the execution of the inner minor +loop and prepares to write back the required TCDn fields into +the local memory. The TCDn word 7 is read and checked for +channel linking or scatter/gather requests. +14 +15 +The appropriate fields in the first part of the TCDn are written +back into the local memory. +Table continues on the next page... +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +515 +General Business Information + +![Image 1 from page 515](pdf-image://page_515_img_1) + +## Page 516 + +Table 22-293. Hardware service request process (continued) +Cycle +Description +With internal peripheral +bus read and internal +SRAM write +With SRAM read and +internal peripheral bus +write +15 +16 +The fields in the second part of the TCDn are written back into +the local memory. This cycle coincides with the next channel +arbitration cycle start. +16 +17 +The next channel to be activated performs the read of the first +part of its TCD from the local memory. This is equivalent to +Cycle 4 for the first channel's service request. +Assuming zero wait states on the system bus, DMA requests can be processed every 9 +cycles. Assuming an average of the access times associated with internal peripheral bus- +to-SRAM (4 cycles) and SRAM-to-internal peripheral bus (5 cycles), DMA requests can +be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle 4 to Cycle x ++5. The resulting peak request rate, as a function of the system frequency, is shown in the +following table. +Table 22-294. eDMA peak request rate (MReq/sec) +System frequency (MHz) +Request rate +with zero wait states +Request rate +with wait states +66.6 +7.4 +5.8 +83.3 +9.2 +7.2 +100.0 +11.1 +8.7 +133.3 +14.8 +11.6 +150.0 +16.6 +13.0 +A general formula to compute the peak request rate with overlapping requests is: +PEAKreq = freq / [ entry + (1 + read\_ws) + (1 + write\_ws) + exit ] +where: +Table 22-295. Peak request formula operands +Operand +Description +PEAKreq +Peak request rate +freq +System frequency +entry +Channel startup (4 cycles) +read\_ws +Wait states seen during the system bus read data phase +write\_ws +Wait states seen during the system bus write data phase +exit +Channel shutdown (3 cycles) +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +516 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 516](pdf-image://page_516_img_1) + +## Page 517 + +22.4.4.3 +eDMA performance example +Consider a system with the following characteristics: +• Internal SRAM can be accessed with one wait-state when viewed from the system +bus data phase +• All internal peripheral bus reads require two wait-states, and internal peripheral bus +writes three wait-states viewed from the system bus data phase +• System operates at 150 MHz +For an SRAM to internal peripheral bus transfer, +PEAKreq = 150 MHz / [ 4 + (1 + 1) + (1 + 3) + 3 ] cycles = 11.5 Mreq/sec +For an internal peripheral bus to SRAM transfer, +PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec +Assuming an even distribution of the two transfer types, the average peak request rate +would be: +PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec +The minimum number of cycles to perform a single read/write, zero wait states on the +system bus, from a cold start where no channel is executing and eDMA is idle are: +• 11 cycles for a software, that is, a TCDn\_CSR[START] bit, request +• 12 cycles for a hardware, that is, an eDMA peripheral request signal, request +Two cycles account for the arbitration pipeline and one extra cycle on the hardware +request resulting from the internal registering of the eDMA peripheral request signals. +For the peak request rate calculations above, the arbitration and request registering is +absorbed in or overlaps the previous executing channel. +Note +When channel linking or scatter/gather is enabled, a two cycle +delay is imposed on the next channel selection and startup. This +allows the link channel or the scatter/gather channel to be +eligible and considered in the arbitration pool for next channel +selection. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +517 +General Business Information + +![Image 1 from page 517](pdf-image://page_517_img_1) + +## Page 518 + +22.5 +Initialization/application information +The following sections discuss initialization of the eDMA and programming +considerations. +22.5.1 +eDMA initialization +To initialize the eDMA: +1. Write to the CR if a configuration other than the default is desired. +2. Write the channel priority levels to the DCHPRIn registers if a configuration other +than the default is desired. +3. Enable error interrupts in the EEI register if so desired. +4. Write the 32-byte TCD for each channel that may request service. +5. Enable any hardware service requests via the ERQ register. +6. Request channel service via either: +• Software: setting the TCDn\_CSR[START] +• Hardware: slave device asserting its eDMA peripheral request signal +After any channel requests service, a channel is selected for execution based on the +arbitration and priority levels written into the programmer's model. The eDMA engine +reads the entire TCD, including the TCD control and status fields, as shown in the +following table, for the selected channel into its internal address path module. +As the TCD is read, the first transfer is initiated on the internal bus, unless a +configuration error is detected. Transfers from the source, as defined by TCDn\_SADDR, +to the destination, as defined by TCDn\_DADDR, continue until the number of bytes +specified by TCDn\_NBYTES are transferred. +When the transfer is complete, the eDMA engine's local TCDn\_SADDR, +TCDn\_DADDR, and TCDn\_CITER are written back to the main TCD memory and any +minor loop channel linking is performed, if enabled. If the major loop is exhausted, +further post processing executes, such as interrupts, major loop channel linking, and +scatter/gather operations, if enabled. +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +518 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 518](pdf-image://page_518_img_1) + +## Page 519 + +Table 22-296. TCD Control and Status fields +TCDn\_CSR field +name +Description +START +Control bit to start channel explicitly when using a software initiated DMA service (Automatically +cleared by hardware) +ACTIVE +Status bit indicating the channel is currently in execution +DONE +Status bit indicating major loop completion (cleared by software when using a software initiated +DMA service) +D\_REQ +Control bit to disable DMA request at end of major loop completion when using a hardware initiated +DMA service +BWC +Control bits for throttling bandwidth control of a channel +E\_SG +Control bit to enable scatter-gather feature +INT\_HALF +Control bit to enable interrupt when major loop is half complete +INT\_MAJ +Control bit to enable interrupt when major loop completes +The following figure shows how each DMA request initiates one minor-loop transfer, or +iteration, without CPU intervention. DMA arbitration can occur after each minor loop, +and one level of minor loop DMA preemption is allowed. The number of minor loops in +a major loop is specified by the beginning iteration count (BITER). +DMA request +DMA request +DMA request +Minor loop +Minor loop +Minor loop +Major loop +Current major +loop iteration +count (CITER) +3 +2 +1 +Source or destination memory +Figure 22-292. Example of multiple loop iterations +The following figure lists the memory array terms and how the TCD settings interrelate. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +519 +General Business Information + +![Image 1 from page 519](pdf-image://page_519_img_1) + +## Page 520 + +xADDR: (Starting address) +xLAST: Number of bytes added to +current address after major loop +(typically used to loop back) +Minor loop +(NBYTES in +minor loop, +often the same +value as xSIZE) +Minor loop +Last minor loop +Offset (xOFF): number of bytes added to +current address after each transfer +(often the same value as xSIZE) +Each DMA source (S) and +destination (D) has its own: +Address (xADDR) +Size (xSIZE) +Offset (xOFF) +Modulo (xMOD) +Last Address Adjustment (xLAST) +where x = S or D +Peripheral queues typically +have size and offset equal +to NBYTES. +xSIZE: (size of one +data transfer) +Figure 22-293. Memory array terms +22.5.2 +Programming errors +The eDMA performs various tests on the transfer control descriptor to verify consistency +in the descriptor data. Most programming errors are reported on a per channel basis with +the exception of channel priority error (ES[CPE]). +For all error types other than channel priority error, the channel number causing the error +is recorded in the ES register. If the error source is not removed before the next activation +of the problem channel, the error is detected and recorded again. +If priority levels are not unique, when any channel requests service, a channel priority +error is reported. The highest channel priority with an active request is selected, but the +lowest numbered channel with that priority is selected by arbitration and executed by the +eDMA engine. The hardware service request handshake signals, error interrupts, and +error reporting is associated with the selected channel. +22.5.3 +Arbitration mode considerations +22.5.3.1 +Fixed channel arbitration +In this mode, the channel service request from the highest priority channel is selected to +execute. +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +520 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 520](pdf-image://page_520_img_1) + +## Page 521 + +22.5.3.2 +Round-robin channel arbitration +Channels are serviced starting with the highest channel number and rotating through to +the lowest channel number without regard to the channel priority levels. +22.5.4 +Performing DMA transfers (examples) +22.5.4.1 +Single request +To perform a simple transfer of n bytes of data with one activation, set the major loop to +one (TCDn\_CITER = TCDn\_BITER = 1). The data transfer begins after the channel +service request is acknowledged and the channel is selected to execute. After the transfer +is complete, the TCDn\_CSR[DONE] bit is set and an interrupt generates if properly +enabled. +For example, the following TCD entry is configured to transfer 16 bytes of data. The +eDMA is programmed for one iteration of the major loop transferring 16 bytes per +iteration. The source memory has a byte wide memory port located at 0x1000. The +destination memory has a 32-bit port located at 0x2000. The address offsets are +programmed in increments to match the transfer size: one byte for the source and four +bytes for the destination. The final source and destination addresses are adjusted to return +to their beginning values. +TCDn\_CITER = TCDn\_BITER = 1 +TCDn\_NBYTES = 16 +TCDn\_SADDR = 0x1000 +TCDn\_SOFF = 1 +TCDn\_ATTR[SSIZE] = 0 +TCDn\_SLAST = -16 +TCDn\_DADDR = 0x2000 +TCDn\_DOFF = 4 +TCDn\_ATTR[DSIZE] = 2 +TCDn\_DLAST\_SGA= –16 +TCDn\_CSR[INT\_MAJ] = 1 +TCDn\_CSR[START] = 1 (Should be written last after all other fields have been initialized) +All other TCDn fields = 0 +This generates the following event sequence: +1. User write to the TCDn_CSR[START] bit requests channel service. +2. The channel is selected by arbitration for servicing. +3. eDMA engine writes: TCDn\_CSR[DONE] = 0, TCDn\_CSR[START] = 0, +TCDn\_CSR[ACTIVE] = 1. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +521 +General Business Information + +![Image 1 from page 521](pdf-image://page_521_img_1) + +## Page 522 + +4. eDMA engine reads: channel TCD data from local memory to internal register file. +5. The source-to-destination transfers are executed as follows: +a. Read byte from location 0x1000, read byte from location 0x1001, read byte from +0x1002, read byte from 0x1003. +b. Write 32-bits to location 0x2000 → first iteration of the minor loop. +c. Read byte from location 0x1004, read byte from location 0x1005, read byte from +0x1006, read byte from 0x1007. +d. Write 32-bits to location 0x2004 → second iteration of the minor loop. +e. Read byte from location 0x1008, read byte from location 0x1009, read byte from +0x100A, read byte from 0x100B. +f. Write 32-bits to location 0x2008 → third iteration of the minor loop. +g. Read byte from location 0x100C, read byte from location 0x100D, read byte +from 0x100E, read byte from 0x100F. +h. Write 32-bits to location 0x200C → last iteration of the minor loop → major loop +complete. +6. The eDMA engine writes: TCDn\_SADDR = 0x1000, TCDn\_DADDR = 0x2000, +TCDn\_CITER = 1 (TCDn\_BITER). +7. The eDMA engine writes: TCDn\_CSR[ACTIVE] = 0, TCDn\_CSR[DONE] = 1, +INT[n] = 1. +8. The channel retires and the eDMA goes idle or services the next channel. +22.5.4.2 +Multiple requests +The following example transfers 32 bytes via two hardware requests, but is otherwise the +same as the previous example. The only fields that change are the major loop iteration +count and the final address offsets. The eDMA is programmed for two iterations of the +major loop transferring 16 bytes per iteration. After the channel's hardware requests are +enabled in the ERQ register, the slave device initiates channel service requests. +TCDn\_CITER = TCDn\_BITER = 2 +TCDn\_SLAST = –32 +TCDn\_DLAST\_SGA = –32 +This would generate the following sequence of events: +1. First hardware, that is, eDMA peripheral, request for channel service. +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +522 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 522](pdf-image://page_522_img_1) + +## Page 523 + +2. The channel is selected by arbitration for servicing. +3. eDMA engine writes: TCDn\_CSR[DONE] = 0, TCDn\_CSR[START] = 0, +TCDn\_CSR[ACTIVE] = 1. +4. eDMA engine reads: channel TCDn data from local memory to internal register file. +5. The source to destination transfers are executed as follows: +a. Read byte from location 0x1000, read byte from location 0x1001, read byte from +0x1002, read byte from 0x1003. +b. Write 32-bits to location 0x2000 → first iteration of the minor loop. +c. Read byte from location 0x1004, read byte from location 0x1005, read byte from +0x1006, read byte from 0x1007. +d. Write 32-bits to location 0x2004 → second iteration of the minor loop. +e. Read byte from location 0x1008, read byte from location 0x1009, read byte from +0x100A, read byte from 0x100B. +f. Write 32-bits to location 0x2008 → third iteration of the minor loop. +g. Read byte from location 0x100C, read byte from location 0x100D, read byte +from 0x100E, read byte from 0x100F. +h. Write 32-bits to location 0x200C → last iteration of the minor loop. +6. eDMA engine writes: TCDn\_SADDR = 0x1010, TCDn\_DADDR = 0x2010, +TCDn\_CITER = 1. +7. eDMA engine writes: TCDn\_CSR[ACTIVE] = 0. +8. The channel retires → one iteration of the major loop. The eDMA goes idle or +services the next channel. +9. Second hardware, that is, eDMA peripheral, requests channel service. +10. The channel is selected by arbitration for servicing. +11. eDMA engine writes: TCDn_CSR[DONE] = 0, TCDn_CSR[START] = 0, +TCDn\_CSR[ACTIVE] = 1. +12. eDMA engine reads: channel TCD data from local memory to internal register file. +13. The source to destination transfers are executed as follows: +a. Read byte from location 0x1010, read byte from location 0x1011, read byte from +0x1012, read byte from 0x1013. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +523 +General Business Information + +![Image 1 from page 523](pdf-image://page_523_img_1) + +## Page 524 + +b. Write 32-bits to location 0x2010 → first iteration of the minor loop. +c. Read byte from location 0x1014, read byte from location 0x1015, read byte from +0x1016, read byte from 0x1017. +d. Write 32-bits to location 0x2014 → second iteration of the minor loop. +e. Read byte from location 0x1018, read byte from location 0x1019, read byte from +0x101A, read byte from 0x101B. +f. Write 32-bits to location 0x2018 → third iteration of the minor loop. +g. Read byte from location 0x101C, read byte from location 0x101D, read byte +from 0x101E, read byte from 0x101F. +h. Write 32-bits to location 0x201C → last iteration of the minor loop → major loop +complete. +14. eDMA engine writes: TCDn\_SADDR = 0x1000, TCDn\_DADDR = 0x2000, +TCDn\_CITER = 2 (TCDn\_BITER). +15. eDMA engine writes: TCDn\_CSR[ACTIVE] = 0, TCDn\_CSR[DONE] = 1, INT[n] = +1. +16. The channel retires → major loop complete. The eDMA goes idle or services the next +channel. +22.5.4.3 +Using the modulo feature +The modulo feature of the eDMA provides the ability to implement a circular data queue +in which the size of the queue is a power of 2. MOD is a 5-bit field for the source and +destination in the TCD, and it specifies which lower address bits increment from their +original value after the address+offset calculation. All upper address bits remain the same +as in the original value. A setting of 0 for this field disables the modulo feature. +The following table shows how the transfer addresses are specified based on the setting +of the MOD field. Here a circular buffer is created where the address wraps to the +original value while the 28 upper address bits (0x1234567x) retain their original value. In +this example the source address is set to 0x12345670, the offset is set to 4 bytes and the +MOD field is set to 4, allowing for a 24 byte (16-byte) size queue. +Table 22-297. Modulo example +Transfer Number +Address +1 +0x12345670 +Table continues on the next page... +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +524 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 524](pdf-image://page_524_img_1) + +## Page 525 + +Table 22-297. Modulo example (continued) +Transfer Number +Address +2 +0x12345674 +3 +0x12345678 +4 +0x1234567C +5 +0x12345670 +6 +0x12345674 +22.5.5 +Monitoring transfer descriptor status +22.5.5.1 +Testing for minor loop completion +There are two methods to test for minor loop completion when using software initiated +service requests. The first is to read the TCDn\_CITER field and test for a change. +Another method may be extracted from the sequence shown below. The second method is +to test the TCDn\_CSR[START] bit and the TCDn\_CSR[ACTIVE] bit. The minor-loop- +complete condition is indicated by both bits reading zero after the TCDn\_CSR[START] +was set. Polling the TCDn\_CSR[ACTIVE] bit may be inconclusive, because the active +status may be missed if the channel execution is short in duration. +The TCD status bits execute the following sequence for a software activated channel: +Stage +TCDn\_CSR bits +State +START +ACTIVE +DONE +1 +1 +0 +0 +Channel service request via software +2 +0 +1 +0 +Channel is executing +3a +0 +0 +0 +Channel has completed the minor loop and is idle +3b +0 +0 +1 +Channel has completed the major loop and is idle +The best method to test for minor-loop completion when using hardware, that is, +peripheral, initiated service requests is to read the TCDn\_CITER field and test for a +change. The hardware request and acknowledge handshake signals are not visible in the +programmer's model. +The TCD status bits execute the following sequence for a hardware-activated channel: +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +525 +General Business Information + +![Image 1 from page 525](pdf-image://page_525_img_1) + +## Page 526 + +Stage +TCDn\_CSR bits +State +START +ACTIVE +DONE +1 +0 +0 +0 +Channel service request via hardware (peripheral +request asserted) +2 +0 +1 +0 +Channel is executing +3a +0 +0 +0 +Channel has completed the minor loop and is idle +3b +0 +0 +1 +Channel has completed the major loop and is idle +For both activation types, the major-loop-complete status is explicitly indicated via the +TCDn\_CSR[DONE] bit. +The TCDn\_CSR[START] bit is cleared automatically when the channel begins execution +regardless of how the channel activates. +22.5.5.2 +Reading the transfer descriptors of active channels +The eDMA reads back the true TCDn\_SADDR, TCDn\_DADDR, and TCDn\_NBYTES +values if read while a channel executes. The true values of the SADDR, DADDR, and +NBYTES are the values the eDMA engine currently uses in its internal register file and +not the values in the TCD local memory for that channel. The addresses, SADDR and +DADDR, and NBYTES, which decrement to zero as the transfer progresses, can give an +indication of the progress of the transfer. All other values are read back from the TCD +local memory. +22.5.5.3 +Checking channel preemption status +Preemption is available only when fixed arbitration is selected as the channel arbitration +mode. A preemptive situation is one in which a preempt-enabled channel runs and a +higher priority request becomes active. When the eDMA engine is not operating in fixed +channel arbitration mode, the determination of the actively running relative priority +outstanding requests become undefined. Channel priorities are treated as equal, that is, +constantly rotating, when Round-Robin Arbitration mode is selected. +The TCDn\_CSR[ACTIVE] bit for the preempted channel remains asserted throughout +the preemption. The preempted channel is temporarily suspended while the preempting +channel executes one major loop iteration. If two TCDn\_CSR[ACTIVE] bits are set +simultaneously in the global TCD map, a higher priority channel is actively preempting a +lower priority channel. +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +526 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 526](pdf-image://page_526_img_1) + +## Page 527 + +22.5.6 +Channel Linking +Channel linking (or chaining) is a mechanism where one channel sets the +TCDn\_CSR[START] bit of another channel (or itself), therefore initiating a service +request for that channel. When properly enabled, the EDMA engine automatically +performs this operation at the major or minor loop completion. +The minor loop channel linking occurs at the completion of the minor loop (or one +iteration of the major loop). The TCDn\_CITER[E\_LINK] field determines whether a +minor loop link is requested. When enabled, the channel link is made after each iteration +of the major loop except for the last. When the major loop is exhausted, only the major +loop channel link fields are used to determine if a channel link should be made. For +example, the initial fields of: +TCDn\_CITER[E\_LINK] = 1 +TCDn\_CITER[LINKCH] = 0xC +TCDn\_CITER[CITER] value = 0x4 +TCDn\_CSR[MAJOR\_E\_LINK] = 1 +TCDn\_CSR[MAJOR\_LINKCH] = 0x7 +executes as: +1. Minor loop done → set TCD12_CSR[START] bit +2. Minor loop done → set TCD12\_CSR[START] bit +3. Minor loop done → set TCD12\_CSR[START] bit +4. Minor loop done, major loop done→ set TCD7\_CSR[START] bit +When minor loop linking is enabled (TCDn\_CITER[E\_LINK] = 1), the +TCDn\_CITER[CITER] field uses a nine bit vector to form the current iteration count. +When minor loop linking is disabled (TCDn\_CITER[E\_LINK] = 0), the +TCDn\_CITER[CITER] field uses a 15-bit vector to form the current iteration count. The +bits associated with the TCDn\_CITER[LINKCH] field are concatenated onto the CITER +value to increase the range of the CITER. +Note +The TCDn\_CITER[E\_LINK] bit and the +TCDn\_BITER[E\_LINK] bit must equal or a configuration error +is reported. The CITER and BITER vector widths must be +equal to calculate the major loop, half-way done interrupt point. +The following table summarizes how a DMA channel can link to another DMA channel, +i.e, use another channel's TCD, at the end of a loop. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +527 +General Business Information + +![Image 1 from page 527](pdf-image://page_527_img_1) + +## Page 528 + +Table 22-298. Channel Linking Parameters +Desired Link +Behavior +TCD Control Field Name +Description +Link at end of +Minor Loop +CITER[E\_LINK] +Enable channel-to-channel linking on minor loop completion (current +iteration) +CITER[LINKCH] +Link channel number when linking at end of minor loop (current iteration) +Link at end of +Major Loop +CSR[MAJOR\_E\_LINK] +Enable channel-to-channel linking on major loop completion +CSR[MAJOR\_LINKCH] +Link channel number when linking at end of major loop +22.5.7 +Dynamic programming +22.5.7.1 +Dynamically changing the channel priority +The following two options are recommended for dynamically changing channel priority +levels: +1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities, +then switch back to Fixed Arbitration mode, +2. Disable all the channels, change the channel priorities, then enable the appropriate +channels. +22.5.7.2 +Dynamic channel linking +Dynamic channel linking is the process of setting the TCD.major.e\_link bit during +channel execution. This bit is read from the TCD local memory at the end of channel +execution, thus allowing the user to enable the feature during channel execution. +Because the user is allowed to change the configuration during execution, a coherency +model is needed. Consider the scenario where the user attempts to execute a dynamic +channel link by enabling the TCD.major.e\_link bit at the same time the eDMA engine is +retiring the channel. The TCD.major.e\_link would be set in the programmer’s model, but +it would be unclear whether the actual link was made before the channel retired. +The following coherency model is recommended when executing a dynamic channel link +request. +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +528 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 528](pdf-image://page_528_img_1) + +## Page 529 + +Step +Action +1 +Write 1b to the TCD.major.e\_link bit. +2 +Read back the TCD.major.e\_link bit. +3 +Test the TCD.major.e\_link request status: +• If TCD.major.e\_link = 1b, the dynamic link attempt was +successful. +• If TCD.major.e\_link = 0b, the attempted dynamic link +did not succeed (the channel was already retiring). +For this request, the TCD local memory controller forces the TCD.major.e\_link bit to +zero on any writes to a channel’s TCD.word7 after that channel’s TCD.done bit is set, +indicating the major loop is complete. +NOTE +The user must clear the TCD.done bit before writing the +TCD.major.e\_link bit. The TCD.done bit is cleared +automatically by the eDMA engine after a channel begins +execution. +22.5.7.3 +Dynamic scatter/gather +Scatter/gather is the process of automatically loading a new TCD into a channel. It allows +a DMA channel to use multiple TCDs; this enables a DMA channel to scatter the DMA +data to multiple destinations or gather it from multiple sources.When scatter/gather is +enabled and the channel has finished its major loop, a new TCD is fetched from system +memory and loaded into that channel’s descriptor location in eDMA programmer’s +model, thus replacing the current descriptor. +Because the user is allowed to change the configuration during execution, a coherency +model is needed. Consider the scenario where the user attempts to execute a dynamic +scatter/gather operation by enabling the TCD.e\_sg bit at the same time the eDMA engine +is retiring the channel. The TCD.e\_sg would be set in the programmer’s model, but it +would be unclear whether the actual scatter/gather request was honored before the +channel retired. +Two methods for this coherency model are shown in the following subsections. Method 1 +has the advantage of reading the major.linkch field and the e\_sg bit with a single read. +For both dynamic channel linking and scatter/gather requests, the TCD local memory +controller forces the TCD.major.e\_link and TCD.e\_sg bits to zero on any writes to a +channel’s TCD.word7 if that channel’s TCD.done bit is set indicating the major loop is +complete. +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +529 +General Business Information + +![Image 1 from page 529](pdf-image://page_529_img_1) + +## Page 530 + +NOTE +The user must clear the TCD.done bit before writing the +TCD.major.e\_link or TCD.e\_sg bits. The TCD.done bit is +cleared automatically by the eDMA engine after a channel +begins execution. +22.5.7.3.1 +Method 1 (channel not using major loop channel linking) +For a channel not using major loop channel linking, the coherency model described here +may be used for a dynamic scatter/gather request. +When the TCD.major.e\_link bit is zero, the TCD.major.linkch field is not used by the +eDMA. In this case, the TCD.major.linkch bits may be used for other purposes. This +method uses the TCD.major.linkch field as a TCD indentification (ID). +1. When the descriptors are built, write a unique TCD ID in the TCD.major.linkch field +for each TCD associated with a channel using dynamic scatter/gather. +2. Write 1b to the TCD.d\_req bit. +Should a dynamic scatter/gather attempt fail, setting the TCD.d\_req bit will prevent a +future hardware activation of this channel. This stops the channel from executing +with a destination address (daddr) that was calculated using a scatter/gather address +(written in the next step) instead of a dlast final offest value. +3. Write the TCD.dlast\_sga field with the scatter/gather address. +4. Write 1b to the TCD.e\_sg bit. +5. Read back the 16 bit TCD control/status field. +6. Test the TCD.e\_sg request status and TCD.major.linkch value: +If e\_sg = 1b, the dynamic link attempt was successful. +If e\_sg = 0b and the major.linkch (ID) did not change, the attempted dynamic link +did not succeed (the channel was already retiring). +If e\_sg = 0b and the major.linkch (ID) changed, the dynamic link attempt was +successful (the new TCD’s e\_sg value cleared the e\_sg bit). +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +530 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 530](pdf-image://page_530_img_1) + +## Page 531 + +22.5.7.3.2 +Method 2 (channel using major loop channel linking) +For a channel using major loop channel linking, the coherency model described here may +be used for a dynamic scatter/gather request. This method uses the TCD.dlast\_sga field as +a TCD indentification (ID). +1. Write 1b to the TCD.d_req bit. +Should a dynamic scatter/gather attempt fail, setting the d\_req bit will prevent a +future hardware activation of this channel. This stops the channel from executing +with a destination address (daddr) that was calculated using a scatter/gather address +(written in the next step) instead of a dlast final offest value. +2. Write theTCD.dlast\_sga field with the scatter/gather address. +3. Write 1b to the TCD.e\_sg bit. +4. Read back the TCD.e\_sg bit. +5. Test the TCD.e\_sg request status: +If e\_sg = 1b, the dynamic link attempt was successful. +If e\_sg = 0b, read the 32 bit TCD dlast\_sga field. +If e\_sg = 0b and the dlast\_sga did not change, the attempted dynamic link did not +succeed (the channel was already retiring). +If e\_sg = 0b and the dlast\_sga changed, the dynamic link attempt was successful (the +new TCD’s e\_sg value cleared the e\_sg bit). +Chapter 22 Direct Memory Access Controller (eDMA) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +531 +General Business Information + +![Image 1 from page 531](pdf-image://page_531_img_1) + +## Page 532 + +Initialization/application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +532 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 532](pdf-image://page_532_img_1) + +## Page 533 + +Chapter 23 +External Watchdog Monitor (EWM) +23.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The watchdog is generally used to monitor the flow and execution of embedded software +within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an +internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET +pin to reset external devices/circuits. The overflow of the watchdog counter must not +occur if the software code works well and services the watchdog to re-start the actual +counter. +For safety, a redundant watchdog system, External Watchdog Monitor (EWM), is +designed to monitor external circuits, as well as the MCU software flow. This provides a +back-up mechanism to the internal watchdog that resets the MCU's CPU and peripherals. +The EWM differs from the internal watchdog in that it does not reset the MCU's CPU +and peripherals. The EWM if allowed to time-out, provides an independent EWM\_out +pin that when asserted resets or places an external circuit into a safe mode. The CPU +resets the EWM counter that is logically ANDed with an external digital input pin. This +pin allows an external circuit to influence the reset\_out signal. +23.1.1 +Features +Features of EWM module include: +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +533 +General Business Information + +![Image 1 from page 533](pdf-image://page_533_img_1) + +## Page 534 + +• Independent LPO clock source +• Programmable time-out period specified in terms of number of EWM LPO clock +cycles. +• Windowed refresh option +• Provides robust check that program flow is faster than expected. +• Programmable window. +• Refresh outside window leads to assertion of EWM\_out. +• Robust refresh mechanism +• Write values of 0xB4 and 0x2C to EWM Refresh Register within 15 +(EWM\_service\_time) peripheral bus clock cycles. +• One output port, EWM\_out, when asserted is used to reset or place the external +circuit into safe mode. +• One Input port, EWM\_in, allows an external circuit to control the EWM\_out signal. +23.1.2 +Modes of Operation +This section describes the module's operating modes. +23.1.2.1 +Stop Mode +When the EWM is in stop mode, the CPU services to the EWM cannot occur. On entry to +stop mode, the EWM’s counter freezes. +There are two possible ways to exit from Stop mode: +• On exit from stop mode through a reset, the EWM remains disabled. +• On exit from stop mode by an interrupt, the EWM is re-enabled, and the counter +continues to be clocked from the same value prior to entry to stop mode. +Note the following if the EWM enters the stop mode during CPU service mechanism: At +the exit from stop mode by an interrupt, refresh mechanism state machine starts from the +previous state which means, if first service command is written correctly and EWM +enters the stop mode immediately, the next command has to be written within the next 15 +(EWM\_service\_time) peripheral bus clocks after exiting from stop mode. User must mask +all interrupts prior to executing EWM service instructions. +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +534 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 534](pdf-image://page_534_img_1) + +## Page 535 + +23.1.2.2 +Wait Mode +The EWM module treats the stop and wait modes as the same. EWM functionality +remains the same in both of these modes. +23.1.2.3 +Debug Mode +Entry to debug mode has no effect on the EWM. +• If the EWM is enabled prior to entry of debug mode, it remains enabled. +• If the EWM is disabled prior to entry of debug mode, it remains disabled. +23.1.3 +Block Diagram +This figure shows the EWM block diagram. +Clock Gating +Cell +EWM\_out +EWM Out +Logic +EWM\_out +OR +Low Power +Clock +Enable +Counter Overflow +CPU Reset +Reset to Counter +EWM refresh +EWM enable +Counter >Compare High +Counter < Compare Low +AND +((EWM\_in ^ assert\_in) || +~EWM\_in\_enable) +Compare High > Counter > Compare Low +1 +1 +Figure 23-1. EWM Block Diagram +Chapter 23 External Watchdog Monitor (EWM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +535 +General Business Information + +![Image 1 from page 535](pdf-image://page_535_img_1) + +## Page 536 + +23.2 +EWM Signal Descriptions +The EWM has two external signals, as shown in the following table. +Table 23-1. EWM Signal Descriptions +Signal +Description +I/O +EWM\_in +EWM input for safety status of external safety circuits. The polarity of +EWM\_in is programmable using the EWM\_CTRL[ASSIN] bit. The default +polarity is active-low. +I +EWM\_out +EWM reset out signal +O +23.3 +Memory Map/Register Definition +This section contains the module memory map and registers. +EWM memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4006\_1000 +Control Register (EWM\_CTRL) +8 +R/W +000h +23.3.1/536 +4006\_1001 +Service Register (EWM\_SERV) +8 +W +(always +reads 0) +000h +23.3.2/537 +4006\_1002 +Compare Low Register (EWM\_CMPL) +8 +R/W +000h +23.3.3/537 +4006\_1003 +Compare High Register (EWM\_CMPH) +8 +R/W +FFFFh +23.3.4/538 +4006\_1005 +Clock Prescaler Register (EWM\_CLKPRESCALER) +8 +R/W +000h +23.3.5/539 +23.3.1 +Control Register (EWM\_CTRL) +The CTRL register is cleared by any reset. +NOTE +INEN, ASSIN and EWMEN bits can be written once after a +CPU reset. Modifying these bits more than once, generates a +bus transfer error. +Address: 4006\_1000h base + 0h offset = 4006\_1000h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +INTEN +INEN +ASSIN +EWMEN +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +EWM Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +536 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 536](pdf-image://page_536_img_1) + +## Page 537 + +EWM\_CTRL field descriptions +Field +Description +7–4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3 +INTEN +Interrupt Enable. +This bit when set and EWM\_out is asserted, an interrupt request is generated. To de-assert interrupt +request, user should clear this bit by writing 0. +2 +INEN +Input Enable. +This bit when set, enables the EWM\_in port. +1 +ASSIN +EWM\_in's Assertion State Select. +Default assert state of the EWM\_in signal is logic zero. Setting ASSIN bit inverts the assert state to a logic +one. +0 +EWMEN +EWM enable. +This bit when set, enables the EWM module. This resets the EWM counter to zero and deasserts the +EWM\_out signal. Clearing EWMEN bit disables the EWM, and therefore it cannot be enabled until a reset +occurs, due to the write-once nature of this bit. +23.3.2 +Service Register (EWM\_SERV) +The SERV register provides the interface from the CPU to the EWM module. It is write- +only and reads of this register return zero. +Address: 4006\_1000h base + 1h offset = 4006\_1001h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +Write +SERVICE +Reset +0 +0 +0 +0 +0 +0 +0 +0 +EWM\_SERV field descriptions +Field +Description +7–0 +SERVICE +The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte +of 0xB4, followed by a second data byte of 0x2C. The EWM service is illegal if either of the following +conditions is true. +• The first or second data byte is not written correctly. +• The second data byte is not written within a fixed number of peripheral bus cycles of the first data +byte. This fixed number of cycles is called EWM\_service\_time. +23.3.3 +Compare Low Register (EWM\_CMPL) +The CMPL register is reset to zero after a CPU reset. This provides no minimum time for +the CPU to service the EWM counter. +Chapter 23 External Watchdog Monitor (EWM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +537 +General Business Information + +![Image 1 from page 537](pdf-image://page_537_img_1) + +## Page 538 + +NOTE +This register can be written only once after a CPU reset. +Writing this register more than once generates a bus transfer +error. +Address: 4006\_1000h base + 2h offset = 4006\_1002h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +COMPAREL +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +EWM\_CMPL field descriptions +Field +Description +7–0 +COMPAREL +To prevent runaway code from changing this field, software should write to this field after a CPU reset +even if the (default) minimum service time is required. +23.3.4 +Compare High Register (EWM\_CMPH) +The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum of 256 +clocks time, for the CPU to service the EWM counter. +NOTE +This register can be written only once after a CPU reset. +Writing this register more than once generates a bus transfer +error. +NOTE +The valid values for CMPH are up to 0xFE because the EWM +counter never expires when CMPH = 0xFF. The expiration +happens only if EWM counter is greater than CMPH. +Address: 4006\_1000h base + 3h offset = 4006\_1003h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +COMPAREH +Write +Reset +1 +1 +1 +1 +1 +1 +1 +1 +EWM\_CMPH field descriptions +Field +Description +7–0 +COMPAREH +To prevent runaway code from changing this field, software should write to this field after a CPU reset +even if the (default) maximum service time is required. +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +538 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 538](pdf-image://page_538_img_1) + +## Page 539 + +23.3.5 +Clock Prescaler Register (EWM\_CLKPRESCALER) +This CLKPRESCALER register is reset to 0x00 after a CPU reset. +NOTE +This register can be written only once after a CPU reset. +Writing this register more than once generates a bus transfer +error. +NOTE +Write the required prescaler value before enabling the EWM. +NOTE +The implementation of this register is chip-specific. See the +Chip Configuration details. +Address: 4006\_1000h base + 5h offset = 4006\_1005h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +CLK\_DIV +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +EWM\_CLKPRESCALER field descriptions +Field +Description +7–0 +CLK\_DIV +Selected low power source for running the EWM counter can be prescaled as below. +• Prescaled clock frequency = low power clock source frequency/ ( 1+ CLK\_DIV ) +23.4 +Functional Description +The following sections describe functional details of the EWM module. +23.4.1 +The EWM\_out Signal +The EWM\_out is a digital output signal used to gate an external circuit (application +specific) that controls critical safety functions. For example, the EWM\_out could be +connected to the high voltage transistors circuits that control an AC motor in a large +appliance. +The EWM\_out signal remains deasserted when the EWM is being regularly serviced by +the CPU within the programmable service window, indicating that the application code is +executed as expected. +Chapter 23 External Watchdog Monitor (EWM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +539 +General Business Information + +![Image 1 from page 539](pdf-image://page_539_img_1) + +## Page 540 + +The EWM\_out signal is asserted in any of the following conditions: +• Servicing the EWM when the counter value is less than CMPL value. +• If the EWM counter value reaches the CMPH value, and no EWM service has +occurred. +• Servicing the EWM when the counter value is more than CMPL and less than CMPH +values and EWM\_in signal is asserted. +• If functionality of EWM\_in pin is enabled and EWM\_in pin is asserted while +servicing the EWM. +• After any reset (by the virtue of the external pull-down mechanism on the EWM\_out +pin) +On a normal reset, the EWM\_out is asserted. To deassert the EWM\_out, set EWMEN bit +in the CTRL register to enable the EWM. +If the EWM\_out signal shares its pad with a digital I/O pin, on reset this actual pad defers +to being an input signal. It takes the EWM\_out output condition only after you enable the +EWM by the EWMEN bit in the CTRL register. +When the EWM\_out pin is asserted, it can only be deasserted by forcing a MCU reset. +Note +EWM\_out pad must be in pull down state when EWM +functionality is used and when EWM is under Reset. +23.4.2 +The EWM\_in Signal +The EWM\_in is a digital input signal that allows an external circuit to control the +EWM\_out signal. For example, in the application, an external circuit monitors a critical +safety function, and if there is fault with this circuit's behavior, it can then actively initiate +the EWM\_out signal that controls the gating circuit. +The EWM\_in signal is ignored if the EWM is disabled, or if INEN bit of CTRL register +is cleared, as after any reset. +On enabling the EWM (setting the CTRL[EWMEN] bit) and enabling EWM\_in +functionality (setting the CTRL[INEN] bit), the EWM\_in signal must be in the deasserted +state prior to the CPU servicing the EWM. This ensures that the EWM\_out stays in the +deasserted state; otherwise, the EWM\_out pin is asserted. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +540 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 540](pdf-image://page_540_img_1) + +## Page 541 + +Note +You must update the CMPH and CMPL registers prior to +enabling the EWM. After enabling the EWM, the counter resets +to zero, therefore providing a reasonable time after a power-on +reset for the external monitoring circuit to stabilize and ensure +that the EWM\_in pin is deasserted. +23.4.3 +EWM Counter +It is an 8-bit ripple counter fed from a clock source that is independent of the peripheral +bus clock source. As the preferred time-out is between 1 ms and 100 ms the actual clock +source should be in the kHz range. +The counter is reset to zero, after a CPU reset, or a EWM refresh cycle. The counter +value is not accessible to the CPU. +23.4.4 +EWM Compare Registers +The compare registers CMPL and CMPH are write-once after a CPU reset and cannot be +modified until another CPU reset occurs. +The EWM compare registers are used to create a service window, which is used by the +CPU to service/refresh the EWM module. +• If the CPU services the EWM when the counter value lies between CMPL value and +CMPH value, the counter is reset to zero. This is a legal service operation. +• If the CPU executes a EWM service/refresh action outside the legal service window, +EWM\_out is asserted. +It is illegal to program CMPL and CMPH with same value. In this case, as soon as +counter reaches (CMPL + 1), EWM\_out is asserted. +23.4.5 +EWM Refresh Mechanism +Other than the initial configuration of the EWM, the CPU can only access the EWM by +the EWM Service Register. The CPU must access the EWM service register with correct +write of unique data within the windowed time frame as determined by the CMPL and +CMPH registers. Therefore, three possible conditions can occur: +Chapter 23 External Watchdog Monitor (EWM) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +541 +General Business Information + +![Image 1 from page 541](pdf-image://page_541_img_1) + +## Page 542 + +Table 23-8. EWM Refresh Mechanisms +Condition +Mechanism +A unique EWM service occurs when CMPL +< Counter < CMPH. +The software behaves as expected and the counter of the EWM is reset to zero, +and EWM\_out pin remains in the deasserted state. +Note: EWM\_in pin is also assumed to be in the deasserted state. +A unique EWM service occurs when +Counter < CMPL +The software services the EWM and therefore resets the counter to zero and +asserts the EWM\_out pin (irrespective of the EWM\_in pin). The EWM\_out pin is +expected to gate critical safety circuits. +Counter value reaches CMPH prior to a +unique EWM service +The counter value reaches the CMPH value and no service of the EWM resets +the counter to zero and assert the EWM\_out pin (irrespective of the EWM\_in +pin). The EWM\_out pin is expected to gate critical safety circuits. +Any illegal service on EWM has no effect on EWM\_out. +23.4.6 +EWM Interrupt +When EWM\_out is asserted, an interrupt request is generated to indicate the assertion of +the EWM reset out signal. This interrupt is enabled when CTRL[INTEN] is set. Clearing +this bit clears the interrupt request but does not affect EWM\_out. The EWM\_out signal +can be deasserted only by forcing a system reset. +23.4.7 +Counter clock prescaler +The EWM counter clock source can be prescaled by a clock divider, by programming +CLKPRESCALER[CLK\_DIV]. This divided clock is used to run the EWM counter. +NOTE +The divided clock used to run the EWM counter must be no +more than half the frequency of the bus clock. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +542 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 542](pdf-image://page_542_img_1) + +## Page 543 + +Chapter 24 +Watchdog Timer (WDOG) +24.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in +case of its failure. Reasons for failure include run-away software code and the stoppage +of the system clock that in a safety critical system can lead to serious consequences. In +such cases, the watchdog brings the system into a safe state of operation. The watchdog +monitors the operation of the system by expecting periodic communication from the +software, generally known as servicing or refreshing the watchdog. If this periodic +refreshing does not occur, the watchdog resets the system. +24.2 +Features +The features of the Watchdog Timer (WDOG) include: +• Clock source input independent from CPU/bus clock. Choice between two clock +sources: +• Low-power oscillator (LPO) +• External system clock +• Unlock sequence for allowing updates to write-once WDOG control/configuration +bits. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +543 +General Business Information + +![Image 1 from page 543](pdf-image://page_543_img_1) + +## Page 544 + +• All WDOG control/configuration bits are writable once only within 256 bus clock +cycles of being unlocked. +• You need to always update these bits after unlocking within 256 bus clock +cycles. Failure to update these bits resets the system. +• Programmable time-out period specified in terms of number of WDOG clock cycles. +• Ability to test WDOG timer and reset with a flag indicating watchdog test. +• Quick test—Small time-out value programmed for quick test. +• Byte test—Individual bytes of timer tested one at a time. +• Read-only access to the WDOG timer—Allows dynamic check that WDOG +timer is operational. +NOTE +Reading the watchdog timer counter while running the +watchdog on the bus clock might not give the accurate +counter value. +• Windowed refresh option +• Provides robust check that program flow is faster than expected. +• Programmable window. +• Refresh outside window leads to reset. +• Robust refresh mechanism +• Write values of 0xA602 and 0xB480 to WDOG Refresh Register within 20 bus +clock cycles. +• Count of WDOG resets as they occur. +• Configurable interrupt on time-out to provide debug breadcrumbs. This is followed +by a reset after 256 bus clock cycles. +Features +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +544 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 544](pdf-image://page_544_img_1) + +## Page 545 + +24.3 +Functional overview +0xC520 +0xD928 +Fast +Fn Test +Clock +Allow update for N bus +clk cycles +N bus clk cycles +LPO +N bus clk cycles +Refresh Sequence +2 writes of data within K +bus clock cycles of each +other +Unlock Sequence +2 Writes of data within K bus clock +cycles of each other +Disable Control/Configuration +bit changes N bus clk cycles after +unlocking +WDOGEN = WDOG Enable +WINEN = Windowed Mode Enable +WDOGT = WDOG Time-out Value +WDOGCLKSRC = WDOG Clock Source +WDOG Test = WDOG Test Mode +WAIT EN = Enable in wait mode +STOP EN = Enable in stop mode +Debug EN = Enable in debug mode +SRS = System Reset Status Register +R = Timer Reload +WDOG +reset count +Alt Clock +Osc +WDOG +Clock +Selection +WDOG CLK +R +System reset +and SRS register +Interrupt +IRQ\_RST\_ +EN = = 1? +Invalid +Unlock Seq +32-bit Timer +Timer Time-out +Refresh +Outside +Window +Invalid Refresh +Seq +No config +after unlocking +No unlock +after reset +0xB480 +0xA602 +System +Bus Clock +32-bit Modulus Reg +(Time-out Value) +DebugEN +Window\_begin +WDOGTEST +STOPEN +WAITEN +WDOGT +WDOG +CLKSRC +WINEN +WDOGEN +WDOG +Y +N +Figure 24-1. WDOG operation +The preceding figure shows the operation of the watchdog. The values for N and K are: +• N = 256 +• K = 20 +The watchdog is a fail safe mechanism that brings the system into a known initial state in +case of its failure due to CPU clock stopping or a run-away condition in code execution. +In its simplest form, the watchdog timer runs continuously off a clock source and expects +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +545 +General Business Information + +![Image 1 from page 545](pdf-image://page_545_img_1) + +## Page 546 + +to be serviced periodically, failing which it resets the system. This ensures that the +software is executing correctly and has not run away in an unintended direction. Software +can adjust the period of servicing or the time-out value for the watchdog timer to meet the +needs of the application. +You can select a windowed mode of operation that expects the servicing to be done only +in a particular window of the time-out period. An attempted servicing of the watchdog +outside this window results in a reset. By operating in this mode, you can get an +indication of whether the code is running faster than expected. The window length is also +user programmable. +If a system fails to update/refresh the watchdog due to an unknown and persistent cause, +it will be caught in an endless cycle of resets from the watchdog. To analyze the cause of +such conditions, you can program the watchdog to first issue an interrupt, followed by a +reset. In the interrupt service routine, the software can analyze the system stack to aid +debugging. +To enhance the independence of watchdog from the system, it runs off an independent +LPO oscillator clock. You can also switch over to an alternate clock source if required, +through a control register bit. +24.3.1 +Unlocking and updating the watchdog +As long as ALLOW\_UPDATE in the watchdog control register is set, you can unlock +and modify the write-once-only control and configuration registers: +1. Write 0xC520 followed by 0xD928 within 20 bus clock cycles to a specific unlock +register (WDOG\_UNLOCK). +2. Wait one bus clock cycle. You cannot update registers on the bus clock cycle +immediately following the write of the unlock sequence. +3. An update window equal in length to the watchdog configuration time (WCT) opens. +Within this window, you can update the configuration and control register bits. +These register bits can be modified only once after unlocking. +If none of the configuration and control registers is updated within the update window, +the watchdog issues a reset, that is, interrupt-then-reset, to the system. Trying to unlock +the watchdog within the WCT after an initial unlock has no effect. During the update +operation, the watchdog timer is not paused and continues running in the background. +After the update window closes, the watchdog timer restarts and the watchdog functions +according to the new configuration. +Functional overview +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +546 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 546](pdf-image://page_546_img_1) + +## Page 547 + +The update feature is useful for applications that have an initial, non-safety critical part, +where the watchdog is kept disabled or with a conveniently long time-out period. This +means the application coder does not have to frequently service the watchdog. After the +critical part of the application begins, the watchdog can be reconfigured as needed. +The watchdog issues a reset, that is, interrupt-then-reset if enabled, to the system for any +of these invalid unlock sequences: +• You write any value other than 0xC520 or 0xD928 to the unlock register. +• ALLOW\_UPDATE is set and you allow a gap of more than 20 bus clock cycles +between the writing of the unlock sequence values. +An attempted refresh operation between the two writes of the unlock sequence and in the +WCT time following a successful unlock, goes undetected. Also, see Watchdog +Operation with 8-bit access for guidelines related to 8-bit accesses to the unlock register. +Note +A context switch during unlocking and refreshing may lead to a +watchdog reset. +24.3.2 +Watchdog configuration time (WCT) +To prevent unintended modification of the watchdog's control and configuration register +bits, you are allowed to update them only within a period of 256 bus clock cycles after +unlocking. This period is known as the watchdog configuration time (WCT). In addition, +these register bits can be modified only once after unlocking them for editing, even after +reset. +You must unlock the registers within WCT after system reset, failing which the WDOG +issues a reset to the system. In other words, you must write at least the first word of the +unlocking sequence within the WCT after reset. After this is done, you have a further 20 +bus clock cycles, the maximum allowed gap between the words of the unlock sequence, +to complete the unlocking operation. Thereafter, to make sure that you do not forget to +configure the watchdog, the watchdog issues a reset if none of the WDOG control and +configuration registers is updated in the WCT after unlock. After the close of this +window or after the first write, these register bits are locked out from any further +changes. +The watchdog timer keeps running according to its default configuration through +unlocking and update operations that can extend up to a maximum total of 2xWCT + 20 +bus clock cycles. Therefore, it must be ensured that the time-out value for the watchdog +is always greater than 2xWCT time + 20 bus clock cycles. +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +547 +General Business Information + +![Image 1 from page 547](pdf-image://page_547_img_1) + +## Page 548 + +Updates in the write-once registers take effect only after the WCT window closes with +the following exceptions for which changes take effect immediately: +• Stop, Wait, and Debug mode enable +• IRQ\_RST\_EN +The operations of refreshing the watchdog goes undetected during the WCT. +24.3.3 +Refreshing the watchdog +A robust refreshing mechanism has been chosen for the watchdog. A valid refresh is a +write of 0xA602 followed by 0xB480 within 20 bus clock cycles to watchdog refresh +register. If these two values are written more than 20 bus cycles apart or if something +other than these two values is written to the register, a watchdog reset, or interrupt-then- +reset if enabled, is issued to the system. A valid refresh makes the watchdog timer restart +on the next bus clock. Also, an attempted unlock operation in between the two writes of +the refresh sequence goes undetected. See Watchdog Operation with 8-bit access for +guidelines related to 8-bit accesses to the refresh register. +24.3.4 +Windowed mode of operation +In this mode of operation, a restriction is placed on the point in time within the time-out +period at which the watchdog can be refreshed. The refresh is considered valid only when +the watchdog timer increments beyond a certain count as specified by the watchdog +window register. This is known as refreshing the watchdog within a window of the total +time-out period. If a refresh is attempted before the timer reaches the window value, the +watchdog generates a reset, or interrupt-then-reset if enabled. If there is no refresh at all, +the watchdog times out and generates a reset or interrupt-then-reset if enabled. +24.3.5 +Watchdog disabled mode of operation +When the watchdog is disabled through the WDOG\_EN bit in the watchdog status and +control register, the watchdog timer is reset to zero and is disabled from counting until +you enable it or it is enabled again by the system reset. In this mode, the watchdog timer +cannot be refreshed–there is no requirement to do so while the timer is disabled. +However, the watchdog still generates a reset, or interrupt-then-reset if enabled, on a non- +Functional overview +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +548 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 548](pdf-image://page_548_img_1) + +## Page 549 + +time-out exception. See Generated Resets and Interrupts. You need to unlock the +watchdog before enabling it. A system reset brings the watchdog out of the disabled +mode. +24.3.6 +Low-power modes of operation +The low-power modes of operation of the watchdog are described in the following table: +Table 24-1. Low-power modes of operation +Mode +Behavior +Wait +If the WDOG is enabled (WAIT\_EN = 1), it can run on bus clock or low-power oscillator clock +(CLK\_SRC = x) to generate interrupt (IRQ\_RST\_EN=1) followed by a reset on time-out. After +reset the WDOG reset counter increments by one. +Stop +Where the bus clock is gated, the WDOG can run only on low-power oscillator clock +(CLK\_SRC=0) if it is enabled in stop (STOP\_EN=1). In this case, the WDOG runs to time-out +twice, and then generates a reset from its backup circuitry. Therefore, if you program the +watchdog to time-out after 100 ms and then enter such a stop mode, the reset will occur after +200 ms. Also, in this case, no interrupt will be generated irrespective of the value of +IRQ\_RST\_EN bit. After WDOG reset, the WDOG reset counter will also not increment. +Power-Down +The watchdog is powered off. +24.3.7 +Debug modes of operation +You can program the watchdog to disable in debug modes through DBG\_EN in the +watchdog control register. This results in the watchdog timer pausing for the duration of +the mode. Register read/writes are still allowed, which means that operations like refresh, +unlock, and so on are allowed. Upon exit from the mode, the timer resumes its operation +from the point of pausing. +The entry of the system into the debug mode does not excuse it from compulsorily +configuring the watchdog in the WCT time after unlock, unless the system bus clock is +gated off, in which case the internal state machine pauses too. Failing to do so still results +in a reset, or interrupt-then-reset, if enabled, to the system. Also, all of the exception +conditions that result in a reset to the system, as described in Generated Resets and +Interrupts, are still valid in this mode. So, if an exception condition occurs and the system +bus clock is on, a reset occurs, or interrupt-then-reset, if enabled. +The entry into Debug mode within WCT after reset is treated differently. The WDOG +timer is kept reset to zero and there is no need to unlock and configure it within WCT. +You must not try to refresh or unlock the WDOG in this state or unknown behavior may +result. Upon exit from this mode, the WDOG timer restarts and the WDOG has to be +unlocked and configured within WCT. +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +549 +General Business Information + +![Image 1 from page 549](pdf-image://page_549_img_1) + +## Page 550 + +24.4 +Testing the watchdog +For IEC 60730 and other safety standards, the expectation is that anything that monitors a +safety function must be tested, and this test is required to be fault tolerant. To test the +watchdog, its main timer and its associated compare and reset logic must be tested. To +this end, two tests are implemented for the watchdog, as described in Quick Test and +Byte Test. A control bit is provided to put the watchdog into functional test mode. There +is also an overriding test-disable control bit which allows the functional test mode to be +disabled permanently. After it is set, this test-disable bit can only be cleared by a reset. +These two tests achieve the overall aim of testing the counter functioning and the +compare and reset logic. +Note +Do not enable the watchdog interrupt during these tests. If +required, you must ensure that the effective time-out value is +greater than WCT time. See Generated Resets and Interrupts for +more details. +To run a particular test: +1. Select either quick test or byte test.. +2. Set a certain test mode bit to put the watchdog in the functional test mode. Setting +this bit automatically switches the watchdog timer to a fast clock source. The +switching of the clock source is done to achieve a faster time-out and hence a faster +test. +In a successful test, the timer times out after reaching the programmed time-out value and +generates a system reset. +Note +After emerging from a reset due to a watchdog test, unlock and +configure the watchdog. The refresh and unlock operations and +interrupt are not automatically disabled in the test mode. +Testing the watchdog +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +550 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 550](pdf-image://page_550_img_1) + +## Page 551 + +24.4.1 +Quick test +In this test, the time-out value of watchdog timer is programmed to a very low value to +achieve quick time-out. The only difference between the quick test and the normal mode +of the watchdog is that TESTWDOG is set for the quick test. This allows for a faster test +of the watchdog reset mechanism. +24.4.2 +Byte test +The byte test is a more thorough a test of the watchdog timer. In this test, the timer is split +up into its constituent byte-wide stages that are run independently and tested for time-out +against the corresponding byte of the time-out value register. The following figure +explains the splitting concept: +CLK +WDOG +en +Mod = = Timer? +Test +32-bit Timer +Modulus Register +(Time-out Value) +WDOG +Reset +Nth Stage Overflow Enables N + 1th Stage +en +en +Reset Value (Hardwired) +Byte +Stage 4 +Equality Comparison +Byte 4 +Byte 2 +Byte 1 +Byte 3 +Byte +Stage 3 +Byte +Stage 2 +Byte +Stage 1 +Figure 24-2. Watchdog timer byte splitting +Each stage is an 8-bit synchronous counter followed by combinational logic that +generates an overflow signal. The overflow signal acts as an enable to the N + 1th stage. +In the test mode, when an individual byte, N, is tested, byte N – 1 is loaded forcefully +with 0xFF, and both these bytes are allowed to run off the clock source. By doing so, the +overflow signal from stage N – 1 is generated immediately, enabling counter stage N. +The Nth stage runs and compares with the Nth byte of the time-out value register. In this +way, the byte N is also tested along with the link between it and the preceding stage. No +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +551 +General Business Information + +![Image 1 from page 551](pdf-image://page_551_img_1) + +## Page 552 + +other stages, N – 2, N – 3... and N + 1, N + 2... are enabled for the test on byte N. These +disabled stages, except the most significant stage of the counter, are loaded with a value +of 0xFF. +24.5 +Backup reset generator +The backup reset generator generates the final reset which goes out to the system. It has a +backup mechanism which ensures that in case the bus clock stops and prevents the main +state machine from generating a reset exception/interrupt, the watchdog timer's time-out +is separately routed out as a reset to the system. Two successive timer time-outs without +an intervening system reset result in the backup reset generator routing out the time-out +signal as a reset to the system. +24.6 +Generated resets and interrupts +The watchdog generates a reset in the following events, also referred to as exceptions: +• A watchdog time-out +• Failure to unlock the watchdog within WCT time after system reset deassertion +• No update of the control and configuration registers within the WCT window after +unlocking. At least one of the following registers must be written to within the WCT +window to avoid reset: +• WDOG\_ST\_CTRL\_H, WDOG\_ST\_CTRL\_L +• WDOG\_TO\_VAL\_H, WDOG\_TO\_VAL\_L +• WDOG\_WIN\_H, WDOG\_WIN\_L +• WDOG\_PRESCALER +• A value other than the unlock sequence or the refresh sequence is written to the +unlock and/or refresh registers, respectively. +• A gap of more than 20 bus cycles exists between the writes of two values of the +unlock sequence. +• A gap of more than 20 bus cycles exists between the writes of two values of the +refresh sequence. +Backup reset generator +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +552 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 552](pdf-image://page_552_img_1) + +## Page 553 + +The watchdog can also generate an interrupt. If IRQ\_RST\_EN is set, then on the above +mentioned events WDOG\_ST\_CTRL\_L[INT\_FLG] is set, generating an interrupt. A +watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant. +The interrupt can be cleared by writing 1 to INT\_FLG. +The gap of WCT between interrupt and reset means that the WDOG time-out value must +be greater than WCT. Otherwise, if the interrupt was generated due to a time-out, a +second consecutive time-out will occur in that WCT gap. This will trigger the backup +reset generator to generate a reset to the system, prematurely ending the interrupt service +routine execution. Also, jobs such as counting the number of watchdog resets would not +be done. +24.7 +Memory map and register definition +This section consists of the memory map and register descriptions. +WDOG memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4005\_2000 +Watchdog Status and Control Register High +(WDOG\_STCTRLH) +16 +R/W +01D\_31D3h +24.7.1/554 +4005\_2002 +Watchdog Status and Control Register Low +(WDOG\_STCTRLL) +16 +R/W +0\_0011h +24.7.2/555 +4005\_2004 +Watchdog Time-out Value Register High (WDOG\_TOVALH) +16 +R/W +00\_4C4Ch +24.7.3/556 +4005\_2006 +Watchdog Time-out Value Register Low (WDOG\_TOVALL) +16 +R/W +4B4C\_4B4Ch +24.7.4/556 +4005\_2008 +Watchdog Window Register High (WDOG\_WINH) +16 +R/W +0\_0000h +24.7.5/557 +4005\_200A +Watchdog Window Register Low (WDOG\_WINL) +16 +R/W +00\_1010h +24.7.6/557 +4005\_200C +Watchdog Refresh register (WDOG\_REFRESH) +16 +R/W +B480\_B480h +24.7.7/558 +4005\_200E +Watchdog Unlock register (WDOG\_UNLOCK) +16 +R/W +D928\_D928h +24.7.8/558 +4005\_2010 +Watchdog Timer Output Register High (WDOG\_TMROUTH) +16 +R/W +0\_0000h +24.7.9/558 +4005\_2012 +Watchdog Timer Output Register Low (WDOG\_TMROUTL) +16 +R/W +0\_0000h +24.7.10/ +559 +4005\_2014 +Watchdog Reset Count register (WDOG\_RSTCNT) +16 +R/W +0\_0000h +24.7.11/ +559 +4005\_2016 +Watchdog Prescaler register (WDOG\_PRESC) +16 +R/W +040\_0400h +24.7.12/ +560 +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +553 +General Business Information + +![Image 1 from page 553](pdf-image://page_553_img_1) + +## Page 554 + +24.7.1 +Watchdog Status and Control Register High +(WDOG\_STCTRLH) +Address: 4005\_2000h base + 0h offset = 4005\_2000h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +DISTESTWDO +G +BYTESEL[1:0] +TESTSEL +TESTWDOG +0 +Reserved +WAITEN +STOPEN +DBGEN +ALLOWUPDAT +E +WINEN +IRQRSTEN +CLKSRC +WDOGEN +Write +Reset +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +0 +1 +0 +0 +1 +1 +WDOG\_STCTRLH field descriptions +Field +Description +15 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +14 +DISTESTWDOG +Allows the WDOG’s functional test mode to be disabled permanently. After it is set, it can only be cleared +by a reset. It cannot be unlocked for editing after it is set. +0 +WDOG functional test mode is not disabled. +1 +WDOG functional test mode is disabled permanently until reset. +13–12 +BYTESEL[1:0] +This 2-bit field selects the byte to be tested when the watchdog is in the byte test mode. +00 +Byte 0 selected +01 +Byte 1 selected +10 +Byte 2 selected +11 +Byte 3 selected +11 +TESTSEL +Effective only if TESTWDOG is set. Selects the test to be run on the watchdog timer. +0 +Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. +1 +Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for +operation and are compared for time-out against the corresponding byte of the programmed time-out +value. Select the byte through BYTESEL[1:0] for testing. +10 +TESTWDOG +Puts the watchdog in the functional test mode. In this mode, the watchdog timer and the associated +compare and reset generation logic is tested for correct operation. The clock for the timer is switched from +the main watchdog clock to the fast clock input for watchdog functional test. The TESTSEL bit selects the +test to be run. +9 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +8 +Reserved +This field is reserved. +7 +WAITEN +Enables or disables WDOG in Wait mode. +0 +WDOG is disabled in CPU Wait mode. +1 +WDOG is enabled in CPU Wait mode. +6 +STOPEN +Enables or disables WDOG in Stop mode. +Table continues on the next page... +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +554 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 554](pdf-image://page_554_img_1) + +## Page 555 + +WDOG\_STCTRLH field descriptions (continued) +Field +Description +0 +WDOG is disabled in CPU Stop mode. +1 +WDOG is enabled in CPU Stop mode. +5 +DBGEN +Enables or disables WDOG in Debug mode. +0 +WDOG is disabled in CPU Debug mode. +1 +WDOG is enabled in CPU Debug mode. +4 +ALLOWUPDATE +Enables updates to watchdog write-once registers, after the reset-triggered initial configuration window +(WCT) closes, through unlock sequence. +0 +No further updates allowed to WDOG write-once registers. +1 +WDOG write-once registers can be unlocked for updating. +3 +WINEN +Enables Windowing mode. +0 +Windowing mode is disabled. +1 +Windowing mode is enabled. +2 +IRQRSTEN +Used to enable the debug breadcrumbs feature. A change in this bit is updated immediately, as opposed +to updating after WCT. +0 +WDOG time-out generates reset only. +1 +WDOG time-out initially generates an interrupt. After WCT, it generates a reset. +1 +CLKSRC +Selects clock source for the WDOG timer and other internal timing operations. +0 +WDOG clock sourced from LPO . +1 +WDOG clock sourced from alternate clock source. +0 +WDOGEN +Enables or disables the WDOG’s operation. In the disabled state, the watchdog timer is kept in the reset +state, but the other exception conditions can still trigger a reset/interrupt. A change in the value of this bit +must be held for more than one WDOG\_CLK cycle for the WDOG to be enabled or disabled. +0 +WDOG is disabled. +1 +WDOG is enabled. +24.7.2 +Watchdog Status and Control Register Low +(WDOG\_STCTRLL) +Address: 4005\_2000h base + 2h offset = 4005\_2002h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +Read +INTFLG +Reserved +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +Reserved +Write +Reset +0 +0 +0 +0 +0 +0 +0 +1 +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +555 +General Business Information + +![Image 1 from page 555](pdf-image://page_555_img_1) + +## Page 556 + +WDOG\_STCTRLL field descriptions +Field +Description +15 +INTFLG +Interrupt flag. It is set when an exception occurs. IRQRSTEN = 1 is a precondition to set this flag. INTFLG += 1 results in an interrupt being issued followed by a reset, WCT later. The interrupt can be cleared by +writing 1 to this bit. It also gets cleared on a system reset. +14–0 +Reserved +This field is reserved. +NOTE: Do not modify this field value. +24.7.3 +Watchdog Time-out Value Register High (WDOG\_TOVALH) +Address: 4005\_2000h base + 4h offset = 4005\_2004h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +TOVALHIGH +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +1 +1 +0 +0 +WDOG\_TOVALH field descriptions +Field +Description +15–0 +TOVALHIGH +Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles +of the watchdog clock. +24.7.4 +Watchdog Time-out Value Register Low (WDOG\_TOVALL) +The time-out value of the watchdog must be set to a minimum of four watchdog clock +cycles. This is to take into account the delay in new settings taking effect in the watchdog +clock domain. +Address: 4005\_2000h base + 6h offset = 4005\_2006h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +TOVALLOW +Write +Reset +0 +1 +0 +0 +1 +0 +1 +1 +0 +1 +0 +0 +1 +1 +0 +0 +WDOG\_TOVALL field descriptions +Field +Description +15–0 +TOVALLOW +Defines the lower 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles +of the watchdog clock. +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +556 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 556](pdf-image://page_556_img_1) + +## Page 557 + +24.7.5 +Watchdog Window Register High (WDOG\_WINH) +NOTE +You must set the Window Register value lower than the Time- +out Value Register. +Address: 4005\_2000h base + 8h offset = 4005\_2008h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +WINHIGH +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +WDOG\_WINH field descriptions +Field +Description +15–0 +WINHIGH +Defines the upper 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is +defined in terms of cycles of the watchdog clock. In this mode, the watchdog can be refreshed only when +the timer has reached a value greater than or equal to this window length. A refresh outside this window +resets the system or if IRQRSTEN is set, it interrupts and then resets the system. +24.7.6 +Watchdog Window Register Low (WDOG\_WINL) +NOTE +You must set the Window Register value lower than the Time- +out Value Register. +Address: 4005\_2000h base + Ah offset = 4005\_200Ah +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +WINLOW +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +WDOG\_WINL field descriptions +Field +Description +15–0 +WINLOW +Defines the lower 16 bits of the 32-bit window for the windowed mode of operation of the watchdog. It is +defined in terms of cycles of the pre-scaled watchdog clock. In this mode, the watchdog can be refreshed +only when the timer reaches a value greater than or equal to this window length value. A refresh outside of +this window resets the system or if IRQRSTEN is set, it interrupts and then resets the system. +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +557 +General Business Information + +![Image 1 from page 557](pdf-image://page_557_img_1) + +## Page 558 + +24.7.7 +Watchdog Refresh register (WDOG\_REFRESH) +Address: 4005\_2000h base + Ch offset = 4005\_200Ch +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +WDOGREFRESH +Write +Reset +1 +0 +1 +1 +0 +1 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +WDOG\_REFRESH field descriptions +Field +Description +15–0 +WDOGREFRESH +Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 bus clock cycles written +to this register refreshes the WDOG and prevents it from resetting the system. Writing a value other than +the above mentioned sequence or if the sequence is longer than 20 bus cycles, resets the system, or if +IRQRSTEN is set, it interrupts and then resets the system. +24.7.8 +Watchdog Unlock register (WDOG\_UNLOCK) +Address: 4005\_2000h base + Eh offset = 4005\_200Eh +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +WDOGUNLOCK +Write +Reset +1 +1 +0 +1 +1 +0 +0 +1 +0 +0 +1 +0 +1 +0 +0 +0 +WDOG\_UNLOCK field descriptions +Field +Description +15–0 +WDOGUNLOCK +Writing the unlock sequence values to this register to makes the watchdog write-once registers writable +again. The required unlock sequence is 0xC520 followed by 0xD928 within 20 bus clock cycles. A valid +unlock sequence opens a window equal in length to the WCT within which you can update the registers. +Writing a value other than the above mentioned sequence or if the sequence is longer than 20 bus cycles, +resets the system or if IRQRSTEN is set, it interrupts and then resets the system. The unlock sequence is +effective only if ALLOWUPDATE is set. +24.7.9 +Watchdog Timer Output Register High (WDOG\_TMROUTH) +Address: 4005\_2000h base + 10h offset = 4005\_2010h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +TIMEROUTHIGH +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Memory map and register definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +558 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 558](pdf-image://page_558_img_1) + +## Page 559 + +WDOG\_TMROUTH field descriptions +Field +Description +15–0 +TIMEROUTHIGH +Shows the value of the upper 16 bits of the watchdog timer. +24.7.10 +Watchdog Timer Output Register Low (WDOG\_TMROUTL) +During Stop mode, the WDOG\_TIMER\_OUT will be caught at the pre-stop value of the +watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG\_CLK cycle + 3 +bus clock cycles will occur before the WDOG\_TIMER\_OUT starts following the +watchdog timer. +Address: 4005\_2000h base + 12h offset = 4005\_2012h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +TIMEROUTLOW +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +WDOG\_TMROUTL field descriptions +Field +Description +15–0 +TIMEROUTLOW +Shows the value of the lower 16 bits of the watchdog timer. +24.7.11 +Watchdog Reset Count register (WDOG\_RSTCNT) +Address: 4005\_2000h base + 14h offset = 4005\_2014h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +RSTCNT +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +WDOG\_RSTCNT field descriptions +Field +Description +15–0 +RSTCNT +Counts the number of times the watchdog resets the system. This register is reset only on a POR. Writing +1 to the bit to be cleared enables you to clear the contents of this register. +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +559 +General Business Information + +![Image 1 from page 559](pdf-image://page_559_img_1) + +## Page 560 + +24.7.12 +Watchdog Prescaler register (WDOG\_PRESC) +Address: 4005\_2000h base + 16h offset = 4005\_2016h +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +PRESCVAL +0 +Write +Reset +0 +0 +0 +0 +0 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +WDOG\_PRESC field descriptions +Field +Description +15–11 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +10–8 +PRESCVAL +3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG +clock. The watchdog clock is divided by (PRESCVAL + 1) to provide the prescaled WDOG\_CLK. +7–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +24.8 +Watchdog operation with 8-bit access +24.8.1 +General guideline +When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is +to access both the bytes of a register, place the two 8-bit accesses one after the other in +your code. +24.8.2 +Refresh and unlock operations with 8-bit access +One exception condition that generates a reset to the system is the write of any value +other than those required for a legal refresh/update sequence to the respective refresh and +unlock registers. +For an 8-bit access to these registers, writing a correct value requires at least two bus +clock cycles, resulting in an invalid value in the registers for one cycle. Therefore, the +system is reset even if the intention is to write a correct value to the refresh/unlock +register. Keeping this in mind, the exception condition for 8-bit accesses is slightly +modified. +Watchdog operation with 8-bit access +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +560 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 560](pdf-image://page_560_img_1) + +## Page 561 + +Whereas the match for a correct value for a refresh/unlock sequence is as according to the +original definition, the match for an incorrect value is done byte-wise on the refresh/ +unlock rather than for the whole 16-bit value. This means that if the high byte of the +refresh/unlock register contains any value other than high bytes of the two values that +make up the sequence, it is treated as an exception condition, leading to a reset or +interrupt-then-reset. The same holds true for the lower byte of the refresh or unlock +register. Take the refresh operation that expects a write of 0xA602 followed by 0xB480 +to the refresh register, as an example. +Table 24-15. Refresh for 8-bit access +WDOG\_REFRESH[15:8] +WDOG\_REFRESH[7:0] +Sequence value1 or +value2 match +Mismatch +exception +Current Value +0xB4 +0x80 +Value2 match +No +Write 1 +0xB4 +0x02 +No match +No +Write 2 +0xA6 +0x02 +Value1 match +No +Write 3 +0xB4 +0x02 +No match +No +Write 4 +0xB4 +0x80 +Value2 match. +Sequence complete. +No +Write 5 +0x02 +0x80 +No match +Yes +As shown in the preceding table, the refresh register holds its reset value initially. +Thereafter, two 8-bit accesses are performed on the register to write the first value of the +refresh sequence. No mismatch exception is registered on the intermediate write, Write1. +The sequence is completed by performing two more 8-bit accesses, writing in the second +value of the sequence for a successful refresh. It must be noted that the match of value2 +takes place only when the complete 16-bit value is correctly written, write4. Hence, the +requirement of writing value2 of the sequence within 20 bus clock cycles of value1 is +checked by measuring the gap between write2 and write4. +It is reiterated that the condition for matching values 1 and 2 of the refresh or unlock +sequence remains unchanged. The difference for 8-bit accesses is that the criterion for +detecting a mismatch is less strict. Any 16-bit access still needs to adhere to the original +guidelines, mentioned in the sections Refreshing the Watchdog. +24.9 +Restrictions on watchdog operation +This section mentions some exceptions to the watchdog operation that may not be +apparent to you. +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +561 +General Business Information + +![Image 1 from page 561](pdf-image://page_561_img_1) + +## Page 562 + +• Restriction on unlock/refresh operations—In the period between the closure of the +WCT window after unlock and the actual reload of the watchdog timer, unlock and +refresh operations need not be attempted. +• The update and reload of the watchdog timer happens two to three watchdog clocks +after WCT window closes, following a successful configuration on unlock. +• Clock Switching Delay—The watchdog uses glitch-free multiplexers at two places – +one to choose between the LPO oscillator input and alternate clock input, and the +other to choose between the watchdog functional clock and fast clock input for +watchdog functional test. A maximum time period of ~2 clock A cycles plus ~2 +clock B cycles elapses from the time a switch is requested to the occurrence of the +actual clock switch, where clock A and B are the two input clocks to the clock mux. +• For the windowed mode, there is a two to three bus clock latency between the +watchdog counter going past the window value and the same registering in the bus +clock domain. +• For proper operation of the watchdog, the watchdog clock must be at least five times +slower than the system bus clock at all times. An exception is when the watchdog +clock is synchronous to the bus clock wherein the watchdog clock can be as fast as +the bus clock. +• WCT must be equivalent to at least three watchdog clock cycles. If not ensured, this +means that even after the close of the WCT window, you have to wait for the +synchronized system reset to deassert in the watchdog clock domain, before +expecting the configuration updates to take effect. +• The time-out value of the watchdog should be set to a minimum of four watchdog +clock cycles. This is to take into account the delay in new settings taking effect in the +watchdog clock domain. +• You must take care not only to refresh the watchdog within the watchdog timer's +actual time-out period, but also provide enough allowance for the time it takes for the +refresh sequence to be detected by the watchdog timer, on the watchdog clock. +• Updates cannot be made in the bus clock cycle immediately following the write of +the unlock sequence, but one bus clock cycle later. +• It should be ensured that the time-out value for the watchdog is always greater than +2xWCT time + 20 bus clock cycles. +• An attempted refresh operation, in between the two writes of the unlock sequence +and in the WCT time following a successful unlock, will go undetected. +Restrictions on watchdog operation +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +562 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 562](pdf-image://page_562_img_1) + +## Page 563 + +• Trying to unlock the watchdog within the WCT time after an initial unlock has no +effect. +• The refresh and unlock operations and interrupt are not automatically disabled in the +watchdog functional test mode. +• After emerging from a reset due to a watchdog functional test, you are still expected +to go through the mandatory steps of unlocking and configuring the watchdog. The +watchdog continues to be in its functional test mode and therefore you should pull +the watchdog out of the functional test mode within WCT time of reset. +• After emerging from a reset due to a watchdog functional test, you still need to go +through the mandatory steps of unlocking and configuring the watchdog. +• You must ensure that both the clock inputs to the glitchless clock multiplexers are +alive during the switching of clocks. Failure to do so results in a loss of clock at their +outputs. +• There is a gap of two to three watchdog clock cycles from the point that stop mode is +entered to the watchdog timer actually pausing, due to synchronization. The same +holds true for an exit from the stop mode, this time resulting in a two to three +watchdog clock cycle delay in the timer restarting. In case the duration of the stop +mode is less than one watchdog clock cycle, the watchdog timer is not guaranteed to +pause. +• Consider the case when the first refresh value is written, following which the system +enters stop mode with system bus clk still on. If the second refresh value is not +written within 20 bus cycles of the first value, the system is reset, or interrupt-then- +reset if enabled. +Chapter 24 Watchdog Timer (WDOG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +563 +General Business Information + +![Image 1 from page 563](pdf-image://page_563_img_1) + +## Page 564 + +Restrictions on watchdog operation +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +564 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 564](pdf-image://page_564_img_1) + +## Page 565 + +Chapter 25 +Multipurpose Clock Generator (MCG) +25.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The multipurpose clock generator (MCG) module provides several clock source choices +for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked +loop (PLL). The FLL is controllable by either an internal or an external reference clock. +The PLL is controllable by the external reference clock. The module can select either of +the FLL or PLL output clocks, or either of the internal or external reference clocks as a +source for the MCU system clock. The MCG operates in conjuction with a crystal +oscillator, which allows an external crystal, ceramic resonator, or another external clock +source to produce the external reference clock. +25.1.1 +Features +Key features of the MCG module are: +• Frequency-locked loop (FLL): +• Digitally-controlled oscillator (DCO) +• DCO frequency range is programmable for up to four different frequency ranges. +• Option to program and maximize DCO output frequency for a low frequency +external reference clock source. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +565 +General Business Information + +![Image 1 from page 565](pdf-image://page_565_img_1) + +## Page 566 + +• Option to prevent FLL from resetting its current locked frequency when +switching clock modes if FLL reference frequency is not changed. +• Internal or external reference clock can be used as the FLL source. +• Can be used as a clock source for other on-chip peripherals. +• Phase-locked loop (PLL): +• Voltage-controlled oscillator (VCO) +• External reference clock is used as the PLL source. +• Modulo VCO frequency divider +• Phase/Frequency detector +• Integrated loop filter +• Can be used as a clock source for other on-chip peripherals. +• Internal reference clock generator: +• Slow clock with nine trim bits for accuracy +• Fast clock with four trim bits +• Can be used as source clock for the FLL. In FEI mode, only the slow Internal +Reference Clock (IRC) can be used as the FLL source. +• Either the slow or the fast clock can be selected as the clock source for the MCU. +• Can be used as a clock source for other on-chip peripherals. +• Control signals for the MCG external reference low power oscillator clock generators +are provided: +• HGO0, RANGE0, EREFS0 +• External clock from the Crystal Oscillator : +• Can be used as a source for the FLL and/or the PLL. +• Can be selected as the clock source for the MCU. +• External clock from the Real Time Counter (RTC): +• Can only be used as a source for the FLL. +• Can be selected as the clock source for the MCU. +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +566 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 566](pdf-image://page_566_img_1) + +## Page 567 + +• External clock monitor with reset and interrupt request capability to check for +external clock failure when running in FBE, PEE,, BLPE, or FEE modes +• Lock detector with interrupt request capability for use with the PLL +• Internal Reference Clocks Auto Trim Machine (ATM) capability using an external +clock as a reference +• Reference dividers for both the FLL and the PLL are provided +• Reference dividers for the Fast Internal Reference Clock are provided +• MCG PLL Clock (MCGPLLCLK) is provided as a clock source for other on-chip +peripherals +• MCG FLL Clock (MCGFLLCLK) is provided as a clock source for other on-chip +peripherals +• MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other +on-chip peripherals +• MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other +on-chip peripherals +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +567 +General Business Information + +![Image 1 from page 567](pdf-image://page_567_img_1) + +## Page 568 + +MCGOUTCLK +MCGIRCLK +MCGFFCLK +DCOOUT +/(24,25,26,...,55) +Phase +Detector +Charge +Pump +Internal +Filter +VCO +VCOOUT +PLL +Multipurpose Clock Generator (MCG) +VDIV0 +Lock +IRCLKEN +PLLS +LOLS0 LOCK0 +Detector +/ 25 +IREFST +FLL +DMX32 +MCGFLLCLK +Crystal Oscillator +FRDIV +n=0-7 +/ 2n +Internal +Reference +Slow Clock +Fast Clock +Clock +Generator +PRDIV0 +LOLIE0 +Sync +Auto Trim Machine +IRCST +PLLST +CLKST +ATMS +SCTRIM +SCFTRIM +FCTRIM +ATMST +IREFSTEN +OSCINIT0 +EREFS0 +HGO0 +RANGE0 +DRS +Clock +Valid +Peripheral BUSCLK +PLLCLKEN0 +IRCSCLK +IRCS +CLKS +CLKS +DCO +LP +Filter +/(1,2,3,4,5....,25) +IREFS +STOP +CLKS +PLLCLKEN0 +IREFS +PLLS +MCG Crystal Oscillator +Enable Detect +External Reference Clock +RTC +Oscillator +OSCSEL +n=0-7 +/ 2n +FLTPRSRV +MCGPLLCLK +Clock +External +CME0 +LOCRE0 +CME1 +LOCRE1 +LOCS0 +LOCS1 +Monitor +Figure 25-1. Multipurpose Clock Generator (MCG) block diagram +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +568 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 568](pdf-image://page_568_img_1) + +## Page 569 + +25.1.2 +Modes of Operation +The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, +BLPE, and Stop. For details, see MCG modes of operation. +25.2 +External Signal Description +There are no MCG signals that connect off chip. +25.3 +Memory Map/Register Definition +This section includes the memory map and register definition. +The MCG registers can only be accessed when in supervisor mode. Read or write +accesses when in user mode will result in a bus error. +MCG memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4006\_4000 +MCG Control 1 Register (MCG\_C1) +8 +R/W +044h +25.3.1/570 +4006\_4001 +MCG Control 2 Register (MCG\_C2) +8 +R/W +8080h +25.3.2/571 +4006\_4002 +MCG Control 3 Register (MCG\_C3) +8 +R/W +Undefined +25.3.3/572 +4006\_4003 +MCG Control 4 Register (MCG\_C4) +8 +R/W +Undefined +25.3.4/573 +4006\_4004 +MCG Control 5 Register (MCG\_C5) +8 +R/W +000h +25.3.5/574 +4006\_4005 +MCG Control 6 Register (MCG\_C6) +8 +R/W +000h +25.3.6/575 +4006\_4006 +MCG Status Register (MCG\_S) +8 +R +1010h +25.3.7/577 +4006\_4008 +MCG Status and Control Register (MCG\_SC) +8 +R/W +022h +25.3.8/578 +4006\_400A +MCG Auto Trim Compare Value High Register +(MCG\_ATCVH) +8 +R/W +000h +25.3.9/580 +4006\_400B +MCG Auto Trim Compare Value Low Register +(MCG\_ATCVL) +8 +R/W +000h +25.3.10/ +580 +4006\_400C +MCG Control 7 Register (MCG\_C7) +8 +R/W +000h +25.3.11/ +580 +4006\_400D +MCG Control 8 Register (MCG\_C8) +8 +R/W +8080h +25.3.12/ +581 +4006\_400E +MCG Control 9 Register (MCG\_C9) +8 +R/W +000h +25.3.13/ +582 +4006\_400F +MCG Control 10 Register (MCG\_C10) +8 +R/W +000h +25.3.14/ +582 +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +569 +General Business Information + +![Image 1 from page 569](pdf-image://page_569_img_1) + +## Page 570 + +25.3.1 +MCG Control 1 Register (MCG\_C1) +Address: 4006\_4000h base + 0h offset = 4006\_4000h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +CLKS +FRDIV +IREFS +IRCLKEN +IREFSTEN +Write +Reset +0 +0 +0 +0 +0 +1 +0 +0 +MCG\_C1 field descriptions +Field +Description +7–6 +CLKS +Clock Source Select +Selects the clock source for MCGOUTCLK . +00 +Encoding 0 — Output of FLL or PLL is selected (depends on PLLS control bit). +01 +Encoding 1 — Internal reference clock is selected. +10 +Encoding 2 — External reference clock is selected. +11 +Encoding 3 — Reserved. +5–3 +FRDIV +FLL External Reference Divider +Selects the amount to divide down the external reference clock for the FLL. The resulting frequency must +be in the range 31.25 kHz to 39.0625 kHz (This is required when FLL/DCO is the clock source for +MCGOUTCLK . In FBE mode, it is not required to meet this range, but it is recommended in the cases +when trying to enter a FLL mode from FBE). +000 +If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is +32. +001 +If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is +64. +010 +If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is +128. +011 +If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is +256. +100 +If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is +512. +101 +If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is +1024. +110 +If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is +1280 . +111 +If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is +1536 . +2 +IREFS +Internal Reference Select +Selects the reference clock source for the FLL. +0 +External reference clock is selected. +1 +The slow internal reference clock is selected. +1 +IRCLKEN +Internal Reference Clock Enable +Enables the internal reference clock for use as MCGIRCLK. +Table continues on the next page... +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +570 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 570](pdf-image://page_570_img_1) + +## Page 571 + +MCG\_C1 field descriptions (continued) +Field +Description +0 +MCGIRCLK inactive. +1 +MCGIRCLK active. +0 +IREFSTEN +Internal Reference Stop Enable +Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode. +0 +Internal reference clock is disabled in Stop mode. +1 +Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI +modes before entering Stop mode. +25.3.2 +MCG Control 2 Register (MCG\_C2) +Address: 4006\_4000h base + 1h offset = 4006\_4001h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +LOCRE0 +0 +RANGE0 +HGO0 +EREFS0 +LP +IRCS +Write +Reset +1 +0 +0 +0 +0 +0 +0 +0 +MCG\_C2 field descriptions +Field +Description +7 +LOCRE0 +Loss of Clock Reset Enable +Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference +clock. The LOCRE0 only has an affect when CME0 is set. +0 +Interrupt request is generated on a loss of OSC0 external reference clock. +1 +Generate a reset request on a loss of OSC0 external reference clock. +6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5–4 +RANGE0 +Frequency Range Select +Selects the frequency range for the crystal oscillator or external clock source. See the Oscillator (OSC) +chapter for more details and the device data sheet for the frequency ranges used. +00 +Encoding 0 — Low frequency range selected for the crystal oscillator . +01 +Encoding 1 — High frequency range selected for the crystal oscillator . +1X +Encoding 2 — Very high frequency range selected for the crystal oscillator . +3 +HGO0 +High Gain Oscillator Select +Controls the crystal oscillator mode of operation. See the Oscillator (OSC) chapter for more details. +0 +Configure crystal oscillator for low-power operation. +1 +Configure crystal oscillator for high-gain operation. +2 +EREFS0 +External Reference Select +Selects the source for the external reference clock. See the Oscillator (OSC) chapter for more details. +Table continues on the next page... +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +571 +General Business Information + +![Image 1 from page 571](pdf-image://page_571_img_1) + +## Page 572 + +MCG\_C2 field descriptions (continued) +Field +Description +0 +External reference clock requested. +1 +Oscillator requested. +1 +LP +Low Power Select +Controls whether the FLL or PLL is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting this +bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the MCG +into BLPI mode. In any other MCG mode, LP bit has no affect. +0 +FLL or PLL is not disabled in bypass modes. +1 +FLL or PLL is disabled in bypass modes (lower power) +0 +IRCS +Internal Reference Clock Select +Selects between the fast or slow internal reference clock source. +0 +Slow internal reference clock selected. +1 +Fast internal reference clock selected. +25.3.3 +MCG Control 3 Register (MCG\_C3) +Address: 4006\_4000h base + 2h offset = 4006\_4002h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +SCTRIM +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +MCG\_C3 field descriptions +Field +Description +7–0 +SCTRIM +Slow Internal Reference Clock Trim Setting +SCTRIM 1 controls the slow internal reference clock frequency by controlling the slow internal reference +clock period. The SCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing +the binary value increases the period, and decreasing the value decreases the period. +An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset, this value is loaded +with a factory trim value. +If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value +from the nonvolatile memory location to this register. +1. A value for SCTRIM is loaded during reset from a factory programmed location . +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +572 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 572](pdf-image://page_572_img_1) + +## Page 573 + +25.3.4 +MCG Control 4 Register (MCG\_C4) +NOTE +Reset values for DRST and DMX32 bits are 0. +Address: 4006\_4000h base + 3h offset = 4006\_4003h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +DMX32 +DRST\_DRS +FCTRIM +SCFTRIM +Write +Reset +0 +0 +0 +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +A value for FCTRIM is loaded during reset from a factory programmed location . x = Undefined at reset. +• +MCG\_C4 field descriptions +Field +Description +7 +DMX32 +DCO Maximum Frequency with 32.768 kHz Reference +The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a +32.768 kHz reference. +The following table identifies settings for the DCO frequency range. +NOTE: The system clocks derived from this source should not exceed their specified maximums. +DRST\_DRS +DMX32 +Reference Range +FLL Factor +DCO Range +00 +0 +31.25–39.0625 kHz 640 +20–25 MHz +1 +32.768 kHz +732 +24 MHz +01 +0 +31.25–39.0625 kHz 1280 +40–50 MHz +1 +32.768 kHz +1464 +48 MHz +10 +0 +31.25–39.0625 kHz 1920 +60–75 MHz +1 +32.768 kHz +2197 +72 MHz +11 +0 +31.25–39.0625 kHz 2560 +80–100 MHz +1 +32.768 kHz +2929 +96 MHz +0 +DCO has a default range of 25%. +1 +DCO is fine-tuned for maximum frequency with 32.768 kHz reference. +6–5 +DRST\_DRS +DCO Range Select +The DRS bits select the frequency range for the FLL output, DCOOUT. When the LP bit is set, writes to +the DRS bits are ignored. The DRST read field indicates the current frequency range for DCOOUT. The +DRST field does not update immediately after a write to the DRS field due to internal synchronization +between clock domains. See the DCO Frequency Range table for more details. +00 +Encoding 0 — Low range (reset default). +Table continues on the next page... +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +573 +General Business Information + +![Image 1 from page 573](pdf-image://page_573_img_1) + +## Page 574 + +MCG\_C4 field descriptions (continued) +Field +Description +01 +Encoding 1 — Mid range. +10 +Encoding 2 — Mid-high range. +11 +Encoding 3 — High range. +4–1 +FCTRIM +Fast Internal Reference Clock Trim Setting +FCTRIM 1 controls the fast internal reference clock frequency by controlling the fast internal reference +clock period. The FCTRIM bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0. Increasing +the binary value increases the period, and decreasing the value decreases the period. +If an FCTRIM[3:0] value stored in nonvolatile memory is to be used, it is your responsibility to copy that +value from the nonvolatile memory location to this register. +0 +SCFTRIM +Slow Internal Reference Clock Fine Trim +SCFTRIM 2 controls the smallest adjustment of the slow internal reference clock frequency. Setting +SCFTRIM increases the period and clearing SCFTRIM decreases the period by the smallest amount +possible. +If an SCFTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value +from the nonvolatile memory location to this bit. +1. A value for FCTRIM is loaded during reset from a factory programmed location . +2. A value for SCFTRIM is loaded during reset from a factory programmed location . +25.3.5 +MCG Control 5 Register (MCG\_C5) +Address: 4006\_4000h base + 4h offset = 4006\_4004h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +PLLCLKEN0 +PLLSTEN0 +PRDIV0 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +MCG\_C5 field descriptions +Field +Description +7 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +6 +PLLCLKEN0 +PLL Clock Enable +Enables the PLL independent of PLLS and enables the PLL clock for use as MCGPLLCLK. (PRDIV 0 +needs to be programmed to the correct divider to generate a PLL reference clock in the range of 2 - 4 MHz +range prior to setting the PLLCLKEN 0 bit). Setting PLLCLKEN 0 will enable the external oscillator if not +already enabled. Whenever the PLL is being enabled by means of the PLLCLKEN 0 bit, and the external +oscillator is being used as the reference clock, the OSCINIT 0 bit should be checked to make sure it is set. +0 +MCGPLLCLK is inactive. +1 +MCGPLLCLK is active. +5 +PLLSTEN0 +PLL Stop Enable +Table continues on the next page... +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +574 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 574](pdf-image://page_574_img_1) + +## Page 575 + +MCG\_C5 field descriptions (continued) +Field +Description +Enables the PLL Clock during Normal Stop. In Low Power Stop mode, the PLL clock gets disabled even if +PLLSTEN 0 =1. All other power modes, PLLSTEN 0 bit has no affect and does not enable the PLL Clock +to run if it is written to 1. +0 +MCGPLLCLK is disabled in any of the Stop modes. +1 +MCGPLLCLK is enabled if system is in Normal Stop mode. +4–0 +PRDIV0 +PLL External Reference Divider +Selects the amount to divide down the external reference clock for the PLL. The resulting frequency must +be in the range of 2 MHz to 4 MHz. After the PLL is enabled (by setting either PLLCLKEN 0 or PLLS), the +PRDIV 0 value must not be changed when LOCK 0 is zero. +Table 25-7. PLL External Reference Divide Factor +PRDIV +0 +Divide +Factor +PRDIV +0 +Divide +Factor +PRDIV +0 +Divide +Factor +PRDIV +0 +Divide +Factor +00000 +1 +01000 +9 +10000 +17 +11000 +25 +00001 +2 +01001 +10 +10001 +18 +11001 +Reserve +d +00010 +3 +01010 +11 +10010 +19 +11010 +Reserve +d +00011 +4 +01011 +12 +10011 +20 +11011 +Reserve +d +00100 +5 +01100 +13 +10100 +21 +11100 +Reserve +d +00101 +6 +01101 +14 +10101 +22 +11101 +Reserve +d +00110 +7 +01110 +15 +10110 +23 +11110 +Reserve +d +00111 +8 +01111 +16 +10111 +24 +11111 +Reserve +d +25.3.6 +MCG Control 6 Register (MCG\_C6) +Address: 4006\_4000h base + 5h offset = 4006\_4005h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +LOLIE0 +PLLS +CME0 +VDIV0 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +MCG\_C6 field descriptions +Field +Description +7 +LOLIE0 +Loss of Lock Interrrupt Enable +Table continues on the next page... +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +575 +General Business Information + +![Image 1 from page 575](pdf-image://page_575_img_1) + +## Page 576 + +MCG\_C6 field descriptions (continued) +Field +Description +Determines if an interrupt request is made following a loss of lock indication. This bit only has an effect +when LOLS 0 is set. +0 +No interrupt request is generated on loss of lock. +1 +Generate an interrupt request on loss of lock. +6 +PLLS +PLL Select +Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS +bit is cleared and PLLCLKEN 0 is not set, the PLL is disabled in all modes. If the PLLS is set, the FLL is +disabled in all modes. +0 +FLL is selected. +1 +PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference +clock in the range of 2–4 MHz prior to setting the PLLS bit). +5 +CME0 +Clock Monitor Enable +Enables the loss of clock monitoring circuit for the OSC0 external reference mux select. The LOCRE0 bit +will determine if a interrupt or a reset request is generated following a loss of OSC0 indication. The CME0 +bit should only be set to a logic 1 when the MCG is in an operational mode that uses the external clock +(FEE, FBE, PEE, PBE, or BLPE) . Whenever the CME0 bit is set to a logic 1, the value of the RANGE0 +bits in the C2 register should not be changed. CME0 bit should be set to a logic 0 before the MCG enters +any Stop mode. Otherwise, a reset request may occur while in Stop mode. CME0 should also be set to a +logic 0 before entering VLPR or VLPW power modes if the MCG is in BLPE mode. +0 +External clock monitor is disabled for OSC0. +1 +External clock monitor is enabled for OSC0. +4–0 +VDIV0 +VCO 0 Divider +Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits establish the multiplication factor +(M) applied to the reference clock frequency. After the PLL is enabled (by setting either PLLCLKEN 0 or +PLLS), the VDIV 0 value must not be changed when LOCK 0 is zero. +Table 25-9. PLL VCO Divide Factor +VDIV 0 +Multiply +Factor +VDIV 0 +Multiply +Factor +VDIV 0 +Multiply +Factor +VDIV 0 +Multiply +Factor +00000 +24 +01000 +32 +10000 +40 +11000 +48 +00001 +25 +01001 +33 +10001 +41 +11001 +49 +00010 +26 +01010 +34 +10010 +42 +11010 +50 +00011 +27 +01011 +35 +10011 +43 +11011 +51 +00100 +28 +01100 +36 +10100 +44 +11100 +52 +00101 +29 +01101 +37 +10101 +45 +11101 +53 +00110 +30 +01110 +38 +10110 +46 +11110 +54 +00111 +31 +01111 +39 +10111 +47 +11111 +55 +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +576 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 576](pdf-image://page_576_img_1) + +## Page 577 + +25.3.7 +MCG Status Register (MCG\_S) +Address: 4006\_4000h base + 6h offset = 4006\_4006h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +LOLS +LOCK0 +PLLST +IREFST +CLKST +OSCINIT0 +IRCST +Write +Reset +0 +0 +0 +1 +0 +0 +0 +0 +MCG\_S field descriptions +Field +Description +7 +LOLS +Loss of Lock Status +This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL +output frequency has fallen outside the lock exit frequency tolerance, D unl . LOLIE determines whether an +interrupt request is made when LOLS is set. LOLRE determines whether a reset request is made when +LOLS is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit has +no effect. +0 +PLL has not lost lock since LOLS 0 was last cleared. +1 +PLL has lost lock since LOLS 0 was last cleared. +6 +LOCK0 +Lock Status +This bit indicates whether the PLL has acquired lock. Lock detection is disabled when not operating in +either PBE or PEE mode unless PLLCLKEN=1 and the MCG is not configured in BLPI or BLPE mode. +While the PLL clock is locking to the desired frequency, the MCG PLL clock (MCGPLLCLK) will be gated +off until the LOCK bit gets asserted. If the lock status bit is set, changing the value of the PRDIV 0 [4:0] +bits in the C5 register or the VDIV0[4:0] bits in the C6 register causes the lock status bit to clear and stay +cleared until the PLL has reacquired lock. Loss of PLL1 reference clock will also cause the LOCK bit to +clear until PLL has reacquired lock Entry into LLS, VLPS, or regular Stop with PLLSTEN=0 also causes +the lock status bit to clear and stay cleared until the Stop mode is exited and the PLL has reacquired lock. +Any time the PLL is enabled and the LOCK bit is cleared, the MCGPLLCLK will be gated off until the +LOCK bit is asserted again. +0 +PLL is currently unlocked. +1 +PLL is currently locked. +5 +PLLST +PLL Select Status +This bit indicates the clock source selected by PLLS . The PLLST bit does not update immediately after a +write to the PLLS bit due to internal synchronization between clock domains. +0 +Source of PLLS clock is FLL clock. +1 +Source of PLLS clock is PLL output clock. +4 +IREFST +Internal Reference Status +This bit indicates the current source for the FLL reference clock. The IREFST bit does not update +immediately after a write to the IREFS bit due to internal synchronization between clock domains. +0 +Source of FLL reference clock is the external reference clock. +1 +Source of FLL reference clock is the internal reference clock. +Table continues on the next page... +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +577 +General Business Information + +![Image 1 from page 577](pdf-image://page_577_img_1) + +## Page 578 + +MCG\_S field descriptions (continued) +Field +Description +3–2 +CLKST +Clock Mode Status +These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the +CLKS bits due to internal synchronization between clock domains. +00 +Encoding 0 — Output of the FLL is selected (reset default). +01 +Encoding 1 — Internal reference clock is selected. +10 +Encoding 2 — External reference clock is selected. +11 +Encoding 3 — Output of the PLL is selected. +1 +OSCINIT0 +OSC Initialization +This bit, which resets to 0, is set to 1 after the initialization cycles of the crystal oscillator clock have +completed. After being set, the bit is cleared to 0 if the OSC is subsequently disabled. See the OSC +module's detailed description for more information. +0 +IRCST +Internal Reference Clock Status +The IRCST bit indicates the current source for the internal reference clock select clock (IRCSCLK). The +IRCST bit does not update immediately after a write to the IRCS bit due to internal synchronization +between clock domains. The IRCST bit will only be updated if the internal reference clock is enabled, +either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN] bit . +0 +Source of internal reference clock is the slow clock (32 kHz IRC). +1 +Source of internal reference clock is the fast clock (4 MHz IRC). +25.3.8 +MCG Status and Control Register (MCG\_SC) +Address: 4006\_4000h base + 8h offset = 4006\_4008h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +ATME +ATMS +ATMF +FLTPRSRV +FCRDIV +LOCS0 +Write +Reset +0 +0 +0 +0 +0 +0 +1 +0 +MCG\_SC field descriptions +Field +Description +7 +ATME +Automatic Trim Machine Enable +Enables the Auto Trim Machine to start automatically trimming the selected Internal Reference Clock. +NOTE: ATME deasserts after the Auto Trim Machine has completed trimming all trim bits of the IRCS +clock selected by the ATMS bit. +Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears +this bit. +0 +Auto Trim Machine disabled. +1 +Auto Trim Machine enabled. +Table continues on the next page... +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +578 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 578](pdf-image://page_578_img_1) + +## Page 579 + +MCG\_SC field descriptions (continued) +Field +Description +6 +ATMS +Automatic Trim Machine Select +Selects the IRCS clock for Auto Trim Test. +0 +32 kHz Internal Reference Clock selected. +1 +4 MHz Internal Reference Clock selected. +5 +ATMF +Automatic Trim Machine Fail Flag +Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the Automatic Trim Machine is +enabled, ATME=1, and a write to the C1, C3, C4, and SC registers is detected or the MCG enters into any +Stop mode. A write to ATMF clears the flag. +0 +Automatic Trim Machine completed normally. +1 +Automatic Trim Machine failed. +4 +FLTPRSRV +FLL Filter Preserve Enable +This bit will prevent the FLL filter values from resetting allowing the FLL output frequency to remain the +same during clock mode changes where the FLL/DCO output is still valid. (Note: This requires that the +FLL reference frequency to remain the same as what it was prior to the new clock mode switch. Otherwise +FLL filter and frequency values will change.) +0 +FLL filter and FLL frequency will reset on changes to currect clock mode. +1 +Fll filter and FLL frequency retain their previous values during new clock mode change. +3–1 +FCRDIV +Fast Clock Internal Reference Divider +Selects the amount to divide down the fast internal reference clock. The resulting frequency will be in the +range 31.25 kHz to 4 MHz (Note: Changing the divider when the Fast IRC is enabled is not supported). +000 +Divide Factor is 1 +001 +Divide Factor is 2. +010 +Divide Factor is 4. +011 +Divide Factor is 8. +100 +Divide Factor is 16 +101 +Divide Factor is 32 +110 +Divide Factor is 64 +111 +Divide Factor is 128. +0 +LOCS0 +OSC0 Loss of Clock Status +The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The LOCS0 bit only has an +effect when CME0 is set. This bit is cleared by writing a logic 1 to it when set. +0 +Loss of OSC0 has not occurred. +1 +Loss of OSC0 has occurred. +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +579 +General Business Information + +![Image 1 from page 579](pdf-image://page_579_img_1) + +## Page 580 + +25.3.9 +MCG Auto Trim Compare Value High Register (MCG\_ATCVH) +Address: 4006\_4000h base + Ah offset = 4006\_400Ah +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +ATCVH +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +MCG\_ATCVH field descriptions +Field +Description +7–0 +ATCVH +ATM Compare Value High +Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM +SAR conversion. +25.3.10 +MCG Auto Trim Compare Value Low Register (MCG\_ATCVL) +Address: 4006\_4000h base + Bh offset = 4006\_400Bh +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +ATCVL +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +MCG\_ATCVL field descriptions +Field +Description +7–0 +ATCVL +ATM Compare Value Low +Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM +SAR conversion. +25.3.11 +MCG Control 7 Register (MCG\_C7) +Address: 4006\_4000h base + Ch offset = 4006\_400Ch +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +OSCSEL +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +580 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 580](pdf-image://page_580_img_1) + +## Page 581 + +MCG\_C7 field descriptions +Field +Description +7–6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5–1 +Reserved +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +OSCSEL +MCG OSC Clock Select +Selects the MCG FLL external reference clock +0 +Selects System Oscillator (OSCCLK). +1 +Selects 32 kHz RTC Oscillator. +25.3.12 +MCG Control 8 Register (MCG\_C8) +Address: 4006\_4000h base + Dh offset = 4006\_400Dh +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +LOCRE1 +LOLRE +CME1 +0 +LOCS1 +Write +Reset +1 +0 +0 +0 +0 +0 +0 +0 +MCG\_C8 field descriptions +Field +Description +7 +LOCRE1 +Loss of Clock Reset Enable +Determines if a interrupt or a reset request is made following a loss of RTC external reference clock. The +LOCRE1 only has an affect when CME1 is set. +0 +Interrupt request is generated on a loss of RTC external reference clock. +1 +Generate a reset request on a loss of RTC external reference clock +6 +LOLRE +0 +Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit +must also be set to generate the interrupt request. +1 +Generate a reset request on a PLL loss of lock indication. +5 +CME1 +Clock Monitor Enable1 +Enables the loss of clock monitoring circuit for the output of the RTC external reference clock. The +LOCRE1 bit will determine whether an interrupt or a reset request is generated following a loss of RTC +clock indication. The CME1 bit should be set to a logic 1 when the MCG is in an operational mode that +uses the RTC as its external reference clock or if the RTC is operational. CME1 bit must be set to a logic 0 +before the MCG enters any Stop mode. Otherwise, a reset request may occur when in Stop mode. CME1 +should also be set to a logic 0 before entering VLPR or VLPW power modes. +0 +External clock monitor is disabled for RTC clock. +1 +External clock monitor is enabled for RTC clock. +4–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Table continues on the next page... +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +581 +General Business Information + +![Image 1 from page 581](pdf-image://page_581_img_1) + +## Page 582 + +MCG\_C8 field descriptions (continued) +Field +Description +0 +LOCS1 +RTC Loss of Clock Status +This bit indicates when a loss of clock has occurred. This bit is cleared by writing a logic 1 to it when set. +0 +Loss of RTC has not occur. +1 +Loss of RTC has occur +25.3.13 +MCG Control 9 Register (MCG\_C9) +Address: 4006\_4000h base + Eh offset = 4006\_400Eh +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +MCG\_C9 field descriptions +Field +Description +7–4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +25.3.14 +MCG Control 10 Register (MCG\_C10) +Address: 4006\_4000h base + Fh offset = 4006\_400Fh +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +0 +0 +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +MCG\_C10 field descriptions +Field +Description +7–4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +582 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 582](pdf-image://page_582_img_1) + +## Page 583 + +Functional Description +25.4.1 +MCG mode state diagram +The nine states of the MCG are shown in the following figure and are described in Table +25-18. The arrows indicate the permitted MCG mode transitions. +FEE +FEI +Reset +BLPI +FBI +FBE +BLPE +PBE +PEE +Stop +Returns to the state that was active before +the MCU entered Stop mode, unless a +reset occurs while in Stop mode. +Entered from any state when +the MCU enters Stop mode +Figure 25-16. MCG mode state diagram +NOTE +• During exits from LLS or VLPS when the MCG is in PEE +mode, the MCG will reset to PBE clock mode and the +C1[CLKS] and S[CLKST] will automatically be set to +2’b10. +• If entering Normal Stop mode when the MCG is in PEE +mode with C5[PLLSTEN]=0, the MCG will reset to PBE +clock mode and C1[CLKS] and S[CLKST] will +automatically be set to 2’b10. +25.4 +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +583 +General Business Information + +![Image 1 from page 583](pdf-image://page_583_img_1) + +## Page 584 + +25.4.1.1 +MCG modes of operation +The MCG operates in one of the following modes. +Note +The MCG restricts transitions between modes. For the +permitted transitions, see Figure 25-16. +Table 25-18. MCG modes of operation +Mode +Description +FLL Engaged Internal +(FEI) +FLL engaged internal (FEI) is the default mode of operation and is entered when all the following +condtions occur: +• C1[CLKS] bits are written to 00 +• C1[IREFS] bit is written to 1 +• C6[PLLS] bit is written to 0 +In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32 +kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as +selected by C4[DRST\_DRS] and C4[DMX32] bits, times the internal reference frequency. See the +C4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power state +unless C5[PLLCLKEN0] is set. +FLL Engaged External +(FEE) +FLL engaged external (FEE) mode is entered when all the following conditions occur: +• C1[CLKS] bits are written to 00 +• C1[IREFS] bit is written to 0 +• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 +kHz to 39.0625 kHz +• C6[PLLS] bit is written to 0 +In FEE mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the +external reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected by +C4[DRST\_DRS] and C4[DMX32] bits, times the external reference frequency, as specified by +C1[FRDIV] and C2[RANGE0]. See the C4[DMX32] bit description for more details. In FEE mode, +the PLL is disabled in a low-power state unless C5[PLLCLKEN0] is set. +FLL Bypassed Internal +(FBI) +FLL bypassed internal (FBI) mode is entered when all the following conditions occur: +• C1[CLKS] bits are written to 01 +• C1[IREFS] bit is written to 1 +• C6[PLLS] is written to 0 +• C2[LP] is written to 0 +In FBI mode, the MCGOUTCLK is derived either from the slow (32 kHz IRC) or fast (2 MHz IRC) +internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is not +used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is +driven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is controlled +by the slow internal reference clock, and the DCO clock frequency locks to a multiplication factor, as +selected by C4[DRST\_DRS] and C4[DMX32] bits, times the internal reference frequency. See the +C4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low-power state +unless C5[PLLCLKEN0] is set. +Table continues on the next page... +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +584 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 584](pdf-image://page_584_img_1) + +## Page 585 + +Table 25-18. MCG modes of operation (continued) +Mode +Description +FLL Bypassed External +(FBE) +FLL bypassed external (FBE) mode is entered when all the following conditions occur: +• C1[CLKS] bits are written to 10 +• C1[IREFS] bit is written to 0 +• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25 +kHz to 39.0625 kHz. +• C6[PLLS] bit is written to 0 +• C2[LP] is written to 0 +In FBE mode, the MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is +operational but its output is not used. This mode is useful to allow the FLL to acquire its target +frequency while the MCGOUTCLK is driven from the external reference clock. The FLL clock +(DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a +multiplication factor, as selected by C4[DRST\_DRS] and C4[DMX32] bits, times the divided external +reference frequency. See the C4[DMX32] bit description for more details. In FBI mode the PLL is +disabled in a low-power state unless C5[PLLCLKEN0] is set. +PLL Engaged External +(PEE) +PLL Engaged External (PEE) mode is entered when all the following conditions occur: +• C1[CLKS] bits are written to 00 +• C1[IREFS] bit is written to 0 +• C6[PLLS] bit is written to 1 +In PEE mode, the MCGOUTCLK is derived from the PLL clock, which is controlled by the external +reference clock. The PLL clock frequency locks to a multiplication factor, as specified by C6[VDIV0], +times the external reference frequency, as specified by C5[PRDIV0]. The PLL's programmable +reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in +a low-power state. +PLL Bypassed External +(PBE) +PLL Bypassed External (PBE) mode is entered when all the following conditions occur: +• C1[CLKS] bits are written to 10 +• C1[IREFS] bit is written to 0 +• C6[PLLS] bit is written to 1 +• C2[LP] bit is written to 0 +In PBE mode, MCGOUTCLK is derived from the OSCSEL external reference clock; the PLL is +operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its target +frequency while MCGOUTCLK is driven from the external reference clock. The PLL clock frequency +locks to a multiplication factor, as specified by its [VDIV], times the PLL reference frequency, as +specified by its [PRDIV]. In preparation for transition to PEE, the PLL's programmable reference +divider must be configured to produce a valid PLL reference clock. The FLL is disabled in a low- +power state. +Table continues on the next page... +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +585 +General Business Information + +![Image 1 from page 585](pdf-image://page_585_img_1) + +## Page 586 + +Table 25-18. MCG modes of operation (continued) +Mode +Description +Bypassed Low Power +Internal (BLPI)1 +Bypassed Low Power Internal (BLPI) mode is entered when all the following conditions occur: +• C1[CLKS] bits are written to 01 +• C1[IREFS] bit is written to 1 +• C6[PLLS] bit is written to 0 +• C2[LP] bit is written to 1 +In BLPI mode, MCGOUTCLK is derived from the internal reference clock. The FLL is disabled and +PLL is disabled even if the C5[PLLCLKEN0] is set to 1. +Bypassed Low Power +External (BLPE) +Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur: +• C1[CLKS] bits are written to 10 +• C1[IREFS] bit is written to 0 +• C2[LP] bit is written to 1 +In BLPE mode, MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is +disabled and PLL is disabled even if the C5[PLLCLKEN0] is set to 1. +Stop +Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power +mode assignments, see the chapter that describes how modules are configured and MCG behavior +during Stop recovery. Entering Stop mode, the FLL is disabled, and all MCG clock signals are static +except in the following case: +MCGPLLCLK is active in Normal Stop mode when PLLSTEN=1 +MCGIRCLK is active in Normal Stop mode when all the following conditions become true: +• C1[IRCLKEN] = 1 +• C1[IREFSTEN] = 1 +NOTE: +• When entering Low Power Stop modes (LLS or VLPS) from PEE mode, on exit the +MCG clock mode is forced to PBE clock mode. C1[CLKS] and S[CLKST] will be +configured to 2’b10 and S[LOCK0] bit will be cleared without setting S[LOLS0]. +• When entering Normal Stop mode from PEE mode and if C5[PLLSTEN0]=0, on exit +the MCG clock mode is forced to PBE mode, the C1[CLKS] and S[CLKST] will be +configured to 2’b10 and S[LOCK0] bit will clear without setting S[LOLS0]. If +C5[PLLSTEN0]=1, the S[LOCK0] bit will not get cleared and on exit the MCG will +continue to run in PEE mode. +1. +If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the Fast IRC clock selected +(C2[IRCS]=1). After it enters VLPR mode, writes to any of the MCG control registers that can cause an MCG clock mode +switch to a non low power clock mode must be avoided. +NOTE +For the chip-specific modes of operation, see the power +management chapter of this MCU. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +586 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 586](pdf-image://page_586_img_1) + +## Page 587 + +25.4.1.2 +MCG mode switching +The C1[IREFS] bit can be changed at any time, but the actual switch to the newly +selected reference clocks is shown by the S[IREFST] bit. When switching between +engaged internal and engaged external modes, the FLL will begin locking again after the +switch is completed. +The C1[CLKS] bits can also be changed at any time, but the actual switch to the newly +selected clock is shown by the S[CLKST] bits. If the newly selected clock is not +available, the previous clock will remain selected. +The C4[DRST\_DRS] write bits can be changed at any time except when C2[LP] bit is 1. +If the C4[DRST\_DRS] write bits are changed while in FLL engaged internal (FEI) or +FLL engaged external (FEE), the MCGOUTCLK will switch to the new selected DCO +range within three clocks of the selected DCO clock. After switching to the new DCO, +the FLL remains unlocked for several reference cycles. DCO startup time is equal to the +FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The +completion of the switch is shown by the C4[DRST\_DRS] read bits. +25.4.2 +Low Power Bit Usage +The C2[LP] bit is provided to allow the FLL or PLL to be disabled and thus conserve +power when these systems are not being used. The C4[DRST\_DRS] can not be written +while C2[LP] bit is 1. However, in some applications, it may be desirable to enable the +FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged +mode. Do this by writing C2[LP] to 0. +25.4.3 +MCG Internal Reference Clocks +This module supports two internal reference clocks with nominal frequencies of 32 kHz +(slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by +programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz. +25.4.3.1 +MCG Internal Reference Clock +The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other on- +chip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is +driven by either the fast internal reference clock (4 MHz IRC which can be divided down +by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS +clock frequency can be re-targeted by trimming the period of its IRCS selected internal +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +587 +General Business Information + +![Image 1 from page 587](pdf-image://page_587_img_1) + +## Page 588 + +reference clock. This can be done by writing a new trim value to the +C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing a +new trim value to the C4[FCTRIM] bits when the fast IRC clock is selected. The internal +reference clock period is proportional to the trim value written. +C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM] (if C2[IRCS]=1) bits +affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI modes. +C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the MCGOUTCLK +frequency if the MCG is in FEI mode. +Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and +C1[IREFSTEN], otherwise this clock is disabled in Stop mode. +25.4.4 +External Reference Clock +The MCG module can support an external reference clock in all modes. See the device +datasheet for external reference frequency range. When C1[IREFS] is set, the external +reference clock will not be used by the FLL or PLL. In these modes, the frequency can be +equal to the maximum frequency the chip-level timing specifications will support. +If any of the CME bits are asserted the slow internal reference clock is enabled along +with the enabled external clock monitor. For the case when C6[CME0]=1, a loss of clock +is detected if the OSC0 external reference falls below a minimum frequency (floc\_high or +floc\_low depending on C2[RANGE0]). For the case when C8[CME1]=1, a loss of clock is +detected if the RTC external reference falls below a minimum frequency (floc\_low). +All clock monitors must be disabled before VLPR or VLPW power modes are entered. +Upon detect of a loss of clock event, the MCU generates a system reset if the respective +LOCRE bit is set. Otherwise the MCG sets the respective LOCS bit and the MCG +generates a LOCS interrupt request. In the case where a OSC0 loss of clock is detected, +the PLL LOCK status bit is cleared if the OSC clock that is lost was selected as the PLL +reference clock. +25.4.5 +MCG Fixed frequency clock +The MCG Fixed Frequency Clock (MCGFFCLK) provides a fixed frequency clock +source for other on-chip peripherals; see the block diagram. This clock is driven by either +the slow clock from the internal reference clock generator or the external reference clock +from the Crystal Oscillator, divided by the FLL reference clock divider. The source of +MCGFFCLK is selected by C1[IREFS]. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +588 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 588](pdf-image://page_588_img_1) + +## Page 589 + +This clock is synchronized to the peripheral bus clock and is valid only when its +frequency is not more than 1/8 of the MCGOUTCLK frequency. When it is not valid, it is +disabled and held high. The MCGFFCLK is not available when the MCG is in BLPI +mode. This clock is also disabled in Stop mode. The FLL reference clock must be set +within the valid frequency range for the MCGFFCLK. +25.4.6 +MCG PLL clock +The MCG PLL Clock (MCGPLLCLK) is available depending on the device's +configuration of the MCG module. For more details, see the clock distribution chapter of +this MCU. The MCGPLLCLK is prevented from coming out of the MCG until it is +enabled and S[LOCK0] is set. +25.4.7 +MCG Auto TRIM (ATM) +The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG +hardware to automatically trim the MCG Internal Reference Clocks using an external +clock as a reference. The selection between which MCG IRC clock gets tested and +enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz +IRC and ATC[ATMS]=1 selects the 4 MHz IRC). If 4 MHz IRC is selected for the ATM, +a divide by 128 is enabled to divide down the 4 MHz IRC to a range of 31.250 kHz. +When MCG ATM is enabled by writing ATC[ATME] bit to 1, The ATM machine will +start auto trimming the selected IRC clock. During the autotrim process, ATC[ATME] +will remain asserted and will deassert after ATM is completed or an abort occurs. The +MCG ATM is aborted if a write to any of the following control registers is detected : C1, +C3, C4, or ATC or if Stop mode is entered. If an abort occurs, ATC[ATMF] fail flag is +asserted. +The ATM machine uses the bus clock as the external reference clock to perform the IRC +auto-trim. Therefore, it is required that the MCG is configured in a clock mode where the +reference clock used to generate the system clock is the external reference clock such as +FBE clock mode. The MCG must not be configured in a clock mode where selected IRC +ATM clock is used to generate the system clock. The bus clock is also required to be +running with in the range of 8–16 MHz. +To perform the ATM on the selected IRC, the ATM machine uses the successive +approximation technique to adjust the IRC trim bits to generate the desired IRC trimmed +frequency. The ATM SARs each of the ATM IRC trim bits starting with the MSB. For +each trim bit test, the ATM uses a pulse that is generated by the ATM selected IRC clock +to enable a counter that counts number of ATM external clocks. At end of each trim bit, +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +589 +General Business Information + +![Image 1 from page 589](pdf-image://page_589_img_1) + +## Page 590 + +the ATM external counter value is compared to the ATCV[15:0] register value. Based on +the comparison result, the ATM trim bit under test will get cleared or stay asserted. This +is done until all trim bits have been tested by ATM SAR machine. +Before the ATM can be enabled, the ATM expected count needs to be derived and stored +into the ATCV register. The ATCV expected count is derived based on the required +target Internal Reference Clock (IRC) frequency, and the frequency of the external +reference clock using the following formula: +ATCV +• Fr = Target Internal Reference Clock (IRC) Trimmed Frequency +• Fe = External Clock Frequency +If the auto trim is being performed on the 4 MHz IRC, the calculated expected count +value must be multiplied by 128 before storing it in the ATCV register. Therefore, the +ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the +following formula. +(128) +25.5 +Initialization / Application information +This section describes how to initialize and configure the MCG module in an application. +The following sections include examples on how to initialize the MCG and properly +switch between the various available modes. +25.5.1 +MCG module initialization sequence +The MCG comes out of reset configured for FEI mode. The internal reference will +stabilize in tirefsts microseconds before the FLL can acquire lock. As soon as the internal +reference is stable, the FLL will acquire lock in tfll\_acquire milliseconds. +25.5.1.1 +Initializing the MCG +Because the MCG comes out of reset in FEI mode, the only MCG modes that can be +directly switched to upon reset are FEE, FBE, and FBI modes (see Figure 25-16). +Reaching any of the other modes requires first configuring the MCG for one of these +three intermediate modes. Care must be taken to check relevant status bits in the MCG +status register reflecting all configuration changes within each mode. +Initialization / Application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +590 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 590](pdf-image://page_590_img_1) + +## Page 591 + +To change from FEI mode to FEE or FBE modes, follow this procedure: +1. Enable the external clock source by setting the appropriate bits in C2 register. +2. Write to C1 register to select the clock mode. +• If entering FEE mode, set C1[FRDIV] appropriately, clear the C1[IREFS] bit to +switch to the external reference, and leave the C1[CLKS] bits at 2'b00 so that the +output of the FLL is selected as the system clock source. +• If entering FBE, clear the C1[IREFS] bit to switch to the external reference and +change the C1[CLKS] bits to 2'b10 so that the external reference clock is +selected as the system clock source. The C1[FRDIV] bits should also be set +appropriately here according to the external reference frequency to keep the FLL +reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is +bypassed, it is still on in FBE mode. +• The internal reference can optionally be kept running by setting the +C1[IRCLKEN] bit. This is useful if the application will switch back and forth +between internal and external modes. For minimum power consumption, leave +the internal reference disabled while in an external clock mode. +3. Once the proper configuration bits have been set, wait for the affected bits in the +MCG status register to be changed appropriately, reflecting that the MCG has moved +into the proper mode. +• If the MCG is in FEE, FBE, PEE, PBE, or BLPE mode, and C2[EREFS0] was +also set in step 1, wait here for S[OSCINIT0] bit to become set indicating that +the external clock source has finished its initialization cycles and stabilized. +• If in FEE mode, check to make sure the S[IREFST] bit is cleared before moving +on. +• If in FBE mode, check to make sure the S[IREFST] bit is cleared and S[CLKST] +bits have changed to 2'b10 indicating the external reference clock has been +appropriately selected. Although the FLL is bypassed, it is still on in FBE mode. +4. Write to the C4 register to determine the DCO output (MCGFLLCLK) frequency +range. +• By default, with C4[DMX32] cleared to 0, the FLL multiplier for the DCO +output is 640. For greater flexibility, if a mid-low-range FLL multiplier of 1280 +is desired instead, set C4[DRST\_DRS] bits to 2'b01 for a DCO output frequency +of 40 MHz. If a mid high-range FLL multiplier of 1920 is desired instead, set the +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +591 +General Business Information + +![Image 1 from page 591](pdf-image://page_591_img_1) + +## Page 592 + +C4[DRST\_DRS] bits to 2'b10 for a DCO output frequency of 60 MHz. If a high- +range FLL multiplier of 2560 is desired instead, set the C4[DRST\_DRS] bits to +2'b11 for a DCO output frequency of 80 MHz. +• When using a 32.768 kHz external reference, if the maximum low-range DCO +frequency that can be achieved with a 32.768 kHz reference is desired, set +C4[DRST_DRS] bits to 2'b00 and set C4[DMX32] bit to 1. The resulting DCO +output (MCGOUTCLK) frequency with the new multiplier of 732 will be 24 +MHz. +• When using a 32.768 kHz external reference, if the maximum mid-range DCO +frequency that can be achieved with a 32.768 kHz reference is desired, set +C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO +output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 +MHz. +• When using a 32.768 kHz external reference, if the maximum mid high-range +DCO frequency that can be achieved with a 32.768 kHz reference is desired, set +C4[DRST_DRS] bits to 2'b10 and set C4[DMX32] bit to 1. The resulting DCO +output (MCGOUTCLK) frequency with the new multiplier of 2197 will be 72 +MHz. +• When using a 32.768 kHz external reference, if the maximum high-range DCO +frequency that can be achieved with a 32.768 kHz reference is desired, set +C4[DRST_DRS] bits to 2'b11 and set C4[DMX32] bit to 1. The resulting DCO +output (MCGOUTCLK) frequency with the new multiplier of 2929 will be 96 +MHz. +5. Wait for the FLL lock time to guarantee FLL is running at new C4[DRST\_DRS] and +C4[DMX32] programmed frequency. +To change from FEI clock mode to FBI clock mode, follow this procedure: +1. Change C1[CLKS] bits in C1 register to 2'b01 so that the internal reference clock is +selected as the system clock source. +2. Wait for S[CLKST] bits in the MCG status register to change to 2'b01, indicating +that the internal reference clock has been appropriately selected. +3. Write to the C2 register to determine the IRCS output (IRCSCLK) frequency range. +• By default, with C2[IRCS] cleared to 0, the IRCS selected output clock is the +slow internal reference clock (32 kHz IRC). If the faster IRC is desired, set +C2[IRCS] bit to 1 for a IRCS clock derived from the 4 MHz IRC source. +Initialization / Application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +592 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 592](pdf-image://page_592_img_1) + +## Page 593 + +25.5.2 +Using a 32.768 kHz reference +In FEE and FBE modes, if using a 32.768 kHz external reference, at the default FLL +multiplication factor of 640, the DCO output (MCGFLLCLK) frequency is 20.97 MHz at +low-range. If C4[DRST\_DRS] bits are set to 2'b01, the multiplication factor is doubled to +1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range. If +C4[DRST\_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the +resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST\_DRS] bits +are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output +frequency is 83.89 MHz at high-range. +In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal +reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication +factor could potentially push the microcontroller system clock out of specification and +damage the part. +25.5.3 +MCG mode switching +When switching between operational modes of the MCG, certain configuration bits must +be changed in order to properly move from one mode to another. Each time any of these +bits are changed (C6[PLLS], C1[IREFS], C1[CLKS], C2[IRCS], or C2[EREFS0]), the +corresponding bits in the MCG status register (PLLST, IREFST, CLKST, IRCST, or +OSCINIT) must be checked before moving on in the application software. +Additionally, care must be taken to ensure that the reference clock divider (C1[FRDIV] +and C5[PRDIV0]) is set properly for the mode being switched to. For instance, in PEE +mode, if using a 4 MHz crystal, C5[PRDIV0] must be set to 5'b000 (divide-by-1) or +5'b001 (divide -by-2) to divide the external reference down to the required frequency +between 2 and 4 MHz. +In FBE, FEE, FBI, and FEI modes, at any time, the application can switch the FLL +multiplication factor between 640, 1280, 1920, and 2560 with C4[DRST\_DRS] bits. +Writes to C4[DRST\_DRS] bits will be ignored if C2[LP]=1. +The table below shows MCGOUTCLK frequency calculations using C1[FRDIV], +C5[PRDIV0], and C6[VDIV0] settings for each clock mode. +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +593 +General Business Information + +![Image 1 from page 593](pdf-image://page_593_img_1) + +## Page 594 + +Table 25-19. MCGOUTCLK Frequency Calculation Options +Clock Mode +fMCGOUTCLK1 +Note +FEI (FLL engaged internal) +(fint * F) +Typical fMCGOUTCLK = 20 MHz +immediately after reset. +FEE (FLL engaged external) +(fext / FLL\_R) \*F +fext / FLL\_R must be in the range of +31.25 kHz to 39.0625 kHz +FBE (FLL bypassed external) +fext +fext / FLL\_R must be in the range of +31.25 kHz to 39.0625 kHz +FBI (FLL bypassed internal) +fint +Typical fint = 32 kHz +PEE (PLL engaged external) +(fext / PLL_R) * M +fext / PLL\_R must be in the range of +2 – 4 MHz +PBE (PLL bypassed external) +fext +fext / PLL\_R must be in the range of +2 – 4 MHz +BLPI (Bypassed low power internal) +fint +BLPE (Bypassed low power external) +fext +1. +FLL\_R is the reference divider selected by the C1[FRDIV] bits, PLL\_R is the reference divider selected by C5[PRDIV0] +bits, F is the FLL factor selected by C4[DRST\_DRS] and C4[DMX32] bits, and M is the multiplier selected by C6[VDIV0] +bits. +This section will include three mode switching examples using an 4 MHz external +crystal. If using an external clock source less than 2 MHz, the MCG must not be +configured for any of the PLL modes (PEE and PBE). +25.5.3.1 +Example 1: Moving from FEI to PEE mode: External Crystal = +4 MHz, MCGOUTCLK frequency = 48 MHz +In this example, the MCG will move through the proper operational modes from FEI to +PEE to achieve 48 MHz MCGOUTCLK frequency from 4 MHz external crystal +reference. First, the code sequence will be described. Then there is a flowchart that +illustrates the sequence. +1. First, FEI must transition to FBE mode: +a. C2 = 0x1C +• C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the +high frequency range. +• C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation. +• C2[EREFS0] set to 1, because a crystal is being used. +b. C1 = 0x90 +Initialization / Application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +594 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 594](pdf-image://page_594_img_1) + +## Page 595 + +• C1[CLKS] set to 2'b10 to select external reference clock as system clock +source +• C1[FRDIV] set to 3'b010, or divide-by-128 because 4 MHz / 128 = 31.25 +kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL +• C1[IREFS] cleared to 0, selecting the external reference clock and enabling +the external oscillator. +c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by C2[EREFS0] has +been initialized. +d. Loop until S[IREFST] is 0, indicating the external reference is the current source +for the reference clock. +e. Loop until S[CLKST] is 2'b10, indicating that the external reference clock is +selected to feed MCGOUTCLK. +2. Then configure C5[PRDIV0] to generate correct PLL reference frequency. +a. C5 = 0x01 +• C5[PRDIV0] set to 5'b001, or divide-by-2 resulting in a pll reference +frequency of 4 MHz/2 = 2 MHz. +3. Then, FBE must transition either directly to PBE mode or first through BLPE mode +and then to PBE mode: +a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1. +b. BLPE/PBE: C6 = 0x40 +• C6[PLLS] set to 1, selects the PLL. At this time, with a C1[PRDIV] value of +2'b001, the PLL reference divider is 2 (see PLL External Reference Divide +Factor table), resulting in a reference frequency of 4 MHz/ 2 = 2 MHz. In +BLPE mode, changing the C6[PLLS] bit only prepares the MCG for PLL +usage in PBE mode. +• C6[VDIV0] set to 5'b0000, or multiply-by-24 because 2 MHz reference * 24 += 48 MHz. In BLPE mode, the configuration of the VDIV bits does not +matter because the PLL is disabled. Changing them only sets up the multiply +value for PLL usage in PBE mode. +c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to +PBE mode. +d. PBE: Loop until S[PLLST] is set, indicating that the current source for the PLLS +clock is the PLL. +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +595 +General Business Information + +![Image 1 from page 595](pdf-image://page_595_img_1) + +## Page 596 + +e. PBE: Then loop until S[LOCK0] is set, indicating that the PLL has acquired +lock. +4. Lastly, PBE mode transitions into PEE mode: +a. C1 = 0x10 +• C1[CLKS] set to 2'b00 to select the output of the PLL as the system clock +source. +b. Loop until S[CLKST] are 2'b11, indicating that the PLL output is selected to +feed MCGOUTCLK in the current clock mode. +• Now, with PRDIV0 of divide-by-2, and C6[VDIV0] of multiply-by-24, +MCGOUTCLK = [(4 MHz / 2) * 24] = 48 MHz. +Initialization / Application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +596 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 596](pdf-image://page_596_img_1) + +## Page 597 + +C2 = 0x1C +(S[LP]=0) +IN +BLPE MODE ? +C6 = 0x40 +C2 = 0x1C +START +IN FEI MODE +NO +NO +NO +NO +NO +NO +NO +NO +YES +YES +YES +YES +YES +YES +YES +YES +CHECK +C1 = 0x90 +CHECK +CHECK +ENTER +BLPE MODE ? +C2 = 0x1E +(C2[LP] = 1) +CHECK +CHECK +C1 = 0x10 +CHECK +CONTINUE +IN PEE MODE +S[PLLST] = 1? +S[LOCK] = 1? +S[CLKST] = %10? +S[CLKST] = %11? +(S[LP]=1) +S[IREFST] = 0? +S[OSCINIT] = 1? +C5 = 0x01 +(C5[VDIV] = 1) +Figure 25-17. Flowchart of FEI to PEE mode transition using an 4 MHz crystal +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +597 +General Business Information + +![Image 1 from page 597](pdf-image://page_597_img_1) + +## Page 598 + +25.5.3.2 +Example 2: Moving from PEE to BLPI mode: MCGOUTCLK +frequency =32 kHz +In this example, the MCG will move through the proper operational modes from PEE +mode with a 4 MHz crystal configured for a 48 MHz MCGOUTCLK frequency (see +previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency. First, the +code sequence will be described. Then there is a flowchart that illustrates the sequence. +1. First, PEE must transition to PBE mode: +a. C1 = 0x90 +• C1[CLKS] set to 2'b10 to switch the system clock source to the external +reference clock. +b. Loop until S[CLKST] are 2'b10, indicating that the external reference clock is +selected to feed MCGOUTCLK. +2. Then, PBE must transition either directly to FBE mode or first through BLPE mode +and then to FBE mode: +a. BLPE: If a transition through BLPE mode is desired, first set C2[LP] to 1. +b. BLPE/FBE: C6 = 0x00 +• C6[PLLS] clear to 0 to select the FLL. At this time, with C1[FRDIV] value +of 3'b010, the FLL divider is set to 128, resulting in a reference frequency of +4 MHz / 128 = 31.25 kHz. If C1[FRDIV] was not previously set to 3'b010 +(necessary to achieve required 31.25–39.06 kHz FLL reference frequency +with an 4 MHz external source frequency), it must be changed prior to +clearing C6[PLLS] bit. In BLPE mode,changing this bit only prepares the +MCG for FLL usage in FBE mode. With C6[PLLS] = 0, the C6[VDIV0] +value does not matter. +c. BLPE: If transitioning through BLPE mode, clear C2[LP] to 0 here to switch to +FBE mode. +d. FBE: Loop until S[PLLST] is cleared, indicating that the current source for the +PLLS clock is the FLL. +3. Next, FBE mode transitions into FBI mode: +a. C1 = 0x54 +• C1[CLKS] set to 2'b01 to switch the system clock to the internal reference +clock. +Initialization / Application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +598 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 598](pdf-image://page_598_img_1) + +## Page 599 + +• C1[IREFS] set to 1 to select the internal reference clock as the reference +clock source. +• C1[FRDIV] remain unchanged because the reference divider does not affect +the internal reference. +b. Loop until S[IREFST] is 1, indicating the internal reference clock has been +selected as the reference clock source. +c. Loop until S[CLKST] are 2'b01, indicating that the internal reference clock is +selected to feed MCGOUTCLK. +4. Lastly, FBI transitions into BLPI mode. +a. C2 = 0x02 +• C2[LP] is 1 +• C2[RANGE0], C2[HGO0], C2[EREFS0], C1[IRCLKEN], and +C1[IREFSTEN] bits are ignored when the C1[IREFS] bit is set. They can +remain set, or be cleared at this point. +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +599 +General Business Information + +![Image 1 from page 599](pdf-image://page_599_img_1) + +## Page 600 + +START +IN PEE MODE +C1 = 0x90 +CHECK +S[CLKST] = %10 ? +NO +NO +NO +NO +YES +C2 = 0x02 +CONTINUE +IN BLPI MODE +YES +YES +CHECK +S[PLLST] = 0? +C1 = 0x54 +CHECK +S[IREFST] = 0? +CHECK +S[CLKST] = %01? +YES +NO +YES +(C2[LP] = 1) +C6 = 0x00 +IN +BLPE MODE ? +IN +BLPE MODE ? +NO +YES +C2 = 0x1C +(C2[LP] = 0) +C2 = 0x1E +ENTER +BLPE MODE ? +(C2[LP]=1) +Figure 25-18. Flowchart of PEE to BLPI mode transition using an 4 MHz crystal +Initialization / Application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +600 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 600](pdf-image://page_600_img_1) + +## Page 601 + +25.5.3.3 +Example 3: Moving from BLPI to FEE mode +In this example, the MCG will move through the proper operational modes from BLPI +mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see +previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz +MCGOUTCLK frequency. First, the code sequence will be described. Then there is a +flowchart that illustrates the sequence. +1. First, BLPI must transition to FBI mode. +a. C2 = 0x00 +• C2[LP] is 0 +2. Next, FBI will transition to FEE mode. +a. C2 = 0x1C +• C2[RANGE0] set to 2'b01 because the frequency of 4 MHz is within the +high frequency range. +• C2[HGO0] set to 1 to configure the crystal oscillator for high gain operation. +• C2[EREFS0] set to 1, because a crystal is being used. +b. C1 = 0x10 +• C1[CLKS] set to 2'b00 to select the output of the FLL as system clock +source. +• C1[FRDIV] remain at 3'b010, or divide-by-128 for a reference of 4 MHz / +128 = 31.25 kHz. +• C1[IREFS] cleared to 0, selecting the external reference clock. +c. Loop until S[OSCINIT0] is 1, indicating the crystal selected by the C2[EREFS0] +bit has been initialized. +d. Loop until S[IREFST] is 0, indicating the external reference clock is the current +source for the reference clock. +e. Loop until S[CLKST] are 2'b00, indicating that the output of the FLL is selected +to feed MCGOUTCLK. +f. Now, with a 31.25 kHz reference frequency, a fixed DCO multiplier of 640, +MCGOUTCLK = 31.25 kHz * 640 / 1 = 20 MHz. +g. At this point, by default, the C4[DRST\_DRS] bits are set to 2'b00 and +C4[DMX32] is cleared to 0. If the MCGOUTCLK frequency of 40 MHz is +desired instead, set the C4[DRST\_DRS] bits to 0x01 to switch the FLL +Chapter 25 Multipurpose Clock Generator (MCG) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +601 +General Business Information + +![Image 1 from page 601](pdf-image://page_601_img_1) + +## Page 602 + +multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency +to 20 MHz, set C4[DRST\_DRS] bits to 2'b00 again, and the FLL multiplication +factor will switch back to 640. +C1 = 0x10 +C2 = 0x00 +C2 = 0x1C +CHECK +CHECK +CHECK +S[OSCINIT] = 1 ? +CONTINUE +IN FEE MODE +NO +NO +NO +YES +YES +YES +START +IN BLPI MODE +S[IREFST] = 0? +S[CLKST] = %00? +Figure 25-19. Flowchart of BLPI to FEE mode transition using an 4 MHz crystal +Initialization / Application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +602 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 602](pdf-image://page_602_img_1) + +## Page 603 + +Chapter 26 +Oscillator (OSC) +26.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The OSC module is a crystal oscillator. The module, in conjunction with an external +crystal or resonator, generates a reference clock for the MCU. +26.2 +Features and Modes +Key features of the module are: +• Supports 32 kHz crystals (Low Range mode) +• Supports 3–8 MHz, 8–32 MHz crystals and resonators (High Range mode) +• Automatic Gain Control (AGC) to optimize power consumption in high frequency +ranges 3–8 MHz, 8–32 MHz using low-power mode +• High gain option in frequency ranges: 32 kHz, 3–8 MHz, and 8–32 MHz +• Voltage and frequency filtering to guarantee clock frequency and stability +• Optionally external input bypass clock from EXTAL signal directly +• One clock for MCU clock system +• Two clocks for on-chip peripherals that can work in Stop modes +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +603 +General Business Information + +![Image 1 from page 603](pdf-image://page_603_img_1) + +## Page 604 + +Functional Description describes the module's operation in more detail. +26.3 +Block Diagram +The OSC module uses a crystal or resonator to generate three filtered oscillator clock +signals. Three clocks are output from OSC module: OSCCLK for MCU system, +OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in +run mode. OSCERCLK and OSC32KCLK can work in low power modes. For the clock +source assignments, refer to the clock distribution information of this MCU. +Refer to the chip configuration chapter for the external reference clock source in this +MCU. +The following figure shows the block diagram of the OSC module. +XTAL +EXTAL +XTL\_CLK +CNT\_DONE\_4096 +OSC\_CLK\_OUT +Mux +4096 +Counter +OSC Clock Enable +STOP +OSC clock selection +OSCERCLK +ERCLKEN +OSCCLK +Range selections +Low Power config +OSC32KCLK +Oscillator Circuits +’ 0 +Control and Decoding +logic +ERCLKEN +EREFSTEN +OSC\_EN +Figure 26-1. OSC Module Block Diagram +26.4 +OSC Signal Descriptions +The following table shows the user-accessible signals available for the OSC module. +Refer to signal multiplexing information for this MCU for more details. +Block Diagram +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +604 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 604](pdf-image://page_604_img_1) + +## Page 605 + +Table 26-1. OSC Signal Descriptions +Signal +Description +I/O +EXTAL +External clock/Oscillator input +I +XTAL +Oscillator output +O +26.5 +External Crystal / Resonator Connections +The connections for a crystal/resonator frequency reference are shown in the following +figures. When using low-frequency, low-power mode, the only external component is the +crystal or ceramic resonator itself. In the other oscillator modes, load capacitors (Cx, Cy) +and feedback resistor (RF) are required. The following table shows all possible +connections. +Table 26-2. External Caystal/Resonator Connections +Oscillator Mode +Connections +Low-frequency (32 kHz), low-power +Connection 1 +Low-frequency (32 kHz), high-gain +Connection 2/Connection 31 +High-frequency (3~32 MHz), low-power +Connection 1/Connection 32,2 +High-frequency (3~32 MHz), high-gain +Connection 2/Connection 32 +1. +When the load capacitors (Cx, Cy) are greater than 30 pF, use Connection 3. +2. +With the low-power mode, the oscillator has the internal feedback resistor RF. Therefore, the feedback resistor must not be +externally with the Connection 3. +OSC +EXTAL +Crystal or Resonator +VSS +XTAL +Figure 26-2. Crystal/Ceramic Resonator Connections - Connection 1 +Chapter 26 Oscillator (OSC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +605 +General Business Information + +![Image 1 from page 605](pdf-image://page_605_img_1) + +## Page 606 + +OSC +VSS +RF +Crystal or Resonator +XTAL +EXTAL +Figure 26-3. Crystal/Ceramic Resonator Connections - Connection 2 +NOTE +Connection 1 and Connection 2 should use internal capacitors +as the load of the oscillator by configuring the CR[SCxP] bits. +OSC +VSS +Cx +Cy +RF +Crystal or Resonator +XTAL +EXTAL +Figure 26-4. Crystal/Ceramic Resonator Connections - Connection 3 +26.6 +External Clock Connections +In external clock mode, the pins can be connected as shown below. +NOTE +XTAL can be used as a GPIO when the GPIO alternate function +is configured for it. +External Clock Connections +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +606 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 606](pdf-image://page_606_img_1) + +## Page 607 + +OSC +VSS +Clock Input +I/O +XTAL +EXTAL +Figure 26-5. External Clock Connections +26.7 +Memory Map/Register Definitions +Some oscillator module register bits are typically incorporated into other peripherals such +as MCG or SIM. +OSC Memory Map/Register Definition +OSC memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4006\_5000 +OSC Control Register (OSC\_CR) +8 +R/W +000h +26.71.1/ +607 +26.71.1 +OSC Control Register (OSC\_CR) +NOTE +After OSC is enabled and starts generating the clocks, the +configurations such as low power and frequency range, must +not be changed. +Address: 4006\_5000h base + 0h offset = 4006\_5000h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +ERCLKEN +0 +EREFSTEN +0 +SC2P +SC4P +SC8P +SC16P +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +26.7.1 +Chapter 26 Oscillator (OSC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +607 +General Business Information + +![Image 1 from page 607](pdf-image://page_607_img_1) + +## Page 608 + +OSC\_CR field descriptions +Field +Description +7 +ERCLKEN +External Reference Enable +Enables external reference clock (OSCERCLK). +0 +External reference clock is inactive. +1 +External reference clock is enabled. +6 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +5 +EREFSTEN +External Reference Stop Enable +Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters +Stop mode. +0 +External reference clock is disabled in Stop mode. +1 +External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. +4 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +3 +SC2P +Oscillator 2 pF Capacitor Load Configure +Configures the oscillator load. +0 +Disable the selection. +1 +Add 2 pF capacitor to the oscillator load. +2 +SC4P +Oscillator 4 pF Capacitor Load Configure +Configures the oscillator load. +0 +Disable the selection. +1 +Add 4 pF capacitor to the oscillator load. +1 +SC8P +Oscillator 8 pF Capacitor Load Configure +Configures the oscillator load. +0 +Disable the selection. +1 +Add 8 pF capacitor to the oscillator load. +0 +SC16P +Oscillator 16 pF Capacitor Load Configure +Configures the oscillator load. +0 +Disable the selection. +1 +Add 16 pF capacitor to the oscillator load. +26.8 +Functional Description +This following sections provide functional details of the module. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +608 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 608](pdf-image://page_608_img_1) + +## Page 609 + +26.8.1 +OSC Module States +The states of the OSC module are shown in the following figure. The states and their +transitions between each other are described in this section. +Stable +Off +OSCCLK +CNT\_DONE\_4096 +Start-Up +OSCCLK requested +External Clock Mode +Oscillator ON, Stable +Oscillator OFF +Oscillator ON, not yet stable +Oscillator ON +OSC\_CLK\_OUT = Static +OSC\_CLK\_OUT = Static +OSC\_CLK\_OUT = EXTAL +OSC\_CLK\_OUT = XTL\_CLK +not requested +&& +Select OSC internal clock +OSCCLK requested +&& +Select clock from EXTAL signal +Figure 26-7. OSC Module State Diagram +NOTE +XTL\_CLK is the clock generated internally from OSC circuits. +26.8.1.1 +Off +The OSC enters the Off state when the system does not require OSC clocks. Upon +entering this state, XTL\_CLK is static unless OSC is configured to select the clock from +the EXTAL pad by clearing the external reference clock selection bit. For details +regarding the external reference clock source in this MCU, refer to the chip configuration +chapter. The EXTAL and XTAL pins are also decoupled from all other oscillator +circuitry in this state. The OSC module circuitry is configured to draw minimal current. +Chapter 26 Oscillator (OSC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +609 +General Business Information + +![Image 1 from page 609](pdf-image://page_609_img_1) + +## Page 610 + +26.8.1.2 +Oscillator Start-Up +The OSC enters start-up state when it is configured to generate clocks (internally the +OSC\_EN transitions high) using the internal oscillator circuits by setting the external +reference clock selection bit. In this state, the OSC module is enabled and oscillations are +starting up, but have not yet stabilized. When the oscillation amplitude becomes large +enough to pass through the input buffer, XTL\_CLK begins clocking the counter. When +the counter reaches 4096 cycles of XTL\_CLK, the oscillator is considered stable and +XTL\_CLK is passed to the output clock OSC\_CLK\_OUT. +26.8.1.3 +Oscillator Stable +The OSC enters stable state when it is configured to generate clocks (internally the +OSC\_EN transitions high) using the internal oscillator circuits by setting the external +reference clock selection bit and the counter reaches 4096 cycles of XTL\_CLK (when +CNT\_DONE\_4096 is high). In this state, the OSC module is producing a stable output +clock on OSC\_CLK\_OUT. Its frequency is determined by the external components being +used. +26.8.1.4 +External Clock Mode +The OSC enters external clock state when it is enabled and external reference clock +selection bit is cleared. For details regarding external reference clock source in this MCU, +refer to the chip configuration chapter. In this state, the OSC module is set to buffer (with +hysteresis) a clock from EXTAL onto the OSC\_CLK\_OUT. Its frequency is determined +by the external clock being supplied. +26.8.2 +OSC Module Modes +The OSC is a Pierce-type oscillator that supports external crystals or resonators operating +over the frequency ranges shown in Table 26-5. These modes assume the following +conditions: OSC is enabled to generate clocks (OSC\_EN=1), configured to generate +clocks internally (MCG\_C2[EREFS] = 1), and some or one of the other peripherals +(MCG, Timer, and so on) is configured to use the oscillator output clock +(OSC\_CLK\_OUT). +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +610 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 610](pdf-image://page_610_img_1) + +## Page 611 + +Table 26-5. Oscillator Modes +Mode +Frequency Range +Low-frequency, high-gain +fosc\_lo (1 kHz) up to fosc\_lo (32.768 kHz) +Low-frequency, low-power (VLP) +High-frequency mode1, high-gain +fosc\_hi\_1 (3 MHz) up to fosc\_hi\_1 (8 MHz) +High-frequency mode1, low-power +High-frequency mode2, high-gain +fosc\_hi\_2 (8 MHz) up to fosc\_hi\_2 (32 MHz) +High-frequency mode2, low-power +NOTE +For information about low power modes of operation used in +this chip and their alignment with some OSC modes, refer to +the chip's Power Management details. +26.8.2.1 +Low-Frequency, High-Gain Mode +In Low-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. +The gain is set to achieve rail-to-rail oscillation amplitudes. +The oscillator input buffer in this mode is single-ended. It provides low pass frequency +filtering as well as hysteresis for voltage filtering and converts the output to logic levels. +In this mode, the internal capacitors could be used. +26.8.2.2 +Low-Frequency, Low-Power Mode +In low-frequency, low-power mode, the oscillator uses a gain control loop to minimize +power consumption. As the oscillation amplitude increases, the amplifier current is +reduced. This continues until a desired amplitude is achieved at steady-state. This mode +provides low pass frequency filtering as well as hysteresis for voltage filtering and +converts the output to logic levels. In this mode, the internal capacitors could be used, the +internal feedback resistor is connected, and no external resistor should be used. +In this mode, the amplifier inputs, gain-control input, and input buffer input are all +capacitively coupled for leakage tolerance (not sensitive to the DC level of EXTAL). +Also in this mode, all external components except for the resonator itself are integrated, +which includes the load capacitors and feeback resistor that biases EXTAL. +Chapter 26 Oscillator (OSC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +611 +General Business Information + +![Image 1 from page 611](pdf-image://page_611_img_1) + +## Page 612 + +26.8.2.3 +High-Frequency, High-Gain Mode +In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. +The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass +frequency filtering as well as hysteresis for voltage filtering and converts the output to +logic levels. In this mode, the internal capacitors could be used. +26.8.2.4 +High-Frequency, Low-Power Mode +In high-frequency, low-power mode, the oscillator uses a gain control loop to minimize +power consumption. As the oscillation amplitude increases, the amplifier current is +reduced. This continues until a desired amplitude is achieved at steady-state. In this +mode, the internal capacitors could be used, the internal feedback resistor is connected, +and no external resistor should be used. +The oscillator input buffer in this mode is differential. It provides low pass frequency +filtering as well as hysteresis for voltage filtering and converts the output to logic levels. +26.8.3 +Counter +The oscillator output clock (OSC\_CLK\_OUT) is gated off until the counter has detected +4096 cycles of its input clock (XTL\_CLK). After 4096 cycles are completed, the counter +passes XTL\_CLK onto OSC\_CLK\_OUT. This counting time-out is used to guarantee +output clock stability. +26.8.4 +Reference Clock Pin Requirements +The OSC module requires use of both the EXTAL and XTAL pins to generate an output +clock in Oscillator mode, but requires only the EXTAL pin in External clock mode. The +EXTAL and XTAL pins are available for I/O. For the implementation of these pins on +this device, refer to the Signal Multiplexing chapter. +26.9 +Reset +There is no reset state associated with the OSC module. The counter logic is reset when +the OSC is not configured to generate clocks. +There are no sources of reset requests for the OSC module. +Reset +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +612 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 612](pdf-image://page_612_img_1) + +## Page 613 + +26.10 +Low Power Modes Operation +When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and +EREFSETN bit settings. If both these bits are set, the OSC is in operation. In Low +Leakage Stop (LLS) modes, the OSC holds all register settings. If ERCLKEN and +EREFSTEN bits are set before entry to Low Leakage Stop modes, the OSC is still +functional in these modes. After waking up from Very Low Leakage Stop (VLLSx) +modes, all OSC register bits are reset and initialization is required through software. +26.11 +Interrupts +The OSC module does not generate any interrupts. +Chapter 26 Oscillator (OSC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +613 +General Business Information + +![Image 1 from page 613](pdf-image://page_613_img_1) + +## Page 614 + +Interrupts +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +614 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 614](pdf-image://page_614_img_1) + +## Page 615 + +Chapter 27 +RTC Oscillator +27.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The RTC oscillator module provides the clock source for the RTC. The RTC oscillator +module, in conjunction with an external crystal, generates a reference clock for the RTC. +27.1.1 +Features and Modes +The key features of the RTC oscillator are as follows: +• Supports 32 kHz crystals with very low power +• Consists of internal feed back resistor +• Consists of internal programmable capacitors as the Cload of the oscillator +• Automatic Gain Control (AGC) to optimize power consumption +The RTC oscillator operations are described in detail in Functional Description . +27.1.2 +Block Diagram +The following is the block diagram of the RTC oscillator. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +615 +General Business Information + +![Image 1 from page 615](pdf-image://page_615_img_1) + +## Page 616 + +gm +control +clk out for RTC +PAD +PAD +XTAL32 +C2 +Amplitude +EXTAL32 +Rf +C1 +detector +Figure 27-1. RTC Oscillator Block Diagram +27.2 +RTC Signal Descriptions +The following table shows the user-accessible signals available for the RTC oscillator. +See the chip-level specification to find out which signals are actually connected to the +external pins. +Table 27-1. RTC Signal Descriptions +Signal +Description +I/O +EXTAL32 +Oscillator Input +I +XTAL32 +Oscillator Output +O +27.2.1 +EXTAL32 — Oscillator Input +This signal is the analog input of the RTC oscillator. +27.2.2 +XTAL32 — Oscillator Output +This signal is the analog output of the RTC oscillator module. +RTC Signal Descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +616 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 616](pdf-image://page_616_img_1) + +## Page 617 + +27.3 +External Crystal Connections +The connections with a crystal is shown in the following figure. External load capacitors +and feedback resistor are not required. +RTC Oscillator Module +EXTAL32 +Crystal or Resonator +XTAL32 +VSS +Figure 27-2. Crystal Connections +27.4 +Memory Map/Register Descriptions +RTC oscillator control bits are part of the RTC registers. Refer to RTC\_CR for more +details. +27.5 +Functional Description +As shown in Figure 27-1, the module includes an amplifier which supplies the negative +resistor for the RTC oscillator. The gain of the amplifier is controlled by the amplitude +detector, which optimizes the power consumption. A schmitt trigger is used to translate +the sine-wave generated by this oscillator to a pulse clock out, which is a reference clock +for the RTC digital core. +The oscillator includes an internal feedback resistor of approximately 100 MΩ between +EXTAL32 and XTAL32. +In addition, there are two programmable capacitors with this oscillator, which can be +used as the Cload of the oscillator. The programmable range is from 0pF to 30pF. +Chapter 27 RTC Oscillator +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +617 +General Business Information + +![Image 1 from page 617](pdf-image://page_617_img_1) + +## Page 618 + +27.6 +Reset Overview +There is no reset state associated with the RTC oscillator. +27.7 +Interrupts +The RTC oscillator does not generate any interrupts. +Reset Overview +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +618 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 618](pdf-image://page_618_img_1) + +## Page 619 + +Chapter 28 +Flash Memory Controller (FMC) +28.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The Flash Memory Controller (FMC) is a memory acceleration unit that provides: +• an interface between the device and the dual-bank nonvolatile memory. Bank 0 +consists of program flash memory, and bank 1 consists of FlexNVM. +• buffers that can accelerate flash memory and FlexNVM data transfers. +28.1.1 +Overview +The Flash Memory Controller manages the interface between the device and the dual- +bank flash memory. The FMC receives status information detailing the configuration of +the memory and uses this information to ensure a proper interface. The following table +shows the supported read/write operations. +Flash memory type +Read +Write +Program flash memory +8-bit, 16-bit, and 32-bit reads +—1 +FlexNVM used as Data flash memory +8-bit, 16-bit, and 32-bit reads +—1 +FlexNVM and FlexRAM used as +EEPROM +8-bit, 16-bit, and 32-bit reads +8-bit, 16-bit, and 32-bit writes +1. +A write operation to program flash memory or to FlexNVM used as data flash memory results in a bus error. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +619 +General Business Information + +![Image 1 from page 619](pdf-image://page_619_img_1) + +## Page 620 + +In addition, for bank 0 and bank 1, the FMC provides three separate mechanisms for +accelerating the interface between the device and the flash memory. A 64-bit speculation +buffer can prefetch the next 64-bit flash memory location, and both a 4-way, 8-set cache +and a single-entry 64-bit buffer can store previously accessed flash memory or FlexNVM +data for quick access times. +28.1.2 +Features +The FMC's features include: +• Interface between the device and the dual-bank flash memory and FlexMemory: +• 8-bit, 16-bit, and 32-bit read operations to program flash memory and FlexNVM +used as data flash memory. +• 8-bit, 16-bit, and 32-bit read and write operations to FlexNVM and FlexRAM +used as EEPROM. +• For bank 0 and bank 1: Read accesses to consecutive 32-bit spaces in memory +return the second read data with no wait states. The memory returns 64 bits via +the 32-bit bus access. +• Crossbar master access protection for setting no access, read-only access, write- +only access, or read/write access for each crossbar master. +• For bank 0 and bank 1: Acceleration of data transfer from program flash memory and +FlexMemory to the device: +• 64-bit prefetch speculation buffer with controls for instruction/data access per +master and bank +• 4-way, 8-set, 64-bit line size cache for a total of thirty-two 64-bit entries with +controls for replacement algorithm and lock per way for each bank +• Single-entry buffer with enable per bank +• Invalidation control for the speculation buffer and the single-entry buffer +28.2 +Modes of operation +The FMC only operates when the device accesses the flash memory or FlexMemory. +In terms of device power modes, the FMC only operates in run and wait modes, including +VLPR and VLPW modes. +For any device power mode where the flash memory or FlexMemory cannot be accessed, +the FMC is disabled. +Modes of operation +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +620 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 620](pdf-image://page_620_img_1) + +## Page 621 + +28.3 +External signal description +The FMC has no external signals. +28.4 +Memory map and register descriptions +The programming model consists of the FMC control registers and the program visible +cache (data and tag/valid entries). +NOTE +Program the registers only while the flash controller is idle (for +example, execute from RAM). Changing configuration settings +while a flash access is in progress can lead to non-deterministic +behavior. +Table 28-2. FMC register access +Registers +Read access +Write access +Mode +Length +Mode +Length +Control registers: +PFAPR, PFB0CR, +PFB1CR +Supervisor (privileged) +mode or user mode +32 bits +Supervisor (privileged) +mode only +32 bits +Cache registers +Supervisor (privileged) +mode or user mode +32 bits +Supervisor (privileged) +mode only +32 bits +NOTE +Accesses to unimplemented registers within the FMC's 4 KB +address space return a bus error. +The cache entries, both data and tag/valid, can be read at any time. +NOTE +System software is required to maintain memory coherence +when any segment of the flash cache is programmed. For +example, all buffer data associated with the reprogrammed flash +should be invalidated. Accordingly, cache program visible +writes must occur after a programming or erase event is +completed and before the new memory image is accessed. +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +621 +General Business Information + +![Image 1 from page 621](pdf-image://page_621_img_1) + +## Page 622 + +The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and +the sets are numbered 0-7. The following table elaborates on the tag/valid and data +entries. +Table 28-3. Program visible cache registers +Cache +storage +Based at +offset +Contents of 32-bit read +Nomenclature +Nomenclature example +Tag +100h +13'h0, tag[18:6], 5'h0, valid +In TAGVDWxSy, x denotes the way +and y denotes the set. +TAGVDW2S0 is the 13-bit tag +and 1-bit valid for cache entry +way 2, set 0. +Data +200h +Upper or lower longword of +data +In DATAWxSyU and DATAWxSyL, x +denotes the way, y denotes the set, +and U and L represent upper and +lower word, respectively. +DATAW1S0U represents bits +[63:32] of data entry way 1, +set 0, and DATAW1S0L +represents bits [31:0] of data +entry way 1, set 0. +FMC memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4001\_F000 +Flash Access Protection Register (FMC\_PFAPR) +32 +R/W +00\_F800 +\_3FF8 +\_003Fh +28.4.1/627 +4001\_F004 +Flash Bank 0 Control Register (FMC\_PFB0CR) +32 +R/W +3002\_001F +\_3002\_001Fh +28.4.2/630 +4001\_F008 +Flash Bank 1 Control Register (FMC\_PFB1CR) +32 +R/W +3002\_001F +\_3002\_001Fh +28.4.3/633 +4001\_F100 +Cache Tag Storage (FMC\_TAGVDW0S0) +32 +R/W +0\_0000 +\_0000h +28.4.4/635 +4001\_F104 +Cache Tag Storage (FMC\_TAGVDW0S1) +32 +R/W +0\_0000 +\_0000h +28.4.4/635 +4001\_F108 +Cache Tag Storage (FMC\_TAGVDW0S2) +32 +R/W +0\_0000 +\_0000h +28.4.4/635 +4001\_F10C +Cache Tag Storage (FMC\_TAGVDW0S3) +32 +R/W +0\_0000 +\_0000h +28.4.4/635 +4001\_F110 +Cache Tag Storage (FMC\_TAGVDW0S4) +32 +R/W +0\_0000 +\_0000h +28.4.4/635 +4001\_F114 +Cache Tag Storage (FMC\_TAGVDW0S5) +32 +R/W +0\_0000 +\_0000h +28.4.4/635 +4001\_F118 +Cache Tag Storage (FMC\_TAGVDW0S6) +32 +R/W +0\_0000 +\_0000h +28.4.4/635 +4001\_F11C +Cache Tag Storage (FMC\_TAGVDW0S7) +32 +R/W +0\_0000 +\_0000h +28.4.4/635 +4001\_F120 +Cache Tag Storage (FMC\_TAGVDW1S0) +32 +R/W +0\_0000 +\_0000h +28.4.5/636 +4001\_F124 +Cache Tag Storage (FMC\_TAGVDW1S1) +32 +R/W +0\_0000 +\_0000h +28.4.5/636 +Table continues on the next page... +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +622 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 622](pdf-image://page_622_img_1) + +## Page 623 + +FMC memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4001\_F128 +Cache Tag Storage (FMC\_TAGVDW1S2) +32 +R/W +0\_0000 +\_0000h +28.4.5/636 +4001\_F12C +Cache Tag Storage (FMC\_TAGVDW1S3) +32 +R/W +0\_0000 +\_0000h +28.4.5/636 +4001\_F130 +Cache Tag Storage (FMC\_TAGVDW1S4) +32 +R/W +0\_0000 +\_0000h +28.4.5/636 +4001\_F134 +Cache Tag Storage (FMC\_TAGVDW1S5) +32 +R/W +0\_0000 +\_0000h +28.4.5/636 +4001\_F138 +Cache Tag Storage (FMC\_TAGVDW1S6) +32 +R/W +0\_0000 +\_0000h +28.4.5/636 +4001\_F13C +Cache Tag Storage (FMC\_TAGVDW1S7) +32 +R/W +0\_0000 +\_0000h +28.4.5/636 +4001\_F140 +Cache Tag Storage (FMC\_TAGVDW2S0) +32 +R/W +0\_0000 +\_0000h +28.4.6/637 +4001\_F144 +Cache Tag Storage (FMC\_TAGVDW2S1) +32 +R/W +0\_0000 +\_0000h +28.4.6/637 +4001\_F148 +Cache Tag Storage (FMC\_TAGVDW2S2) +32 +R/W +0\_0000 +\_0000h +28.4.6/637 +4001\_F14C +Cache Tag Storage (FMC\_TAGVDW2S3) +32 +R/W +0\_0000 +\_0000h +28.4.6/637 +4001\_F150 +Cache Tag Storage (FMC\_TAGVDW2S4) +32 +R/W +0\_0000 +\_0000h +28.4.6/637 +4001\_F154 +Cache Tag Storage (FMC\_TAGVDW2S5) +32 +R/W +0\_0000 +\_0000h +28.4.6/637 +4001\_F158 +Cache Tag Storage (FMC\_TAGVDW2S6) +32 +R/W +0\_0000 +\_0000h +28.4.6/637 +4001\_F15C +Cache Tag Storage (FMC\_TAGVDW2S7) +32 +R/W +0\_0000 +\_0000h +28.4.6/637 +4001\_F160 +Cache Tag Storage (FMC\_TAGVDW3S0) +32 +R/W +0\_0000 +\_0000h +28.4.7/638 +4001\_F164 +Cache Tag Storage (FMC\_TAGVDW3S1) +32 +R/W +0\_0000 +\_0000h +28.4.7/638 +4001\_F168 +Cache Tag Storage (FMC\_TAGVDW3S2) +32 +R/W +0\_0000 +\_0000h +28.4.7/638 +4001\_F16C +Cache Tag Storage (FMC\_TAGVDW3S3) +32 +R/W +0\_0000 +\_0000h +28.4.7/638 +4001\_F170 +Cache Tag Storage (FMC\_TAGVDW3S4) +32 +R/W +0\_0000 +\_0000h +28.4.7/638 +4001\_F174 +Cache Tag Storage (FMC\_TAGVDW3S5) +32 +R/W +0\_0000 +\_0000h +28.4.7/638 +4001\_F178 +Cache Tag Storage (FMC\_TAGVDW3S6) +32 +R/W +0\_0000 +\_0000h +28.4.7/638 +4001\_F17C +Cache Tag Storage (FMC\_TAGVDW3S7) +32 +R/W +0\_0000 +\_0000h +28.4.7/638 +Table continues on the next page... +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +623 +General Business Information + +![Image 1 from page 623](pdf-image://page_623_img_1) + +## Page 624 + +FMC memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4001\_F200 +Cache Data Storage (upper word) (FMC\_DATAW0S0U) +32 +R/W +0\_0000 +\_0000h +28.4.8/638 +4001\_F204 +Cache Data Storage (lower word) (FMC\_DATAW0S0L) +32 +R/W +0\_0000 +\_0000h +28.4.9/639 +4001\_F208 +Cache Data Storage (upper word) (FMC\_DATAW0S1U) +32 +R/W +0\_0000 +\_0000h +28.4.8/638 +4001\_F20C +Cache Data Storage (lower word) (FMC\_DATAW0S1L) +32 +R/W +0\_0000 +\_0000h +28.4.9/639 +4001\_F210 +Cache Data Storage (upper word) (FMC\_DATAW0S2U) +32 +R/W +0\_0000 +\_0000h +28.4.8/638 +4001\_F214 +Cache Data Storage (lower word) (FMC\_DATAW0S2L) +32 +R/W +0\_0000 +\_0000h +28.4.9/639 +4001\_F218 +Cache Data Storage (upper word) (FMC\_DATAW0S3U) +32 +R/W +0\_0000 +\_0000h +28.4.8/638 +4001\_F21C +Cache Data Storage (lower word) (FMC\_DATAW0S3L) +32 +R/W +0\_0000 +\_0000h +28.4.9/639 +4001\_F220 +Cache Data Storage (upper word) (FMC\_DATAW0S4U) +32 +R/W +0\_0000 +\_0000h +28.4.8/638 +4001\_F224 +Cache Data Storage (lower word) (FMC\_DATAW0S4L) +32 +R/W +0\_0000 +\_0000h +28.4.9/639 +4001\_F228 +Cache Data Storage (upper word) (FMC\_DATAW0S5U) +32 +R/W +0\_0000 +\_0000h +28.4.8/638 +4001\_F22C +Cache Data Storage (lower word) (FMC\_DATAW0S5L) +32 +R/W +0\_0000 +\_0000h +28.4.9/639 +4001\_F230 +Cache Data Storage (upper word) (FMC\_DATAW0S6U) +32 +R/W +0\_0000 +\_0000h +28.4.8/638 +4001\_F234 +Cache Data Storage (lower word) (FMC\_DATAW0S6L) +32 +R/W +0\_0000 +\_0000h +28.4.9/639 +4001\_F238 +Cache Data Storage (upper word) (FMC\_DATAW0S7U) +32 +R/W +0\_0000 +\_0000h +28.4.8/638 +4001\_F23C +Cache Data Storage (lower word) (FMC\_DATAW0S7L) +32 +R/W +0\_0000 +\_0000h +28.4.9/639 +4001\_F240 +Cache Data Storage (upper word) (FMC\_DATAW1S0U) +32 +R/W +0\_0000 +\_0000h +28.4.10/ +639 +4001\_F244 +Cache Data Storage (lower word) (FMC\_DATAW1S0L) +32 +R/W +0\_0000 +\_0000h +28.4.11/ +640 +4001\_F248 +Cache Data Storage (upper word) (FMC\_DATAW1S1U) +32 +R/W +0\_0000 +\_0000h +28.4.10/ +639 +4001\_F24C +Cache Data Storage (lower word) (FMC\_DATAW1S1L) +32 +R/W +0\_0000 +\_0000h +28.4.11/ +640 +4001\_F250 +Cache Data Storage (upper word) (FMC\_DATAW1S2U) +32 +R/W +0\_0000 +\_0000h +28.4.10/ +639 +4001\_F254 +Cache Data Storage (lower word) (FMC\_DATAW1S2L) +32 +R/W +0\_0000 +\_0000h +28.4.11/ +640 +Table continues on the next page... +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +624 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 624](pdf-image://page_624_img_1) + +## Page 625 + +FMC memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4001\_F258 +Cache Data Storage (upper word) (FMC\_DATAW1S3U) +32 +R/W +0\_0000 +\_0000h +28.4.10/ +639 +4001\_F25C +Cache Data Storage (lower word) (FMC\_DATAW1S3L) +32 +R/W +0\_0000 +\_0000h +28.4.11/ +640 +4001\_F260 +Cache Data Storage (upper word) (FMC\_DATAW1S4U) +32 +R/W +0\_0000 +\_0000h +28.4.10/ +639 +4001\_F264 +Cache Data Storage (lower word) (FMC\_DATAW1S4L) +32 +R/W +0\_0000 +\_0000h +28.4.11/ +640 +4001\_F268 +Cache Data Storage (upper word) (FMC\_DATAW1S5U) +32 +R/W +0\_0000 +\_0000h +28.4.10/ +639 +4001\_F26C +Cache Data Storage (lower word) (FMC\_DATAW1S5L) +32 +R/W +0\_0000 +\_0000h +28.4.11/ +640 +4001\_F270 +Cache Data Storage (upper word) (FMC\_DATAW1S6U) +32 +R/W +0\_0000 +\_0000h +28.4.10/ +639 +4001\_F274 +Cache Data Storage (lower word) (FMC\_DATAW1S6L) +32 +R/W +0\_0000 +\_0000h +28.4.11/ +640 +4001\_F278 +Cache Data Storage (upper word) (FMC\_DATAW1S7U) +32 +R/W +0\_0000 +\_0000h +28.4.10/ +639 +4001\_F27C +Cache Data Storage (lower word) (FMC\_DATAW1S7L) +32 +R/W +0\_0000 +\_0000h +28.4.11/ +640 +4001\_F280 +Cache Data Storage (upper word) (FMC\_DATAW2S0U) +32 +R/W +0\_0000 +\_0000h +28.4.12/ +640 +4001\_F284 +Cache Data Storage (lower word) (FMC\_DATAW2S0L) +32 +R/W +0\_0000 +\_0000h +28.4.13/ +641 +4001\_F288 +Cache Data Storage (upper word) (FMC\_DATAW2S1U) +32 +R/W +0\_0000 +\_0000h +28.4.12/ +640 +4001\_F28C +Cache Data Storage (lower word) (FMC\_DATAW2S1L) +32 +R/W +0\_0000 +\_0000h +28.4.13/ +641 +4001\_F290 +Cache Data Storage (upper word) (FMC\_DATAW2S2U) +32 +R/W +0\_0000 +\_0000h +28.4.12/ +640 +4001\_F294 +Cache Data Storage (lower word) (FMC\_DATAW2S2L) +32 +R/W +0\_0000 +\_0000h +28.4.13/ +641 +4001\_F298 +Cache Data Storage (upper word) (FMC\_DATAW2S3U) +32 +R/W +0\_0000 +\_0000h +28.4.12/ +640 +4001\_F29C +Cache Data Storage (lower word) (FMC\_DATAW2S3L) +32 +R/W +0\_0000 +\_0000h +28.4.13/ +641 +4001\_F2A0 +Cache Data Storage (upper word) (FMC\_DATAW2S4U) +32 +R/W +0\_0000 +\_0000h +28.4.12/ +640 +4001\_F2A4 +Cache Data Storage (lower word) (FMC\_DATAW2S4L) +32 +R/W +0\_0000 +\_0000h +28.4.13/ +641 +4001\_F2A8 +Cache Data Storage (upper word) (FMC\_DATAW2S5U) +32 +R/W +0\_0000 +\_0000h +28.4.12/ +640 +4001\_F2AC +Cache Data Storage (lower word) (FMC\_DATAW2S5L) +32 +R/W +0\_0000 +\_0000h +28.4.13/ +641 +Table continues on the next page... +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +625 +General Business Information + +![Image 1 from page 625](pdf-image://page_625_img_1) + +## Page 626 + +FMC memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4001\_F2B0 +Cache Data Storage (upper word) (FMC\_DATAW2S6U) +32 +R/W +0\_0000 +\_0000h +28.4.12/ +640 +4001\_F2B4 +Cache Data Storage (lower word) (FMC\_DATAW2S6L) +32 +R/W +0\_0000 +\_0000h +28.4.13/ +641 +4001\_F2B8 +Cache Data Storage (upper word) (FMC\_DATAW2S7U) +32 +R/W +0\_0000 +\_0000h +28.4.12/ +640 +4001\_F2BC +Cache Data Storage (lower word) (FMC\_DATAW2S7L) +32 +R/W +0\_0000 +\_0000h +28.4.13/ +641 +4001\_F2C0 +Cache Data Storage (upper word) (FMC\_DATAW3S0U) +32 +R/W +0\_0000 +\_0000h +28.4.14/ +641 +4001\_F2C4 +Cache Data Storage (lower word) (FMC\_DATAW3S0L) +32 +R/W +0\_0000 +\_0000h +28.4.15/ +642 +4001\_F2C8 +Cache Data Storage (upper word) (FMC\_DATAW3S1U) +32 +R/W +0\_0000 +\_0000h +28.4.14/ +641 +4001\_F2CC +Cache Data Storage (lower word) (FMC\_DATAW3S1L) +32 +R/W +0\_0000 +\_0000h +28.4.15/ +642 +4001\_F2D0 +Cache Data Storage (upper word) (FMC\_DATAW3S2U) +32 +R/W +0\_0000 +\_0000h +28.4.14/ +641 +4001\_F2D4 +Cache Data Storage (lower word) (FMC\_DATAW3S2L) +32 +R/W +0\_0000 +\_0000h +28.4.15/ +642 +4001\_F2D8 +Cache Data Storage (upper word) (FMC\_DATAW3S3U) +32 +R/W +0\_0000 +\_0000h +28.4.14/ +641 +4001\_F2DC +Cache Data Storage (lower word) (FMC\_DATAW3S3L) +32 +R/W +0\_0000 +\_0000h +28.4.15/ +642 +4001\_F2E0 +Cache Data Storage (upper word) (FMC\_DATAW3S4U) +32 +R/W +0\_0000 +\_0000h +28.4.14/ +641 +4001\_F2E4 +Cache Data Storage (lower word) (FMC\_DATAW3S4L) +32 +R/W +0\_0000 +\_0000h +28.4.15/ +642 +4001\_F2E8 +Cache Data Storage (upper word) (FMC\_DATAW3S5U) +32 +R/W +0\_0000 +\_0000h +28.4.14/ +641 +4001\_F2EC +Cache Data Storage (lower word) (FMC\_DATAW3S5L) +32 +R/W +0\_0000 +\_0000h +28.4.15/ +642 +4001\_F2F0 +Cache Data Storage (upper word) (FMC\_DATAW3S6U) +32 +R/W +0\_0000 +\_0000h +28.4.14/ +641 +4001\_F2F4 +Cache Data Storage (lower word) (FMC\_DATAW3S6L) +32 +R/W +0\_0000 +\_0000h +28.4.15/ +642 +4001\_F2F8 +Cache Data Storage (upper word) (FMC\_DATAW3S7U) +32 +R/W +0\_0000 +\_0000h +28.4.14/ +641 +4001\_F2FC +Cache Data Storage (lower word) (FMC\_DATAW3S7L) +32 +R/W +0\_0000 +\_0000h +28.4.15/ +642 +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +626 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 626](pdf-image://page_626_img_1) + +## Page 627 + +28.4.1 +Flash Access Protection Register (FMC\_PFAPR) +Address: 4001\_F000h base + 0h offset = 4001\_F000h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +M7PFD +M6PFD +M5PFD +M4PFD +M3PFD +M2PFD +M1PFD +M0PFD +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +M7AP[1:0] +M6AP[1:0] +M5AP[1:0] +M4AP[1:0] +M3AP[1:0] +M2AP[1:0] +M1AP[1:0] +M0AP[1:0] +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +1 +FMC\_PFAPR field descriptions +Field +Description +31–24 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +23 +M7PFD +Master 7 Prefetch Disable +These bits control whether prefetching is enabled based on the logical number of the requesting crossbar +switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. +0 +Prefetching for this master is enabled. +1 +Prefetching for this master is disabled. +22 +M6PFD +Master 6 Prefetch Disable +These bits control whether prefetching is enabled based on the logical number of the requesting crossbar +switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. +0 +Prefetching for this master is enabled. +1 +Prefetching for this master is disabled. +21 +M5PFD +Master 5 Prefetch Disable +These bits control whether prefetching is enabled based on the logical number of the requesting crossbar +switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. +0 +Prefetching for this master is enabled. +1 +Prefetching for this master is disabled. +20 +M4PFD +Master 4 Prefetch Disable +These bits control whether prefetching is enabled based on the logical number of the requesting crossbar +switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. +0 +Prefetching for this master is enabled. +1 +Prefetching for this master is disabled. +Table continues on the next page... +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +627 +General Business Information + +![Image 1 from page 627](pdf-image://page_627_img_1) + +## Page 628 + +FMC\_PFAPR field descriptions (continued) +Field +Description +19 +M3PFD +Master 3 Prefetch Disable +These bits control whether prefetching is enabled based on the logical number of the requesting crossbar +switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. +0 +Prefetching for this master is enabled. +1 +Prefetching for this master is disabled. +18 +M2PFD +Master 2 Prefetch Disable +These bits control whether prefetching is enabled based on the logical number of the requesting crossbar +switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. +0 +Prefetching for this master is enabled. +1 +Prefetching for this master is disabled. +17 +M1PFD +Master 1 Prefetch Disable +These bits control whether prefetching is enabled based on the logical number of the requesting crossbar +switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. +0 +Prefetching for this master is enabled. +1 +Prefetching for this master is disabled. +16 +M0PFD +Master 0 Prefetch Disable +These bits control whether prefetching is enabled based on the logical number of the requesting crossbar +switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. +0 +Prefetching for this master is enabled. +1 +Prefetching for this master is disabled. +15–14 +M7AP[1:0] +Master 7 Access Protection +This field controls whether read and write access to the flash are allowed based on the logical master +number of the requesting crossbar switch master. +00 +No access may be performed by this master. +01 +Only read accesses may be performed by this master. +10 +Only write accesses may be performed by this master. +11 +Both read and write accesses may be performed by this master. +13–12 +M6AP[1:0] +Master 6 Access Protection +This field controls whether read and write access to the flash are allowed based on the logical master +number of the requesting crossbar switch master. +00 +No access may be performed by this master +01 +Only read accesses may be performed by this master +10 +Only write accesses may be performed by this master +11 +Both read and write accesses may be performed by this master +11–10 +M5AP[1:0] +Master 5 Access Protection +This field controls whether read and write access to the flash are allowed based on the logical master +number of the requesting crossbar switch master. +00 +No access may be performed by this master +Table continues on the next page... +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +628 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 628](pdf-image://page_628_img_1) + +## Page 629 + +FMC\_PFAPR field descriptions (continued) +Field +Description +01 +Only read accesses may be performed by this master +10 +Only write accesses may be performed by this master +11 +Both read and write accesses may be performed by this master +9–8 +M4AP[1:0] +Master 4 Access Protection +This field controls whether read and write access to the flash are allowed based on the logical master +number of the requesting crossbar switch master. +00 +No access may be performed by this master +01 +Only read accesses may be performed by this master +10 +Only write accesses may be performed by this master +11 +Both read and write accesses may be performed by this master +7–6 +M3AP[1:0] +Master 3 Access Protection +This field controls whether read and write access to the flash are allowed based on the logical master +number of the requesting crossbar switch master. +00 +No access may be performed by this master +01 +Only read accesses may be performed by this master +10 +Only write accesses may be performed by this master +11 +Both read and write accesses may be performed by this master +5–4 +M2AP[1:0] +Master 2 Access Protection +This field controls whether read and write access to the flash are allowed based on the logical master +number of the requesting crossbar switch master. +00 +No access may be performed by this master +01 +Only read accesses may be performed by this master +10 +Only write accesses may be performed by this master +11 +Both read and write accesses may be performed by this master +3–2 +M1AP[1:0] +Master 1 Access Protection +This field controls whether read and write access to the flash are allowed based on the logical master +number of the requesting crossbar switch master. +00 +No access may be performed by this master +01 +Only read accesses may be performed by this master +10 +Only write accesses may be performed by this master +11 +Both read and write accesses may be performed by this master +1–0 +M0AP[1:0] +Master 0 Access Protection +This field controls whether read and write access to the flash are allowed based on the logical master +number of the requesting crossbar switch master. +00 +No access may be performed by this master +01 +Only read accesses may be performed by this master +10 +Only write accesses may be performed by this master +11 +Both read and write accesses may be performed by this master +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +629 +General Business Information + +![Image 1 from page 629](pdf-image://page_629_img_1) + +## Page 630 + +28.4.2 +Flash Bank 0 Control Register (FMC\_PFB0CR) +Address: 4001\_F000h base + 4h offset = 4001\_F004h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +B0RWSC[3:0] +CLCK\_WAY[3:0] +0 +0 +B0MW[1:0] +0 +W +CINV\_WAY[3:0] +S\_B\_ +INV +Reset +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +CRC[2:0] +B0DCE +B0ICE +B0DPE +B0IPE +B0SEBE +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +FMC\_PFB0CR field descriptions +Field +Description +31–28 +B0RWSC[3:0] +Bank 0 Read Wait State Control +This read-only field defines the number of wait states required to access the bank 0 flash memory. +The relationship between the read access time of the flash array (expressed in system clock cycles) and +RWSC is defined as: +Access time of flash array [system clocks] = RWSC + 1 +The FMC automatically calculates this value based on the ratio of the system clock speed to the flash +clock speed. For example, when this ratio is 4:1, the field's value is 3h. +27–24 +CLCK\_WAY[3:0] +Cache Lock Way x +These bits determine if the given cache way is locked such that its contents will not be displaced by future +misses. +The bit setting definitions are for each bit in the field. +0 +Cache way is unlocked and may be displaced +1 +Cache way is locked and its contents are not displaced +23–20 +CINV\_WAY[3:0] +Cache Invalidate Way x +Table continues on the next page... +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +630 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 630](pdf-image://page_630_img_1) + +## Page 631 + +FMC\_PFB0CR field descriptions (continued) +Field +Description +These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is +written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents +are cleared. This field always reads as zero. +Cache invalidation takes precedence over locking. The cache is invalidated by system reset. System +software is required to maintain memory coherency when any segment of the flash memory is +programmed or erased. Accordingly, cache invalidations must occur after a programming or erase event is +completed and before the new memory image is accessed. +The bit setting definitions are for each bit in the field. +0 +No cache way invalidation for the corresponding cache +1 +Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected +19 +S\_B\_INV +Invalidate Prefetch Speculation Buffer +This bit determines if the FMC's prefetch speculation buffer and the single entry page buffer are to be +invalidated (cleared). When this bit is written, the speculation buffer and single entry buffer are +immediately cleared. This bit always reads as zero. +0 +Speculation buffer and single entry buffer are not affected. +1 +Invalidate (clear) speculation buffer and single entry buffer. +18–17 +B0MW[1:0] +Bank 0 Memory Width +This read-only field defines the width of the bank 0 memory. +00 +32 bits +01 +64 bits +10 +Reserved +11 +Reserved +16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7–5 +CRC[2:0] +Cache Replacement Control +This 3-bit field defines the replacement algorithm for accesses that are cached. +000 +LRU replacement algorithm per set across all four ways +001 +Reserved +010 +Independent LRU with ways [0-1] for ifetches, [2-3] for data +011 +Independent LRU with ways [0-2] for ifetches, [3] for data +1xx +Reserved +4 +B0DCE +Bank 0 Data Cache Enable +This bit controls whether data references are loaded into the cache. +0 +Do not cache data references. +1 +Cache data references. +3 +B0ICE +Bank 0 Instruction Cache Enable +This bit controls whether instruction fetches are loaded into the cache. +Table continues on the next page... +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +631 +General Business Information + +![Image 1 from page 631](pdf-image://page_631_img_1) + +## Page 632 + +FMC\_PFB0CR field descriptions (continued) +Field +Description +0 +Do not cache instruction fetches. +1 +Cache instruction fetches. +2 +B0DPE +Bank 0 Data Prefetch Enable +This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. +0 +Do not prefetch in response to data references. +1 +Enable prefetches in response to data references. +1 +B0IPE +Bank 0 Instruction Prefetch Enable +This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction +fetches. +0 +Do not prefetch in response to instruction fetches. +1 +Enable prefetches in response to instruction fetches. +0 +B0SEBE +Bank 0 Single Entry Buffer Enable +This bit controls whether the single entry page buffer is enabled in response to flash read accesses. Its +operation is independent from bank 1's cache. +A high-to-low transition of this enable forces the page buffer to be invalidated. +0 +Single entry buffer is disabled. +1 +Single entry buffer is enabled. +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +632 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 632](pdf-image://page_632_img_1) + +## Page 633 + +28.4.3 +Flash Bank 1 Control Register (FMC\_PFB1CR) +This register has a format similar to that for PFB0CR, except it controls the operation of +flash bank 1, and the "global" cache control fields are empty. +Address: 4001\_F000h base + 8h offset = 4001\_F008h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +B1RWSC[3:0] +0 +B1MW[1:0] +0 +W +Reset +0 +0 +1 +1 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +0 +B1DCE +B1ICE +B1DPE +B1IPE +B1SEBE +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +1 +1 +1 +1 +1 +FMC\_PFB1CR field descriptions +Field +Description +31–28 +B1RWSC[3:0] +Bank 1 Read Wait State Control +This read-only field defines the number of wait states required to access the bank 1 flash memory. +The relationship between the read access time of the flash array (expressed in system clock cycles) and +RWSC is defined as: +Access time of flash array [system clocks] = RWSC + 1 +The FMC automatically calculates this value based on the ratio of the system clock speed to the flash +clock speed. For example, when this ratio is 4:1, the field's value is 3h. +27–19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18–17 +B1MW[1:0] +Bank 1 Memory Width +This read-only field defines the width of the bank 1 memory. +Table continues on the next page... +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +633 +General Business Information + +![Image 1 from page 633](pdf-image://page_633_img_1) + +## Page 634 + +FMC\_PFB1CR field descriptions (continued) +Field +Description +00 +32 bits +01 +64 bits +10 +Reserved +11 +Reserved +16 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +15–8 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +7–5 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +4 +B1DCE +Bank 1 Data Cache Enable +This bit controls whether data references are loaded into the cache. +0 +Do not cache data references. +1 +Cache data references. +3 +B1ICE +Bank 1 Instruction Cache Enable +This bit controls whether instruction fetches are loaded into the cache. +0 +Do not cache instruction fetches. +1 +Cache instruction fetches. +2 +B1DPE +Bank 1 Data Prefetch Enable +This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. +0 +Do not prefetch in response to data references. +1 +Enable prefetches in response to data references. +1 +B1IPE +Bank 1 Instruction Prefetch Enable +This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction +fetches. +0 +Do not prefetch in response to instruction fetches. +1 +Enable prefetches in response to instruction fetches. +0 +B1SEBE +Bank 1 Single Entry Buffer Enable +This bit controls whether the single entry buffer is enabled in response to flash read accesses. Its +operation is independent from bank 0's cache. +A high-to-low transition of this enable forces the page buffer to be invalidated. +0 +Single entry buffer is disabled. +1 +Single entry buffer is enabled. +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +634 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 634](pdf-image://page_634_img_1) + +## Page 635 + +28.4.4 +Cache Tag Storage (FMC\_TAGVDW0Sn) +The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and +the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. +This section represents tag/vld information for all sets in the indicated way. +Address: 4001\_F000h base + 100h offset + (4d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +tag[18:6] +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +tag[18:6] +0 +valid +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FMC\_TAGVDW0Sn field descriptions +Field +Description +31–19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18–6 +tag[18:6] +13-bit tag for cache entry +5–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +valid +1-bit valid for cache entry +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +635 +General Business Information + +![Image 1 from page 635](pdf-image://page_635_img_1) + +## Page 636 + +28.4.5 +Cache Tag Storage (FMC\_TAGVDW1Sn) +The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and +the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. +This section represents tag/vld information for all sets in the indicated way. +Address: 4001\_F000h base + 120h offset + (4d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +tag[18:6] +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +tag[18:6] +0 +valid +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FMC\_TAGVDW1Sn field descriptions +Field +Description +31–19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18–6 +tag[18:6] +13-bit tag for cache entry +5–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +valid +1-bit valid for cache entry +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +636 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 636](pdf-image://page_636_img_1) + +## Page 637 + +28.4.6 +Cache Tag Storage (FMC\_TAGVDW2Sn) +The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and +the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. +This section represents tag/vld information for all sets in the indicated way. +Address: 4001\_F000h base + 140h offset + (4d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +tag[18:6] +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +tag[18:6] +0 +valid +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FMC\_TAGVDW2Sn field descriptions +Field +Description +31–19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18–6 +tag[18:6] +13-bit tag for cache entry +5–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +valid +1-bit valid for cache entry +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +637 +General Business Information + +![Image 1 from page 637](pdf-image://page_637_img_1) + +## Page 638 + +28.4.7 +Cache Tag Storage (FMC\_TAGVDW3Sn) +The cache is a 4-way, set-associative cache with 8 sets. The ways are numbered 0-3 and +the sets are numbered 0-7. In TAGVDWxSy, x denotes the way, and y denotes the set. +This section represents tag/vld information for all sets in the indicated way. +Address: 4001\_F000h base + 160h offset + (4d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +0 +tag[18:6] +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +tag[18:6] +0 +valid +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FMC\_TAGVDW3Sn field descriptions +Field +Description +31–19 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +18–6 +tag[18:6] +13-bit tag for cache entry +5–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +valid +1-bit valid for cache entry +28.4.8 +Cache Data Storage (upper word) (FMC\_DATAW0SnU) +The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are +numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x +denotes the way, y denotes the set, and U and L represent upper and lower word, +respectively. This section represents data for the upper word (bits [63:32]) of all sets in +the indicated way. +Address: 4001\_F000h base + 200h offset + (8d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +data[63:32] +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +638 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 638](pdf-image://page_638_img_1) + +## Page 639 + +FMC\_DATAW0SnU field descriptions +Field +Description +31–0 +data[63:32] +Bits [63:32] of data entry +28.4.9 +Cache Data Storage (lower word) (FMC\_DATAW0SnL) +The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are +numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x +denotes the way, y denotes the set, and U and L represent upper and lower word, +respectively. This section represents data for the lower word (bits [31:0]) of all sets in the +indicated way. +Address: 4001\_F000h base + 204h offset + (8d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +data[31:0] +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FMC\_DATAW0SnL field descriptions +Field +Description +31–0 +data[31:0] +Bits [31:0] of data entry +28.4.10 +Cache Data Storage (upper word) (FMC\_DATAW1SnU) +The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are +numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x +denotes the way, y denotes the set, and U and L represent upper and lower word, +respectively. This section represents data for the upper word (bits [63:32]) of all sets in +the indicated way. +Address: 4001\_F000h base + 240h offset + (8d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +data[63:32] +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +639 +General Business Information + +![Image 1 from page 639](pdf-image://page_639_img_1) + +## Page 640 + +FMC\_DATAW1SnU field descriptions +Field +Description +31–0 +data[63:32] +Bits [63:32] of data entry +28.4.11 +Cache Data Storage (lower word) (FMC\_DATAW1SnL) +The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are +numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x +denotes the way, y denotes the set, and U and L represent upper and lower word, +respectively. This section represents data for the lower word (bits [31:0]) of all sets in the +indicated way. +Address: 4001\_F000h base + 244h offset + (8d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +data[31:0] +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FMC\_DATAW1SnL field descriptions +Field +Description +31–0 +data[31:0] +Bits [31:0] of data entry +28.4.12 +Cache Data Storage (upper word) (FMC\_DATAW2SnU) +The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are +numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x +denotes the way, y denotes the set, and U and L represent upper and lower word, +respectively. This section represents data for the upper word (bits [63:32]) of all sets in +the indicated way. +Address: 4001\_F000h base + 280h offset + (8d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +data[63:32] +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Memory map and register descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +640 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 640](pdf-image://page_640_img_1) + +## Page 641 + +FMC\_DATAW2SnU field descriptions +Field +Description +31–0 +data[63:32] +Bits [63:32] of data entry +28.4.13 +Cache Data Storage (lower word) (FMC\_DATAW2SnL) +The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are +numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x +denotes the way, y denotes the set, and U and L represent upper and lower word, +respectively. This section represents data for the lower word (bits [31:0]) of all sets in the +indicated way. +Address: 4001\_F000h base + 284h offset + (8d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +data[31:0] +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FMC\_DATAW2SnL field descriptions +Field +Description +31–0 +data[31:0] +Bits [31:0] of data entry +28.4.14 +Cache Data Storage (upper word) (FMC\_DATAW3SnU) +The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are +numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x +denotes the way, y denotes the set, and U and L represent upper and lower word, +respectively. This section represents data for the upper word (bits [63:32]) of all sets in +the indicated way. +Address: 4001\_F000h base + 2C0h offset + (8d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +data[63:32] +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +641 +General Business Information + +![Image 1 from page 641](pdf-image://page_641_img_1) + +## Page 642 + +FMC\_DATAW3SnU field descriptions +Field +Description +31–0 +data[63:32] +Bits [63:32] of data entry +28.4.15 +Cache Data Storage (lower word) (FMC\_DATAW3SnL) +The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are +numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x +denotes the way, y denotes the set, and U and L represent upper and lower word, +respectively. This section represents data for the lower word (bits [31:0]) of all sets in the +indicated way. +Address: 4001\_F000h base + 2C4h offset + (8d × i), where i=0d to 7d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +data[31:0] +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FMC\_DATAW3SnL field descriptions +Field +Description +31–0 +data[31:0] +Bits [31:0] of data entry +28.5 +Functional description +The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides +managing the interface between the device and the flash memory and FlexMemory, the +FMC can be used to restrict access from crossbar switch masters and customize the cache +and buffers to provide single-cycle system-clock data-access times. Whenever a hit +occurs for the prefetch speculation buffer, the cache, or the single-entry buffer, the +requested data is transferred within a single system clock. +28.5.1 +Default configuration +Upon system reset, the FMC is configured to provide a significant level of buffering for +transfers from the flash memory or FlexMemory: +• Crossbar masters 0, 1, 2 have read access to bank 0 and bank 1. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +642 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 642](pdf-image://page_642_img_1) + +## Page 643 + +• These masters have write access to a portion of bank 1 when FlexNVM is used with +FlexRAM as EEPROM. +• For bank 0 and bank 1: +• Prefetch support for data and instructions is enabled for crossbar masters 0, 1, 2. +• The cache is configured for least recently used (LRU) replacement for all four +ways. +• The cache is configured for data or instruction replacement. +• The single-entry buffer is enabled. +28.5.2 +Configuration options +Though the default configuration provides a high degree of flash acceleration, advanced +users may desire to customize the FMC buffer configurations to maximize throughput for +their use cases. When reconfiguring the FMC for custom use cases, do not program the +FMC's control registers while the flash memory or FlexMemory is being accessed. +Instead, change the control registers with a routine executing from RAM in supervisor +mode. +The FMC's cache and buffering controls within PFB0CR and PFB1CR allow the tuning +of resources to suit particular applications' needs. The cache and two buffers are each +controlled individually. The register controls enable buffering and prefetching per +memory bank and access type (instruction fetch or data reference). The cache also +supports three types of LRU replacement algorithms: +• LRU per set across all four ways, +• LRU with ways [0-1] for instruction fetches and ways [2-3] for data fetches, and +• LRU with ways [0-2] for instruction fetches and way [3] for data fetches. +As an application example: if both instruction fetches and data references are accessing +bank 0, control is available to send instruction fetches, data references, or both to the +cache or the single-entry buffer. Likewise, speculation can be enabled or disabled for +either type of access. If both instruction fetches and data references are cached, the +cache's way resources may be divided in several ways between the instruction fetches and +data references. +In another application example, the cache can be configured for replacement from bank +0, while the single-entry buffer can be enabled for bank 1 only. This configuration is +ideal for applications that use bank 0 for program space and bank 1 for data space. +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +643 +General Business Information + +![Image 1 from page 643](pdf-image://page_643_img_1) + +## Page 644 + +28.5.3 +Wait states +Because the core, crossbar switch, and bus masters can be clocked at a higher frequency +than the flash clock, flash memory accesses that do not hit in the speculation buffer or +cache usually require wait states. The number of wait states depends on both of the +following: +1. the ratio of the core clock to the flash clock, and +2. the phase relationship of the core clock and flash clock at the time the read is +requested. +The ratio of the core clock to the flash clock is equal to the value of PFB0CR[B0RWSC] ++ 1 for bank 0 and to the value of PFB1CR[B1RWSC] + 1 for bank 1. +For example, in a system with a 4:1 core-to-flash clock ratio, a read that does not hit in +the speculation buffer or the cache can take between 4 and 7 core clock cycles to +complete. +• The best-case scenario is a period of 4 core clock cycles because a read from the +flash memory takes 1 flash clock, which translates to 4 core clocks. +• The worst-case scenario is a period of 7 core clock cycles, consisting of 4 cycles for +the read operation and 3 cycles of delay to align the core and flash clocks. +• A delay to align the core and flash clocks might occur because you can request a +read cycle on any core clock edge, but that edge does not necessarily align with a +flash clock edge where the read can start. +• In this case, the read operation is delayed by a number of core clocks equal to the +core-to-flash clock ratio minus one: 4 - 1 = 3. That is, 3 additional core clock +cycles are required to synchronize the clocks before the read operation can start. +All wait states and synchronization delays are handled automatically by the Flash +Memory Controller. No direct user configuration is required or even allowed to set up the +flash wait states. +28.5.4 +Speculative reads +The FMC has a single buffer that reads ahead to the next word in the flash memory if +there is an idle cycle. Speculative prefetching is programmable for each bank for +instruction and/or data accesses using the B0DPE and B0IPE fields of PFB0CR and the +B1DPE and B1IPE fields of PFB1CR. Because many code accesses are sequential, using +the speculative prefetch buffer improves performance in most cases. +When speculative reads are enabled, the FMC immediately requests the next sequential +address after a read completes. By requesting the next word immediately, speculative +reads can help to reduce or even eliminate wait states when accessing sequential code +and/or data. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +644 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 644](pdf-image://page_644_img_1) + +## Page 645 + +For example, consider the following scenario: +• Assume a system with a 4:1 core-to-flash clock ratio and with speculative reads +enabled. +• The core requests four sequential longwords in back-to-back requests, meaning there +are no core cycle delays except for stalls waiting for flash memory data to be +returned. +• None of the data is already stored in the cache or speculation buffer. +In this scenario, the sequence of events for accessing the four longwords is as follows: +1. The first longword read requires 4 to 7 core clocks. See Wait states for more +information. +2. Due to the 64-bit data bus of the flash memory, the second longword read takes only +1 core clock because the data is already available inside the FMC. While the data for +the second longword is being returned to the core, the FMC also starts reading the +third and fourth longwords from the flash memory. +3. Accessing the third longword requires 3 core clock cycles. The flash memory read +itself takes 4 clocks, but the first clock overlaps with the second longword read. +4. Reading the fourth longword, like the second longword, takes only 1 clock due to the +64-bit flash memory data bus. +28.6 +Initialization and application information +The FMC does not require user initialization. Flash acceleration features are enabled by +default. +The FMC has no visibility into flash memory erase and program cycles because the Flash +Memory module manages them directly. As a result, if an application is executing flash +memory commands, the FMC's cache might need to be disabled and/or flushed to prevent +the possibility of returning stale data. Use the PFB0CR[CINV\_WAY] field to invalidate +the cache in this manner. +Chapter 28 Flash Memory Controller (FMC) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +645 +General Business Information + +![Image 1 from page 645](pdf-image://page_645_img_1) + +## Page 646 + +Initialization and application information +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +646 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 646](pdf-image://page_646_img_1) + +## Page 647 + +Chapter 29 +Flash Memory Module (FTFL) +29.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +The flash memory module includes the following accessible memory regions: +• Program flash memory for vector space and code store +• For FlexNVM devices: FlexNVM for data store and additional code store +• For FlexNVM devices: FlexRAM for high-endurance data store or traditional RAM +• For program flash only devices: Programming acceleration RAM to speed flash +programming +Flash memory is ideal for single-supply applications, permitting in-the-field erase and +reprogramming operations without the need for any external high voltage power sources. +The flash memory module includes a memory controller that executes commands to +modify flash memory contents. An erased bit reads '1' and a programmed bit reads '0'. +The programming operation is unidirectional; it can only move bits from the '1' state +(erased) to the '0' state (programmed). Only the erase operation restores bits from '0' to +'1'; bits cannot be programmed from a '0' to a '1'. +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +647 +General Business Information + +![Image 1 from page 647](pdf-image://page_647_img_1) + +## Page 648 + +CAUTION +A flash memory location must be in the erased state before +being programmed. Cumulative programming of bits (back-to- +back program operations without an intervening erase) within a +flash memory location is not allowed. Re-programming of +existing 0s to 0 is not allowed as this overstresses the device. +The standard shipping condition for flash memory is erased +with security disabled. Data loss over time may occur due to +degradation of the erased ('1') states and/or programmed ('0') +states. Therefore, it is recommended that each flash block or +sector be re-erased immediately prior to factory programming +to ensure that the full data retention capability is achieved. +29.1.1 +Features +The flash memory module includes the following features. +NOTE +See the device's Chip Configuration details for the exact +amount of flash memory available on your device. +29.1.1.1 +Program Flash Memory Features +• Sector size of 2 Kbytes +• Program flash protection scheme prevents accidental program or erase of stored data +• Automated, built-in, program and erase algorithms with verify +• Section programming for faster bulk programming times +• For devices containing only program flash memory: Read access to one logical +program flash block is possible while programming or erasing data in the other +logical program flash block +• For devices containing FlexNVM memory: Read access to program flash memory +possible while programming or erasing data in the data flash memory or FlexRAM +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +648 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 648](pdf-image://page_648_img_1) + +## Page 649 + +29.1.1.2 +FlexNVM Memory Features +When FlexNVM is partitioned for data flash memory (on devices that contain FlexNVM +memory): +• Sector size of 2 Kbytes +• Protection scheme prevents accidental program or erase of stored data +• Automated, built-in program and erase algorithms with verify +• Section programming for faster bulk programming times +• Read access to data flash memory possible while programming or erasing data in the +program flash memory +29.1.1.3 +Programming Acceleration RAM Features +• For devices with only program flash memory: RAM to support section programming +29.1.1.4 +FlexRAM Features +For devices with FlexNVM memory: +• Memory that can be used as traditional RAM or as high-endurance EEPROM storage +• Up to 4 Kbytes of FlexRAM configured for EEPROM or traditional RAM operations +• When configured for EEPROM: +• Protection scheme prevents accidental program or erase of data written for +EEPROM +• Built-in hardware emulation scheme to automate EEPROM record maintenance +functions +• Programmable EEPROM data set size and FlexNVM partition code facilitating +EEPROM memory endurance trade-offs +• Supports FlexRAM aligned writes of 1, 2, or 4 bytes at a time +• Read access to FlexRAM possible while programming or erasing data in the +program or data flash memory +• When configured for traditional RAM: +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +649 +General Business Information + +![Image 1 from page 649](pdf-image://page_649_img_1) + +## Page 650 + +• Read and write access possible to the FlexRAM while programming or erasing +data in the program or data flash memory +29.1.1.5 +Other Flash Memory Module Features +• Internal high-voltage supply generator for flash memory program and erase +operations +• Optional interrupt generation upon flash command completion +• Supports MCU security mechanisms which prevent unauthorized access to the flash +memory contents +29.1.2 +Block Diagram +The block diagram of the flash memory module is shown in the following figure. +For devices with FlexNVM feature: +FlexNVM +FlexRAM +Program flash +EEPROM backup +To MCU's +flash controller +Interrupt +Control +registers +Status +registers +Register access +Data flash +Memory controller +Figure 29-1. Flash Block Diagram +For devices that contain only program flash: +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +650 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 650](pdf-image://page_650_img_1) + +## Page 651 + +Program flash +1 +Programming +acceleration +RAM +Program flash +0 +To MCU's +flash controller +Interrupt +Control +registers +Status +registers +Register access +Memory controller +Figure 29-2. Flash Block Diagram +29.1.3 +Glossary +Command write sequence — A series of MCU writes to the flash FCCOB register +group that initiates and controls the execution of flash algorithms that are built into the +flash memory module. +Data flash memory — Partitioned from the FlexNVM block, the data flash memory +provides nonvolatile storage for user data, boot code, and additional code store. +Data flash sector — The data flash sector is the smallest portion of the data flash +memory that can be erased. +EEPROM — Using a built-in filing system, the flash memory module emulates the +characteristics of an EEPROM by effectively providing a high-endurance, byte-writeable +(program and erase) NVM. +EEPROM backup data header — The EEPROM backup data header is comprised of a +32-bit field found in EEPROM backup data memory which contains information used by +the EEPROM filing system to determine the status of a specific EEPROM backup flash +sector. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +651 +General Business Information + +![Image 1 from page 651](pdf-image://page_651_img_1) + +## Page 652 + +EEPROM backup data record — The EEPROM backup data record is comprised of a +2-bit status field, a 14-bit address field, and a 16-bit data field found in EEPROM backup +data memory which is used by the EEPROM filing system. If the status field indicates a +record is valid, the data field is mirrored in the FlexRAM at a location determined by the +address field. +EEPROM backup data memory — Partitioned from the FlexNVM block, EEPROM +backup data memory provides nonvolatile storage for the EEPROM filing system +representing data written to the FlexRAM requiring highest endurance. +EEPROM backup data sector — The EEPROM backup data sector contains one +EEPROM backup data header and up to 255 EEPROM backup data records, which are +used by the EEPROM filing system. +Endurance — The number of times that a flash memory location can be erased and +reprogrammed. +FCCOB (Flash Common Command Object) — A group of flash registers that are used +to pass command, address, data, and any associated parameters to the memory controller +in the flash memory module. +Flash block — A macro within the flash memory module which provides the nonvolatile +memory storage. +FlexMemory — Flash configuration that supports data flash, EEPROM, and FlexRAM. +FlexNVM Block — The FlexNVM block can be configured to be used as data flash +memory, EEPROM backup flash memory, or a combination of both. +FlexRAM — The FlexRAM refers to a RAM, dedicated to the flash memory module, +that can be configured to store EEPROM data or as traditional RAM. When configured +for EEPROM, valid writes to the FlexRAM generate new EEPROM backup data records +stored in the EEPROM backup flash memory. +Flash Memory Module — All flash blocks plus a flash management unit providing +high-level control and an interface to MCU buses. +IFR — Nonvolatile information register found in each flash block, separate from the +main memory array. +NVM — Nonvolatile memory. A memory technology that maintains stored data during +power-off. The flash array is an NVM using NOR-type flash memory technology. +NVM Normal Mode — An NVM mode that provides basic user access to flash memory +module resources. The CPU or other bus masters initiate flash program and erase +operations (or other flash commands) using writes to the FCCOB register group in the +flash memory module. +Introduction +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +652 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 652](pdf-image://page_652_img_1) + +## Page 653 + +NVM Special Mode — An NVM mode enabling external, off-chip access to the memory +resources in the flash memory module. A reduced flash command set is available when +the MCU is secured. See the Chip Configuration details for information on when this +mode is used. +Phrase — 64 bits of data with an aligned phrase having byte-address[2:0] = 000. +Longword — 32 bits of data with an aligned longword having byte-address[1:0] = 00. +Word — 16 bits of data with an aligned word having byte-address[0] = 0. +Program flash — The program flash memory provides nonvolatile storage for vectors +and code store. +Program flash Sector — The smallest portion of the program flash memory +(consecutive addresses) that can be erased. +Retention — The length of time that data can be kept in the NVM without experiencing +errors upon readout. Since erased (1) states are subject to degradation just like +programmed (0) states, the data retention limit may be reached from the last erase +operation (not from the programming time). +RWW— Read-While-Write. The ability to simultaneously read from one memory +resource while commanded operations are active in another memory resource. +Section Program Buffer — Lower half of the programming acceleration RAM or +FlexRAM allocated for storing large amounts of data for programming via the Program +Section command. +Secure — An MCU state conveyed to the flash memory module as described in the Chip +Configuration details for this device. In the secure state, reading and changing NVM +contents is restricted. +29.2 +External Signal Description +The flash memory module contains no signals that connect off-chip. +29.3 +Memory Map and Registers +This section describes the memory map and registers for the flash memory module. Data +read from unimplemented memory space in the flash memory module is undefined. +Writes to unimplemented or reserved memory space (registers) in the flash memory +module are ignored. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +653 +General Business Information + +![Image 1 from page 653](pdf-image://page_653_img_1) + +## Page 654 + +29.3.1 +Flash Configuration Field Description +The program flash memory contains a 16-byte flash configuration field that stores default +protection settings (loaded on reset) and security information that allows the MCU to +restrict access to the flash memory module. +Flash Configuration Field Byte +Address +Size (Bytes) +Field Description +0x0_0400 - 0x0_0407 +8 +Backdoor Comparison Key. Refer to +Verify Backdoor Access Key Command +and Unsecuring the Chip Using +Backdoor Key Access. +0x0_0408 - 0x0_040B +4 +Program flash protection bytes. Refer to +the description of the Program Flash +Protection Registers (FPROT0-3). +0x0\_040F +1 +Program flash only devices: Reserved +FlexNVM devices: Data flash protection +byte. Refer to the description of the +Data Flash Protection Register +(FDPROT). +0x0\_040E +1 +Program flash only devices: Reserved +FlexNVM devices: EEPROM protection +byte. Refer to the description of the +EEPROM Protection Register +(FEPROT). +0x0\_040D +1 +Flash nonvolatile option byte. Refer to +the description of the Flash Option +Register (FOPT). +0x0\_040C +1 +Flash security byte. Refer to the +description of the Flash Security +Register (FSEC). +29.3.2 +Program Flash IFR Map +The program flash IFR is nonvolatile information memory that can be read freely, but the +user has no erase and limited program capabilities (see the Read Once, Program Once, +and Read Resource commands in Read Once Command, Program Once Command and +Read Resource Command). The contents of the program flash IFR are summarized in the +following table and further described in the subsequent paragraphs. +The program flash IFR is located within the program flash 0 memory block for devices +that only contain program flash. +Memory Map and Registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +654 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 654](pdf-image://page_654_img_1) + +## Page 655 + +Address Range +Size (Bytes) +Field Description +0x00 – 0xBF +192 +Reserved +0xC0 – 0xFF +64 +Program Once Field +29.3.2.1 +Program Once Field +The Program Once Field in the program flash IFR provides 64 bytes of user data storage +separate from the program flash main array. The user can program the Program Once +Field one time only as there is no program flash IFR erase mechanism available to the +user. The Program Once Field can be read any number of times. This section of the +program flash IFR is accessed in 4-Byte records using the Read Once and Program Once +commands (see Read Once Command and Program Once Command). +29.3.3 +Data Flash IFR Map +The following only applies to devices with FlexNVM. +The data flash IFR is a 256 byte nonvolatile information memory that can be read and +erased, but the user has limited program capabilities in the data flash IFR (see the +Program Partition command in Program Partition Command, the Erase All Blocks +command in Erase All Blocks Command, and the Read Resource command in Read +Resource Command). The contents of the data flash IFR are summarized in the following +table and further described in the subsequent paragraphs. +Address Range +Size (Bytes) +Field Description +0x00 – 0xFB, 0xFE – 0xFF +254 +Reserved +0xFD +1 +EEPROM data set size +0xFC +1 +FlexNVM partition code +29.3.3.1 +EEPROM Data Set Size +The EEPROM data set size byte in the data flash IFR supplies information which +determines the amount of FlexRAM used in each of the available EEPROM subsystems. +To program the EEESPLIT and EEESIZE values, see the Program Partition command +described in Program Partition Command. +Table 29-1. EEPROM Data Set Size +Data flash IFR: 0x00FD +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +655 +General Business Information + +![Image 1 from page 655](pdf-image://page_655_img_1) + +## Page 656 + +Table 29-1. EEPROM Data Set Size (continued) +7 +6 +5 +4 +3 +2 +1 +0 +1 +1 +EEESPLIT +EEESIZE += Unimplemented or Reserved +Table 29-2. EEPROM Data Set Size Field Description +Field +Description +7-6 +Reserved +This read-only bitfield is reserved and must always be written as one. +5-4 +EEESPLIT +EEPROM Split Factor — Determines the relative sizes of the two EEPROM subsystems. +‘00’ = Subsystem A: EEESIZE\*1/8, subsystem B: EEESIZE\*7/8 +‘01’ = Subsystem A: EEESIZE\*1/4, subsystem B: EEESIZE\*3/4 +‘10’ = Subsystem A: EEESIZE\*1/2, subsystem B: EEESIZE\*1/2 +‘11’ = Subsystem A: EEESIZE\*1/2, subsystem B: EEESIZE\*1/2 +3-0 +EEESIZE +EEPROM Size — Encoding of the total available FlexRAM for EEPROM use. +NOTE: EEESIZE must be 0 bytes (1111b) when the FlexNVM partition code (FlexNVM Partition +Code) is set to 'No EEPROM'. +'0000' = Reserved +'0001' = Reserved +'0010' = 4,096 Bytes +'0011' = 2,048 Bytes +'0100' = 1,024 Bytes +'0101' = 512 Bytes +'0110' = 256 Bytes +'0111' = 128 Bytes +'1000' = 64 Bytes +'1001' = 32 Bytes +'1010' = Reserved +'1011' = Reserved +'1100' = Reserved +'1101' = Reserved +'1110' = Reserved +'1111' = 0 Bytes +Memory Map and Registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +656 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 656](pdf-image://page_656_img_1) + +## Page 657 + +29.3.3.2 +FlexNVM Partition Code +The FlexNVM Partition Code byte in the data flash IFR supplies a code which specifies +how to split the FlexNVM block between data flash memory and EEPROM backup +memory supporting EEPROM functions. To program the DEPART value, see the +Program Partition command described in Program Partition Command. +Table 29-3. FlexNVM Partition Code +Data Flash IFR: 0x00FC +7 +6 +5 +4 +3 +2 +1 +0 +1 +1 +1 +1 +DEPART += Unimplemented or Reserved +Table 29-4. FlexNVM Partition Code Field Description +Field +Description +7-4 +Reserved +This read-only bitfield is reserved and must always be written as one. +3-0 +DEPART +FlexNVM Partition Code — Encoding of the data flash / EEPROM backup split within the FlexNVM +memory block. FlexNVM memory not partitioned for data flash will be used to store EEPROM +records. +DEPART +Data flash (KByte) +EEPROM backup (KByte) +0000 +256 +0 +0001 +Reserved +Reserved +0010 +Reserved +Reserved +0011 +224 +32 +0100 +192 +64 +0101 +128 +128 +0110 +0 +256 +0111 +Reserved +Reserved +1000 +0 +256 +1001 +Reserved +Reserved +1010 +Reserved +Reserved +1011 +32 +224 +1100 +64 +192 +1101 +128 +128 +1110 +256 +0 +1111 +Reserved (defaults to 256) +Reserved (defaults to 0) +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +657 +General Business Information + +![Image 1 from page 657](pdf-image://page_657_img_1) + +## Page 658 + +29.3.4 +Register Descriptions +The flash memory module contains a set of memory-mapped control and status registers. +NOTE +While a command is running (FSTAT[CCIF]=0), register +writes are not accepted to any register except FCNFG and +FSTAT. The no-write rule is relaxed during the start-up reset +sequence, prior to the initial rise of CCIF. During this +initialization period the user may write any register. All register +writes are also disabled (except for registers FCNFG and +FSTAT) whenever an erase suspend request is active +(FCNFG[ERSSUSP]=1). +FTFL memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4002\_0000 +Flash Status Register (FTFL\_FSTAT) +8 +R/W +000h +29.34.1/ +659 +4002\_0001 +Flash Configuration Register (FTFL\_FCNFG) +8 +R/W +000h +29.34.2/ +661 +4002\_0002 +Flash Security Register (FTFL\_FSEC) +8 +R +Undefined +29.34.3/ +663 +4002\_0003 +Flash Option Register (FTFL\_FOPT) +8 +R +Undefined +29.34.4/ +664 +4002\_0004 +Flash Common Command Object Registers +(FTFL\_FCCOB3) +8 +R/W +000h +29.34.5/ +665 +4002\_0005 +Flash Common Command Object Registers +(FTFL\_FCCOB2) +8 +R/W +000h +29.34.5/ +665 +4002\_0006 +Flash Common Command Object Registers +(FTFL\_FCCOB1) +8 +R/W +000h +29.34.5/ +665 +4002\_0007 +Flash Common Command Object Registers +(FTFL\_FCCOB0) +8 +R/W +000h +29.34.5/ +665 +4002\_0008 +Flash Common Command Object Registers +(FTFL\_FCCOB7) +8 +R/W +000h +29.34.5/ +665 +4002\_0009 +Flash Common Command Object Registers +(FTFL\_FCCOB6) +8 +R/W +000h +29.34.5/ +665 +4002\_000A +Flash Common Command Object Registers +(FTFL\_FCCOB5) +8 +R/W +000h +29.34.5/ +665 +4002\_000B +Flash Common Command Object Registers +(FTFL\_FCCOB4) +8 +R/W +000h +29.34.5/ +665 +4002\_000C +Flash Common Command Object Registers +(FTFL\_FCCOBB) +8 +R/W +000h +29.34.5/ +665 +4002\_000D +Flash Common Command Object Registers +(FTFL\_FCCOBA) +8 +R/W +000h +29.34.5/ +665 +Table continues on the next page... +Memory Map and Registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +658 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 658](pdf-image://page_658_img_1) + +## Page 659 + +FTFL memory map (continued) +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4002\_000E +Flash Common Command Object Registers +(FTFL\_FCCOB9) +8 +R/W +000h +29.34.5/ +665 +4002\_000F +Flash Common Command Object Registers +(FTFL\_FCCOB8) +8 +R/W +000h +29.34.5/ +665 +4002\_0010 +Program Flash Protection Registers (FTFL\_FPROT3) +8 +R/W +Undefined +29.34.6/ +666 +4002\_0011 +Program Flash Protection Registers (FTFL\_FPROT2) +8 +R/W +Undefined +29.34.6/ +666 +4002\_0012 +Program Flash Protection Registers (FTFL\_FPROT1) +8 +R/W +Undefined +29.34.6/ +666 +4002\_0013 +Program Flash Protection Registers (FTFL\_FPROT0) +8 +R/W +Undefined +29.34.6/ +666 +4002\_0016 +EEPROM Protection Register (FTFL\_FEPROT) +8 +R/W +Undefined +29.34.7/ +667 +4002\_0017 +Data Flash Protection Register (FTFL\_FDPROT) +8 +R/W +Undefined +29.34.8/ +669 +29.34.1 +Flash Status Register (FTFL\_FSTAT) +The FSTAT register reports the operational status of the flash memory module. +The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The +MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. +NOTE +When set, the Access Error (ACCERR) and Flash Protection +Violation (FPVIOL) bits in this register prevent the launch of +any more commands or writes to the FlexRAM (when +EEERDY is set) until the flag is cleared (by writing a one to it). +Address: 4002\_0000h base + 0h offset = 4002\_0000h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +CCIF +RDCOLERR +ACCERR +FPVIOL +0 +MGSTAT0 +Write +w1c +w1c +w1c +w1c +Reset +0 +0 +0 +0 +0 +0 +0 +0 +FTFL\_FSTAT field descriptions +Field +Description +7 +CCIF +Command Complete Interrupt Flag +The CCIF flag indicates that a flash command or EEPROM file system operation has completed. The +CCIF flag is cleared by writing a 1 to CCIF to launch a command, and CCIF stays low until command +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +659 +General Business Information + +![Image 1 from page 659](pdf-image://page_659_img_1) + +## Page 660 + +FTFL\_FSTAT field descriptions (continued) +Field +Description +completion or command violation. The CCIF flag is also cleared by a successful write to FlexRAM while +enabled for EEE, and CCIF stays low until the EEPROM file system has created the associated EEPROM +data record. +The CCIF bit is reset to 0 but is set to 1 by the memory controller at the end of the reset initialization +sequence. Depending on how quickly the read occurs after reset release, the user may or may not see the +0 hardware reset value. +0 +Flash command or EEPROM file system operation in progress +1 +Flash command or EEPROM file system operation has completed +6 +RDCOLERR +Flash Read Collision Error Flag +The RDCOLERR error bit indicates that the MCU attempted a read from a flash memory resource that +was being manipulated by a flash command (CCIF=0). Any simultaneous access is detected as a collision +error by the block arbitration logic. The read data in this case cannot be guaranteed. The RDCOLERR bit +is cleared by writing a 1 to it. Writing a 0 to RDCOLERR has no effect. +0 +No collision error detected +1 +Collision error detected +5 +ACCERR +Flash Access Error Flag +The ACCERR error bit indicates an illegal access has occurred to a flash memory resource caused by a +violation of the command write sequence or issuing an illegal flash command. While ACCERR is set, the +CCIF flag cannot be cleared to launch a command. The ACCERR bit is cleared by writing a 1 to it. Writing +a 0 to the ACCERR bit has no effect. +0 +No access error detected +1 +Access error detected +4 +FPVIOL +Flash Protection Violation Flag +The FPVIOL error bit indicates an attempt was made to program or erase an address in a protected area +of program flash or data flash memory during a command write sequence or a write was attempted to a +protected area of the FlexRAM while enabled for EEPROM. While FPVIOL is set, the CCIF flag cannot be +cleared to launch a command. The FPVIOL bit is cleared by writing a 1 to it. Writing a 0 to the FPVIOL bit +has no effect. +0 +No protection violation detected +1 +Protection violation detected +3–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +MGSTAT0 +Memory Controller Command Completion Status Flag +The MGSTAT0 status flag is set if an error is detected during execution of a flash command or during the +flash reset sequence. As a status flag, this bit cannot (and need not) be cleared by the user like the other +error flags in this register. +The value of the MGSTAT0 bit for "command-N" is valid only at the end of the "command-N" execution +when CCIF=1 and before the next command has been launched. At some point during the execution of +"command-N+1," the previous result is discarded and any previous error is cleared. +Memory Map and Registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +660 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 660](pdf-image://page_660_img_1) + +## Page 661 + +29.34.2 +Flash Configuration Register (FTFL\_FCNFG) +This register provides information on the current functional state of the flash memory +module. +The erase control bits (ERSAREQ and ERSSUSP) have write restrictions. +SWAP,PFLSH, RAMRDY, and EEERDY are read-only status bits . The unassigned bits +read as noted and are not writable. The reset values for the SWAP, PFLASH, +RAMRDY , and EEERDY bits are determined during the reset sequence. +Address: 4002\_0000h base + 1h offset = 4002\_0001h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +CCIE +RDCOLLIE +ERSAREQ +ERSSUSP +SWAP +PFLSH +RAMRDY +EEERDY +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +FTFL\_FCNFG field descriptions +Field +Description +7 +CCIE +Command Complete Interrupt Enable +The CCIE bit controls interrupt generation when a flash command completes. +0 +Command complete interrupt disabled +1 +Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] +flag is set. +6 +RDCOLLIE +Read Collision Error Interrupt Enable +The RDCOLLIE bit controls interrupt generation when a flash memory read collision error occurs. +0 +Read collision error interrupt disabled +1 +Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory +read collision error is detected (see the description of FSTAT[RDCOLERR]). +5 +ERSAREQ +Erase All Request +This bit issues a request to the memory controller to execute the Erase All Blocks command and release +security. ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip +Configuration details on how to request this command. +The ERSAREQ bit sets when an erase all request is triggered external to the flash memory module and +CCIF is set (no command is currently being executed). ERSAREQ is cleared by the flash memory module +when the operation completes. +0 +No request or request complete +1 +Request to: +1. run the Erase All Blocks command, +2. verify the erased state, +3. program the security byte in the Flash Configuration Field to the unsecure state, and +4. release MCU security by setting the FSEC[SEC] field to the unsecure state. +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +661 +General Business Information + +![Image 1 from page 661](pdf-image://page_661_img_1) + +## Page 662 + +FTFL\_FCNFG field descriptions (continued) +Field +Description +4 +ERSSUSP +Erase Suspend +The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector command while it is +executing. +0 +No suspend requested +1 +Suspend the current Erase Flash Sector command execution. +3 +SWAP +Swap +For program flash only configurations, the SWAP flag indicates which physical program flash block is +located at relative address 0x0000. The state of the SWAP flag is set by the flash memory module during +the reset sequence. See the Swap Control command section for information on swap management. +0 +Physical program flash 0 is located at relative address 0x0000 +1 +If the PFLSH flag is set, physical program flash 1 is located at relative address 0x0000. If the PFLSH +flag is not set, physical program flash 0 is located at relative address 0x0000 +2 +PFLSH +Flash memory configuration +0 +For devices with FlexNVM: Flash memory module configured for FlexMemory that supports data flash +and/or EEPROM. For devices with program flash only: Reserved +1 +For devices with FlexNVM: Reserved. For devices with program flash only: Flash memory module +configured for program flash only, without support for data flash and/or EEPROM +1 +RAMRDY +RAM Ready +This flag indicates the current status of the FlexRAM/programming acceleration RAM. +For devices with FlexNVM: The state of the RAMRDY flag is normally controlled by the Set FlexRAM +Function command. During the reset sequence, the RAMRDY flag is cleared if the FlexNVM block is +partitioned for EEPROM and is set if the FlexNVM block is not partitioned for EEPROM. The RAMRDY +flag is cleared if the Program Partition command is run to partition the FlexNVM block for EEPROM. The +RAMRDY flag sets after completion of the Erase All Blocks command or execution of the erase-all +operation triggered external to the flash memory module. +For devices without FlexNVM: This bit should always be set. +0 +For devices with FlexNVM: FlexRAM is not available for traditional RAM access. For devices without +FlexNVM: Programming acceleration RAM is not available. +1 +For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do +not trigger EEPROM operations. For devices without FlexNVM: Programming acceleration RAM is +available. +0 +EEERDY +For devices with FlexNVM: This flag indicates if the EEPROM backup data has been copied to the +FlexRAM and is therefore available for read access. During the reset sequence, the EEERDY flag will +remain cleared while CCIF is clear and will only set if the FlexNVM block is partitioned for EEPROM. +For devices without FlexNVM: This field is reserved. +0 +For devices with FlexNVM: FlexRAM is not available for EEPROM operation. +1 +For devices with FlexNVM: FlexRAM is available for EEPROM operations where: +• reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and +• writes to the FlexRAM clear EEERDY and launch an EEPROM operation to store the written +data in the FlexRAM and EEPROM backup. +Memory Map and Registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +662 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 662](pdf-image://page_662_img_1) + +## Page 663 + +29.34.3 +Flash Security Register (FTFL\_FSEC) +This read-only register holds all bits associated with the security of the MCU and flash +memory module. +During the reset sequence, the register is loaded with the contents of the flash security +byte in the Flash Configuration Field located in program flash memory. The flash basis +for the values is signified by X in the reset value. +Address: 4002\_0000h base + 2h offset = 4002\_0002h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +KEYEN +MEEN +FSLACC +SEC +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +FTFL\_FSEC field descriptions +Field +Description +7–6 +KEYEN +Backdoor Key Security Enable +These bits enable and disable backdoor key access to the flash memory module. +00 +Backdoor key access disabled +01 +Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) +10 +Backdoor key access enabled +11 +Backdoor key access disabled +5–4 +MEEN +Mass Erase Enable Bits +Enables and disables mass erase capability of the flash memory module. The state of the MEEN bits is +only relevant when the SEC bits are set to secure outside of NVM Normal Mode. When the SEC field is +set to unsecure, the MEEN setting does not matter. +00 +Mass erase is enabled +01 +Mass erase is enabled +10 +Mass erase is disabled +11 +Mass erase is enabled +3–2 +FSLACC +Freescale Failure Analysis Access Code +These bits enable or disable access to the flash memory contents during returned part failure analysis at +Freescale. When SEC is secure and FSLACC is denied, access to the program flash contents is denied +and any failure analysis performed by Freescale factory test must begin with a full erase to unsecure the +part. +When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted), Freescale factory +testing has visibility of the current flash contents. The state of the FSLACC bits is only relevant when the +SEC bits are set to secure. When the SEC field is set to unsecure, the FSLACC setting does not matter. +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +663 +General Business Information + +![Image 1 from page 663](pdf-image://page_663_img_1) + +## Page 664 + +FTFL\_FSEC field descriptions (continued) +Field +Description +00 +Freescale factory access granted +01 +Freescale factory access denied +10 +Freescale factory access denied +11 +Freescale factory access granted +1–0 +SEC +Flash Security +These bits define the security state of the MCU. In the secure state, the MCU limits access to flash +memory module resources. The limitations are defined per device and are detailed in the Chip +Configuration details. If the flash memory module is unsecured using backdoor key access, the SEC bits +are forced to 10b. +00 +MCU security status is secure +01 +MCU security status is secure +10 +MCU security status is unsecure (The standard shipping condition of the flash memory module is +unsecure.) +11 +MCU security status is secure +29.34.4 +Flash Option Register (FTFL\_FOPT) +The flash option register allows the MCU to customize its operations by examining the +state of these read-only bits, which are loaded from NVM at reset. The function of the +bits is defined in the device's Chip Configuration details. +All bits in the register are read-only . +During the reset sequence, the register is loaded from the flash nonvolatile option byte in +the Flash Configuration Field located in program flash memory. The flash basis for the +values is signified by X in the reset value. +Address: 4002\_0000h base + 3h offset = 4002\_0003h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +OPT +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +FTFL\_FOPT field descriptions +Field +Description +7–0 +OPT +Nonvolatile Option +These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details +for the definition and use of these bits. +Memory Map and Registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +664 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 664](pdf-image://page_664_img_1) + +## Page 665 + +29.34.5 +Flash Common Command Object Registers +(FTFL\_FCCOBn) +The FCCOB register group provides 12 bytes for command codes and parameters. The +individual bytes within the set append a 0-B hex identifier to the FCCOB register name: +FCCOB0, FCCOB1, ..., FCCOBB. +Address: 4002\_0000h base + 4h offset + (1d × i), where i=0d to 11d +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +CCOBn +Write +Reset +0 +0 +0 +0 +0 +0 +0 +0 +FTFL\_FCCOBn field descriptions +Field +Description +7–0 +CCOBn +The FCCOB register provides a command code and relevant parameters to the memory controller. The +individual registers that compose the FCCOB data set can be written in any order, but you must provide all +needed values, which vary from command to command. First, set up all required FCCOB fields and then +initiate the command’s execution by writing a 1 to the FSTAT[CCIF] bit. This clears the CCIF bit, which +locks all FCCOB parameter fields and they cannot be changed by the user until the command completes +(CCIF returns to 1). No command buffering or queueing is provided; the next command can be loaded +only after the current command completes. +Some commands return information to the FCCOB registers. Any values returned to FCCOB are available +for reading after the FSTAT[CCIF] flag returns to 1 by the memory controller. +The following table shows a generic flash command format. The first FCCOB register, FCCOB0, always +contains the command code. This 8-bit value defines the command to be executed. The command code is +followed by the parameters required for this specific flash command, typically an address and/or data +values. +NOTE: The command parameter table is written in terms of FCCOB Number (which is equivalent to the +byte number). This number is a reference to the FCCOB register name and is not the register +address. +FCCOB Number +Typical Command Parameter Contents [7:0] +0 +FCMD (a code that defines the flash command) +1 +Flash address [23:16] +2 +Flash address [15:8] +3 +Flash address [7:0] +4 +Data Byte 0 +5 +Data Byte 1 +6 +Data Byte 2 +7 +Data Byte 3 +8 +Data Byte 4 +9 +Data Byte 5 +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +665 +General Business Information + +![Image 1 from page 665](pdf-image://page_665_img_1) + +## Page 666 + +FTFL\_FCCOBn field descriptions (continued) +Field +Description +FCCOB Number +Typical Command Parameter Contents [7:0] +A +Data Byte 6 +B +Data Byte 7 +FCCOB Endianness and Multi-Byte Access : +The FCCOB register group uses a big endian addressing convention. For all command parameter fields +larger than 1 byte, the most significant data resides in the lowest FCCOB register number. The FCCOB +register group may be read and written as individual bytes, aligned words (2 bytes) or aligned longwords +(4 bytes). +29.34.6 +Program Flash Protection Registers (FTFL\_FPROTn) +The FPROT registers define which logical program flash regions are protected from +program and erase operations. Protected flash regions cannot have their content changed; +that is, these regions cannot be programmed and cannot be erased by any flash command. +Unprotected regions can be changed by program and erase operations. +The four FPROT registers allow 32 protectable regions. Each bit protects a 1/32 region of +the program flash memory . The bitfields are defined in each register as follows: +Program flash protection register +Program flash protection bits +FPROT0 +PROT[31:24] +FPROT1 +PROT[23:16] +FPROT2 +PROT[15:8] +FPROT3 +PROT[7:0] +During the reset sequence, the FPROT registers are loaded with the contents of the +program flash protection bytes in the Flash Configuration Field as indicated in the +following table. +Program flash protection register +Flash Configuration Field offset address +FPROT0 +0x0008 +FPROT1 +0x0009 +FPROT2 +0x000A +FPROT3 +0x000B +Memory Map and Registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +666 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 666](pdf-image://page_666_img_1) + +## Page 667 + +To change the program flash protection that is loaded during the reset sequence, +unprotect the sector of program flash memory that contains the Flash Configuration +Field. Then, reprogram the program flash protection byte. +Address: 4002\_0000h base + 10h offset + (1d × i), where i=0d to 3d +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +PROT +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +FTFL\_FPROTn field descriptions +Field +Description +7–0 +PROT +Program Flash Region Protect +Each program flash region can be protected from program and erase operations by setting the associated +PROT bit. +In NVM Normal mode: The protection can only be increased, meaning that currently unprotected memory +can be protected, but currently protected memory cannot be unprotected. Since unprotected regions are +marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 +transition check is performed on a bit-by-bit basis. Those FPROT bits with 1-to-0 transitions are accepted +while all bits with 0-to-1 transitions are ignored. +In NVM Special mode: All bits of FPROT are writable without restriction. Unprotected areas can be +protected and protected areas can be unprotected. +Restriction: The user must never write to any FPROT register while a command is running (CCIF=0). +Trying to alter data in any protected area in the program flash memory results in a protection violation +error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it +contains any protected region. +Each bit in the 32-bit protection register represents 1/32 of the total program flash. +0 +Program flash region is protected. +1 +Program flash region is not protected +29.34.7 +EEPROM Protection Register (FTFL\_FEPROT) +For devices with FlexNVM: The FEPROT register defines which EEPROM regions of +the FlexRAM are protected against program and erase operations. Protected EEPROM +regions cannot have their content changed by writing to it. Unprotected regions can be +changed by writing to the FlexRAM. +For devices with program flash only: This register is reserved and not used. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +667 +General Business Information + +![Image 1 from page 667](pdf-image://page_667_img_1) + +## Page 668 + +Address: 4002\_0000h base + 16h offset = 4002\_0016h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +EPROT +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +FTFL\_FEPROT field descriptions +Field +Description +7–0 +EPROT +EEPROM Region Protect +For devices with program flash only: Reserved +For devices with FlexNVM: +Individual EEPROM regions can be protected from alteration by setting the associated EPROT bit. The +EPROT bits are not used when the FlexNVM Partition Code is set to data flash only. When the FlexNVM +Partition Code is set to data flash and EEPROM or EEPROM only, each EPROT bit covers one-eighth of +the configured EEPROM data (see the EEPROM Data Set Size parameter description). +In NVM Normal mode: The protection can only be increased. This means that currently-unprotected +memory can be protected, but currently-protected memory cannot be unprotected. Since unprotected +regions are marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. +This 1-to-0 transition check is performed on a bit-by-bit basis. Those FEPROT bits with 1-to-0 transitions +are accepted while all bits with 0-to-1 transitions are ignored. +In NVM Special mode : All bits of the FEPROT register are writable without restriction. Unprotected areas +can be protected and protected areas can be unprotected. +Restriction: Never write to the FEPROT register while a command is running (CCIF=0). +Reset: During the reset sequence, the FEPROT register is loaded with the contents of the FlexRAM +protection byte in the Flash Configuration Field located in program flash. The flash basis for the reset +values is signified by X in the register diagram. To change the EEPROM protection that will be loaded +during the reset sequence, the sector of program flash that contains the Flash Configuration Field must be +unprotected; then the EEPROM protection byte must be erased and reprogrammed. +Trying to alter data by writing to any protected area in the EEPROM results in a protection violation error +and sets the FPVIOL bit in the FSTAT register. +0 +For devices with program flash only: Reserved. For devices with FlexNVM: EEPROM region is +protected +1 +For devices with program flash only: Reserved. For devices with FlexNVM: EEPROM region is not +protected +Memory Map and Registers +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +668 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 668](pdf-image://page_668_img_1) + +## Page 669 + +29.34.8 +Data Flash Protection Register (FTFL\_FDPROT) +The FDPROT register defines which data flash regions are protected against program and +erase operations. Protected Flash regions cannot have their content changed; that is, these +regions cannot be programmed and cannot be erased by any flash command. Unprotected +regions can be changed by both program and erase operations. +Address: 4002\_0000h base + 17h offset = 4002\_0017h +Bit +7 +6 +5 +4 +3 +2 +1 +0 +Read +DPROT +Write +Reset +x\* +x\* +x\* +x\* +x\* +x\* +x\* +x\* +* Notes: +x = Undefined at reset. +• +FTFL\_FDPROT field descriptions +Field +Description +7–0 +DPROT +Data Flash Region Protect +For devices with program flash only: Reserved. +For devices with FlexNVM:Individual data flash regions can be protected from program and erase +operations by setting the associated DPROT bit. Each DPROT bit protects one-eighth of the partitioned +data flash memory space. The granularity of data flash protection cannot be less than the data flash sector +size. If an unused DPROT bit is set, the Erase all Blocks command does not execute and the +FSTAT[FPVIOL] flag is set. +In NVM Normal mode: The protection can only be increased, meaning that currently unprotected memory +can be protected but currently protected memory cannot be unprotected. Since unprotected regions are +marked with a 1 and protected regions use a 0, only writes changing 1s to 0s are accepted. This 1-to-0 +transition check is performed on a bit-by-bit basis. Those FDPROT bits with 1-to-0 transitions are +accepted while all bits with 0-to-1 transitions are ignored. +In NVM Special mode: All bits of the FDPROT register are writable without restriction. Unprotected areas +can be protected and protected areas can be unprotected. +Restriction: The user must never write to the FDPROT register while a command is running (CCIF=0). +Reset: During the reset sequence, the FDPROT register is loaded with the contents of the data flash +protection byte in the Flash Configuration Field located in program flash memory. The flash basis for the +reset values is signified by X in the register diagram. To change the data flash protection that will be +loaded during the reset sequence, unprotect the sector of program flash that contains the Flash +Configuration Field. Then, erase and reprogram the data flash protection byte. +Trying to alter data with the program and erase commands in any protected area in the data flash memory +results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of the data flash +memory (see the Erase Flash Block command description) is not possible if the data flash memory +contains any protected region or if the FlexNVM block has been partitioned for EEPROM. +0 +Data Flash region is protected +1 +Data Flash region is not protected +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +669 +General Business Information + +![Image 1 from page 669](pdf-image://page_669_img_1) + +## Page 670 + +29.4 +Functional Description +The following sections describe functional details of the flash memory module. +29.4.1 +Program Flash Memory Swap +For devices that only contain program flash memory: The user can configure the logical +memory map of the program flash space such that either of the two physical program +flash blocks can exist at relative address 0x0000. This swap feature enables the lower half +of the logical program flash space to be operational while the upper half is being updated +for future use. +The Swap Control command handles swapping the two logical P-Flash memory blocks +within the memory map. See Swap Control Command for details. +29.4.2 +Flash Protection +Individual regions within the flash memory can be protected from program and erase +operations. Protection is controlled by the following registers: +• FPROTn — Four registers that protect 32 regions of the program flash memory as +shown in the following figure +Program flash size / 32 +Program flash size / 32 +Program flash size / 32 +Program flash size / 32 +Program flash size / 32 +Program flash size / 32 +Program flash size / 32 +FPROT3[PROT0] +0x0\_0000 +FPROT3[PROT1] +FPROT3[PROT2] +FPROT3[PROT3] +FPROT0[PROT29] +FPROT0[PROT31] +FPROT0[PROT30] +Program flash +Last program flash address +Figure 29-27. Program flash protection +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +670 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 670](pdf-image://page_670_img_1) + +## Page 671 + +• FDPROT — +• For 2n data flash sizes, protects eight regions of the data flash memory as shown +in the following figure +Data flash size / 8 +DPROT0 +0x0\_0000 +DPROT1 +DPROT2 +DPROT3 +DPROT5 +DPROT7 +DPROT6 +FlexNVM +Last data flash address +Data flash size / 8 +Data flash size / 8 +Data flash size / 8 +Data flash size / 8 +Data flash size / 8 +Data flash size / 8 +Data flash size / 8 +DPROT4 +EEPROM backup +EEPROM backup +size (DEPART) +Last FlexNVM address +Figure 29-28. Data flash protection +• For the non-2n data flash sizes (192KB and 224KB), the protection granularity is +32KB. Therefore, for 192KB data flash size, only the DPROT[5:0] bits are used, +and for 224KB data flash size, only the DPROT[6:0] bits are used. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +671 +General Business Information + +![Image 1 from page 671](pdf-image://page_671_img_1) + +## Page 672 + +32KB +DPROT0 +0x0\_0000 +DPROT1 +DPROT2 +DPROT3 +DPROT5 +DPROT6 +224KB data flash +0x3\_7FFF +32KB +32KB +32KB +32KB +32KB +32KB +DPROT4 +32KB +EEPROM backup +0x3\_FFFF +32KB +DPROT0 +0x0\_0000 +DPROT1 +DPROT2 +DPROT3 +DPROT5 +192KB data flash +0x2\_FFFF +32KB +32KB +32KB +32KB +32KB +DPROT4 +64KB +EEPROM backup +0x3\_FFFF +Figure 29-29. Data flash protection (192 and 224KB) +• FEPROT — Protects eight regions of the EEPROM memory as shown in the +following figure +EEPROM size / 8 +EPROT0 +0x0\_0000 +EPROT1 +EPROT2 +EPROT5 +EPROT7 +EPROT6 +FlexRAM +Last EEPROM address +EEPROM size / 8 +EEPROM size / 8 +EEPROM size / 8 +EEPROM size / 8 +EEPROM size / 8 +EEPROM size / 8 +EEPROM size / 8 +EPROT3 +EPROT4 +Unavailable +EEPROM size (EEESIZE) +Last FlexRAM address +Figure 29-30. EEPROM protection +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +672 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 672](pdf-image://page_672_img_1) + +## Page 673 + +29.4.3 +FlexNVM Description +This section describes the FlexNVM memory. This section does not apply for devices +that contain only program flash memory. +29.4.3.1 +FlexNVM Block Partitioning for FlexRAM +The user can configure the FlexNVM block as either: +• Basic data flash, +• EEPROM flash records to support the built-in EEPROM feature, or +• A combination of both. +The user's FlexNVM configuration choice is specified using the Program Partition +command described in Program Partition Command. +CAUTION +While different partitions of the FlexNVM block are available, +the intention is that a single partition choice is used throughout +the entire lifetime of a given application. The FlexNVM +partition code choices affect the endurance and data retention +characteristics of the device. +29.4.3.2 +EEPROM User Perspective +The EEPROM system is shown in the following figure. +File +system +handler +User access +(effective +EEPROM) +FlexRAM +EEPROM backup +with 1KByte +erase sectors +Figure 29-31. Top Level EEPROM Architecture +To handle varying customer requirements, the FlexRAM and FlexNVM blocks can be +split into partitions as shown in the figure below. +1. EEPROM partition (EEESIZE) — The amount of FlexRAM used for EEPROM +can be set from 0 Bytes (no EEPROM) to the maximum FlexRAM size (see Table +29-2). The remainder of the FlexRAM is not accessible while the FlexRAM is +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +673 +General Business Information + +![Image 1 from page 673](pdf-image://page_673_img_1) + +## Page 674 + +configured for EEPROM (see Set FlexRAM Function Command). The EEPROM +partition grows upward from the bottom of the FlexRAM address space. +2. Data flash partition (DEPART) — The amount of FlexNVM memory used for data +flash can be programmed from 0 bytes (all of the FlexNVM block is available for +EEPROM backup) to the maximum size of the FlexNVM block (see Table 29-4). +3. FlexNVM EEPROM partition — The amount of FlexNVM memory used for +EEPROM backup, which is equal to the FlexNVM block size minus the data flash +memory partition size. The EEPROM backup size must be at least 16 times the +EEPROM partition size in FlexRAM. +4. EEPROM split factor (EEESPLIT) — The FlexRAM partitioned for EEPROM can +be divided into two subsystems, each backed by half of the partitioned EEPROM +backup. One subsystem (A) is 1/8, 1/4, or 1/2 of the partitioned FlexRAM with the +remainder belonging to the other subsystem (B). +The partition information (EEESIZE, DEPART, EEESPLIT) is stored in the data flash +IFR and is programmed using the Program Partition command (see Program Partition +Command). Typically, the Program Partition command is executed only once in the +lifetime of the device. +Data flash memory is useful for applications that need to quickly store large amounts of +data or store data that is static. The EEPROM partition in FlexRAM is useful for storing +smaller amounts of data that will be changed often. The EEPROM partition in FlexRAM +can be further sub-divided to provide subsystems, each backed by the same amount of +EEPROM backup with subsystem A having higher endurance if the split factor is 1/8 or +1/4. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +674 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 674](pdf-image://page_674_img_1) + +## Page 675 + +FlexRAM +Data flash 1 +DEPART /2 +FlexNVM Block 1 +Subsystem B +EEESIZE +Unavailable +EEPROM partition A +DEPART /2 +FlexNVM Block 0 +Subsystem A +Size of EEPROM partition A = EEESIZE x EEESPLIT +Data flash 0 and 1 interleaved +Data flash 0 +EEPROM partition B +EEPROM +backup A +EEESPLIT = 1/8, 1/4, or 1/2 +Size of EEPROM partition B = EEESIZE x (1 - EEESPLIT) +EEPROM +backup B +Figure 29-32. FlexRAM to FlexNVM Memory Mapping with 2 Sub-systems +29.4.3.3 +EEPROM Implementation Overview +Out of reset with the FSTAT[CCIF] bit clear, the partition settings (EEESIZE, DEPART, +EEESPLIT) are read from the data flash IFR and the EEPROM file system is initialized +accordingly. The EEPROM file system locates all valid EEPROM data records in +EEPROM backup and copies the newest data to FlexRAM. The FSTAT[CCIF] and +FCNFG[EEERDY] bits are set after data from all valid EEPROM data records is copied +to the FlexRAM. After the CCIF bit is set, the FlexRAM is available for read or write +access. +When configured for EEPROM use, writes to an unprotected location in FlexRAM +invokes the EEPROM file system to program a new EEPROM data record in the +EEPROM backup memory in a round-robin fashion. As needed, the EEPROM file +system identifies the EEPROM backup sector that is being erased for future use and +partially erases that EEPROM backup sector. After a write to the FlexRAM, the +FlexRAM is not accessible until the FSTAT[CCIF] bit is set. The FCNFG[EEERDY] bit +will also be set. If enabled, the interrupt associated with the FSTAT[CCIF] bit can be +used to determine when the FlexRAM is available for read or write access. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +675 +General Business Information + +![Image 1 from page 675](pdf-image://page_675_img_1) + +## Page 676 + +After a sector in EEPROM backup is full of EEPROM data records, EEPROM data +records from the sector holding the oldest data are gradually copied over to a previously- +erased EEPROM backup sector. When the sector copy completes, the EEPROM backup +sector holding the oldest data is tagged for erase. +29.4.3.4 +Write endurance to FlexRAM for EEPROM +When the FlexNVM partition code is not set to full data flash, the EEPROM data set size +can be set to any of several non-zero values. +The bytes not assigned to data flash via the FlexNVM partition code are used by the flash +memory module to obtain an effective endurance increase for the EEPROM data. The +built-in EEPROM record management system raises the number of program/erase cycles +that can be attained prior to device wear-out by cycling the EEPROM data through a +larger EEPROM NVM storage space. +While different partitions of the FlexNVM are available, the intention is that a single +choice for the FlexNVM partition code and EEPROM data set size is used throughout the +entire lifetime of a given application. The EEPROM endurance equation and graph +shown below assume that only one configuration is ever used. +Writes\_subsystem = +× Write\_efficiency × n +EEPROM – 2 × EEESPLIT × EEESIZE +EEESPLIT × EEESIZE +nvmcycd +where +• Writes\_subsystem — minimum number of writes to each FlexRAM location for +subsystem (each subsystem can have different endurance) +• EEPROM — allocated FlexNVM for each EEPROM subsystem based on DEPART; +entered with the Program Partition command +• EEESPLIT — FlexRAM split factor for subsystem; entered with the Program +Partition command +• EEESIZE — allocated FlexRAM based on DEPART; entered with the Program +Partition command +• Write\_efficiency — +• 0.25 for 8-bit writes to FlexRAM +• 0.50 for 16-bit or 32-bit writes to FlexRAM +• nnvmcycd — data flash cycling endurance (the following graph assumes 10,000 +cycles) +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +676 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 676](pdf-image://page_676_img_1) + +## Page 677 + +Figure 29-33. EEPROM backup writes to FlexRAM +29.4.4 +Interrupts +The flash memory module can generate interrupt requests to the MCU upon the +occurrence of various flash events. These interrupt events and their associated status and +control bits are shown in the following table. +Table 29-30. Flash Interrupt Sources +Flash Event +Readable +Status Bit +Interrupt +Enable Bit +Flash Command Complete +FSTAT[CCIF] +FCNFG[CCIE] +Flash Read Collision Error +FSTAT[RDCOLERR] +FCNFG[RDCOLLIE] +Note +Vector addresses and their relative interrupt priority are +determined at the MCU level. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +677 +General Business Information + +![Image 1 from page 677](pdf-image://page_677_img_1) + +![Image 2 from page 677](pdf-image://page_677_img_2) + +## Page 678 + +29.4.5 +Flash Operation in Low-Power Modes +29.4.5.1 +Wait Mode +When the MCU enters wait mode, the flash memory module is not affected. The flash +memory module can recover the MCU from wait via the command complete interrupt +(see Interrupts). +29.4.5.2 +Stop Mode +When the MCU requests stop mode, if a flash command is active (CCIF = 0) the +command execution completes before the MCU is allowed to enter stop mode. +CAUTION +The MCU should never enter stop mode while any flash +command is running (CCIF = 0). +NOTE +While the MCU is in very-low-power modes (VLPR, VLPW, +VLPS), the flash memory module does not accept flash +commands. +29.4.6 +Functional Modes of Operation +The flash memory module has two operating modes: NVM Normal and NVM Special. +The operating mode affects the command set availability (see Table 29-31). Refer to the +Chip Configuration details of this device for how to activate each mode. +29.4.7 +Flash Reads and Ignored Writes +The flash memory module requires only the flash address to execute a flash memory +read. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +678 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 678](pdf-image://page_678_img_1) + +## Page 679 + +The MCU must not read from the flash memory while commands are running (as +evidenced by CCIF=0) on that block. Read data cannot be guaranteed from a flash block +while any command is processing within that block. The block arbitration logic detects +any simultaneous access and reports this as a read collision error (see the +FSTAT[RDCOLERR] bit). +29.4.8 +Read While Write (RWW) +The following simultaneous accesses are allowed for devices with FlexNVM: +• The user may read from the program flash memory while commands (typically +program and erase operations) are active in the data flash and FlexRAM memory +space. +• The MCU can fetch instructions from program flash during both data flash program +and erase operations and while EEPROM backup data is maintained by the +EEPROM commands. +• Conversely, the user may read from data flash and FlexRAM while program and +erase commands are executing on the program flash. +• When configured as traditional RAM, writes to the FlexRAM are allowed during +program and data flash operations. +Simultaneous data flash operations and FlexRAM writes, when FlexRAM is used for +EEPROM, are not possible. +The following simultaneous accesses are allowed for devices with program flash only: +• The user may read from one logical program flash memory space while flash +commands are active in the other logical program flash memory space. +Simultaneous operations are further discussed in Allowed Simultaneous Flash +Operations. +29.4.9 +Flash Program and Erase +All flash functions except read require the user to setup and launch a flash command +through a series of peripheral bus writes. The user cannot initiate any further flash +commands until notified that the current command has completed. The flash command +structure and operation are detailed in Flash Command Operations. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +679 +General Business Information + +![Image 1 from page 679](pdf-image://page_679_img_1) + +## Page 680 + +29.4.10 +Flash Command Operations +Flash command operations are typically used to modify flash memory contents. The next +sections describe: +• The command write sequence used to set flash command parameters and launch +execution +• A description of all flash commands available +29.4.10.1 +Command Write Sequence +Flash commands are specified using a command write sequence illustrated in Figure +29-34. The flash memory module performs various checks on the command (FCCOB) +content and continues with command execution if all requirements are fulfilled. +Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register +must be zero and the CCIF flag must read 1 to verify that any previous command has +completed. If CCIF is zero, the previous command execution is still active, a new +command write sequence cannot be started, and all writes to the FCCOB registers are +ignored. +29.4.10.1.1 +Load the FCCOB Registers +The user must load the FCCOB registers with all parameters required by the desired flash +command. The individual registers that make up the FCCOB data set can be written in +any order. +29.4.10.1.2 +Launch the Command by Clearing CCIF +Once all relevant command parameters have been loaded, the user launches the command +by clearing the FSTAT[CCIF] bit by writing a '1' to it. The CCIF flag remains zero until +the flash command completes. +The FSTAT register contains a blocking mechanism that prevents a new command from +launching (can't clear CCIF) if the previous command resulted in an access error +(FSTAT[ACCERR]=1) or a protection violation (FSTAT[FPVIOL]=1). In error +scenarios, two writes to FSTAT are required to initiate the next command: the first write +clears the error flags, the second write clears CCIF. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +680 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 680](pdf-image://page_680_img_1) + +## Page 681 + +29.4.10.1.3 +Command Execution and Error Reporting +The command processing has several steps: +1. The flash memory module reads the command code and performs a series of +parameter checks and protection checks, if applicable, which are unique to each +command. +If the parameter check fails, the FSTAT[ACCERR] (access error) flag is set. +ACCERR reports invalid instruction codes and out-of bounds addresses. Usually, +access errors suggest that the command was not set-up with valid parameters in the +FCCOB register group. +Program and erase commands also check the address to determine if the operation is +requested to execute on protected areas. If the protection check fails, the +FSTAT[FPVIOL] (protection error) flag is set. +Command processing never proceeds to execution when the parameter or protection +step fails. Instead, command processing is terminated after setting the FSTAT[CCIF] +bit. +2. If the parameter and protection checks pass, the command proceeds to execution. +Run-time errors, such as failure to erase verify, may occur during the execution +phase. Run-time errors are reported in the FSTAT[MGSTAT0] bit. A command may +have access errors, protection errors, and run-time errors, but the run-time errors are +not seen until all access and protection errors have been corrected. +3. Command execution results, if applicable, are reported back to the user via the +FCCOB and FSTAT registers. +4. The flash memory module sets the FSTAT[CCIF] bit signifying that the command +has completed. +The flow for a generic command write sequence is illustrated in the following figure. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +681 +General Business Information + +![Image 1 from page 681](pdf-image://page_681_img_1) + +## Page 682 + +Clear the CCIF to launch the command +Write 0x80 to FSTAT register +Clear the old errors +Access Error and +Protection Violation +Check +FCCOB +ACCERR/ +FPVIOL +Set? +EXIT +Write to the FCCOB registers +to load the required command parameter. +More +Parameters? +Availability Check +Results from previous command +Read: FSTAT register +Write 0x30 to FSTAT register +no +yes +no +yes +Previous command complete? +no +CCIF += ‘1’? +yes +START +Figure 29-34. Generic Flash Command Write Sequence Flowchart +29.4.10.2 +Flash Commands +The following table summarizes the function of all flash commands. If the program flash, +data flash, or FlexRAM column is marked with an 'X', the flash command is relevant to +that particular memory resource. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +682 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 682](pdf-image://page_682_img_1) + +## Page 683 + +FCMD +Command +Program +flash 0 +Program +flash 1 +(Devices +with only +program +flash) +Data flash +(Devices +with +FlexNVM) +FlexRAM +(Devices +with +FlexNVM) +Function +0x00 +Read 1s Block +× +× +× +Verify that a +program flash +or data flash +block is erased. +FlexNVM block +must not be +partitioned for +EEPROM. +0x01 +Read 1s +Section +× +× +× +Verify that a +given number of +program flash +or data flash +locations from a +starting address +are erased. +0x02 +Program Check +× +× +× +Tests +previously- +programmed +locations at +margin read +levels. +0x03 +Read Resource +IFR, ID +IFR +IFR +Read 4 bytes +from program +flash IFR, data +flash IFR, or +version ID. +0x06 +Program +Longword +× +× +× +Program 4 +bytes in a +program flash +block or a data +flash block. +0x08 +Erase Flash +Block +× +× +× +Erase a +program flash +block or data +flash block. An +erase of any +flash block is +only possible +when +unprotected. +FlexNVM block +must not be +partitioned for +EEPROM. +0x09 +Erase Flash +Sector +× +× +× +Erase all bytes +in a program +flash or data +flash sector. +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +683 +General Business Information + +![Image 1 from page 683](pdf-image://page_683_img_1) + +## Page 684 + +FCMD +Command +Program +flash 0 +Program +flash 1 +(Devices +with only +program +flash) +Data flash +(Devices +with +FlexNVM) +FlexRAM +(Devices +with +FlexNVM) +Function +0x0B +Program +Section +× +× +× +× +Program data +from the +Section +Program Buffer +to a program +flash or data +flash block. +0x40 +Read 1s All +Blocks +× +× +× +Verify that all +program flash, +data flash +blocks, +EEPROM +backup data +records, and +data flash IFR +are erased then +release MCU +security. +0x41 +Read Once +IFR +Read 4 bytes of +a dedicated 64 +byte field in the +program flash 0 +IFR. +0x43 +Program Once +IFR +One-time +program of 4 +bytes of a +dedicated 64- +byte field in the +program flash 0 +IFR. +Table continues on the next page... +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +684 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 684](pdf-image://page_684_img_1) + +## Page 685 + +FCMD +Command +Program +flash 0 +Program +flash 1 +(Devices +with only +program +flash) +Data flash +(Devices +with +FlexNVM) +FlexRAM +(Devices +with +FlexNVM) +Function +0x44 +Erase All Blocks × +× +× +× +Erase all +program flash +blocks, program +flash 1 IFR, +data flash +blocks, +FlexRAM, +EEPROM +backup data +records, and +data flash IFR. +Then, verify- +erase and +release MCU +security. +NOTE: +An erase is only +possible when +all memory +locations are +unprotected. +0x45 +Verify Backdoor +Access Key +× +× +Release MCU +security after +comparing a set +of user-supplied +security keys to +those stored in +the program +flash. +0x46 +Swap Control +× +× +Handles swap- +related activities +0x80 +Program +Partition +IFR +× +Program the +FlexNVM +Partition Code +and EEPROM +Data Set Size +into the data +flash IFR. +Format all +EEPROM +backup data +sectors +allocated for +EEPROM. +Initialize the +FlexRAM. +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +685 +General Business Information + +![Image 1 from page 685](pdf-image://page_685_img_1) + +## Page 686 + +FCMD +Command +Program +flash 0 +Program +flash 1 +(Devices +with only +program +flash) +Data flash +(Devices +with +FlexNVM) +FlexRAM +(Devices +with +FlexNVM) +Function +0x81 +Set FlexRAM +Function +x +× +Switches +FlexRAM +function +between RAM +and EEPROM. +When switching +to EEPROM, +FlexNVM is not +available while +valid data +records are +being copied +from EEPROM +backup to +FlexRAM. +NOTE +FlexRAM, or Programming Acceleration RAM, is used during +PGMSEC command. +29.4.10.3 +Flash Commands by Mode +The following table shows the flash commands that can be executed in each flash +operating mode. +Table 29-31. Flash Commands by Mode +FCMD +Command +NVM Normal +NVM Special +Unsecure +Secure +MEEN=10 +Unsecure +Secure +MEEN=10 +0x00 +Read 1s Block +× +× +× +× +— +— +0x01 +Read 1s Section +× +× +× +× +— +— +0x02 +Program Check +× +× +× +× +— +— +0x03 +Read Resource +× +× +× +× +— +— +0x06 +Program Longword +× +× +× +× +— +— +0x08 +Erase Flash Block +× +× +× +× +— +— +0x09 +Erase Flash Sector +× +× +× +× +— +— +0x0B +Program Section +× +× +× +× +— +— +0x40 +Read 1s All Blocks +× +× +× +× +× +— +0x41 +Read Once +× +× +× +× +— +— +0x43 +Program Once +× +× +× +× +— +— +Table continues on the next page... +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +686 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 686](pdf-image://page_686_img_1) + +## Page 687 + +Table 29-31. Flash Commands by Mode (continued) +FCMD +Command +NVM Normal +NVM Special +Unsecure +Secure +MEEN=10 +Unsecure +Secure +MEEN=10 +0x44 +Erase All Blocks +× +× +× +× +× +— +0x45 +Verify Backdoor Access +Key +× +× +× +× +— +— +0x46 +Swap Control +× +× +× +× +— +— +0x80 +Program Partition +× +× +× +× +— +— +0x81 +Set FlexRAM Function +× +× +× +× +— +— +29.4.10.4 +Allowed Simultaneous Flash Operations +Only the operations marked 'OK' in the following table are permitted to run +simultaneously on the program flash, data flash, and FlexRAM memories. Some +operations cannot be executed simultaneously because certain hardware resources are +shared by the memories. The priority has been placed on permitting program flash reads +while program and erase operations execute on the FlexNVM and FlexRAM. This +provides read (program flash) while write (FlexNVM, FlexRAM) functionality. +For devices containing FlexNVM: +Table 29-32. Allowed Simultaneous Memory Operations +Program Flash +Data Flash +FlexRAM +Read +Program +Sector +Erase +Read +Program +Sector +Erase +Read +E-Write1 +R-Write2 +Program +flash +Read +— +OK +OK +OK +Program +— +OK +OK +OK3 +Sector +Erase +— +OK +OK +OK +Data +flash +Read +OK +OK +— +Program +OK +— +OK +OK +Sector +Erase +OK +— +OK +OK +FlexRAM +Read +OK +OK +OK +OK +— +E-Write1 +OK +— +R-Write2 +OK +OK +OK +OK +— +1. +When FlexRAM configured for EEPROM (writes are effectively multi-cycle operations). +2. +When FlexRAM configured as traditional RAM (writes are single-cycle operations). +3. +When FlexRAM configured as traditional RAM, writes to the RAM are ignored while the Program Section command is +active (CCIF = 0). +For devices containing program flash only: +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +687 +General Business Information + +![Image 1 from page 687](pdf-image://page_687_img_1) + +## Page 688 + +Table 29-33. Allowed Simultaneous Memory Operations +Program Flash 0 +Program Flash 1 +Read +Program +Sector Erase +Read +Program +Sector Erase +Program +flash 0 +Read +— +OK +OK +Program +— +OK +Sector Erase +— +OK +Program +flash 1 +Read +OK +OK +— +Program +OK +— +Sector Erase +OK +— +29.4.11 +Margin Read Commands +The Read-1s commands (Read 1s All Blocks, Read 1s Block, and Read 1s Section) and +the Program Check command have a margin choice parameter that allows the user to +apply non-standard read reference levels to the program flash and data flash array reads +performed by these commands. Using the preset 'user' and 'factory' margin levels, these +commands perform their associated read operations at tighter tolerances than a 'normal' +read. These non-standard read levels are applied only during the command execution. All +simple (uncommanded) flash array reads to the MCU always use the standard, un- +margined, read reference level. +Only the 'normal' read level should be employed during normal flash usage. The non- +standard, 'user' and 'factory' margin levels should be employed only in special cases. +They can be used during special diagnostic routines to gain confidence that the device is +not suffering from the end-of-life data loss customary of flash memory devices. +Erased ('1') and programmed ('0') bit states can degrade due to elapsed time and data +cycling (number of times a bit is erased and re-programmed). The lifetime of the erased +states is relative to the last erase operation. The lifetime of the programmed states is +measured from the last program time. +The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads +pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads +have at least this much safety margin before they experience data loss. +The 'user' margin is a small delta to the normal read reference level. 'User' margin levels +can be employed to check that flash memory contents have adequate margin for normal +level read operations. If unexpected read results are encountered when checking flash +memory contents at the 'user' margin levels, loss of information might soon occur during +'normal' readout. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +688 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 688](pdf-image://page_688_img_1) + +## Page 689 + +The 'factory' margin is a bigger deviation from the norm, a more stringent read criteria +that should only be attempted immediately (or very soon) after completion of an erase or +program command, early in the cycling life. 'Factory' margin levels can be used to check +that flash memory contents have adequate margin for long-term data retention at the +normal level setting. If unexpected results are encountered when checking flash memory +contents at 'factory' margin levels, the flash memory contents should be erased and +reprogrammed. +CAUTION +Factory margin levels must only be used during verify of the +initial factory programming. +29.4.12 +Flash Command Description +This section describes all flash commands that can be launched by a command write +sequence. The flash memory module sets the FSTAT[ACCERR] bit and aborts the +command execution if any of the following illegal conditions occur: +• There is an unrecognized command code in the FCCOB FCMD field. +• There is an error in a FCCOB field for the specific commands. Refer to the error +handling table provided for each command. +Ensure that the ACCERR and FPVIOL bits in the FSTAT register are cleared prior to +starting the command write sequence. As described in Launch the Command by Clearing +CCIF, a new command cannot be launched while these error flags are set. +Do not attempt to read a flash block while the flash memory module is running a +command (CCIF = 0) on that same block. The flash memory module may return invalid +data to the MCU with the collision error flag (FSTAT[RDCOLERR]) set. +When required by the command, address bit 23 selects between: +• program flash (=0) +• data flash (=1) +CAUTION +Flash data must be in the erased state before being +programmed. Cumulative programming of bits (adding more +zeros) is not allowed. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +689 +General Business Information + +![Image 1 from page 689](pdf-image://page_689_img_1) + +## Page 690 + +29.4.12.1 +Read 1s Block Command +The Read 1s Block command checks to see if an entire program flash or data flash block +has been erased to the specified margin level. The FCCOB flash address bits determine +which logical block is erase-verified. +Table 29-34. Read 1s Block Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x00 (RD1BLK) +1 +Flash address [23:16] in the flash block to be verified +2 +Flash address [15:8] in the flash block to be verified +3 +Flash address [7:0]1 in the flash block to be verified +4 +Read-1 Margin Choice +1. +Must be longword aligned (Flash address [1:0] = 00). +After clearing CCIF to launch the Read 1s Block command, the flash memory module +sets the read margin for 1s according to Table 29-35 and then reads all locations within +the selected program flash or data flash block. +When the data flash is targeted, DEPART must be set for no EEPROM, else the Read 1s +Block command aborts setting the FSTAT[ACCERR] bit. If the flash memory module +fails to read all 1s (i.e. the flash block is not fully erased), the FSTAT[MGSTAT0] bit is +set. The CCIF flag sets after the Read 1s Block operation has completed. +Table 29-35. Margin Level Choices for Read 1s Block +Read Margin Choice +Margin Level Description +0x00 +Use the 'normal' read level for 1s +0x01 +Apply the 'User' margin to the normal read-1 level +0x02 +Apply the 'Factory' margin to the normal read-1 level +Table 29-36. Read 1s Block Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +An invalid margin choice is specified +FSTAT[ACCERR] +Program flash is selected and the address is out of program flash range +FSTAT[ACCERR] +Data flash is selected and the address is out of data flash range +FSTAT[ACCERR] +Data flash is selected with EEPROM enabled +FSTAT[ACCERR] +Flash address is not longword aligned +FSTAT[ACCERR] +Read-1s fails +FSTAT[MGSTAT0] +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +690 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 690](pdf-image://page_690_img_1) + +## Page 691 + +29.4.12.2 +Read 1s Section Command +The Read 1s Section command checks if a section of program flash or data flash memory +is erased to the specified read margin level. The Read 1s Section command defines the +starting address and the number of phrases to be verified. +Table 29-37. Read 1s Section Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x01 (RD1SEC) +1 +Flash address [23:16] of the first phrase to be verified +2 +Flash address [15:8] of the first phrase to be verified +3 +Flash address [7:0]1 of the first phrase to be verified +4 +Number of phrases to be verified [15:8] +5 +Number of phrases to be verified [7:0] +6 +Read-1 Margin Choice +1. +Must be phrase aligned (Flash address [2:0] = 000). +Upon clearing CCIF to launch the Read 1s Section command, the flash memory module +sets the read margin for 1s according to Table 29-38 and then reads all locations within +the specified section of flash memory. If the flash memory module fails to read all 1s (i.e. +the flash section is not erased), the FSTAT[MGSTAT0] bit is set. The CCIF flag sets +after the Read 1s Section operation completes. +Table 29-38. Margin Level Choices for Read 1s Section +Read Margin Choice +Margin Level Description +0x00 +Use the 'normal' read level for 1s +0x01 +Apply the 'User' margin to the normal read-1 level +0x02 +Apply the 'Factory' margin to the normal read-1 level +Table 29-39. Read 1s Section Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +An invalid margin code is supplied +FSTAT[ACCERR] +An invalid flash address is supplied +FSTAT[ACCERR] +Flash address is not phrase aligned +FSTAT[ACCERR] +The requested section crosses a Flash block boundary +FSTAT[ACCERR] +The requested number of phrases is zero +FSTAT[ACCERR] +Read-1s fails +FSTAT[MGSTAT0] +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +691 +General Business Information + +![Image 1 from page 691](pdf-image://page_691_img_1) + +## Page 692 + +29.4.12.3 +Program Check Command +The Program Check command tests a previously programmed program flash or data flash +longword to see if it reads correctly at the specified margin level. +Table 29-40. Program Check Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x02 (PGMCHK) +1 +Flash address [23:16] +2 +Flash address [15:8] +3 +Flash address [7:0]1 +4 +Margin Choice +8 +Byte 0 expected data +9 +Byte 1 expected data +A +Byte 2 expected data +B +Byte 3 expected data +1. +Must be longword aligned (Flash address [1:0] = 00). +Upon clearing CCIF to launch the Program Check command, the flash memory module +sets the read margin for 1s according to Table 29-41, reads the specified longword, and +compares the actual read data to the expected data provided by the FCCOB. If the +comparison at margin-1 fails, the FSTAT[MGSTAT0] bit is set. +The flash memory module then sets the read margin for 0s, re-reads, and compares again. +If the comparison at margin-0 fails, the FSTAT[MGSTAT0] bit is set. The CCIF flag is +set after the Program Check operation completes. +The supplied address must be longword aligned (the lowest two bits of the byte address +must be 00): +• Byte 3 data is written to the supplied byte address ('start'), +• Byte 2 data is programmed to byte address start+0b01, +• Byte 1 data is programmed to byte address start+0b10, +• Byte 0 data is programmed to byte address start+0b11. +NOTE +See the description of margin reads, Margin Read Commands +Table 29-41. Margin Level Choices for Program Check +Read Margin Choice +Margin Level Description +0x01 +Read at 'User' margin-1 and 'User' margin-0 +0x02 +Read at 'Factory' margin-1 and 'Factory' margin-0 +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +692 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 692](pdf-image://page_692_img_1) + +## Page 693 + +Table 29-42. Program Check Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +An invalid flash address is supplied +FSTAT[ACCERR] +Flash address is not longword aligned +FSTAT[ACCERR] +An invalid margin choice is supplied +FSTAT[ACCERR] +Either of the margin reads does not match the expected data +FSTAT[MGSTAT0] +29.4.12.4 +Read Resource Command +The Read Resource command allows the user to read data from special-purpose memory +resources located within the flash memory module. The special-purpose memory +resources available include program flash IFR space, data flash IFR space, and the +Version ID field. Each resource is assigned a select code as shown in Table 29-44. +Table 29-43. Read Resource Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x03 (RDRSRC) +1 +Flash address [23:16] +2 +Flash address [15:8] +3 +Flash address [7:0]1 +Returned Values +4 +Read Data [31:24] +5 +Read Data [23:16] +6 +Read Data [15:8] +7 +Read Data [7:0] +User-provided values +8 +Resource Select Code (see Table 29-44) +1. +Must be longword aligned (Flash address [1:0] = 00). +Table 29-44. Read Resource Select Codes +Resource +Select Code +Description +Resource Size +Local Address Range +0x00 +Program Flash 0 IFR +256 Bytes +0x00_0000 - 0x00_00FF +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +693 +General Business Information + +![Image 1 from page 693](pdf-image://page_693_img_1) + +## Page 694 + +Table 29-44. Read Resource Select Codes (continued) +Resource +Select Code +Description +Resource Size +Local Address Range +0x00 +Program Flash Swap IFR1 +256 Bytes +0x02_0000 - 0x02_00FF +(512 KB of program flash) +0x01_0000 - 0x01_00FF +(256 KB of program flash) +0x00_8000 - 0x00_80FF +(128 KB of program flash) +0x00 +Data Flash 0 IFR2 +256 Bytes +0x80_0000 - 0x80_00FF +0x013 +Version ID +8 Bytes +0x00_0000 - 0x00_0007 +1. +This is for devices with program flash only. +2. +This is for devices with FlexNVM. +3. +Located in program flash 0 reserved space. +After clearing CCIF to launch the Read Resource command, four consecutive bytes are +read from the selected resource at the provided relative address and stored in the FCCOB +register. The CCIF flag sets after the Read Resource operation completes. The Read +Resource command exits with an access error if an invalid resource code is provided or if +the address for the applicable area is out-of-range. +Table 29-45. Read Resource Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +An invalid resource code is entered +FSTAT[ACCERR] +Flash address is out-of-range for the targeted resource. +FSTAT[ACCERR] +Flash address is not longword aligned +FSTAT[ACCERR] +29.4.12.5 +Program Longword Command +The Program Longword command programs four previously-erased bytes in the program +flash memory or in the data flash memory using an embedded algorithm. +CAUTION +A flash memory location must be in the erased state before +being programmed. Cumulative programming of bits (back-to- +back program operations without an intervening erase) within a +flash memory location is not allowed. Re-programming of +existing 0s to 0 is not allowed as this overstresses the device. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +694 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 694](pdf-image://page_694_img_1) + +## Page 695 + +Table 29-46. Program Longword Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x06 (PGM4) +1 +Flash address [23:16] +2 +Flash address [15:8] +3 +Flash address [7:0]1 +4 +Byte 0 program value +5 +Byte 1 program value +6 +Byte 2 program value +7 +Byte 3 program value +1. +Must be longword aligned (Flash address [1:0] = 00). +Upon clearing CCIF to launch the Program Longword command, the flash memory +module programs the data bytes into the flash using the supplied address. The swap +indicator address in each program flash block is implicitly protected from programming. +The targeted flash locations must be currently unprotected (see the description of the +FPROT and FDPROT registers) to permit execution of the Program Longword operation. +The programming operation is unidirectional. It can only move NVM bits from the erased +state ('1') to the programmed state ('0'). Erased bits that fail to program to the '0' state are +flagged as errors in FSTAT[MGSTAT0]. The CCIF flag is set after the Program +Longword operation completes. +The supplied address must be longword aligned (flash address [1:0] = 00): +• Byte 3 data is written to the supplied byte address ('start'), +• Byte 2 data is programmed to byte address start+0b01, +• Byte 1 data is programmed to byte address start+0b10, and +• Byte 0 data is programmed to byte address start+0b11. +Table 29-47. Program Longword Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +An invalid flash address is supplied +FSTAT[ACCERR] +Flash address is not longword aligned +FSTAT[ACCERR] +Flash address points to a protected area +FSTAT[FPVIOL] +Any errors have been encountered during the verify operation +FSTAT[MGSTAT0] +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +695 +General Business Information + +![Image 1 from page 695](pdf-image://page_695_img_1) + +## Page 696 + +29.4.12.6 +Erase Flash Block Command +The Erase Flash Block operation erases all addresses in a single program flash or data +flash block. +Table 29-48. Erase Flash Block Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x08 (ERSBLK) +1 +Flash address [23:16] in the flash block to be erased +2 +Flash address [15:8] in the flash block to be erased +3 +Flash address [7:0]1 in the flash block to be erased +1. +Must be longword aligned (Flash address [1:0] = 00). +Upon clearing CCIF to launch the Erase Flash Block command, the flash memory +module erases the main array of the selected flash block and verifies that it is erased. +When the data flash is targeted, DEPART must be set for no EEPROM (see Table 29-4) +else the Erase Flash Block command aborts setting the FSTAT[ACCERR] bit. The Erase +Flash Block command aborts and sets the FSTAT[FPVIOL] bit if any region within the +block is protected (see the description of the FPROT and FDPROT registers). The swap +indicator address in each program flash block is implicitly protected from block erase +unless the swap system is in the UPDATE or UPDATE-ERASED state and the program +flash block being erased is the non-active block. If the erase verify fails, +FSTAT[MGSTAT0] is set. The CCIF flag will set after the Erase Flash Block operation +has completed. +Table 29-49. Erase Flash Block Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +Program flash is selected and the address is out of program flash range +FSTAT[ACCERR] +Data flash is selected and the address is out of data flash range +FSTAT[ACCERR] +Data flash is selected with EEPROM enabled +FSTAT[ACCERR] +Flash address is not longword aligned +FSTAT[ACCERR] +Any area of the selected flash block is protected +FSTAT[FPVIOL] +Any errors have been encountered during the verify operation +FSTAT[MGSTAT0] +29.4.12.7 +Erase Flash Sector Command +The Erase Flash Sector operation erases all addresses in a flash sector. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +696 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 696](pdf-image://page_696_img_1) + +## Page 697 + +Table 29-50. Erase Flash Sector Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x09 (ERSSCR) +1 +Flash address [23:16] in the flash sector to be erased +2 +Flash address [15:8] in the flash sector to be erased +3 +Flash address [7:0]1 in the flash sector to be erased +1. +Must be phrase aligned (flash address [2:0] = 000). +After clearing CCIF to launch the Erase Flash Sector command, the flash memory +module erases the selected program flash or data flash sector and then verifies that it is +erased. The Erase Flash Sector command aborts if the selected sector is protected (see the +description of the FPROT and FDPROT registers). The swap indicator address in each +program flash block is implicitly protected from sector erase unless the swap system is in +the UPDATE or UPDATE-ERASED state and the program flash sector containing the +swap indicator address being erased is the non-active block. If the erase-verify fails the +FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase Flash Sector operation +completes. The Erase Flash Sector command is suspendable (see the FCNFG[ERSSUSP] +bit and Figure 29-35). +Table 29-51. Erase Flash Sector Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +An invalid Flash address is supplied +FSTAT[ACCERR] +Flash address is not phrase aligned +FSTAT[ACCERR] +The selected program flash or data flash sector is protected +FSTAT[FPVIOL] +Any errors have been encountered during the verify operation +FSTAT[MGSTAT0] +29.4.12.7.1 +Suspending an Erase Flash Sector Operation +To suspend an Erase Flash Sector operation set the FCNFG[ERSSUSP] bit (see Flash +Configuration Field Description) when CCIF is clear and the CCOB command field holds +the code for the Erase Flash Sector command. During the Erase Flash Sector operation +(see Erase Flash Sector Command), the flash memory module samples the state of the +ERSSUSP bit at convenient points. If the flash memory module detects that the +ERSSUSP bit is set, the Erase Flash Sector operation is suspended and the flash memory +module sets CCIF. While ERSSUSP is set, all writes to flash registers are ignored except +for writes to the FSTAT and FCNFG registers. +If an Erase Flash Sector operation effectively completes before the flash memory module +detects that a suspend request has been made, the flash memory module clears the +ERSSUSP bit prior to setting CCIF. When an Erase Flash Sector operation has been +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +697 +General Business Information + +![Image 1 from page 697](pdf-image://page_697_img_1) + +## Page 698 + +successfully suspended, the flash memory module sets CCIF and leaves the ERSSUSP bit +set. While CCIF is set, the ERSSUSP bit can only be cleared to prevent the withdrawal of +a suspend request before the flash memory module has acknowledged it. +29.4.12.7.2 +Resuming a Suspended Erase Flash Sector Operation +If the ERSSUSP bit is still set when CCIF is cleared to launch the next command, the +previous Erase Flash Sector operation resumes. The flash memory module acknowledges +the request to resume a suspended operation by clearing the ERSSUSP bit. A new +suspend request can then be made by setting ERSSUSP. A single Erase Flash Sector +operation can be suspended and resumed multiple times. +There is a minimum elapsed time limit between the request to resume the Erase Flash +Sector operation (CCIF is cleared) and the request to suspend the operation again +(ERSSUSP is set). This minimum time period is required to ensure that the Erase Flash +Sector operation will eventually complete. If the minimum period is continually violated, +i.e. the suspend requests come repeatedly and too quickly, no forward progress is made +by the Erase Flash Sector algorithm. The resume/suspend sequence runs indefinitely +without completing the erase. +29.4.12.7.3 +Aborting a Suspended Erase Flash Sector Operation +The user may choose to abort a suspended Erase Flash Sector operation by clearing the +ERSSUSP bit prior to clearing CCIF for the next command launch. When a suspended +operation is aborted, the flash memory module starts the new command using the new +FCCOB contents. +While FCNFG[ERSSUSP] is set, a write to the FlexRAM while FCNFG[EEERDY] is set +clears ERSSUSP and aborts the suspended operation. The FlexRAM write operation is +executed by the flash memory module. +Note +Aborting the erase leaves the bitcells in an indeterminate, +partially-erased state. Data in this sector is not reliable until a +new erase command fully completes. +The following figure shows how to suspend and resume the Erase Flash Sector operation. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +698 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 698](pdf-image://page_698_img_1) + +## Page 699 + +Restore Erase Algo +Clear SUSPACK = 0 +ERSSCR Command +(Write FCCOB) +Launch/Resume Command +(Clear CCIF) +CCIF = 1? +Request Suspend +(Set ERSSUSP) +Interrupt? +CCIF = 1? +Service Interrupt +(Read Flash) +ERSSUSP=0? +Next Command +(Write FCCOB) +Clear ERSSUSP +Enter with CCIF = 1 +Resume +ERSSCR +No +Memory Controller +Command Processing +SUSPACK=1 +Clear ERSSUSP +Execute +Yes +DONE? +No +ERSSUSP=1? +Save Erase Algo +Set CCIF +No +Yes +Start +New +Resume Erase? +No, Abort +User Cmd Interrupt/Suspend +Set SUSPACK = 1 +ERSSCR Suspended +Command Initiation +Yes +No +Yes +Yes +ERSSCR +Completed +ERSSCR Suspended +ERSSUSP=1 +ERSSUSP: Bit in FCNFG register +SUSPACK: Internal Suspend Acknowledge +No +Yes +Yes +No +Yes +No +ERSSCR Completed +ERSSUSP=0 +Figure 29-35. Suspend and Resume of Erase Flash Sector Operation +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +699 +General Business Information + +![Image 1 from page 699](pdf-image://page_699_img_1) + +## Page 700 + +29.4.12.8 +Program Section Command +The Program Section operation programs the data found in the section program buffer to +previously erased locations in the flash memory using an embedded algorithm. Data is +preloaded into the section program buffer by writing to the FlexRAM while it is set to +function as traditional RAM or the programming acceleration RAM (see Flash Sector +Programming). +The section program buffer is limited to the lower half of the RAM. Data written to the +upper half of the RAM is ignored and may be overwritten during Program Section +command execution. +CAUTION +A flash memory location must be in the erased state before +being programmed. Cumulative programming of bits (back-to- +back program operations without an intervening erase) within a +flash memory location is not allowed. Re-programming of +existing 0s to 0 is not allowed as this overstresses the device. +Table 29-52. Program Section Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x0B (PGMSEC) +1 +Flash address [23:16] +2 +Flash address [15:8] +3 +Flash address [7:0]1 +4 +Number of phrases to program [15:8] +5 +Number of phrases to program [7:0] +1. +Must be phrase aligned (Flash address [2:0] = 000). +After clearing CCIF to launch the Program Section command, the flash memory module +blocks access to the programming acceleration RAM (program flash only devices) or +FlexRAM (FlexNVM devices) and programs the data residing in the section program +buffer into the flash memory starting at the flash address provided. +The starting address must be unprotected (see the description of the FPROT and +FDPROT registers) to permit execution of the Program Section operation. The swap +indicator address in each program flash block is implicitly protected from programming. +If the swap indicator address is encountered during the Program Section operation, it is +bypassed without setting FPVIOL and the contents are not programmed. Programming, +which is not allowed to cross a flash sector boundary, continues until all requested +phrases have been programmed. The Program Section command also verifies that after +programming, all bits requested to be programmed are programmed. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +700 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 700](pdf-image://page_700_img_1) + +## Page 701 + +After the Program Section operation completes, the CCIF flag is set and normal access to +the RAM is restored. The contents of the section program buffer may be changed by the +Program Section operation. +Table 29-53. Program Section Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +An invalid flash address is supplied +FSTAT[ACCERR] +Flash address is not phrase aligned +FSTAT[ACCERR] +The requested section crosses a program flash sector boundary +FSTAT[ACCERR] +The requested number of phrases is zero +FSTAT[ACCERR] +The space required to store data for the requested number of phrases is more than half the +size of the programming acceleration RAM (program flash only devices) or FlexRAM +(FlexNVM devices) +FSTAT[ACCERR] +The FlexRAM is not set to function as a traditional RAM, i.e. set if RAMRDY=0 +FSTAT[ACCERR] +The flash address falls in a protected area +FSTAT[FPVIOL] +Any errors have been encountered during the verify operation +FSTAT[MGSTAT0] +29.4.12.8.1 +Flash Sector Programming +The process of programming an entire flash sector using the Program Section command +is as follows: +1. If required, for FlexNVM devices, execute the Set FlexRAM Function command to +make the FlexRAM available as traditional RAM and initialize the FlexRAM to all +ones. +2. Launch the Erase Flash Sector command to erase the flash sector to be programmed. +3. Beginning with the starting address of the programming acceleration RAM (program +flash only devices) or FlexRAM (FlexNVM devices), sequentially write enough data +to the RAM to fill an entire flash sector. This area of the RAM serves as the section +program buffer. +NOTE +In step 1, the section program buffer was initialized to all +ones, the erased state of the flash memory. +The section program buffer can be written to while the operation launched in step 2 +is executing, i.e. while CCIF = 0. +4. Execute the Program Section command to program the contents of the section +program buffer into the selected flash sector. +5. If a flash sector is larger than half the RAM, repeat steps 3 and 4 until the sector is +completely programmed. +6. To program additional flash sectors, repeat steps 2 through 4. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +701 +General Business Information + +![Image 1 from page 701](pdf-image://page_701_img_1) + +## Page 702 + +7. To restore EEPROM functionality for FlexNVM devices, execute the Set FlexRAM +Function command to make the FlexRAM available as EEPROM. +29.4.12.9 +Read 1s All Blocks Command +The Read 1s All Blocks command checks if the program flash blocks, data flash blocks, +EEPROM backup records, and data flash IFR have been erased to the specified read +margin level, if applicable, and releases security if the readout passes, i.e. all data reads as +'1'. +Table 29-54. Read 1s All Blocks Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x40 (RD1ALL) +1 +Read-1 Margin Choice +After clearing CCIF to launch the Read 1s All Blocks command, the flash memory +module : +• sets the read margin for 1s according to Table 29-55, +• checks the contents of the program flash, data flash, EEPROM backup records, and +data flash IFR are in the erased state. +If the flash memory module confirms that these memory resources are erased, security is +released by setting the FSEC[SEC] field to the unsecure state. The security byte in the +flash configuration field (see Flash Configuration Field Description) remains unaffected +by the Read 1s All Blocks command. If the read fails, i.e. all memory resources are not in +the fully erased state, the FSTAT[MGSTAT0] bit is set. +The EEERDY and RAMRDY bits are clear during the Read 1s All Blocks operation and +are restored at the end of the Read 1s All Blocks operation. +The CCIF flag sets after the Read 1s All Blocks operation has completed. +Table 29-55. Margin Level Choices for Read 1s All Blocks +Read Margin Choice +Margin Level Description +0x00 +Use the 'normal' read level for 1s +0x01 +Apply the 'User' margin to the normal read-1 level +0x02 +Apply the 'Factory' margin to the normal read-1 level +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +702 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 702](pdf-image://page_702_img_1) + +## Page 703 + +Table 29-56. Read 1s All Blocks Command Error Handling +Error Condition +Error Bit +An invalid margin choice is specified +FSTAT[ACCERR] +Read-1s fails +FSTAT[MGSTAT0] +29.4.12.10 +Read Once Command +The Read Once command provides read access to a reserved 64-byte field located in the +program flash 0 IFR (see Program Flash IFR Map and Program Once Field). Access to +this field is via 16 records, each 4 bytes long. The Read Once field is programmed using +the Program Once command described in Program Once Command. +Table 29-57. Read Once Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x41 (RDONCE) +1 +Read Once record index (0x00 - 0x0F) +2 +Not used +3 +Not used +Returned Values +4 +Read Once byte 0 value +5 +Read Once byte 1 value +6 +Read Once byte 2 value +7 +Read Once byte 3 value +After clearing CCIF to launch the Read Once command, a 4-byte Read Once record is +read from the program flash IFR and stored in the FCCOB register. The CCIF flag is set +after the Read Once operation completes. Valid record index values for the Read Once +command range from 0x00 to 0x0F. During execution of the Read Once command, any +attempt to read addresses within the program flash block containing this 64-byte field +returns invalid data. The Read Once command can be executed any number of times. +Table 29-58. Read Once Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +An invalid record index is supplied +FSTAT[ACCERR] +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +703 +General Business Information + +![Image 1 from page 703](pdf-image://page_703_img_1) + +## Page 704 + +29.4.12.11 +Program Once Command +The Program Once command enables programming to a reserved 64-byte field in the +program flash 0 IFR (see Program Flash IFR Map and Program Once Field). Access to +the Program Once field is via 16 records, each 4 bytes long. The Program Once field can +be read using the Read Once command (see Read Once Command) or using the Read +Resource command (see Read Resource Command). Each Program Once record can be +programmed only once since the program flash 0 IFR cannot be erased. +Table 29-59. Program Once Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x43 (PGMONCE) +1 +Program Once record index (0x00 - 0x0F) +2 +Not Used +3 +Not Used +4 +Program Once Byte 0 value +5 +Program Once Byte 1 value +6 +Program Once Byte 2 value +7 +Program Once Byte 3 value +After clearing CCIF to launch the Program Once command, the flash memory module +first verifies that the selected record is erased. If erased, then the selected record is +programmed using the values provided. The Program Once command also verifies that +the programmed values read back correctly. The CCIF flag is set after the Program Once +operation has completed. +The reserved program flash 0 IFR location accessed by the Program Once command +cannot be erased and any attempt to program one of these records when the existing value +is not Fs (erased) is not allowed. Valid record index values for the Program Once +command range from 0x00 to 0x0F. During execution of the Program Once command, +any attempt to read addresses within the program flash block containing this 64-byte field +returns invalid data. +Table 29-60. Program Once Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +An invalid record index is supplied +FSTAT[ACCERR] +The requested record has already been programmed to a non-FFFF value1 +FSTAT[ACCERR] +Any errors have been encountered during the verify operation +FSTAT[MGSTAT0] +1. +If a Program Once record is initially programmed to 0xFFFF\_FFFF, the Program Once command is allowed to execute +again on that same record. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +704 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 704](pdf-image://page_704_img_1) + +## Page 705 + +29.4.12.12 +Erase All Blocks Command +The Erase All Blocks operation erases all flash memory, initializes the FlexRAM, verifies +all memory contents, and releases MCU security. +Table 29-61. Erase All Blocks Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x44 (ERSALL) +After clearing CCIF to launch the Erase All Blocks command, the flash memory module +erases all program flash memory, program flash swap IFR space, data flash memory, data +flash IFR space, EEPROM backup memory, and FlexRAM, then verifies that all are +erased. +If the flash memory module verifies that all flash memories and the FlexRAM were +properly erased, security is released by setting the FSEC[SEC] field to the unsecure state +and the FCNFG[RAMRDY] bit is set. The Erase All Blocks command aborts if any flash +or FlexRAM region is protected. The swap indicator address in each program flash block +is not implicitly protected from the Erase All Blocks operation. The security byte and all +other contents of the flash configuration field (see Flash Configuration Field Description) +are erased by the Erase All Blocks command. If the erase-verify fails, the +FSTAT[MGSTAT0] bit is set. The CCIF flag is set after the Erase All Blocks operation +completes. +Table 29-62. Erase All Blocks Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +Any region of the program flash memory, data flash memory, or FlexRAM is protected +FSTAT[FPVIOL] +Any errors have been encountered during the verify operation +FSTAT[MGSTAT0] +29.4.12.12.1 +Triggering an Erase All External to the Flash Memory Module +The functionality of the Erase All Blocks command is also available in an uncommanded +fashion outside of the flash memory. Refer to the device's Chip Configuration details for +information on this functionality. +Before invoking the external erase all function, the FSTAT[ACCERR and PVIOL] flags +must be cleared and the FCCOB0 register must not contain 0x44. When invoked, the +erase-all function erases all program flash memory, program flash swap IFR space, data +flash memory, data flash IFR space, EEPROM backup, and FlexRAM regardless of the +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +705 +General Business Information + +![Image 1 from page 705](pdf-image://page_705_img_1) + +## Page 706 + +protection settings or if the swap system has been initialized. If the post-erase verify +passes, the routine then releases security by setting the FSEC[SEC] field register to the +unsecure state and the FCNFG[RAMRDY] bit sets. The security byte in the Flash +Configuration Field is also programmed to the unsecure state. The status of the erase-all +request is reflected in the FCNFG[ERSAREQ] bit. The FCNFG[ERSAREQ] bit is +cleared once the operation completes and the normal FSTAT error reporting is available +as described in Erase All Blocks Command. +29.4.12.13 +Verify Backdoor Access Key Command +The Verify Backdoor Access Key command only executes if the mode and security +conditions are satisfied (see Flash Commands by Mode). Execution of the Verify +Backdoor Access Key command is further qualified by the FSEC[KEYEN] bits. The +Verify Backdoor Access Key command releases security if user-supplied keys in the +FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash +Configuration Field (see Flash Configuration Field Description). The column labelled +Flash Configuration Field offset address shows the location of the matching byte in the +Flash Configuration Field. +Table 29-63. Verify Backdoor Access Key Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +Flash Configuration Field Offset Address +0 +0x45 (VFYKEY) +1-3 +Not Used +4 +Key Byte 0 +0x0\_0000 +5 +Key Byte 1 +0x0\_0001 +6 +Key Byte 2 +0x0\_0002 +7 +Key Byte 3 +0x0\_0003 +8 +Key Byte 4 +0x0\_0004 +9 +Key Byte 5 +0x0\_0005 +A +Key Byte 6 +0x0\_0006 +B +Key Byte 7 +0x0\_0007 +After clearing CCIF to launch the Verify Backdoor Access Key command, the flash +memory module checks the FSEC[KEYEN] bits to verify that this command is enabled. +If not enabled, the flash memory module sets the FSTAT[ACCERR] bit and terminates. +If the command is enabled, the flash memory module compares the key provided in +FCCOB to the backdoor comparison key in the Flash Configuration Field. If the +backdoor keys match, the FSEC[SEC] field is changed to the unsecure state and security +is released. If the backdoor keys do not match, security is not released and all future +attempts to execute the Verify Backdoor Access Key command are immediately aborted +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +706 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 706](pdf-image://page_706_img_1) + +## Page 707 + +and the FSTAT[ACCERR] bit is (again) set to 1 until a reset of the flash memory module +module occurs. If the entire 8-byte key is all zeros or all ones, the Verify Backdoor +Access Key command fails with an access error. The CCIF flag is set after the Verify +Backdoor Access Key operation completes. +Table 29-64. Verify Backdoor Access Key Command Error Handling +Error Condition +Error Bit +The supplied key is all-0s or all-Fs +FSTAT[ACCERR] +An incorrect backdoor key is supplied +FSTAT[ACCERR] +Backdoor key access has not been enabled (see the description of the FSEC register) +FSTAT[ACCERR] +This command is launched and the backdoor key has mismatched since the last power down +reset +FSTAT[ACCERR] +29.4.12.14 +Swap Control Command +The Swap Control command handles specific activities associated with swapping the two +logical program flash memory blocks within the memory map. +Table 29-65. Swap Control Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x46 (SWAP) +1 +Flash address [23:16] +2 +Flash address [15:8] +3 +Flash address [7:0] 1 +4 +Swap Control Code: +0x01 - Initialize Swap System +0x02 - Set Swap in Update State +0x04 - Set Swap in Complete State +0x08 - Report Swap Status +Returned values +5 +Current Swap State: +0x00 - Uninitialized +0x01 - Ready +0x02 - Update +0x03 - Update-Erased +0x04 - Complete +6 +Current Swap Block Status: +0x00 - Program flash block 0 at 0x0_0000 +0x01 - Program flash block 1 at 0x0_0000 +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +707 +General Business Information + +![Image 1 from page 707](pdf-image://page_707_img_1) + +## Page 708 + +Table 29-65. Swap Control Command FCCOB Requirements (continued) +FCCOB Number +FCCOB Contents [7:0] +7 +Next Swap Block Status (after any reset): +0x00 - Program flash block 0 at 0x0_0000 +0X01 - Program flash block 1 at 0x0_0000 +1. +Must be phrase-aligned (Flash address [2:0] = 000). +Upon clearing CCIF to launch the Swap Control command, the flash memory module +will handle swap-related activities based on the swap control code provided in FCCOB4 +as follows: +• 0x01 (Initialize Swap System to UPDATE-ERASED State) - After verifying that the +current swap state is UNINITIALIZED and that the flash address provided is in +Program flash block 0 but not in the Flash Configuration Field, the flash address +(shifted with bits[2:0] removed) will be programmed into the IFR Swap Field found +in program flash swap IFR. After the swap indicator address has been programmed +into the IFR Swap Field, the swap enable word will be programmed to 0x0000. After +the swap enable word has been programmed, the swap indicator, located within the +Program flash block 0 address provided, will be programmed to 0xFF00. +• 0x02 (Progress Swap to UPDATE State) - After verifying that the current swap state +is READY and that the flash address provided matches the one stored in the IFR +Swap Field, the swap indicator located within bits [15:0] of the flash address in the +currently active program flash block will be programmed to 0xFF00. +• 0x04 (Progress Swap to COMPLETE State) - After verifying that the current swap +state is UPDATE-ERASED and that the flash address provided matches the one +stored in the IFR Swap Field, the swap indicator located within bits [15:0] of the +flash address in the currently active program flash block will be programmed to +0x0000. Before executing with this swap control code, the user must erase the non- +active swap indicator using the Erase Flash Block or Erase Flash Sector commands +and update the application code or data as needed. The non-active swap indicator will +be checked at the erase verify level and if the check fails, the current swap state will +be changed to UPDATE with FSTAT[ACCERR] set. +• 0x08 (Report Swap System Status) - After verifying that the flash address provided +matches the one stored in the IFR Swap Field, the status of the swap system will be +reported as follows: +• FCCOB5 (Current Swap State) - indicates the current swap state based on the +status of the swap enable word and the swap indicators. If the +FSTAT[MGSTAT0] flag is set after command completion, the swap state +returned was not successfully transitioned from and the appropriate swap +command code must be attempted again. If the current swap state is UPDATE +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +708 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 708](pdf-image://page_708_img_1) + +## Page 709 + +and the non-active swap indicator is 0xFFFF, the current swap state is changed +to UPDATE-ERASED. +• FCCOB6 (Current Swap Block Status) - indicates which program flash block is +currently located at relative flash address 0x0\_0000. +• FCCOB7 (Next Swap Block Status) - indicates which program flash block will +be located at relative flash address 0x0\_0000 after the next reset of the flash +memory module. +NOTE +It is recommended that the user execute the Swap Control +command to report swap status (code 0x08) after any reset to +determine if issues with the swap system were detected during +the swap state determination procedure. +NOTE +It is recommended that the user write 0xFF to FCCOB5, +FCCOB6, and FCCOB7 since the Swap Control command will +not always return the swap state and status fields when an +access error is detected. +The swap indicators are implicitly protected from being programmed during Program +Longword or Program Section command operations and are implicitly unprotected during +Swap Control command operations. The swap indicators are implicitly protected from +being erased during Erase Flash Block and Erase Flash Sector command operations +unless the swap indicator being erased is in the non-active program flash block and the +swap system is in the UPDATE or UPDATE-ERASED state. Once the swap system has +been initialized, the Erase All Blocks command can be used to uninitialize the swap +system. +Table 29-66. Swap Control Command Error Handling +Error Condition +Swap +Control +Code +Error Bit +Command not available in current mode/security1 +All +FSTAT[ACCERR] +Flash address is not in program flash block 0 +All +FSTAT[ACCERR] +Flash address is in the Flash Configuration Field +All +FSTAT[ACCERR] +Flash address is not phrase aligned +All +FSTAT[ACCERR] +Flash address does not match the swap indicator address in the IFR +2, 4 +FSTAT[ACCERR] +Swap initialize requested when swap system is not in the uninitialized state +1 +FSTAT[ACCERR] +Swap update requested when swap system is not in the ready state +2 +FSTAT[ACCERR] +Swap complete requested when swap system is not in the update-erased +state +4 +FSTAT[ACCERR] +An undefined swap control code is provided +- +FSTAT[ACCERR] +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +709 +General Business Information + +![Image 1 from page 709](pdf-image://page_709_img_1) + +## Page 710 + +Table 29-66. Swap Control Command Error Handling (continued) +Error Condition +Swap +Control +Code +Error Bit +Any errors have been encountered during the swap determination and +program-verify operations +1, 2, 4 +FSTAT[MGSTAT0] +Any brownouts were detected during the swap determination procedure +8 +FSTAT[MGSTAT0] +1. +Returned fields will not be updated, i.e. no swap state or status reporting +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +710 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 710](pdf-image://page_710_img_1) + +## Page 711 + +Reset +2 +Erase +4 +Erase +Reset +Block0 Active States +Block1 Active States +Ready0 +Update0 +Complete0 +Ready1 +UpErs1 +Complete1 +1 +0xFFFF +0x0000 +0xFF00 +0x0000 +0x0000 +0xFFFF +0x0000 +0xFFFF +0xFFFF +0xFF00 +0xFFFF +0x0000 +Swap State +Indicator0 +Indicator1 +Legend +Swap Control Code +4 +UpErs0 +0xFF00 +0xFFFF +2 +Update1 +0x0000 +0xFF00 +Erase: ERSBLK or ERSSCR commands +Reset: POR, VLLSx exit, warm/system reset +Uninitialized0 +0xFFFF +0xFFFF +Figure 29-36. Valid Swap State Sequencing +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +711 +General Business Information + +![Image 1 from page 711](pdf-image://page_711_img_1) + +## Page 712 + +Table 29-67. Swap State Report Mapping +Case +Swap Enable +Field1 +Swap Indicator +01 +Swap Indicator +11 +Swap State2 +State +Code +MGST +AT0 +Active +Block +1 +0xFFFF +- +- +Uninitialized +0 +0 +0 +2 +0x0000 +0xFF00 +0x0000 +Update +2 +0 +0 +3 +0x0000 +0xFF00- +0xFFFF +Update-Erased +3 +0 +0 +4 +0x0000 +0x0000 +0xFFFF3 +Complete4 +4 +0 +0 +5 +0x0000 +0x0000 +0xFFFF +Ready5 +1 +0 +1 +6 +0x0000 +0x0000 +0xFF00 +Update +2 +0 +1 +7 +0x0000 +0xFFFF +0xFF00 +Update-Erased +3 +0 +1 +8 +0x0000 +0xFFFF3 +0x0000 +Complete4 +4 +0 +1 +9 +0x0000 +0xFFFF +0x0000 +Ready5 +1 +0 +0 +10 +0xXXXX +- +- +Uninitialized +0 +1 +0 +11 +0x0000 +0xFFFF +0xFFFF +Uninitialized +0 +1 +0 +12 +0x0000 +0xFFXX +0xFFFF +Ready +1 +1 +0 +13 +0x0000 +0xFFXX +0x0000 +Ready +1 +1 +0 +146 +0x0000 +0xXXXX +0x0000 +Ready +1 +1 +0 +156 +0x0000 +0xFFFF +0xFFXX +Ready +1 +1 +1 +16 +0x0000 +0x0000 +0xFFXX +Ready +1 +1 +1 +176 +0x0000 +0x0000 +0xXXXX +Ready +1 +1 +1 +18 +0x0000 +0xFF00 +0xFFFF7 +Update +2 +1 +0 +19 +0x0000 +0xFF00 +0xXXXX +Update +2 +1 +0 +20 +0x0000 +0xFF(00) +0xFFXX +Update +2 +1 +0 +216 +0x0000 +0x0000 +0x0000 +Update +2 +1 +0 +226 +0x0000 +0xXXXX +0xXXXX +Update +2 +1 +0 +23 +0x0000 +0xFFFF7 +0xFF00 +Update +2 +1 +1 +24 +0x0000 +0xXXXX +0xFF00 +Update +2 +1 +1 +25 +0x0000 +0xFFXX +0xFF(00) +Update +2 +1 +1 +26 +0x0000 +0xXX00 +0xFFFF +Update-Erased +3 +1 +0 +27 +0x0000 +0xXXXX +0xFFFF +Update-Erased +3 +1 +0 +28 +0x0000 +0xFFFF +0xXX00 +Update-Erased +3 +1 +1 +29 +0x0000 +0xFFFF +0xXXXX +Update-Erased +3 +1 +1 +1. +0xXXXX, 0xFFXX, 0xXX00 indicates a non-valid value was read; 0xFF(00) indicates more 0’s than other indicator (if same +number of 0’s, then swap system defaults to block 0 active) +2. +Cases 10-29 due to brownout (abort) detected during program or erase steps related to swap +3. +Must read 0xFFFF with erase verify level before transition to Complete allowed +4. +No reset since successful Swap Complete execution +5. +Reset after successful Swap Complete execution +6. +Not a valid case +7. +Fails to read 0xFFFF at erase verify level +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +712 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 712](pdf-image://page_712_img_1) + +## Page 713 + +29.4.12.14.1 +Swap State Determination +During the reset sequence, the state of the swap system is determined by evaluating the +IFR Swap Field in the program flash swap IFR and the swap indicators located in each of +the program flash blocks at the swap indicator address stored in the IFR Swap Field. +Table 29-68. Program Flash 1 IFR Swap Field +Address Range +Size (Bytes) +Field Description +0x00 – 0x01 +2 +Swap Enable Word +0x02 – 0x03 +2 +Swap Indicator Address +0x04 – 0xFF +252 +Reserved +29.4.12.15 +Program Partition Command +The Program Partition command prepares the FlexNVM block for use as data flash, +EEPROM backup, or a combination of both and initializes the FlexRAM. The Program +Partition command must not be launched from flash memory, since flash memory +resources are not accessible during Program Partition command execution. +CAUTION +While different partitions of the FlexNVM are available, the +intention is that a single partition choice is used throughout the +entire lifetime of a given application. The FlexNVM Partition +Code choices affect the endurance and data retention +characteristics of the device. +Table 29-69. Program Partition Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x80 (PGMPART) +1 +Not Used +2 +Not Used +3 +Not Used +4 +EEPROM Data Size Code1 +5 +FlexNVM Partition Code2 +1. +See Table 29-70 and EEPROM Data Set Size +2. +See Table 29-71 and +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +713 +General Business Information + +![Image 1 from page 713](pdf-image://page_713_img_1) + +## Page 714 + +Table 29-70. Valid EEPROM Data Set Size Codes +EEPROM Data Size Code (FCCOB4)1 +EEPROM Data Set Size (Bytes) +Subsystem A + B +FCCOB4[EEESPLIT] +FCCOB4[EEESIZE] +11 +0xF +02 +00 +0x9 +4 + 28 +01 +0x9 +8 + 24 +10 +0x9 +16 + 16 +11 +0x9 +16 + 16 +00 +0x8 +8 + 56 +01 +0x8 +16 + 48 +10 +0x8 +32 + 32 +11 +0x8 +32 + 32 +00 +0x7 +16 + 112 +01 +0x7 +32 + 96 +10 +0x7 +64 + 64 +11 +0x7 +64 + 64 +00 +0x6 +32 + 224 +01 +0x6 +64 + 192 +10 +0x6 +128 + 128 +11 +0x6 +128 + 128 +00 +0x5 +64 + 448 +01 +0x5 +128 + 384 +10 +0x5 +256 + 256 +11 +0x5 +256 + 256 +00 +0x4 +128 + 896 +01 +0x4 +256 + 768 +10 +0x4 +512 + 512 +11 +0x4 +512 + 512 +00 +0x3 +256 + 1,792 +01 +0x3 +512 + 1,536 +10 +0x3 +1,024 + 1,024 +11 +0x3 +1,024 + 1,024 +00 +0x2 +512 + 3,584 +01 +0x2 +1,024 + 3,072 +10 +0x2 +2,048 + 2,048 +11 +0x2 +2,048 + 2,048 +1. +FCCOB4[7:6] = 00 +2. +EEPROM Data Set Size must be set to 0 bytes when the FlexNVM Partition Code is set for no EEPROM. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +714 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 714](pdf-image://page_714_img_1) + +## Page 715 + +Table 29-71. Valid FlexNVM Partition Codes +FlexNVM Partition Code +(FCCOB5[DEPART])1 +Data flash Size (Kbytes) +EEPROM backup Size (Kbytes) +0000 +256 +0 +0011 +224 +32 +0100 +192 +64 +0101 +128 +128 +0110 +0 +256 +1000 +0 +256 +1011 +32 +224 +1100 +64 +192 +1101 +128 +128 +1110 +256 +0 +1. +FCCOB5[7:4] = 0000 +After clearing CCIF to launch the Program Partition command, the flash memory module +first verifies that the EEPROM Data Size Code and FlexNVM Partition Code in the data +flash IFR are erased. If erased, the Program Partition command erases the contents of the +FlexNVM memory. If the FlexNVM is to be partitioned for EEPROM backup, the +allocated EEPROM backup sectors are formatted for EEPROM use. Finally, the partition +codes are programmed into the data flash IFR using the values provided. The Program +Partition command also verifies that the partition codes read back correctly after +programming. If the FlexNVM is partitioned for EEPROM backup, the EEERDY flag +will set with RAMRDY clear. If the FlexNVM is not partitioned for EEPROM backup, +the RAMRDY flag will set with EEERDY clear. The CCIF flag is set after the Program +Partition operation completes. +Prior to launching the Program Partition command, the data flash IFR must be in an +erased state, which can be accomplished by executing the Erase All Blocks command or +by an external request (see Erase All Blocks Command). The EEPROM Data Size Code +and FlexNVM Partition Code are read using the Read Resource command (see Read +Resource Command). +Table 29-72. Program Partition Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +The EEPROM data size and FlexNVM partition code bytes are not initially 0xFFFF +FSTAT[ACCERR] +Invalid EEPROM Data Size Code is entered (see Table 29-70 for valid codes) +FSTAT[ACCERR] +Invalid FlexNVM Partition Code is entered (see Table 29-71 for valid codes) +FSTAT[ACCERR] +FlexNVM Partition Code = full data flash (no EEPROM) and EEPROM Data Size Code +allocates FlexRAM for EEPROM +FSTAT[ACCERR] +Table continues on the next page... +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +715 +General Business Information + +![Image 1 from page 715](pdf-image://page_715_img_1) + +## Page 716 + +Table 29-72. Program Partition Command Error Handling (continued) +Error Condition +Error Bit +FlexNVM Partition Code allocates space for EEPROM backup, but EEPROM Data Size Code +allocates no FlexRAM for EEPROM +FSTAT[ACCERR] +FCCOB4[7:6] != 00 +FSTAT[ACCERR] +FCCOB5[7:4] != 0000 +FSTAT[ACCERR] +Any errors have been encountered during the verify operation +FSTAT[MGSTAT0] +29.4.12.16 +Set FlexRAM Function Command +The Set FlexRAM Function command changes the function of the FlexRAM: +• When not partitioned for EEPROM, the FlexRAM is typically used as traditional +RAM. +• When partitioned for EEPROM, the FlexRAM is typically used to store EEPROM +data. +Table 29-73. Set FlexRAM Function Command FCCOB Requirements +FCCOB Number +FCCOB Contents [7:0] +0 +0x81 (SETRAM) +1 +FlexRAM Function Control Code +(see Table 29-74) +Table 29-74. FlexRAM Function Control +FlexRAM Function +Control Code +Action +0xFF +Make FlexRAM available as RAM: +• Clear the FCNFG[EEERDY] and FCNFG[RAMRDY] flags +• Write a background of ones to all FlexRAM locations +• Set the FCNFG[RAMRDY] flag +0x00 +Make FlexRAM available for EEPROM: +• Clear the FCNFG[EEERDY] and FCNFG[RAMRDY] flags +• Write a background of ones to all FlexRAM locations +• Copy-down existing EEPROM data to FlexRAM +• Set the FCNFG[EEERDY] flag +After clearing CCIF to launch the Set FlexRAM Function command, the flash memory +module sets the function of the FlexRAM based on the FlexRAM Function Control Code. +When making the FlexRAM available as traditional RAM, the flash memory module +clears the FCNFG[EEERDY] and FCNFG[RAMRDY] flags, overwrites the contents of +the entire FlexRAM with a background pattern of all ones, and sets the +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +716 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 716](pdf-image://page_716_img_1) + +## Page 717 + +FCNFG[RAMRDY] flag. The state of the FEPROT register does not prevent the +FlexRAM from being overwritten. When the FlexRAM is set to function as a RAM, +normal read and write accesses to the FlexRAM are available. When large sections of +flash memory need to be programmed, e.g. during factory programming, the FlexRAM +can be used as the Section Program Buffer for the Program Section command (see +Program Section Command). +When making the FlexRAM available for EEPROM, the flash memory module clears the +FCNFG[EEERDY] and FCNFG[RAMRDY] flags, overwrites the contents of the +FlexRAM allocated for EEPROM with a background pattern of all ones, and copies the +existing EEPROM data from the EEPROM backup record space to the FlexRAM. After +completion of the EEPROM copy-down, the FCNFG[EEERDY] flag is set. When the +FlexRAM is set to function as EEPROM, normal read and write access to the FlexRAM +is available, but writes to the FlexRAM also invoke EEPROM activity. The CCIF flag is +set after the Set FlexRAM Function operation completes. +Table 29-75. Set FlexRAM Function Command Error Handling +Error Condition +Error Bit +Command not available in current mode/security +FSTAT[ACCERR] +FlexRAM Function Control Code is not defined +FSTAT[ACCERR] +FlexRAM Function Control Code is set to make the FlexRAM available for EEPROM, but +FlexNVM is not partitioned for EEPROM +FSTAT[ACCERR] +29.4.13 +Security +The flash memory module provides security information to the MCU based on contents +of the FSEC security register. The MCU then limits access to flash memory resources as +defined in the device's Chip Configuration details. During reset, the flash memory +module initializes the FSEC register using data read from the security byte of the Flash +Configuration Field (see Flash Configuration Field Description). +The following fields are available in the FSEC register. The settings are described in the +Flash Security Register (FTFL\_FSEC) details. +Table 29-76. FSEC register fields +FSEC field +Description +KEYEN +Backdoor Key Access +MEEN +Mass Erase Capability +FSLACC +Freescale Factory Access +SEC +MCU security +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +717 +General Business Information + +![Image 1 from page 717](pdf-image://page_717_img_1) + +## Page 718 + +29.4.13.1 +Flash Memory Access by Mode and Security +The following table summarizes how access to the flash memory module is affected by +security and operating mode. +Table 29-77. Flash Memory Access Summary +Operating Mode +Chip Security State +Unsecure +Secure +NVM Normal +Full command set +NVM Special +Full command set +Only the Erase All Blocks and Read 1s All +Blocks commands. +29.4.13.2 +Changing the Security State +The security state out of reset can be permanently changed by programming the security +byte of the flash configuration field. This assumes that you are starting from a mode +where the necessary program flash erase and program commands are available and that +the region of the program flash containing the flash configuration field is unprotected. If +the flash security byte is successfully programmed, its new value takes affect after the +next chip reset. +29.4.13.2.1 +Unsecuring the Chip Using Backdoor Key Access +The chip can be unsecured by using the backdoor key access feature, which requires +knowledge of the contents of the 8-byte backdoor key value stored in the Flash +Configuration Field (see Flash Configuration Field Description). If the FSEC[KEYEN] +bits are in the enabled state, the Verify Backdoor Access Key command (see Verify +Backdoor Access Key Command) can be run; it allows the user to present prospective +keys for comparison to the stored keys. If the keys match, the FSEC[SEC] bits are +changed to unsecure the chip. The entire 8-byte key cannot be all 0s or all 1s; that is, +0000\_0000\_0000\_0000h and FFFF\_FFFF\_FFFF\_FFFFh are not accepted by the Verify +Backdoor Access Key command as valid comparison values. While the Verify Backdoor +Access Key command is active, program flash memory is not available for read access +and returns invalid data. +The user code stored in the program flash memory must have a method of receiving the +backdoor keys from an external stimulus. This external stimulus would typically be +through one of the on-chip serial ports. +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +718 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 718](pdf-image://page_718_img_1) + +## Page 719 + +If the KEYEN bits are in the enabled state, the chip can be unsecured by the following +backdoor key access sequence: +1. Follow the command sequence for the Verify Backdoor Access Key command as +explained in Verify Backdoor Access Key Command +2. If the Verify Backdoor Access Key command is successful, the chip is unsecured and +the FSEC[SEC] bits are forced to the unsecure state +An illegal key provided to the Verify Backdoor Access Key command prohibits further +use of the Verify Backdoor Access Key command. A reset of the chip is the only method +to re-enable the Verify Backdoor Access Key command when a comparison fails. +After the backdoor keys have been correctly matched, the chip is unsecured by changing +the FSEC[SEC] bits. A successful execution of the Verify Backdoor Access Key +command changes the security in the FSEC register only. It does not alter the security +byte or the keys stored in the Flash Configuration Field (Flash Configuration Field +Description). After the next reset of the chip, the security state of the flash memory +module reverts back to the flash security byte in the Flash Configuration Field. The +Verify Backdoor Access Key command sequence has no effect on the program and erase +protections defined in the program flash protection registers. +If the backdoor keys successfully match, the unsecured chip has full control of the +contents of the Flash Configuration Field. The chip may erase the sector containing the +Flash Configuration Field and reprogram the flash security byte to the unsecure state and +change the backdoor keys to any desired value. +29.4.14 +Reset Sequence +On each system reset the flash memory module executes a sequence which establishes +initial values for the flash block configuration parameters, FPROT, FDPROT, FEPROT, +FOPT, and FSEC registers and the FCNFG[SWAP, PFLSH, RAMRDY, EEERDY] bits. +FSTAT[CCIF] is cleared throughout the reset sequence. The flash memory module holds +off CPU access during the reset sequence. Flash reads are possible when the hold is +removed. Completion of the reset sequence is marked by setting CCIF which enables +flash user commands. +If a reset occurs while any flash command is in progress, that command is immediately +aborted. The state of the word being programmed or the sector/block being erased is not +guaranteed. Commands and operations do not automatically resume after exiting reset. +Chapter 29 Flash Memory Module (FTFL) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +719 +General Business Information + +![Image 1 from page 719](pdf-image://page_719_img_1) + +## Page 720 + +Functional Description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +720 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 720](pdf-image://page_720_img_1) + +## Page 721 + +Chapter 30 +External Bus Interface (FlexBus) +30.1 +Introduction +NOTE +For the chip-specific implementation details of this module's +instances see the chip configuration information. +PUBLICATION ERROR: In module memory map tables, +register reset values may be incorrect. See the individual +register diagrams for accurate reset information. +This chapter describes external bus data transfer operations and error conditions. It +describes transfers initiated by the core processor (or any other bus master) and includes +detailed timing diagrams showing the interaction of signals in supported bus operations. +30.1.1 +Definition +The FlexBus multifunction external bus interface controller is a hardware module that: +• Provides memory expansion and provides connection to external peripherals with a +parallel bus +• Can be directly connected to the following asynchronous or synchronous slave-only +devices with little or no additional circuitry: +• External ROMs +• Flash memories +• Programmable logic devices +• Other simple target (slave) devices +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +721 +General Business Information + +![Image 1 from page 721](pdf-image://page_721_img_1) + +## Page 722 + +30.1.2 +Features +FlexBus offers the following features: +• Six independent, user-programmable chip-select signals (FB\_CS5 –FB\_CS0) +• 8-bit, 16-bit, and 32-bit port sizes with configuration for multiplexed or +nonmultiplexed address and data buses +• 8-bit, 16-bit, 32-bit, and 16-byte transfers +• Programmable burst and burst-inhibited transfers selectable for each chip-select and +transfer direction +• Programmable address-setup time with respect to the assertion of a chip-select +• Programmable address-hold time with respect to the deassertion of a chip-select and +transfer direction +• Extended address latch enable option to assist with glueless connections to +synchronous and asynchronous memory devices +30.2 +Signal descriptions +This table describes the external signals involved in data-transfer operations. +NOTE +Not all of the following signals may be available on a particular +device. See the Chip Configuration details for information on +which signals are available. +Table 30-1. FlexBus signal descriptions +Signal +I/O +Function +FB\_A31–FB\_A0 +O +Address Bus +When FlexBus is used in a nonmultiplexed configuration, this is the address bus. When +FlexBus is used in a multiplexed configuration, this bus is not used. +FB\_D31–FB\_D0 +I/O +Data Bus—During the first cycle, this bus drives the upper address byte, addr[31:24]. +When FlexBus is used in a nonmultiplexed configuration, this is the data bus, FB\_D. +When FlexBus is used in a multiplexed configuration, this is the address and data bus, +FB\_AD. +The number of byte lanes carrying the data is determined by the port size associated +with the matching chip-select. +When FlexBus is used in a multiplexed configuration, the full 32-bit address is driven on +the first clock of a bus cycle (address phase). After the first clock, the data is driven on +the bus (data phase). During the data phase, the address is driven on the pins not used +for data. For example, in 16-bit mode, the lower address is driven on FB\_AD15– +FB\_AD0, and in 8-bit mode, the lower address is driven on FB\_AD23–FB\_AD0. +Table continues on the next page... +Signal descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +722 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 722](pdf-image://page_722_img_1) + +## Page 723 + +Table 30-1. FlexBus signal descriptions (continued) +Signal +I/O +Function +FB\_CS5–FB\_CS0 +O +General Purpose Chip-Selects—Indicate which external memory or peripheral is +selected. A particular chip-select is asserted when the transfer address is within the +external memory's or peripheral's address space, as defined in CSAR[BA] and +CSMR[BAM]. +FB\_BE\_31\_24 +FB\_BE\_23\_16 +FB\_BE\_15\_8 +FB\_BE\_7\_0 +O +Byte Enables—Indicate that data is to be latched or driven onto a specific byte lane of +the data bus. CSCR[BEM] determines if these signals are asserted on reads and writes +or on writes only. +For external SRAM or flash devices, the FB\_BE outputs should be connected to +individual byte strobe signals. +FB\_OE +O +Output Enable—Sent to the external memory or peripheral to enable a read transfer. +This signal is asserted during read accesses only when a chip-select matches the +current address decode. +FB\_R/W +O +Read/Write—Indicates whether the current bus operation is a read operation (FB\_R/W +high) or a write operation (FB\_R/W low). +FB\_TS +O +Transfer Start—Indicates that the chip has begun a bus transaction and that the +address and attributes are valid. +An inverted FB\_TS is available as an address latch enable (FB\_ALE), which indicates +when the address is being driven on the FB\_AD bus. +FB\_TS/FB\_ALE is asserted for one bus clock cycle. +The chip can extend this signal until the first positive clock edge after FB\_CS asserts. +See CSCR[EXTS] and Extended Transfer Start/Address Latch Enable. +FB\_ALE +O +Address Latch Enable—Indicates when the address is being driven on the FB\_A bus +(inverse of FB\_TS). +Table continues on the next page... +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +723 +General Business Information + +![Image 1 from page 723](pdf-image://page_723_img_1) + +## Page 724 + +Table 30-1. FlexBus signal descriptions (continued) +Signal +I/O +Function +FB\_TSIZ1–FB\_TSIZ0 +O +Transfer Size—Indicates (along with FB\_TBST) the data transfer size of the current +bus operation. The interface supports 8-, 16-, and 32-bit operand transfers and allows +accesses to 8-, 16-, and 32-bit data ports. +• 00b = 4 bytes +• 01b = 1 byte +• 10b = 2 bytes +• 11b = 16 bytes (line) +For misaligned transfers, FB\_TSIZ1–FB\_TSIZ0 indicate the size of each transfer. For +example, if a 32-bit access through a 32-bit port device occurs at a misaligned offset of +1h, 8 bits are transferred first (FB\_TSIZ1–FB\_TSIZ0 = 01b), 16 bits are transferred +next at offset 2h (FB\_TSIZ1–FB\_TSIZ0 = 10b), and the final 8 bits are transferred at +offset 4h (FB\_TSIZ1–FB\_TSIZ0 = 01b). +For aligned transfers larger than the port size, FB\_TSIZ1–FB\_TSIZ0 behave as follows: +• If bursting is used, FB\_TSIZ1–FB\_TSIZ0 are driven to the transfer size. +• If bursting is inhibited, FB\_TSIZ1–FB\_TSIZ0 first show the entire transfer size +and then show the port size. +For burst-inhibited transfers, FB\_TSIZ1–FB\_TSIZ0 change with each FB\_TS assertion +to reflect the next transfer size. +For transfers to port sizes smaller than the transfer size, FB\_TSIZ1–FB\_TSIZ0 indicate +the size of the entire transfer on the first access and the size of the current port transfer +on subsequent transfers. For example, for a 32-bit write to an 8-bit port, FB\_TSIZ1– +FB\_TSIZ0 are 00b for the first transaction and 01b for the next three transactions. If +bursting is used for a 32-bit write to an 8-bit port, FB\_TSIZ1–FB\_TSIZ0 are driven to +00b for the entire transfer. +FB\_TBST +O +Transfer Burst—Indicates that a burst transfer is in progress as driven by the chip. A +burst transfer can be 2 to 16 beats depending on FB\_TSIZ1–FB\_TSIZ0 and the port +size. +Note: When a burst transfer is in progress (FB\_TBST = 0b), the transfer size is 16 +bytes (FB\_TSIZ1–FB\_TSIZ0 = 11b), and the address is misaligned within the +16-byte boundary, the external memory or peripheral must be able to wrap +around the address. +Table continues on the next page... +Signal descriptions +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +724 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 724](pdf-image://page_724_img_1) + +## Page 725 + +Table 30-1. FlexBus signal descriptions (continued) +Signal +I/O +Function +FB\_TA +I +Transfer Acknowledge—Indicates that the external data transfer is complete. When +FB\_TA is asserted during a read transfer, FlexBus latches the data and then terminates +the transfer. When FB\_TA is asserted during a write transfer, the transfer is terminated. +If auto-acknowledge is disabled (CSCR[AA] = 0), the external memory or peripheral +drives FB\_TA to terminate the transfer. If auto-acknowledge is enabled (CSCR[AA] = +1), FB\_TA is generated internally after a specified number of wait states, or the external +memory or peripheral may assert external FB\_TA before the wait-state countdown to +terminate the transfer early. The chip deasserts FB\_CS one cycle after the last FB\_TA +is asserted. During read transfers, the external memory or peripheral must continue to +drive data until FB\_TA is recognized. For write transfers, the chip continues driving +data one clock cycle after FB\_CS is deasserted. +The number of wait states is determined by CSCR or the external FB\_TA input. If the +external FB\_TA is used, the external memory or peripheral has complete control of the +number of wait states. +Note: External memory or peripherals should assert FB\_TA only while the FB\_CS +signal to the external memory or peripheral is asserted. +The CSPMCR register controls muxing of FB\_TA with other signals. If auto- +acknowledge is not used and CSPMCR does not allow FB\_TA control, FlexBus +may hang. +FB\_CLK +O +FlexBus Clock Output +30.3 +Memory Map/Register Definition +The following tables describe the registers and bit meanings for configuring chip-select +operation. +The actual number of chip selects available depends upon the device and its pin +configuration. If the device does not support certain chip select signals or the pin is not +configured for a chip-select function, then that corresponding set of chip-select registers +has no effect on an external pin. +Note +You must set CSMR0[V] before the chip select registers take +effect. +A bus error occurs when writing to reserved register locations. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +725 +General Business Information + +![Image 1 from page 725](pdf-image://page_725_img_1) + +## Page 726 + +FB memory map +Absolute +address +(hex) +Register name +Width +(in bits) +Access +Reset value +Section/ +page +4000\_C000 +Chip Select Address Register (FB\_CSAR0) +32 +R/W +0\_0000 +\_0000h +30.3.1/727 +4000\_C004 +Chip Select Mask Register (FB\_CSMR0) +32 +R/W +0\_0000 +\_0000h +30.3.2/727 +4000\_C008 +Chip Select Control Register (FB\_CSCR0) +32 +R/W +0\_0000 +\_0000h +30.3.3/728 +4000\_C00C +Chip Select Address Register (FB\_CSAR1) +32 +R/W +0\_0000 +\_0000h +30.3.1/727 +4000\_C010 +Chip Select Mask Register (FB\_CSMR1) +32 +R/W +0\_0000 +\_0000h +30.3.2/727 +4000\_C014 +Chip Select Control Register (FB\_CSCR1) +32 +R/W +0\_0000 +\_0000h +30.3.3/728 +4000\_C018 +Chip Select Address Register (FB\_CSAR2) +32 +R/W +0\_0000 +\_0000h +30.3.1/727 +4000\_C01C +Chip Select Mask Register (FB\_CSMR2) +32 +R/W +0\_0000 +\_0000h +30.3.2/727 +4000\_C020 +Chip Select Control Register (FB\_CSCR2) +32 +R/W +0\_0000 +\_0000h +30.3.3/728 +4000\_C024 +Chip Select Address Register (FB\_CSAR3) +32 +R/W +0\_0000 +\_0000h +30.3.1/727 +4000\_C028 +Chip Select Mask Register (FB\_CSMR3) +32 +R/W +0\_0000 +\_0000h +30.3.2/727 +4000\_C02C +Chip Select Control Register (FB\_CSCR3) +32 +R/W +0\_0000 +\_0000h +30.3.3/728 +4000\_C030 +Chip Select Address Register (FB\_CSAR4) +32 +R/W +0\_0000 +\_0000h +30.3.1/727 +4000\_C034 +Chip Select Mask Register (FB\_CSMR4) +32 +R/W +0\_0000 +\_0000h +30.3.2/727 +4000\_C038 +Chip Select Control Register (FB\_CSCR4) +32 +R/W +0\_0000 +\_0000h +30.3.3/728 +4000\_C03C +Chip Select Address Register (FB\_CSAR5) +32 +R/W +0\_0000 +\_0000h +30.3.1/727 +4000\_C040 +Chip Select Mask Register (FB\_CSMR5) +32 +R/W +0\_0000 +\_0000h +30.3.2/727 +4000\_C044 +Chip Select Control Register (FB\_CSCR5) +32 +R/W +0\_0000 +\_0000h +30.3.3/728 +4000\_C060 +Chip Select port Multiplexing Control Register +(FB\_CSPMCR) +32 +R/W +0\_0000 +\_0000h +30.3.4/731 +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +726 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 726](pdf-image://page_726_img_1) + +## Page 727 + +30.3.1 +Chip Select Address Register (FB\_CSARn) +Specifies the associated chip-select's base address. +Address: 4000\_C000h base + 0h offset + (12d × i), where i=0d to 5d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +BA +0 +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FB\_CSARn field descriptions +Field +Description +31–16 +BA +Base Address +Defines the base address for memory dedicated to the associated chip-select. BA is compared to bits 31– +16 on the internal address bus to determine if the associated chip-select's memory is being accessed. +NOTE: Because the FlexBus module is one of the slaves connected to the crossbar switch, it is only +accessible within a certain memory range. See the chip memory map for the applicable FlexBus +"expansion" address range for which the chip-selects can be active. Set the CSARn and CSMRn +registers appropriately before accessing this region. +15–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +30.3.2 +Chip Select Mask Register (FB\_CSMRn) +Specifies the address mask and allowable access types for the associated chip-select. +Address: 4000\_C000h base + 4h offset + (12d × i), where i=0d to 5d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +BAM +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +0 +WP +0 +V +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FB\_CSMRn field descriptions +Field +Description +31–16 +BAM +Base Address Mask +Defines the associated chip-select's block size by masking address bits. +Table continues on the next page... +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +727 +General Business Information + +![Image 1 from page 727](pdf-image://page_727_img_1) + +## Page 728 + +FB\_CSMRn field descriptions (continued) +Field +Description +0 +The corresponding address bit in CSAR is used in the chip-select decode. +1 +The corresponding address bit in CSAR is a don’t care in the chip-select decode. +15–9 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +8 +WP +Write Protect +Controls write accesses to the address range in the corresponding CSAR. +0 +Write accesses are allowed. +1 +Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is +set results in a bus error termination of the internal cycle and no external cycle. +7–1 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +0 +V +Valid +Specifies whether the corresponding CSAR, CSMR, and CSCR contents are valid. Programmed chip- +selects do not assert until the V bit is 1b (except for FB\_CS0, which acts as the global chip-select). +NOTE: At reset, no chip-select other than FB\_CS0 can be used until CSMR0[V] is 1b. Afterward, the +FB\_CS [5:0] signals function as programmed. +0 +Chip-select is invalid. +1 +Chip-select is valid. +30.3.3 +Chip Select Control Register (FB\_CSCRn) +Controls the auto-acknowledge, address setup and hold times, port size, burst capability, +and number of wait states for the associated chip select. +NOTE +To support the global chip-select ( FB\_CS0 ), the CSCR0 reset +values differ from the other CSCRs. The reset value of CSCR0 +is as follows: +• Bits 31–24 are 0b +• Bit 23–3 are chip-dependent +• Bits 3–0 are 0b +See the chip configuration details for your particular chip for +information on the exact CSCR0 reset value. +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +728 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 728](pdf-image://page_728_img_1) + +## Page 729 + +Address: 4000\_C000h base + 8h offset + (12d × i), where i=0d to 5d +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +R +SWS +0 +SWSEN +EXTS +ASET +RDAH +WRAH +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Bit +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +WS +BLS +AA +PS +BEM +BSTR +BSTW +0 +W +Reset +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +FB\_CSCRn field descriptions +Field +Description +31–26 +SWS +Secondary Wait States +Used only when the SWSEN bit is 1b. Specifies the number of wait states inserted before an internal +transfer acknowledge is generated for a burst transfer (except for the first termination, which is controlled +by WS). +25–24 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +23 +SWSEN +Secondary Wait State Enable +0 +Disabled. A number of wait states (specified by WS) are inserted before an internal transfer +acknowledge is generated for all transfers. +1 +Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer +acknowledge is generated for burst transfer secondary terminations. +22 +EXTS +Extended Transfer Start/Extended Address Latch Enable +Controls how long FB\_TS /FB\_ALE is asserted. +0 +Disabled. FB\_TS /FB\_ALE asserts for one bus clock cycle. +1 +Enabled. FB\_TS /FB\_ALE remains asserted until the first positive clock edge after FB\_CSn asserts. +21–20 +ASET +Address Setup +Controls when the chip-select is asserted with respect to assertion of a valid address and attributes. +00 +Assert FB\_CSn on the first rising clock edge after the address is asserted (default for all but +FB\_CS0 ). +01 +Assert FB\_CSn on the second rising clock edge after the address is asserted. +10 +Assert FB\_CSn on the third rising clock edge after the address is asserted. +11 +Assert FB\_CSn on the fourth rising clock edge after the address is asserted (default for FB\_CS0 ). +19–18 +RDAH +Read Address Hold or Deselect +Controls the address and attribute hold time after the termination during a read cycle that hits in the +associated chip-select's address space. +Table continues on the next page... +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +729 +General Business Information + +![Image 1 from page 729](pdf-image://page_729_img_1) + +## Page 730 + +FB\_CSCRn field descriptions (continued) +Field +Description +NOTE: +• The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a +transfer to a port size smaller than the transfer size, the hold time is only added after the +last bus cycle. +• The number of cycles the address and attributes are held after FB\_CSn deassertion +depends on the value of the AA bit. +00 +When AA is 0b, 1 cycle. When AA is 1b, 0 cycles. +01 +When AA is 0b, 2 cycles. When AA is 1b, 1 cycle. +10 +When AA is 0b, 3 cycles. When AA is 1b, 2 cycles. +11 +When AA is 0b, 4 cycles. When AA is 1b, 3 cycles. +17–16 +WRAH +Write Address Hold or Deselect +Controls the address, data, and attribute hold time after the termination of a write cycle that hits in the +associated chip-select's address space. +NOTE: The hold time applies only at the end of a transfer. Therefore, during a burst transfer or a transfer +to a port size smaller than the transfer size, the hold time is only added after the last bus cycle. +00 +1 cycle (default for all but FB\_CS0 ) +01 +2 cycles +10 +3 cycles +11 +4 cycles (default for FB\_CS0 ) +15–10 +WS +Wait States +Specifies the number of wait states inserted after FlexBus asserts the associated chip-select and before +an internal transfer acknowledge is generated (WS = 00h inserts 0 wait states, ..., WS = 3Fh inserts 63 +wait states). +9 +BLS +Byte-Lane Shift +Specifies if data on FB\_AD appears left-aligned or right-aligned during the data phase of a FlexBus +access. +0 +Not shifted. Data is left-aligned on FB\_AD. +1 +Shifted. Data is right-aligned on FB\_AD. +8 +AA +Auto-Acknowledge Enable +Asserts the internal transfer acknowledge for accesses specified by the chip-select address. +NOTE: If AA is 1b for a corresponding FB\_CSn and the external system asserts an external FB\_TA +before the wait-state countdown asserts the internal FB\_TA, the cycle is terminated. Burst cycles +increment the address bus between each internal termination. +NOTE: This field must be 1b if CSPMCR disables FB\_TA. +0 +Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally. +1 +Enabled. Internal transfer acknowledge is asserted as specified by WS. +7–6 +PS +Port Size +Specifies the data port width of the associated chip-select, and determines where data is driven during +write cycles and where data is sampled during read cycles. +00 +32-bit port size. Valid data is sampled and driven on FB\_D[31:0]. +01 +8-bit port size. Valid data is sampled and driven on FB\_D[31:24] when BLS is 0b, or FB\_D[7:0] when +BLS is 1b. +Table continues on the next page... +Memory Map/Register Definition +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +730 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 730](pdf-image://page_730_img_1) + +## Page 731 + +FB\_CSCRn field descriptions (continued) +Field +Description +10 +16-bit port size. Valid data is sampled and driven on FB\_D[31:16] when BLS is 0b, or FB\_D[15:0] +when BLS is 1b. +11 +16-bit port size. Valid data sampled and driven on FB\_D[31:16] when BLS is 0b, or FB\_D[15:0] when +BLS is 1b. +5 +BEM +Byte-Enable Mode +Specifies whether the corresponding FB\_BE is asserted for read accesses. Certain memories have byte +enables that must be asserted during reads and writes. Write 1b to the BEM bit in the relevant CSCR to +provide the appropriate mode of byte enable support for these SRAMs. +0 +FB\_BE is asserted for data write only. +1 +FB\_BE is asserted for data read and write accesses. +4 +BSTR +Burst-Read Enable +Specifies whether burst reads are enabled for memory associated with each chip select. +0 +Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. +For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads. +1 +Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- +and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. +3 +BSTW +Burst-Write Enable +Specifies whether burst writes are enabled for memory associated with each chip select. +0 +Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. +For example, a 32-bit write to an 8-bit port takes four byte writes. +1 +Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8 and +16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. +2–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +30.3.4 +Chip Select port Multiplexing Control Register (FB\_CSPMCR) +Controls the multiplexing of the FlexBus signals. +NOTE +A bus error occurs when you do any of the following: +• Write to a reserved address +• Write to a reserved field in this register, or +• Access this register using a size other than 32 bits. +Address: 4000\_C000h base + 60h offset = 4000\_C060h +Bit +31 +30 +29 +28 +27 +26 +25 +24 +23 +22 +21 +20 +19 +18 +17 +16 +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 +R +GROUP1 +GROUP2 +GROUP3 +GROUP4 +GROUP5 +0 +W +Reset 0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +0 +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +731 +General Business Information + +![Image 1 from page 731](pdf-image://page_731_img_1) + +## Page 732 + +FB\_CSPMCR field descriptions +Field +Description +31–28 +GROUP1 +FlexBus Signal Group 1 Multiplex control +Controls the multiplexing of the FB\_ALE, FB\_CS1 , and FB\_TS signals. +0000 +FB\_ALE +0001 +FB\_CS1 +0010 +FB\_TS +Any other value Reserved +27–24 +GROUP2 +FlexBus Signal Group 2 Multiplex control +Controls the multiplexing of the FB\_CS4 , FB\_TSIZ0, and FB\_BE\_31\_24 signals. +0000 +FB\_CS4 +0001 +FB\_TSIZ0 +0010 +FB\_BE\_31\_24 +Any other value Reserved +23–20 +GROUP3 +FlexBus Signal Group 3 Multiplex control +Controls the multiplexing of the FB\_CS5 , FB\_TSIZ1, and FB\_BE\_23\_16 signals. +0000 +FB\_CS5 +0001 +FB\_TSIZ1 +0010 +FB\_BE\_23\_16 +Any other value Reserved +19–16 +GROUP4 +FlexBus Signal Group 4 Multiplex control +Controls the multiplexing of the FB\_TBST , FB\_CS2 , and FB\_BE\_15\_8 signals. +0000 +FB\_TBST +0001 +FB\_CS2 +0010 +FB\_BE\_15\_8 +Any other value Reserved +15–12 +GROUP5 +FlexBus Signal Group 5 Multiplex control +Controls the multiplexing of the FB\_TA , FB\_CS3 , and FB\_BE\_7\_0 signals. +NOTE: When GROUP5 is not 0000b, you must write 1b to the CSCR[AA] bit. Otherwise, the bus hangs +during a transfer. +0000 +FB\_TA +0001 +FB\_CS3 . You must also write 1b to CSCR[AA]. +0010 +FB\_BE\_7\_0 . You must also write 1b to CSCR[AA]. +Any other value Reserved +11–0 +Reserved +This field is reserved. +This read-only field is reserved and always has the value 0. +30.4 +Functional description +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +732 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 732](pdf-image://page_732_img_1) + +## Page 733 + +30.4.1 +Modes of operation +FlexBus supports the following modes of operation: +• Multiplexed 32-bit address and 32-bit data +• Multiplexed 32-bit address and 16-bit data (non-multiplexed 16-bit address and 16- +bit data) +• Multiplexed 32-bit address and 8-bit data (non-multiplexed 24-bit address and 8-bit +data) +• Non-multiplexed 32-bit address and 32-bit data busses +30.4.2 +Address comparison +When a bus cycle is routed to FlexBus, FlexBus compares the transfer address to the base +address and base address mask. This table describes how FlexBus decides to assert a +chip-select and complete the bus cycle based on the address comparison. +When the transfer address +Then FlexBus +Matches one address register +configuration +Asserts the appropriate chip-select, generating a FlexBus bus cycle as defined in the +appropriate CSCR. +If CSMR[WP] is set and a write access is performed, FlexBus terminates the internal +bus cycle with a bus error, does not assert a chip-select, and does not perform an +external bus cycle. +Does not match a address register +configuration +Terminates the transfer with a bus error response, does not assert a chip-select, and +does not perform a FlexBus cycle. +Matches more than one address +register configuration +Terminates the transfer with a bus error response, does not assert a chip-select, and +does not perform a FlexBus cycle. +30.4.3 +Address driven on address bus +FlexBus always drives a 32-bit address on the FB\_AD bus regardless of the external +memory's or peripheral's address size. +30.4.4 +Connecting address/data lines +The external device must connect its address and data lines as follows: +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +733 +General Business Information + +![Image 1 from page 733](pdf-image://page_733_img_1) + +## Page 734 + +• Address lines +• FB\_AD from FB\_AD0 upward +• Data lines +• If CSCR[BLS] = 0, FB\_AD from FB\_AD31 downward +• If CSCR[BLS] = 1, FB\_AD from FB\_AD0 upward +30.4.5 +Bit ordering +No bit ordering is required when connecting address and data lines to the FB\_AD bus. +For example, a full 16-bit address/16-bit data device connects its addr15–addr0 to +FB\_AD16–FB\_AD1 and data15–data0 to FB\_AD31–FB\_AD16. See Data-byte +alignment and physical connections for a graphical connection. +30.4.6 +Data transfer signals +Data transfers between FlexBus and the external memory or peripheral involve these +signals: +• Address/data bus (FB\_AD31–FB\_AD0 ) +• Control signals (FB\_TS/FB\_ALE, FB\_TA, FB\_CSn, FB\_OE, FB\_R/W, FB\_BEn) +• Attribute signals (FB\_TBST, FB\_TSIZ1–FB\_TSIZ0) +30.4.7 +Signal transitions +These signals change on the rising edge of the FlexBus clock (FB\_CLK): +• Address +• Write data +• FB\_TS/FB\_ALE +• FB\_CSn +• All attribute signals +FlexBus latches the read data on the rising edge of the clock. +30.4.8 +Data-byte alignment and physical connections +The device aligns data transfers in FlexBus byte lanes with the number of lanes +depending on the data port width. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +734 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 734](pdf-image://page_734_img_1) + +## Page 735 + +The following figure shows the byte lanes that external memory or peripheral connects to +and the sequential transfers of a 32-bit transfer for the supported port sizes when byte +lane shift is disabled. For example, an 8-bit memory connects to the single lane +FB\_AD31–FB\_AD24 (FB\_BE\_31\_24). A 32-bit transfer through this 8-bit port takes +four transfers, starting with the LSB to the MSB. A 32-bit transfer through a 32-bit port +requires one transfer on each four-byte lane. +External +Data Bus +32-Bit Port +Memory +16-Bit Port +Memory +8-Bit Port +Memory +Byte Select +Byte 0 +Byte 1 +Byte 2 +Byte 3 +Byte 1 +Byte 0 +Byte 3 +Byte 2 +Byte 3 +Byte 2 +Byte 1 +Byte 0 +Driven with +address values +Driven with +address values +FB\_D[31:24] +FB\_D[23:16] +FB\_D[15:8] +FB\_D[7:0] +FB\_BE\_7\_0 +FB\_BE\_15\_8 +FB\_BE\_23\_16 +FB\_BE\_31\_24 +Figure 30-23. Connections for external memory port sizes (CSCRn[BLS] = 0) +The following figure shows the byte lanes that external memory or peripheral connects to +and the sequential transfers of a 32-bit transfer for the supported port sizes when byte +lane shift is enabled. +32-Bit Port +Memory +16-Bit Port +Memory +8-Bit Port +Memory +Byte 3 +Byte 2 +Byte 1 +Byte 0 +Driven with +address values +Driven with +address values +Byte 1 +Byte 0 +Byte 3 +Byte 2 +Byte 0 +Byte 1 +Byte 2 +Byte 3 +External Data Bus +Byte Select +FB\_AD[31:24] +FB\_AD[23:16] +FB\_AD15:8] +FB\_AD[7:0] +FB\_BE31\_24 +FB\_BE23\_16 +FB\_BE15\_8 +FB\_BE7\_0 +FB\_BE23\_16 +FB\_BE31\_24 +FB\_BE31\_24 +Figure 30-24. Connections for external memory port sizes (CSCRn[BLS] = 1) +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +735 +General Business Information + +![Image 1 from page 735](pdf-image://page_735_img_1) + +## Page 736 + +30.4.9 +Address/data bus multiplexing +FlexBus supports a single 32-bit wide multiplexed address and data bus (FB\_AD31– +FB\_AD0). FlexBus always drives the full 32-bit address on the first clock of a bus cycle. +During the data phase, the FB\_AD31– FB\_AD0 lines used for data are determined by the +programmed port size and BLS setting for the corresponding chip-select. FlexBus +continues to drive the address on any FB\_AD31– FB\_AD0 lines not used for data. +30.4.9.1 +FlexBus multiplexed operating modes for CSCRn[BLS]=0 +This table shows the supported combinations of address and data bus widths when +CSCRn[BLS] is 0b. +Port size and phase +FB\_AD +31–24 +23–16 +15–8 +7–0 +32-bit +Address phase +Address +Data phase +Data +16-bit +Address phase +Address +Data phase +Data +Address +8-bit +Address phase +Address +Data phase +Data +Address +30.4.9.2 +FlexBus multiplexed operating modes for CSCRn[BLS]=1 +This table shows the supported combinations of address and data bus widths when +CSCRn[BLS] is 1b. +Port size and phase +FB\_AD +31–24 +23–16 +15–8 +7–0 +32-bit +Address phase +Address +Data phase +Data +16-bit +Address phase +Address +Data phase +Address +Data +8-bit +Address phase +Address +Data phase +Address +Data +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +736 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 736](pdf-image://page_736_img_1) + +## Page 737 + +30.4.10 +Data transfer states +Basic data transfers occur in four clocks or states. (See Figure 30-26 and Figure 30-28 for +examples of basic data transfers.) The FlexBus state machine controls the data-transfer +operation. This figure shows the state-transition diagram for basic read and write cycles. +S0 +S1 +S2 +Wait States +S3 +Next Cycle +The states are described in this table. +State +Cycle +Description +S0 +All +The read or write cycle is initiated. On the rising clock edge, FlexBus: +• Places a valid address on FB\_ADn +• Asserts FB\_TS/FB\_ALE +• Drives FB\_R/W high for a read and low for a write +S1 +All +FlexBus: +• Negates FB\_TS/FB\_ALE on the rising edge of FB\_CLK +• Asserts FB\_CSn +• Drives the data on FB\_AD31– FB\_ADX for writes +• Tristates FB\_AD31– FB\_ADX for reads +• Continues to drive the address on FB\_AD pins that are unused for data +If the external memory or perihperal asserts FB\_TA, then the process moves to S2. If FB\_TA is not +asserted internally or externally, then S1 repeats. +Read +The external memory or peripheral drives the data before the next rising edge of FB\_CLK (the rising +edge that begins S2) with FB\_TA asserted. +S2 +All +For internal termination, FlexBus negates FB\_CSn and the transfer is complete. For external +termination, the external memory or peripheral negates FB\_TA, and FlexBus negates FB\_CSn after +the rising edge of FB\_CLK at the end of S2. +Read +FlexBus latches the data on the rising clock edge entering S2. The external memory or peripheral +can stop driving the data after this edge or continue to drive the data until the end of S3 or through +any additional address hold cycles. +S3 +All +FlexBus invalidates the address, data, and FB\_R/W on the rising edge of FB\_CLK at the beginning +of S3, terminating the transfer. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +737 +General Business Information + +![Image 1 from page 737](pdf-image://page_737_img_1) + +## Page 738 + +30.4.11 +FlexBus Timing Examples +Note +The timing diagrams throughout this section use signal names +that may not be included on your particular device. Ignore these +extraneous signals. +Note +Throughout this section: +• FB\_D[X] indicates a 32-, 16-, or 8-bit wide data bus +• FB\_A[Y] indicates an address bus that can be 32, 24, or 16 +bits wide. +30.4.11.1 +Basic Read Bus Cycle +During a read cycle, the MCU receives data from memory or a peripheral device. The +following figure shows a read cycle flowchart. +1. Decode address. +3. Assert FB\_TA (external termination). +1. Negate FB_TA (external termination). +1. Set FB_R/W to read. +2. Assert FB\_CSn. +(auto-acknowledge/internal termination). +2. Sample FB\_TA low and latch data. +1. Start next cycle. +System +2. Place address on the external address signals. +2. Drive data on the external data signals. +1. Select the appropriate slave device. +3. Assert transfer start. +1. Negate transfer start. +1. FlexBus asserts internal FB_TA +Microcontroller +Figure 30-25. Read Cycle Flowchart +The read cycle timing diagram is shown in the following figure. +Note +FB\_TA does not have to be driven by the external device for +internally-terminated bus cycles. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +738 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 738](pdf-image://page_738_img_1) + +## Page 739 + +Note +The processor drives the data lines during the first clock cycle +of the transfer with the full 32-bit address. This may be ignored +by standard connected devices using non-multiplexed address +and data buses. However, some applications may find this +feature beneficial. +The address and data busses are muxed between the FlexBus +and another module. At the end of the read bus cycles the +address signals are indeterminate. +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-26. Basic Read-Bus Cycle +30.4.11.2 +Basic Write Bus Cycle +During a write cycle, the device sends data to memory or to a peripheral device. The +following figure shows the write cycle flowchart. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +739 +General Business Information + +![Image 1 from page 739](pdf-image://page_739_img_1) + +## Page 740 + +1. Set FB_R/W to write. +2. Place address on the external address signals. +3. Assert transfer start. +1. Decode address. +1. Start next cycle. +2. Sample FB\_TA low. +External Memory/Peripheral +2. Latch data on the external address signals. +3. Assert FB\_TA (external termination). +1. Negate FB_TA (external termination). +1. Select the appropriate slave device. +1. Negate transfer start. +2. Assert FB\_CSn. +3. Drive data. +1. FlexBus asserts internal FB_TA +(auto acknowledge/internal termination). +FlexBus +Figure 30-27. Write-Cycle Flowchart +The following figure shows the write cycle timing diagram. +Note +The address and data busses are muxed between the FlexBus +and another module. At the end of the write bus cycles, the +address signals are indeterminate. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +740 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 740](pdf-image://page_740_img_1) + +## Page 741 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-28. Basic Write-Bus Cycle +30.4.11.3 +Bus Cycle Sizing +This section shows timing diagrams for various port size scenarios. +30.4.11.3.1 +Bus Cycle Sizing—Byte Transfer, 8-bit Device, No Wait States +The following figure illustrates the basic byte read transfer to an 8-bit device with no wait +states: +• The address is driven on the full FB\_AD[31:8] bus in the first clock. +• The device tristates FB\_AD[31:24] on the second clock and continues to drive +address on FB\_AD[23:0] throughout the bus cycle. +• The external device returns the read data on FB\_AD[31:24] and may tristate the data +line or continue driving the data one clock after FB\_TA is sampled asserted. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +741 +General Business Information + +![Image 1 from page 741](pdf-image://page_741_img_1) + +## Page 742 + +Address +Address +Data +TSIZ = 01 +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-29. Single Byte-Read Transfer +The following figure shows the similar configuration for a write transfer. The data is +driven from the second clock on FB\_AD[31:24]. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +742 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 742](pdf-image://page_742_img_1) + +## Page 743 + +Address +Address +Data +TSIZ=01 +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-30. Single Byte-Write Transfer +30.4.11.3.2 +Bus Cycle Sizing—Word Transfer, 16-bit Device, No Wait +States +The following figure illustrates the basic word read transfer to a 16-bit device with no +wait states. +• The address is driven on the full FB\_AD[31:8] bus in the first clock. +• The device tristates FB\_AD[31:16] on the second clock and continues to drive +address on FB\_AD[15:0] throughout the bus cycle. +• The external device returns the read data on FB\_AD[31:16] and may tristate the data +line or continue driving the data one clock after FB\_TA is sampled asserted. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +743 +General Business Information + +![Image 1 from page 743](pdf-image://page_743_img_1) + +## Page 744 + +Address +Address +Data +TSIZ = 10 +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-31. Single Word-Read Transfer +The following figure shows the similar configuration for a write transfer. The data is +driven from the second clock on FB\_AD[31:16]. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +744 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 744](pdf-image://page_744_img_1) + +## Page 745 + +Address +Address +Data +TSIZ=10 +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-32. Single Word-Write Transfer +30.4.11.3.3 +Bus Cycle Sizing—Longword Transfer, 32-bit Device, No Wait +States +The following figure depicts a longword read from a 32-bit device. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +745 +General Business Information + +![Image 1 from page 745](pdf-image://page_745_img_1) + +## Page 746 + +Address +Address +Data +TSIZ = 00 +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-33. Longword-Read Transfer +The following figure illustrates the longword write to a 32-bit device. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +746 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 746](pdf-image://page_746_img_1) + +## Page 747 + +Address +Address +Data +TSIZ=00 +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-34. Longword-Write Transfer +30.4.11.4 +Timing Variations +The FlexBus module has several features that can change the timing characteristics of a +basic read- or write-bus cycle to provide additional address setup, address hold, and time +for a device to provide or latch data. +30.4.11.4.1 +Wait States +Wait states can be inserted before each beat of a transfer by programming the CSCRn +registers. Wait states can give the peripheral or memory more time to return read data or +sample write data. +The following figures show the basic read and write bus cycles (also shown in Figure +30-26 and Figure 30-31) with the default of no wait states respectively. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +747 +General Business Information + +![Image 1 from page 747](pdf-image://page_747_img_1) + +## Page 748 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-35. Basic Read-Bus Cycle (No Wait States) +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +748 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 748](pdf-image://page_748_img_1) + +## Page 749 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-36. Basic Write-Bus Cycle (No Wait States) +If wait states are used, the S1 state repeats continuously until the chip-select auto- +acknowledge unit asserts internal transfer acknowledge or the external FB\_TA is +recognized as asserted. The following figures show a read and write cycle with one wait +state respectively. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +749 +General Business Information + +![Image 1 from page 749](pdf-image://page_749_img_1) + +## Page 750 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-37. Read-Bus Cycle (One Wait State) +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +750 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 750](pdf-image://page_750_img_1) + +## Page 751 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-38. Write-Bus Cycle (One Wait State) +30.4.11.4.2 +Address Setup and Hold +The timing of the assertion and negation of the chip selects, byte selects, and output +enable can be programmed on a chip-select basis. Each chip-select can be programmed to +assert one to four clocks after transfer start/address-latch enable (FB\_TS/FB\_ALE) is +asserted. The following figures show read- and write-bus cycles with two clocks of +address setup respectively. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +751 +General Business Information + +![Image 1 from page 751](pdf-image://page_751_img_1) + +## Page 752 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-39. Read-Bus Cycle with Two-Clock Address Setup (No Wait States) +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +752 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 752](pdf-image://page_752_img_1) + +## Page 753 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-40. Write-Bus Cycle with Two Clock Address Setup (No Wait States) +In addition to address setup, a programmable address hold option for each chip select +exists. Address and attributes can be held one to four clocks after chip-select, byte- +selects, and output-enable negate. The following figures show read and write bus cycles +with two clocks of address hold respectively. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +753 +General Business Information + +![Image 1 from page 753](pdf-image://page_753_img_1) + +## Page 754 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-41. Read Cycle with Two-Clock Address Hold (No Wait States) +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +754 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 754](pdf-image://page_754_img_1) + +## Page 755 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-42. Write Cycle with Two-Clock Address Hold (No Wait States) +The following figure shows a bus cycle using address setup, wait states, and address hold. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +755 +General Business Information + +![Image 1 from page 755](pdf-image://page_755_img_1) + +## Page 756 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +Figure 30-43. Write Cycle with Two-Clock Address Setup and Two-Clock Hold (One Wait +State) +30.4.12 +Burst cycles +The chip can be programmed to initiate burst cycles if its transfer size exceeds the port +size of the selected destination. The initiation of a burst cycle is encoded on the transfer +size pins (FB\_TSIZ[1:0]). For burst transfers to smaller port sizes, FB\_TSIZ[1:0] +indicates the size of the entire transfer. For example, with bursting enabled, a 16-bit +transfer to an 8-bit port takes two beats (two byte-sized transfers), for which +FB\_TSIZ[1:0] equals 10b throughout. A 32-bit transfer to an 8-bit port takes four beats +(four byte-sized transfers), for which FB\_TSIZ[1:0] equals 00b throughout. +30.4.12.1 +Enabling and inhibiting burst +The CSCRn registers enable bursting for reads, writes, or both. +Memory spaces can be declared burst-inhibited for reads and writes by writing 0b to the +appropriate CSCRn[BSTR] and CSCRn[BSTW] fields. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +756 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 756](pdf-image://page_756_img_1) + +## Page 757 + +30.4.12.2 +Transfer size and port size translation +With bursting disabled, any transfer larger than the port size breaks into multiple +individual transfers (e.g. ). With +bursting enabled, any transfer larger than the port size results in a burst cycle of multiple +beats (e.g. ). The following table shows the result of such +transfer translations. +Port size PS[1:0] +Transfer size FB\_TSIZ[1:0] +Burst-inhibited: Number of transfers +Burst enabled: Number of beats +01b (8 bit) +10b (16 bits) +2 +00b (32 bits) +4 +11b (16 bytes) +16 +1Xb (16 bit) +00b (32 bits) +2 +11b (16 bytes) +8 +00b (32 bit) +11b (line) +4 +The FlexBus can support X-1-1-1 burst cycles to maximize system performance, where X +is the primary number of wait states (max 63). Delaying termination of the cycle can add +wait states. If internal termination is used, different wait state counters can be used for the +first access and the following beats. +30.4.12.3 +32-bit-Read burst from 8-Bit port 2-1-1-1 (no wait states) +The following figure shows a 32-bit read to an 8-bit external chip programmed for burst +enable. The transfer results in a 4-beat burst and the data is driven on FB\_AD[31:24]. +The transfer size is driven at 32-bit (00b) throughout the bus cycle. +Note +In non-multiplexed address/data mode, the address on FB\_A +increments only during internally-terminated burst cycles. The +first address is driven throughout the entire burst for externally- +terminated cycles. +In multiplexed address/data mode, the address is driven on +FB\_AD only during the first cycle for all terminated cycles. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +757 +General Business Information + +![Image 1 from page 757](pdf-image://page_757_img_1) + +## Page 758 + +Address +Address +Data +TSIZ = 11 +AA=1 +AA=0 +AA=1 +AA=0 +Data +Data +Data +Add+1 +Add+2 +Add+3 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +30.4.12.4 +32-bit-Write burst to 8-Bit port 3-1-1-1 (no wait states) +The following figure shows a 32-bit write to an 8-bit external chip with burst enabled. +The transfer results in a 4-beat burst and the data is driven on FB\_AD[31:24]. The +transfer size is driven at 32-bit (00b) throughout the bus cycle. +Note +The first beat of any write burst cycle has at least one wait state. +If the bus cycle is programmed for zero wait states +(CSCRn[WS] = 0b), one wait state is added. Otherwise, the +programmed number of wait states are used. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +758 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 758](pdf-image://page_758_img_1) + +## Page 759 + +Address +Address +Data +TSIZ +AA=1 +AA=0 +AA=1 +AA=0 +Data +Data +Data +Add+1 +Add+2 +Add+3 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +30.4.12.5 +32-bit-write burst-inhibited to 8-bit port (no wait states) +The following figure shows a 32-bit write to an 8-bit device with burst inhibited. The +transfer results in four individual transfers. The transfer size is driven at 32-bit (00b) +during the first transfer and at byte (01b) during the next three transfers. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +759 +General Business Information + +![Image 1 from page 759](pdf-image://page_759_img_1) + +## Page 760 + +Add +Data +TSIZ = 00 +AA=1 +AA=0 +AA=1 +AA=0 +Data +Data +Data +TSIZ = 01 +Add+3 +Add+2 +Add+1 +Add+1 +Add+2 +Add+3 +Address +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TBST +FB\_TSIZ[1:0] +30.4.12.6 +32-bit-read burst from 8-bit port 3-2-2-2 (one wait state) +The following figure illustrates another read burst transfer, but in this case a wait state is +added between individual beats. +Note +CSCRn[WS] determines the number of wait states in the first +beat. However, for subsequent beats, the CSCRn[WS] (or +CSCRn[SWS] if CSCRn[SWSEN] = 1b) determines the +number of wait states. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +760 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 760](pdf-image://page_760_img_1) + +## Page 761 + +Address +Address +Data +TSIZ = 00 +AA=1 +AA=0 +AA=1 +AA=0 +Data +Data +Add+1 +Add+2 +Add+3 +Data +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +30.4.12.7 +32-bit-write burst to 8-bit port 3-2-2-2 (one wait state) +The following figure illustrates a write burst transfer with one wait state. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +761 +General Business Information + +![Image 1 from page 761](pdf-image://page_761_img_1) + +## Page 762 + +Address +Address +Data +TSIZ = 00 +AA=1 +AA=0 +AA=1 +AA=0 +Data +Data +Add+1 +Add+2 +Add+3 +Data +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +30.4.12.8 +32-bit-read burst from 8-bit port 3-1-1-1 (address setup and +hold) +If address setup and hold are used, only the first and last beat of the burst cycle are +affected. The following figure shows a read cycle with one clock of address setup and +address hold. +Note +In non-multiplexed address/data mode, the address on FB\_A +increments only during internally-terminated burst cycles +(CSCRn[AA] = 1b). The attached device must be able to +account for this, or a wait state must be added. The first address +is driven throughout the entire burst for externally-terminated +cycles. +In multiplexed address/data mode, the address is driven on +FB_AD only during the first cycle for internally- and +externally-terminated cycles. +Functional description +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +762 +Preliminary +Freescale Semiconductor, Inc. +General Business Information + +![Image 1 from page 762](pdf-image://page_762_img_1) + +## Page 763 + +Address +Address +Data +TSIZ=11 +AA=1 +AA=0 +AA=1 +AA=0 +Data +Data +Data +Add+1 +Add+2 +Add+3 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +30.4.12.9 +32-bit-write burst to 8-bit port 3-1-1-1 (address setup and +hold) +The following figure shows a write cycle with one clock of address setup and address +hold. +Chapter 30 External Bus Interface (FlexBus) +K60 Sub-Family Reference Manual, Rev. 2 Jun 2012 +Freescale Semiconductor, Inc. +Preliminary +763 +General Business Information + +![Image 1 from page 763](pdf-image://page_763_img_1) + +## Page 764 + +Address +Address +Data +TSIZ=11 +AA=1 +AA=0 +AA=1 +AA=0 +Data +Data +Data +Add+1 +Add+2 +Add+3 +FB\_CLK +FB\_A[Y] +FB\_D[X] +FB\_RW +FB\_TS +FB\_ALE +FB\_CSn +FB\_OEn +FB\_BE/BWEn +FB\_TA +FB\_TSIZ[1:0] +30.4.13 +Extended Transfer Start/Address Latch Enable +The FB\_TS/FB\_ALE signal indicates that a bus transaction has begun and the address +and attributes are valid. By default, the FB\_TS/FB\_ALE signal asserts for a single bus +clock cycle. When CSCRn[EXTS] is set, the FB\_TS/FB\_ALE signal asserts and remain +asserted until the first positive clock edge after FB\_CSn asserts. See the following figure. +NOTE +When EXTS is set, CSCRn[WS] must be programmed to have + +## Page 765 + +## Page 766 + +## Page 767 + +## Page 768 + +## Page 769 + +## Page 770 + +## Page 771 + +## Page 772 + +## Page 773 + +## Page 774 + +## Page 775 + +## Page 776 + +## Page 777 + +## Page 778 + +## Page 779 + +## Page 780 + +## Page 781 + +## Page 782 + +## Page 783 + +## Page 784 + +## Page 785 + +## Page 786 + +## Page 787 + +## Page 788 + +## Page 789 + +## Page 790 + +## Page 791 + +## Page 792 + +## Page 793 + +## Page 794 + +## Page 795 + +## Page 796 + +## Page 797 + +## Page 798 + +## Page 799 + +## Page 800 + +## Page 801 + +## Page 802 + +## Page 803 + +## Page 804 + +## Page 805 + +## Page 806 + +## Page 807 + +## Page 808 + +## Page 809 + +## Page 810 + +## Page 811 + +## Page 812 + +## Page 813 + +## Page 814 + +## Page 815 + +## Page 816 + +## Page 817 + +## Page 818 + +## Page 819 + +## Page 820 + +## Page 821 + +## Page 822 + +## Page 823 + +## Page 824 + +## Page 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................................................................................................................................................ 6 +2 +NMEA Protocol ......................................................................................................................................... 7 +2.1. +Structure of NMEA Protocol Messages .............................................................................................. 7 +2.2. +Standard Messages ........................................................................................................................... 9 +2.2.2. +GGA ...................................................................................................................................... 11 +2.2.3. +GSV ....................................................................................................................................... 13 +2.2.4. +GSA ....................................................................................................................................... 14 +2.2.5. +VTG ....................................................................................................................................... 16 +2.2.6. +GLL ........................................................................................................................................ 17 +2.2.7. +ZDA ....................................................................................................................................... 19 +2.2.8. +GNS ...................................................................................................................................... 10 +2.2.9. +GST ....................................................................................................................................... 13 +2.2.10. +GRS ....................................................................................................................................... 14 +2.2.11. +RLM ...................................................................................................................................... 15 +2.3. +PAIR Messages ................................................................................................................................ 17 +2.3.1. +Packet Type: 001 PAIR\_ACK .................................................................................................. 17 +2.3.2. +Packet Type: 002 PAIR\_GNSS\_SUBSYS\_POWER\_ON ............................................................. 17 +2.3.3. +Packet Type: 003 PAIR\_GNSS\_SUBSYS\_POWER\_OFF ............................................................ 18 +2.3.4. +Packet Type: 004 PAIR\_GNSS\_SUBSYS\_HOT\_START ............................................................. 19 +2.3.5. +Packet Type: 005 PAIR\_GNSS\_SUBSYS\_WARM\_START ......................................................... 19 +2.3.6. +Packet Type: 006 PAIR\_GNSS\_SUBSYS\_COLD\_START ........................................................... 20 +2.3.7. +Packet Type: 007 PAIR\_GNSS\_SUBSYS\_FULL\_COLD\_START .................................................. 20 +2.3.8. +Packet Type: 010 PAIR\_REQUEST\_AIDING ............................................................................ 21 +2.3.9. +Packet Type: 050 PAIR\_COMMON\_SET\_FIX\_RATE ................................................................ 21 +2.3.10. +Packet Type: 051 PAIR\_COMMON\_GET\_FIX\_RATE ................................................................ 22 +2.3.11. +Packet Type: 058 PAIR\_COMMON\_SET\_MIN\_SNR................................................................ 23 +2.3.12. +Packet Type: 062 PAIR\_COMMON\_SET\_NMEA\_OUTPUT\_RATE ............................................ 23 +2.3.13. +Packet Type: 059 PAIR\_COMMON\_GET\_MIN\_SNR ............................................................... 24 +2.3.14. +Packet Type: 063 PAIR\_COMMON\_GET\_NMEA\_OUTPUT\_RATE ........................................... 25 +2.3.15. +Packet Type: 066 PAIR\_COMMON\_SET\_GNSS\_SEARCH\_MODE ........................................... 26 +2.3.16. +Packet Type: 067 PAIR\_COMMON\_GET\_GNSS\_SEARCH\_MODE ........................................... 27 +2.3.17. +Packet Type: 070 PAIR\_COMMON\_SET\_STATIC\_THRESHOLD .............................................. 28 +2.3.18. +Packet Type: 071 PAIR\_COMMON\_GET\_STATIC\_THRESHOLD ............................................. 28 +2.3.19. +Packet Type: 072 PAIR\_COMMON\_SET\_ELEV\_MASK ............................................................ 29 +2.3.20. +Packet Type: 073 PAIR\_COMMON\_GET\_ELEV\_MASK ........................................................... 40 +2.3.21. +Packet Type: 074 PAIR\_COMMON\_SET\_AIC\_ENABLE ........................................................... 30 +2.3.22. +Packet Type: 075 PAIR\_COMMON\_GET\_AIC\_STATUS ........................................................... 31 +2.3.23. +Packet Type: 080 PAIR\_COMMON\_SET\_NAVIGATION\_MODE ............................................. 42 + +## Page 3 + +3 +2.3.24. +Packet Type: 081 PAIR\_COMMON\_GET\_NAVIGATION\_MODE ............................................. 34 +2.3.25. +Packet Type: 086 PAIR\_COMMON\_SET\_DEBUGLOG\_OUTPUT ............................................. 34 +2.3.26. +Packet Type: 087 PAIR\_COMMON\_GET\_DEBUGLOG\_OUTPUT ............................................. 34 +2.3.27. +Packet Type: 154 PAIR\_COMMON\_SET\_RLM\_OUTPUT\_ENABLE .......................................... 36 +2.3.28. +Packet Type: 155 PAIR\_COMMON\_GET\_RLM\_OUTPUT\_STATUS .......................................... 36 +2.3.29. +Packet Type: 158 PAIR\_COMMON\_SET\_B1C\_ENABLE .......................................................... 36 +2.3.30. +Packet Type: 382 PAIR\_TEST\_LOCK\_SYSTEM\_SLEEP ............................................................. 38 +2.3.31. +Packet Type: 400 PAIR\_DGPS\_SET\_MODE ............................................................................ 39 +2.3.32. +Packet Type: 401 PAIR\_DGPS\_GET\_MODE ............................................................................ 39 +2.3.33. +Packet Type: 410 PAIR\_SBAS\_ENABLE .................................................................................. 40 +2.3.34. +Packet Type: 411 PAIR\_SBAS\_GET\_STATUS .......................................................................... 41 +2.3.35. +Packet Type: 432 PAIR\_RTCM\_SET\_OUTPUT\_MODE ............................................................. 42 +2.3.36. +Packet Type: 433 PAIR\_RTCM\_GET\_OUTPUT\_MODE ............................................................ 42 +2.3.37. +Packet Type: 434 PAIR\_RTCM\_SET\_OUTPUT\_ANT\_PNT ........................................................ 43 +2.3.38. +Packet Type: 435 PAIR\_RTCM\_GET\_OUTPUT\_ANT\_PNT ....................................................... 43 +2.3.39. +Packet Type: 436 PAIR\_RTCM\_SET\_OUTPUT\_EPHEMERIS ..................................................... 44 +2.3.40. +Packet Type: 437 PAIR\_RTCM\_GET\_OUTPUT\_EPHEMERIS .................................................... 45 +2.3.41. +Packet Type: 490 PAIR\_EASY\_ENABLE .................................................................................. 45 +2.3.42. +Packet Type: 491 PAIR\_EASY\_GET\_STATUS ........................................................................... 46 +2.3.43. +Packet Type: 511 PAIR\_NVRAM\_SAVE\_NAVIGATION\_DATA ................................................ 47 +2.3.44. +Packet Type: 513 PAIR\_NVRAM\_SAVE\_SETTING ................................................................... 48 +2.3.45. +Packet Type: 650 PAIR\_LOW\_POWER\_ENTRY\_RTC\_MODE ................................................... 48 +2.3.46. +Packet Type: 680 PAIR\_GLP\_ENABLE .................................................................................... 49 +2.3.47. +Packet Type: 681 PAIR\_GLP\_GET\_STATUS............................................................................. 50 +2.3.48. +Packet Type: 690 PAIR\_PERIODIC\_SET\_MODE ...................................................................... 50 +2.3.49. +Packet Type: 691 PAIR\_PERIODIC\_GET\_MODE ..................................................................... 51 +2.3.50. +Packet Type: 730 PAIR\_FLP\_ENABLE ..................................................................................... 52 +2.3.51. +Packet Type: 731 PAIR\_FLP\_GET\_STATUS ............................................................................. 53 +2.3.52. +Packet Type: 732 PAIR\_FLP\_ENABLE ..................................................................................... 53 +2.3.53. +Packet Type: 733 PAIR\_ALP\_GET\_STATUS ............................................................................. 54 +2.3.54. +Packet Type: 752 PAIR\_PPS\_SET\_CONFIG\_CMD ................................................................... 55 +2.3.55. +Packet Type: 900 PAIR\_LOCUS\_ENABLE ............................................................................... 55 +2.3.56. +Packet Type: 901 PAIR\_LOCUS\_GET\_STATUS ........................................................................ 57 +2.3.57. +Packet Type: 902 PAIR\_LOCUS\_SET\_MODE .......................................................................... 57 +2.3.58. +Packet Type: 903 PAIR\_LOCUS\_GET\_MODE .......................................................................... 58 +2.3.59. +Packet Type: 904 PAIR\_LOCUS\_SET\_THRESHOLD ................................................................. 59 +2.3.60. +Packet Type: 905 PAIR\_LOCUS\_GET\_THRESHOLD ................................................................ 69 +2.3.61. +Packet Type: 906 PAIR\_LOCUS\_CLEAR .................................................................................. 69 +2.3.62. +Packet Type: 907 PAIR\_LOCUS\_LOG\_NOW ........................................................................... 70 +2.3.63. +Packet Type: 908 PAIR\_LOCUS\_GET\_DATA ........................................................................... 70 + +## Page 4 + +4 +2.3.64. +Packet Type: 909 PAIR\_LOCUS\_GET\_RECORD\_NUM ............................................................ 73 +3 +RTCM Protocol .......................................................................................................................................... 74 +4 +Appendix A – References ......................................................................................................................... 77 +5 +Appendix B - GNSS Satellites (NEMA) Numbering ............................................................................... 78 +6 +Appendix C – Special characters ............................................................................................................. 79 + +## Page 5 + +5 +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Table Index +Table 1: Applicable Modules and Variants .................................................................................................................... 6 +Table 2: Supported Protocols ................................................................................................................................. …...6 +Table 3: Structure of NMEA Protocol Messages ......................................................................................................... ..7 +Table 4: NMEA Talker ID ..................................................................................................................................................... ..8 +Table 5: Supported RTCM3 Messages ...................................................................................................................... …74 +Table 6: Terms and Abbreviations .................................................................................................................................. …75 +Table 7: GNSS Satellites (NEMA) Numbering ........................................................................................................... …78 +Table 8: Special Characters ...................................................................................................................................... …79 + +## Page 6 + +RYS352x +PAIR Command Guide +1 Introduction +RYS3520 GNSS modules support GPS, GLONASS, Galileo, BDS and QZSS constellations. Concurrent +tracking of multi-frequency bands provides fast and accurate acquisition and makes these modules +ideal solutions for positioning and navigation in various vertical markets. +This document describes the software commands that are used to control and modify the module +configuration. The software commands are NMEA proprietary commands defined by REYAX. To report +GNSS information, the modules support outputting messages in NMEA 0183 protocol format and RTCM +protocol format. +Table 1: Applicable Variants and Supported Frequency Bands +Module +Variant +Frequency Band +RYS352x +RYS3520 +GPS L1 C/A + GLONASS L1 + Galileo E1 + BDS B1I + QZSS L1 C/A +,,, +Table 2: Supported Protocols +Protocol +Type +RYS352x +Output, ASCII, standard +Input/output, ASCII, proprietary +RTCM 10403.3 +Output, binary, proprietary +6 + +![Image 1 from page 6](pdf-image://page_6_img_1) + +![Image 2 from page 6](pdf-image://page_6_img_2) + +## Page 7 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +2 NMEA Protocol +2.1. Structure of NMEA Protocol Messages +Start of sentence +character. Always ‘$’ +Start with a ‘\*’, 8-bit +checksum value converted to +two ASCII characters +Address field - contains talker identifier +and sentence formatter +Data field(s), +delimited by ‘,’ +End of sentence. Always + +$ +
+() +[,] +\* + +Range for checksum calculation +Field +Description +$ +Start of the sentence (Hex 0x24). +
+In Standard Messages: +In NMEA standard messages, this field consists of a two-character talker identifier (TalkerID) +and a three-character sentence formatter (SentenceFormatter). +The talker identifier identifies the data type of talker. For more information on the TalkerID, see +Table 4: NMEA Talker ID. +The sentence formatter identifies the data type and the string format of the successive fields. +In Proprietary Messages: +In NMEA proprietary messages, this field consists of the proprietary character P followed by a +three-character Manufacturer's Mnemonic Code, used to identify the TALKER issuing a +proprietary sentence, and any additional characters as required + +Data fields, delimited by data field delimiter ‘,’. +Variable length (depends on the NMEA message type). + +Checksum field follows the checksum delimiter character \*. +Checksum is the 8-bit exclusive OR of all characters in the sentence, including the ‘,’ +field delimiter, between but not including the ‘$’ and the ‘\*’ delimiters. + +End of the sentence (Hex 0x0D 0x0A). +Figure 1: Structure of NMEA Protocol Messages +Table 3: Structure of NMEA Protocol Messages +7 + +![Image 1 from page 7](pdf-image://page_7_img_1) + +![Image 2 from page 7](pdf-image://page_7_img_2) + +![Image 3 from page 7](pdf-image://page_7_img_3) + +![Image 4 from page 7](pdf-image://page_7_img_4) + +## Page 8 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Table 4: NMEA Talker ID +GNSS Constellation Configuration +TalkerID (NMEA V4.10) +GPS +GP +GLONASS +GL +Galileo +GA +BDS +GB +QZSS +GP +Combination of Multiple Satellite Systems +GN +Sample Code for NMEA Checksum: +// pData is the data array whose checksum needs to be calculated: +unsigned char Ql\_Check\_XOR(const unsigned char \*pData, unsigned int Length) +{ +unsigned char result = 0; +unsigned int i = 0; +if((NULL == pData) || (Length < 1)) +{ +return 0; +} +for(i = 0; i < Length; i++) +{ +result ^= \*(pData + i); +} +return result; +} +8 + +![Image 1 from page 8](pdf-image://page_8_img_1) + +![Image 2 from page 8](pdf-image://page_8_img_2) + +## Page 9 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +2.2. Standard Messages +This chapter explains the NMEA 0183 V4.10 standard messages supported by the modules. +2.2.1. RMC +Message +RMC +Description +Recommended Minimum Specific GNSS Data. Time, date, position, course, and +speed data provided by a GNSS receiver +Type +Output +Message Structure: +Example: +$GNRMC,040143.000,A,3149.334166,N,11706.941670,E,0.01,0.00,010522,,,D,V\*0E +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GN +Talker identifier. +See Table 4: NMEA Talker ID +RMC +String, 3 characters +RMC +Recommended +Minimum Specific +GNSS Data. + +hhmmss.sss +040143.000 +GNSS Data. +Position fix UTC. +hh: Hours (00–23) +mm: Minutes (00–59) +ss: Seconds (00–59) +sss: Decimal fraction of seconds + +Character +A +Positioning system status. +A = Data valid +V = Navigation receiver warning + +ddmm.mmmmmm +3149.334166 +Latitude. +dd. Degrees (00–90) +mm. Minutes (00–59) +mmmmmm: +Decimal +fraction +of +minutes +Note that this field is empty in case of an +invalid value. +$RMC,,,,,,,,,,, +,,\* +9 + +![Image 1 from page 9](pdf-image://page_9_img_1) + +![Image 2 from page 9](pdf-image://page_9_img_2) + +## Page 10 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description + +Character +N +North-south direction. +N = North +S = South +Note that this field is empty in case of +an invalid value. + +dddmm.mmmmmm +11706.941670 +Longitude. +ddd: Degrees (000–180) +mm: Minutes (00–59) +mmmmmm: +Decimal +fraction +of +minutes. +Note that this field is empty in case of +an invalid value. + +Character +E +East-west direction. +E = East +W = West +Note that this field is empty in case of +an invalid value. + +Numeric +Knot +0.01 +Speed over ground. Variable length. +Note that this field is empty in case of +an invalid value. + +Numeric +Degree +0.00 +Course over ground. Variable length. +Maximum value: 359.99. +Note that this field is empty in case of +an invalid value. + +ddmmyy +010522 +Date. +dd: Day of month +mm: Month +yy: Year + +Magnetic variation. Not supported. + +Direction of magnetic variation. +Not supported. +10 + +![Image 1 from page 10](pdf-image://page_10_img_1) + +![Image 2 from page 10](pdf-image://page_10_img_2) + +## Page 11 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description + +Character +D +Mode indicator. +A = Autonomous mode. Satellite +system used in non-differential mode +for position fixing. +D = Differential mode. Satellite system +used in differential mode for position +fixing. Corrections from ground stations +or +Satellite +Based +Augmentation +System (SBAS). +E = Estimated (dead reckoning) mode +F = Float RTK. Satellite system used in +RTK mode with floating integers. +M = Manual input mode +N = No fix. Satellite system not used for +position fixing, or fix not valid. +R = Real Time Kinematic (RTK). +Satellite system used in RTK mode with +fixed integers + +Character +V +Navigational status indication. +Note that this parameter is only +available in messages in line with +NMEA0183 V4.10 and later versions. + +Hexadecimal +\*0E +Checksum. + +Character +Carriage return and line feed. +2.2.2. GGA +Message +GGA +Description +Global Positioning System Fix Data. Time, position, and fix-related data +for a GNSS receiver +Type +Output +Message Structure: +Example: +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GN +Talker identifier. +See Table 4: NMEA Talker ID +$GGA,,,,,,,,,,M, +,M,,\* +$GNRMC,040143.000,A,3149.334166,N,11706.941670,E,0.01,0.00,010522,,,D,V\*0E +11 + +![Image 1 from page 11](pdf-image://page_11_img_1) + +![Image 2 from page 11](pdf-image://page_11_img_2) + +## Page 12 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description +GGA +String, 3 characters +GGA +Global Positioning System Fix Data. + +hhmmss.sss +040143.000 +GNSS Data. +Position fix UTC. +hh: Hours (00–23) +mm: Minutes (00–59) +ss: Seconds (00–59) +sss: Decimal fraction of seconds + +ddmm.mmmmmm +3149.334166 +Latitude. +dd. Degrees (00–90) +mm. Minutes (00–59) +mmmmmm: Decimal +fraction +of +minutes +Note that this field is empty in case of an +invalid value. + +Character +N +North-south direction. +N = North +S = South +Note that this field is empty in case of +an invalid value. + +dddmm.mmmmmm +11706.941670 +Longitude. +ddd: Degrees (000–180) +mm: Minutes (00–59) +mmmmmm: +Decimal +fraction +of +minutes. +Note that this field is empty in case of +an invalid value. + +Character +E +East-west direction. +E = East +W = West +Note that this field is empty in case of +an invalid value. + +Numeric, 1 digit +2 +GPS quality indicator. +0 = Fix not available or invalid +1 = GPS SPS Mode, fix valid +2 = Differential GPS, SPS Mode, or +Satellite Based Augmentation. System +(SBAS), fix valid +3 = GPS PPS Mode, fix valid +4 = Real Time Kinematic (RTK) System +used in RTK mode with fixed integers +5 = Float RTK. Satellite system used in +RTK mode, floating integers +6 = Estimated (dead reckoning) mode + 1) +Numeric, 2 digits +36 +Number of satellites in use. + +Numeric +0.48 +Horizontal dilution of precision. +Note that this field is empty in case of +an invalid value. +12 + +![Image 1 from page 12](pdf-image://page_12_img_1) + +![Image 2 from page 12](pdf-image://page_12_img_2) + +## Page 13 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description + +Numeric +Meter +61.496 +Altitude above mean-sea-level (geoid). +Note that this field is empty in case of +an invalid value. +M +Character +M +Unit of . +“M” = Meter. + +Differential GPS data age. +Not supported. + +Differential reference station ID. +Not supported. + +Hexadecimal +\*58 +Checksum. + +Character +Carriage return and line feed. +Note: +1. The NMEA 0183 specification indicates that GGA messages are GPS specific. However, when the +receiver is configured for multi-constellations, the content of GGA messages will be generated +from the multi-constellation solution. +2.2.3. GSV +Message +GSV +Description +GNSS Satellites in View. The GSV sentence provides the number of +satellites in view (SV), satellite ID numbers, elevation, azimuth, and SNR +value, and it contains maximum four satellites per transmission. +Therefore, it may take several sentences to get complete information. The +total number of sentences being transmitted and the sentence number are +indicated in the first two data fields. +Type +Output +Message Structure: +Example: +$GSV,,,{,,,,},\* +$GPGSV,3,1,12,195,72,076,42,01,69,158,45,194,66,111,29,21,61,060,44,1\*6D +$GPGSV,3,2,12,07,61,233,42,30,52,284,44,199,51,162,37,08,39,045,42,1\*59 +$GPGSV,3,3,12,14,29,312,29,196,20,148,36,17,18,258,36,27,07,061,36,1\*53 +$GLGSV,2,1,05,79,80,068,47,82,62,248,44,81,56,014,38,78,31,137,24,1\*7F +$GLGSV,2,2,05,88,07,034,29,1\*46 +$GAGSV,2,1,06,26,80,095,42,01,69,353,13,21,49,106,26,33,42,207,41,7\*72 +$GAGSV,2,2,06,13,28,040,34,31,19,313,34,7\*72 +$GBGSV,4,1,16,46,81,194,38,07,68,349,31,40,61,016,40,30,60,259,43,1\*71 +$GBGSV,4,2,16,10,59,321,,03,51,192,36,36,41,314,38,02,37,229,32,1\*71 +$GBGSV,4,3,16,09,31,219,26,08,27,175,31,37,25,146,29,06,23,202,29,1\*78 +$GBGSV,4,4,16,16,20,199,31,13,17,186,26,39,12,192,29,28,09,048,30,1\*7C +13 + +![Image 1 from page 13](pdf-image://page_13_img_1) + +![Image 2 from page 13](pdf-image://page_13_img_2) + +## Page 14 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GP +Talker identifier. +See Table 4: NMEA Talker ID +GSV +String, 3 characters +GSV +GNSS Satellites in view + +Numeric +3 +Total number of sentences. +Range: 1–9. + +Numeric +1 +Sentence number. +Range: 1–. + +Numeric +12 +Total number of satellites in view. +Start of repeat block. Repeat times: 1–4. + +Numeric +195 +Satellite ID. +See Table 8: GNSS Satellites (NEMA) +Numbering. + +Numeric +Degree +72 +Satellite elevation. Range: 00–90. + +Numeric +Degree +076 +Satellite azimuth, with true north as the +reference plane. Range: 000–359. + +Numeric +dB-Hz +42 +Satellite C/N0. Range 00–99. +Null when not tracking. + +Numeric +1 +GNSS signal ID. +See Table 8: GNSS Satellites (NEMA) +Numbering. +Note that this parameter is only +available in messages in line with +NMEA 0183 V4.10 and later versions. + +Hexadecimal +\*58 +Checksum. + +Character +Carriage return and line feed. +Note: +1. GN cannot be used for GSV sentences. If satellites of multiple constellations are in view, use separate +GSV sentences with the corresponding talker ID for each constellation. +2.2.4. GSA +Message +GSA +Description +GNSS DOP and Active Satellites. GNSS receiver operating mode, satellites +used in the navigation solution reported by the GGA sentence, and DOP +values. +Type +Output +14 + +![Image 1 from page 14](pdf-image://page_14_img_1) + +![Image 2 from page 14](pdf-image://page_14_img_2) + +## Page 15 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Message Structure: +Example: +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GN +Talker identifier. +See Table 4: NMEA Talker ID +GSA +String, 3 characters +GSA +GNSS DOP and Active Satellites. + +Character +A +Selection of 2D or 3D fix. +M = Manual, forced to operate in 2D or +3D Mode +A= Automatic, allowed to automatically +switch to 2D/3D + +Numeric +- +3 +Fix mode. +1 = Fix not available +2 = 2D +3 = 3D +Start of repeat block. Repeat times: 12. + +Numeric +195 +ID numbers of satellites used in +solution. +See Table 8: GNSS Satellites (NEMA) +Numbering. +Note that this field is empty in case of +an invalid value. +End of repeat block. + +Numeric +0.71 +Position dilution of precision. +Maximum value: 99.00. +Note that this field is empty in case of +an invalid value. + +Numeric +0.48 +Horizontal dilution of precision. +Maximum value: 99.00. +Note that this field is empty in case of +an invalid value. + +Numeric +0.52 +Vertical dilution of precision. +Maximum value: 99.00. +Note that this field is empty in case of +an invalid value +$GSA,,{,},,,\* +$GNGSA,A,3,195,01,194,21,07,30,199,08,14,17,27,,0.71,0.48,0.52,1\*34 +$GNGSA,A,3,79,82,81,78,88,,,,,,,,0.71,0.48,0.52,2\*0D +$GNGSA,A,3,26,21,33,13,31,,,,,,,,0.71,0.48,0.52,3\*09 +$GNGSA,A,3,46,07,40,30,03,36,02,09,08,37,06,16,0.71,0.48,0.52,4\*0B +$GNGSA,A,3,13,39,28,,,,,,,,,,0.71,0.48,0.52,4\*0B +15 + +![Image 1 from page 15](pdf-image://page_15_img_1) + +![Image 2 from page 15](pdf-image://page_15_img_2) + +## Page 16 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description + +Numeric +0.48 +Horizontal dilution of precision. +Maximum value: 99.00. +Note that this field is empty in case of +an invalid value. + +Numeric +0.52 +Vertical dilution of precision. +Maximum value: 99.00. +Note that this field is empty in case of +an invalid value + +Numeric +1 +GNSS system ID. +See Table 8: GNSS Satellites (NEMA) +Numbering + +Hexadecimal +\*34 +Checksum + +Character +Carriage return and line feed. +Note: +1. If less than 12 satellites are used for navigation, the remaining fields are left empty. If more +than 12 satellites are used for navigation, only the IDs of the first 12 are output +2.2.5. VTG +Message +VTG +Description +Course Over Ground & Ground Speed. The actual course and speed relative +to the ground. +Type +Output +Message Structure: +Example: +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GN +Talker identifier. +See Table 4: NMEA Talker ID +VTG +String, 3 characters +GSA +Course Over Ground & Ground Speed. + +Numeric +Degrees +0.00 +Course over ground, in true north +course direction. +Note that this field is empty in case of +an invalid value. +$VTG,,T,,M,,N,,K,\* +$GNVTG,0.00,T,,M,0.01,N,0.02,K,D\*25 +16 + +![Image 1 from page 16](pdf-image://page_16_img_1) + +![Image 2 from page 16](pdf-image://page_16_img_2) + +## Page 17 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description +T +Character +T +Fixed field: true. + +Numeric +Degrees +M +Course over ground (magnetic). +Not supported. +M +Character +Fixed field: magnetic. + +Numeric +Knots +0.01 +Speed over ground in knots. +Note that this field is empty in case of +an invalid value. +N +Character +N +Fixed field: knot. + +Numeric +km/h +0.02 +Speed over ground in kilometers per +hour. +Note that this field is empty in case of +an invalid value0 +K +Character +K +Fixed field: kilometers per hour. + +Character +D +Mode indicator. +A = Autonomous mode +D = Differential mode +E = Estimated (dead reckoning) mode +F = Float RTK. Satellite system used in +real time kinematic mode with floating +integers +M = Manual input mode +N = No fix. Satellite system not used for +position fixing, or fix not valid +R = Real Time Kinematic. Satellite +system used in RTK mode with fixed +integers + +Hexadecimal +\*25 +Checksum + +Character +Carriage return and line feed. +2.2.6. GLL +Message +GLL +Description +Geographic Position – Latitude/Longitude. Latitude and longitude of the +GNSS receiver position, the time of position fix and status +Type +Output +Message Structure: +Example: +$GLL,,,,,,,\* +$GNGLL,3149.334166,N,11706.941670,E,040143.000,A,D\*46 +17 + +![Image 1 from page 17](pdf-image://page_17_img_1) + +![Image 2 from page 17](pdf-image://page_17_img_2) + +## Page 18 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GN +Talker identifier. +See Table 4: NMEA Talker ID +GLL +String, 3 characters +GLL +Geographic Position – +Latitude/Longitude. + +ddmm.mmmmmm +- +3149.334166 +Latitude. +dd: Degrees (00–90) +mm: Minutes (00–59) +mmmmmm: +Decimal +fraction +of +minutes +Note that this field is empty in case of +an invalid value. + +Character +N +North-south direction. +N = North +S = South +Note that this field is empty in case of +an invalid value. + +dddmm.mmmmmm +11706.941670 +Latitude. +dd: Degrees (000–180) +mm: Minutes (00–59) +mmmmmm: +Decimal +fraction +of +minutes +Note that this field is empty in case of +an invalid value. + +Character +E +East-west direction. +E = East +W = West +Note that this field is empty in case of +an invalid value + +hhmmss.sss +040143.000 +Position UTC. +hh: Hours (00–23) +mm: Minutes (00–59) +ss: Seconds (00–59) +sss: Decimal fraction of seconds + +Character +A +Positioning system status. +A = Data valid +V = Invalid data +18 + +![Image 1 from page 18](pdf-image://page_18_img_1) + +![Image 2 from page 18](pdf-image://page_18_img_2) + +## Page 19 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description + +Character +GN +Mode indicator. +A = Autonomous mode +D = Differential mode +E = Estimated (dead reckoning) mode +F = Float RTK. Satellite system used in +real time kinematic mode with floating +integers +M = Manual input mode +N = No fix. Satellite system not used for +position fixing, or fix not valid +R = Real Time Kinematic. Satellite +system used in RTK mode with fixed +integers. + +Hexadecimal +\*46 +Checksum + +Character +Carriage return and line feed. +2.2.7. ZDA +Message +ZDA +Description +Time and date. UTC, day, month, year and local time zone. +Type +Output +Message Structure: +Example: +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GN +Talker identifier. +See Table 4: NMEA Talker ID +ZDA +String, 3 characters +ZDA +Time&Date. UTC, day, month, year and +local time zone. +$ZDA,,,,,,\* +$GNZDA,055054.000,19,09,2022,,\*4A +19 + +![Image 1 from page 19](pdf-image://page_19_img_1) + +![Image 2 from page 19](pdf-image://page_19_img_2) + +## Page 20 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description + +hhmmss.sss +055054.000 +Position fix UTC. +hh: Hours (00–23) +mm: Minutes (00–59) +ss: Seconds (00–59) +sss: Decimal fraction of seconds + +Numeric +19 +Day of month. Range: 01–31. + +Numeric +09 +Month. Range: 01–12. + +Numeric +2022 +Year. + +Numeric +Local zone hours, 00 to ±13 hours. +Not supported. + +Numeric +Local zone minutes, 00 to +59 minutes. +Not supported. + +Hexadecimal +\*4A +Checksum + +Character +Carriage return and line feed. +2.2.8. GNS +Message +GNS +Description +GNSS fix data. Fix data for single or combined satellite navigation systems +(GNSS). +Type +Output +Message Structure: +Example: +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +Talker identifier. +See Table 4: NMEA Talker ID +GNS +String, 3 characters +GNS +GNSS Fix Data. +$GNS,,,,,,,,,, +M,,M,,,\* +$GNGNS,053106.000,3149.334190,N,11706.948654,E,DANN,16,0.63,51.287,M,-0.335,M,,,V\*05 +20 + +![Image 1 from page 20](pdf-image://page_20_img_1) + +![Image 2 from page 20](pdf-image://page_20_img_2) + +## Page 21 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description + +hhmmss.sss +053106.000 +North-south direction. +N = North +S = South +Note that this field is empty in case of +an invalid value. + +ddmm.mmmmmm +3149.334190 +Longitude. +ddd: Degrees (00–90) +mm: Minutes (00–59) +mmmmmm: +Decimal +fraction +of +minutes +Note that this field is empty in case of +an invalid value. + +Character +N +East-west direction. +E = East +W = West +Note that this field is empty in case of +an invalid value. + +dddmm.mmmmmm +11706.948654 +Longitude. +ddd: Degrees (000–180) +mm: Minutes (00–59) +mmmmmm: +Decimal +fraction +of +minutes +Note that this field is empty in case of +an invalid value. + +Character +E +East-west direction. +E = East +W = West +Note that this field is empty in case of +an invalid value. +< ModeInd>1) +Character +DANN +Mode indicator. +A = Autonomous mode. Satellite system +used +in +non-differential +mode +for +position fixing +D = Differential mode. Satellite system +used in differential mode for position +fixing. Corrections from ground stations +or Satellite Based Augmentation System +(SBAS) +E = Estimated (dead reckoning) mode +F = Float RTK. Satellite system used in +RTK mode with floating integers +M = Manual input mode +N = No fix. Satellite system not used for +position fixing, or fix not valid +R = Real Time Kinematic (RTK). +Satellite system used in RTK mode with +fixed integers. +21 + +![Image 1 from page 21](pdf-image://page_21_img_1) + +![Image 2 from page 21](pdf-image://page_21_img_2) + +## Page 22 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description + +Numeric +16 +Total number of satellites in use. +Range: 0–99. + +Numeric +0.63 +Horizontal dilution of precision. +Maximum value: 99.00. +Note that this field is empty in case of +an invalid value. + +Numeric +Meter +51.287 +Antenna altitude above the meansea- +level (geoid). +Note that this field is empty in case of +an invalid value. +M +Character +M +Unit of . +“M” = Meter. + +Numeric +Meter +-0.335 +Geoid +separation +(the +difference +between the earth ellipsoid surface and +the mean-sea-level (geoid) surface +defined by the reference datum used in +the position solution). +Note that this field is empty in case of +an invalid value. +M +Character +M +Unit of . +“M” = Meter. + +Differential GPS data age. +Not supported. + +Differential reference station ID. +Not supported. + +Character +V +Navigational status indicator. +Always “V” (Navigational status not +valid). + +Hexadecimal +\*05 +Checksum + +Character +Carriage return and line feed. +Note: +1. 1) is a variable length field. The first character indicates the use of GPS satellites, the +second character indicates the use of GLONASS satellites, and the third character indicates the +use of Galileo satellites. The fourth character indicates the use of BDS satellites, the fifth character +indicates the use of QZSS satellites, and the sixth character indicates the use of NavIC (IRNSS) +satellites. +. +22 + +![Image 1 from page 22](pdf-image://page_22_img_1) + +![Image 2 from page 22](pdf-image://page_22_img_2) + +## Page 23 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +2.2.9. GST +Message +GST +Description +GNSS Psuedorange Error Statistics. This sentence supports Receiver +Autonomous Integrity Monitoring (RAIM). Pseudorange measurement +error statistics can be translated in the position domain in order to give +statistical measures of the quality of the position solution +Type +Output +Message Structure: +Example: +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GN +Talker identifier. +See Table 4: NMEA Talker ID +GST +String, 3 characters +GST +GNSS Psuedorange Error Statistics + +hhmmss.sss +123624.000 +UTC time of the GGA or GNS fix +associated with this sentence. +< RMS\_D> +Numeric +Meter +6.3 +RMS value of the standard deviation of +the range inputs to the navigation +process. + +Numeric +Meter +2.5 +Standard deviation of semi-major axis +of error ellipse. + +Numeric +Meter +2.4 +Standard deviation of semi-minor axis +of error ellipse. + +Numeric +Degree +s +88.4 +Orientation of semi-major axis of error +ellipse. +< LatD> +Numeric +Meter +2.4 +Standard deviation of latitude error. + +Numeric +Meter +2.5 +Standard deviation of longitude error. + +Numeric +Meter +5.9 +Standard deviation of altitude error. + +Hexadecimal +\*43 +Checksum. + +Character +Carriage return and line feed. +$GST,,,,,,,,\* + +$GNGST,123624.000,6.3,2.5,2.4,88.4,2.4,2.5,9.2\*43 +23 + +![Image 1 from page 23](pdf-image://page_23_img_1) + +![Image 2 from page 23](pdf-image://page_23_img_2) + +## Page 24 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +2.2.10. GRS +Message +GRS +Description +GNSS range residuals. This sentence supports Receiver Autonomous +Integrity Monitoring (RAIM). Range residuals can be computed in two +ways for this process. The basic measurement integration cycle of most +navigation filters generates a set of residuals and uses these to update +the position state of the receiver. +Type +Output +Message Structure: +Example: +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GN +Talker identifier. +See Table 4: NMEA Talker ID +GRS +String, 3 characters +GRS +GNSS Range Residuals + +hhmmss.sss +125524.000 +Position fix UTC. +hh: Hours (00–23) +mm: Minutes (00–59) +ss: Seconds (00–59) +sss: Decimal fraction of seconds + +Numeric +1 +Residual calculation mode. +0 = Residuals were used to calculate +the position given in the matching GGA +or GNS sentence +1 = Residuals were recomputed after +the +GGA +or +GNS +position +was +computed +Start of repeat block. Repeat times: 12. +< Resi> +Numeric +Meter +-0.4 +Range residuals for SVs used in +navigation. +Range: -999 to 999. +Note that this field is empty in case of +an invalid value. +End of repeat block. +$GRS,,{,},,\* +$GNGRS,125524.000,1,-0.4,-0.7,0.5,-4.6,0.2,1.1,-2.2,-0.6,-1.1,9.2,-2.1,3.1,1,1\*42 +$GNGRS,125524.000,1,-11.4,,,,,,,,,,,,1,1\*52 +$GNGRS,125524.000,1,19.4,-5.0,11.4,6.3,-118,3.3,-7.5,,,,,,2,1\*79 +$GNGRS,125524.000,1,-5.6,4.6,21.1,,,,,,,,,,3,7\*51 +24 + +![Image 1 from page 24](pdf-image://page_24_img_1) + +![Image 2 from page 24](pdf-image://page_24_img_2) + +## Page 25 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description + +Numeric +1 +GNSS system ID. +See Table 8: GNSS Satellites (NEMA) +Numbering. +Note that this parameter is only +available in messages in line with +NMEA 0183 V4.10 or later versions. + +Numeric +1 +GNSS system ID. +See Table 8: GNSS Satellites (NEMA) +Numbering. +Note that this parameter is only +available in messages in line with +NMEA 0183 V4.10 or later versions. + +Hexadecimal +\*42 +Checksum. + +Character +Carriage return and line feed. +2.2.11. RLM +Message +RLM +Description +Return Link Message. The receiver will detect the Galileo Search and +Rescue (SAR) Return Link Message when the RLM function is enabled +Type +Output +Message Structure: +Example: +Parameter: +Field +Format +Unit +Example +Description +$ +Character +- +$ +Each NMEA message starts with $. + +String, 2 characters +GN +Talker identifier. +See Table 4: NMEA Talker ID +RLM +String, 3 characters +RLM +Return Link Message + +Hexadecimal +9A22BE296 +30F010 +Beacon of RLM. Beacon ID 15 hex +characters (60 bits). + +hhmmss.sss +055054.000 +Position fix UTC. +hh: Hours (00–23) +mm: Minutes (00–59) +ss: Seconds (00–59) +sss: Decimal fraction of seconds +$RLM,,,,\* +$GARLM,9A22BE29630F010,125713.000,F,5402\*3B +25 + +![Image 1 from page 25](pdf-image://page_25_img_1) + +![Image 2 from page 25](pdf-image://page_25_img_2) + +## Page 26 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Field +Format +Unit +Example +Description +< +Meg\_Code> +Hexadecimal +F +Message code, a hex character (4 bits). +Identifies the Type of RLM Message +Service. +0 = Reserved for future RLM services. +1 = Acknowledgement Service RLM +2 = Command Service RLM +3 = Message Service RLM +4 – E = Reserved for future RLM +services +F = Test Service RLM (currently used +only by the Galieo Program) + +Numeric +5402 +The data parameters provided by RLS. +Short +message +contains +4 +hex +characters (16 bits) and long message +contains 24 hex characters (96 bits). + +Hexadecimal +\*3B +Checksum. + +Character +Carriage return and line feed. +26 + +![Image 1 from page 26](pdf-image://page_26_img_1) + +![Image 2 from page 26](pdf-image://page_26_img_2) + +## Page 27 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +2.3. PAIR Messages +This chapter explains PAIR messages (proprietary NMEA messages defined by the chipset supplier) +supported by the modules. +2.3.1. Packet Type: 001 PAIR_ACK +Message +$PAIR001 +Description +Acknowledges a PAIR command. An acknowledgement packet $PAIR001 is +returned to inform the sender that the receiver has received the packet. +Type +Output +Message Structure: +Example: +$PAIR001,004,0\*3F +Parameter: +Field +Format +Unit +Description + +Numeric +- +Type of command/packet to be acknowledged. + +Numeric +0 = Command has been successfully sent +1 = Command is being processed. Please wait for the +result. +2 = Command sending failed. +3 = is not supported. +4 = Command parameter error. Out of range/Some +parameters were lost/Checksum error. +5 = MNL service is busy. You can try again soon. +2.3.2. Packet Type: 002 PAIR\_GNSS\_SUBSYS\_POWER\_ON +Message +$PAIR002 +Description +Acknowledges a PAIR command. An acknowledgement packet $PAIR001 is +returned to inform the sender that the receiver has received the packet. +Type +Command +Message Structure: +Example: +$PAIR001,,\* +$PAIR002\* +$PAIR002\*38 +$PAIR001,002,1\*38 +$PAIR001,002,0\*39 +27 + +![Image 1 from page 27](pdf-image://page_27_img_1) + +![Image 2 from page 27](pdf-image://page_27_img_2) + +## Page 28 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +Parameter: +None +Result: +Returns $PAIR001 message. +2.3.3. Packet Type: 003 PAIR\_GNSS\_SUBSYS\_POWER\_OFF +Message +$PAIR003 +Description +Power off GNSS system. Include DSP/RF/Clock and other GNSS modules. +CM4 also can receive commands (Include the AT command / the race Command / +the part of PAIR command which is not dependent on DSP.) after sending this +command. +Type +Command +Message Structure: +Example: +Parameter: +None +Result: +Returns $PAIR001 message. +Note: +1. +The location service is not available after this command is executed. +2. +The system can still receive configuration PAIR commands. The application is running if necessary. +3. +CM4 will go to sleep if the application is not working at this time. The system can be awoken by the +GNSS\_DATA\_IN\_EINT pin after going to sleep. +$PAIR003\* +$PAIR003\*39 +$PAIR001,003,1\*39 +$PAIR001,003,0\*38 +28 + +![Image 1 from page 28](pdf-image://page_28_img_1) + +![Image 2 from page 28](pdf-image://page_28_img_2) + +## Page 29 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +2.3.4. Packet Type: 004 PAIR\_GNSS\_SUBSYS\_HOT\_START +Message +$PAIR004 +Description +Performs a hot start (uses all available data in the NVRAM). Normally a hot start +means that the GNSS module has been powered down for less than 2 hours (RTC +must be alive) with its ephemeris still valid. Therefore, there is no need to download +an ephemeris again upon a hot start, thus making this startup method the fastest +Type +Command +Message Structure: +Example: +Parameter: +None +Result: +Returns $PAIR001 message. +2.3.5. Packet Type: 005 PAIR\_GNSS\_SUBSYS\_WARM\_START +Message +$PAIR005 +Description +Performs a warm start. A warm start means that the GNSS module remembers only +rough time, position,and almanacs data, and thus needs to download an ephemeris +before it can fix a position. +Type +Command +Message Structure: +Example: +Parameter: +None +Result: +Returns $PAIR001 message. +$PAIR004\* +$PAIR004\*3E +$PAIR001,004,1\*3E +$PAIR001,004,0\*3F +$PAIR005\* +$PAIR005\*3F +$PAIR001,005,1\*3F +$PAIR001,005,0\*3E +29 + +![Image 1 from page 29](pdf-image://page_29_img_1) + +![Image 2 from page 29](pdf-image://page_29_img_2) + +## Page 30 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +2.3.6. Packet Type: 006 PAIR\_GNSS\_SUBSYS\_COLD\_START +Message +$PAIR006 +Description +Performs a cold start, which means that there is no location information stored in +the receiver, including time, position, and almanacs and ephemeris data. +Type +Command +Message Structure: +Example: +Parameter: +None +Result: +Returns $PAIR001 message. +2.3.7. Packet Type: 007 +PAIR\_GNSS\_SUBSYS\_FULL\_COLD\_START +Message +$PAIR007 +Description +Performs a cold start and clears system and user configurations at the start, i.e., +resets the module to its factory settings. Upon a full cold start, the module loses all +data on the previous position. Therefore, it needs to search over the full frequency +spectrum for all visible satellites before fixing a position. +Type +Command +Message Structure: +Example: +Parameter: +None +Result: +Returns $PAIR001 message. +$PAIR006\* +$PAIR006\*3C +$PAIR001,006,1\*3C +$PAIR001,006,0\*3D +$PAIR007\* +$PAIR007\*3D +$PAIR001,007,1\*3D +$PAIR001,007,0\*3C +30 + +![Image 1 from page 30](pdf-image://page_30_img_1) + +![Image 2 from page 30](pdf-image://page_30_img_2) + +## Page 31 + +RYS352x +PAIR Command Guide +Copyright © 2023, REYAX TECHNOLOGY CO., LTD. +2.3.8. Packet Type: 010 PAIR\_REQUEST\_AIDING +Message +$PAIR010 +Description +Notifies the expiration of GNSS aiding data stored in the module. This message is +automatically output when the module powers on +Type +Output +Message Structure: +Example: +Parameter: +Field +Format +Unit +Description + +Numeric +Type of data to be updated. +0 = EPO data +1 = Time +2 = Location + +Numeric +Type of required GNSS data. +0 = GPS data +1 = GLONASS data +2 = Galileo data +3 = BDS data +4 = QZSS data + +Numeric +Week +Week number (including roll-over) + +Numeric +Second +Time of week +Note: +1. +The GNSS system outputs this message automatically. Do not send $PAIR010 manually. +2.3.9. Packet Type: 050 PAIR\_COMMON\_SET\_FIX\_RATE +Message +$PAIR050 +Description +Set Position Fix Interval. +If set less than 1000 ms, ASCII NMEA will automatically increase the update +interval in order to decrease IO throughput. +It will return false if the operating voltage setting is not correct. +(Any fix interval change between 1Hz <-> multihz causes GNSS to power on/off) +Type +Set +Message Structure: +$PAIR010,,,,\* +$PAIR010,0,0,2044,369413\*33 +$PAIR050,